LE79489-3JC [MICROSEMI]
SLIC, PQCC32, PLASTIC, LCC-32;
| 型号： | LE79489-3JC |
| 厂家： | 
Microsemi |
| 描述： | SLIC, PQCC32, PLASTIC, LCC-32 电信 电信集成电路 |
| 文件： | 总19页 (文件大小：491K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Le79489
Subscriber Line Interface Circuit
DISTINCTIVE CHARACTERISTICS
I Ideal for low power sensitive applications
I Low standby power (normal and reverse)
I Automatic on-chip battery switching
I On-chip thermal management
I Selectable overhead for metering applications
I Two-wire impedance set by single external
impedance
I On-chip ring and test relay drivers and relay
snubber circuits
I On-chip thermal shutdown
I Polarity reversal (full transmission)
I Loop and ground-key detector
I Comparator for ring-trip detection
I Ground-start capability
I –20 V to –60 V battery operation
I Programmable current limit
I Programmable resistive feed
I Programmable loop-detect threshold
I On-hook transmission
BLOCK DIAGRAM
TMG
DA
DB
TESTOUT
RINGOUT
Test Relay
Driver
Ring Relay
Driver
A(TIP)
HPA
C1
Ring-Trip
Comparator
C2
C3
C4
Input
Decoder
and
Two-Wire
Interface
Ground-Key
Detector
E1
Control
HPB
Loop Detector
DET
RD
VTX
Signal
B(RING)
Transmission
RSN
Power-Feed
Controller
RDC
CAS
OVH
RFA
VBAT2
Switch Control
VBAT1
BGND
VCC
AGND/DGND
BSWOUT
BSWEN BSWTH
Document ID# 080201 Date: Jun 18, 2002
Rev:
F
Version:
1
Distribution:
Public Document
ORDERING INFORMATION
Standard Products
Legerity standard products are available in several packages and operating ranges. The order number (Valid Combination) is
formed by a combination of the elements below.
Le79489*
J
C
–1
TEMPERATURE RANGE
C = Commercial (0°C to 70°C)*
PACKAGE TYPE
J = 32-pin Plastic Leaded Chip Carrier (PL 032)
PERFORMANCE GRADE OPTION
–1 = 52 dB Longitudinal Balance, Polarity Reversal
–2 = 60 dB Longitudinal Balance, Polarity Reversal
–3 = 52 dB Longitudinal Balance, No Polarity Reversal
–4 = 60 dB Longitudinal Balance, No Polarity Reversal
–5 = 52 dB Longitudinal Balance, No Polarity Reversal, Metering
–6 = 52 dB Longitudinal Balance, Polarity Reversal, Metering
DEVICE NUMBER/DESCRIPTION
Le79489
Subscriber Line Interface Circuit
Valid Combinations
Valid Combinations
–1
–2
–3
–4
–5
–6
Valid Combinations list configurations planned to
be supported in volume for this device. Consult the
local Legerity sales office to confirm availability of
specific valid combinations and to check on newly
released combinations, and to obtain additional
data on Legerity’s standard military–grade
products.
Le79489*
JC
*Legerity reserves the right to fulfill all orders for this device with parts marked with the "Am" part number prefix, until such
time as all inventory bearing this mark has been depleted. It should be noted that parts marked with either the "Am" or the
"Le" part number prefix are equivalent devices in terms of form, fit, and function. The only difference between the two is in
the part number prefix appearing on the topside mark.
2
Le79489 Data Sheet
CONNECTION DIAGRAM
Top View
4
3
2
1
32 31 30
29
28
DA
RD
TESTOUT
5
6
7
BSWOUT
TMG
27
26
25
24
23
HPB
HPA
NC
8
9
VBAT1
32-Pin PLCC
C4
VTX
10
BSWEN
C1
RSVD
11
12
13
RSN
E1
22
21
DET
AGND/DGND
14 15 16 17 18 19 20
Notes:
1. Pin 1 is marked for orientation.
2. NC = No Connect
3. RSVD = Reserved. Do not connect to this pin.
Le79489 Data Sheet
3
PIN DESCRIPTIONS
Pin Names
AGND/DGND
A(TIP)
Type
Description
Gnd
Analog and Digital ground.
Output
Gnd
Output of A(TIP) power amplifier.
Battery (power) ground.
BGND
B(RING)
BSWEN
Output
—
Output of B(RING) power amplifier.
Battery Switch Control. Internally connected to automatic battery switch circuitry. BSWEN
can be overridden by external logic. BSWEN Low connects VBAT1 to VBAT2. BSWEN
High disconnects VBAT1 from VBAT2.
BSWOUT
Output
Buffered Output. Internally connected to battery switch circuitry. The output is open-
collector with a built-in pull-up resistor. BSWOUT Low indicates VBAT1 is connected to
VBAT2. BSWOUT High indicates VBAT1 is disconnected from VBAT2. This output is
valid only in the Active states.
BSWTH
Input
Input for setting automatic battery switch threshold. Normally tied to Battery 2. Tie to
ground for manual switching.
C3–C1
C4
Input
Input
Decoder. TTL compatible. C3 is MSB and C1 is LSB.
Test Relay Input – Active Low. 1 = Off. 0 = On.
CAS
DA
Capacitor
Input
Anti-sat pin for capacitor to filter reference voltage when operating in anti-sat region.
Ring-trip negative. Negative input to ring-trip comparator.
Ring-trip positive. Positive input to ring-trip comparator.
DB
Input
DET
Output
Switchhook detector. When enabled, a logic Low indicates the selected detector is
tripped. The detector is selected by the logic inputs (C3–C1). The output is open-collector
with a built-in 15 kΩ pull-up resistor.
E1
Input
Ground-Key Detect Select. E1 = 1 selects the hook switch detector. E1 = 0 selects the
ground-key detector. In the Tip Open state, ground key is selected independent of E1.
HPA
HPB
NC
Capacitor
Capacitor
—
High-Pass Filter Capacitor. A(TIP) side of high-pass filter capacitor.
High-Pass Filter Capacitor. B(RING) side of high-pass filter capacitor.
No connect. This pin not internally connected.
OVH
Input
Overhead Control. Logic High enables minimized nonmetering overhead. Logic Low
enables 2.2 V metering DC overhead. TTL-compatible.
RD
Resistor
Resistor
Detector resistor. Detector threshold set and filter pin.
RDC
DC feed resistor. Connection point for the DC feed current programming network. The
other end of the network connects to the receiver summing node (RSN). Connection point
for the DC feed current programming network. The other end of the network connects to
RSN. VRDC is negative for normal polarity and positive for reverse polarity.
RFA
—
Resistive feed adjust. Adjust the DC feed resistance gain coefficient, GDC, with external
resistor connected to ground.
RINGOUT
RSN
Output
Input
Ring Relay Driver. Open-collector driver with emitter internally connected to BGND.
Receive Summing Node. The metallic current (AC and DC) between A(TIP) and B(RING)
is equal to 500 times the current into this pin. The networks that program receive gain,
two-wire impedance, and feed current all connect to this node.
RSVD
TESTOUT
TMG
—
Output
—
Reserved. These pins are reserved for Legerity use. Make no connection to these pins.
Test Relay Driver. Open collector driver with emitter internally connected to AGND.
Thermal Management. External resistor connects this pin to VBAT2 to offload power dis-
sipation from SLIC. Functions during normal polarity, Active state.
VBAT1
VBAT2
VCC
Battery
Battery
Power
Output
Most negative battery supply and substrate connection.
Battery supply for output power amplifiers. Switched to VBAT1 by BSWEN.
+5 V power supply.
VTX
Transmit Audio. This output is a 0.5066 unity gain version of the A(TIP) and B(RING)
metallic voltage. VTX also sources the two-wire input impedance programming network.
4
Le79489 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Storage temperature . . . . . . . . . . . . –55°C to +150°C
With respect to AGND/DGND:
OPERATING RANGES
Commercial (C) Devices
Ambient temperature. . . . . . . . . . . . . –40°C to +85°C*
V
CC. . . . . . . . . . . . . . . . . . . . . . . . . . .–0.4 V to +7.0 V
VBAT1
Continuous . . . . . . . . . . . . . . . . . . +0.4 V to –70 V
VCC . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75 V to 5.25 V
BAT1 . . . . . . . . . . . . . . . . . . . . . . . . .–40.5 V to –60 V
BAT2 . . . . . . . . . . . . . . . . . . . . . . . . . . .–20 V to BAT1
AGND/DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V
BGND with respect to GND . . . –100 mV to +100 mV
Load resistance on VTX to GND. . . . . . . . . 20 kΩ min
10 ms . . . . . . . . . . . . . . . . . . . . . . +0.4 V to –75 V
VBAT2 and BSWTH. . . . . . . . . . . . . . . +0.4 V to VBAT1
BGND. . . . . . . . . . . . . . . . . . . . . . . . . . . .+3 V to –3 V
A(TIP) or B(RING) with respect to BGND:
Continuous . . . . . . . . . . . . . . . . . . . .VBAT1 to +1 V
10 ms (f = 0.1 Hz) . . . . . . . . . . . . . . .–70 V to +5 V
1 µs (f = 0.1 Hz) . . . . . . . . . . . . . . . .–80 V to +8 V
250 ns (f = 0.1 Hz) . . . . . . . . . . . . .–90 V to +12 V
Operating ranges define those limits over which the
functionality of the device is guaranteed by production
testing.
* Legerity guarantees the performance of this device over
commercial (0 to 70°C) and industrial (-40 to 85 °C)
temperature ranges by conducting electrical characterization
over each range and by conducting a production test with
single insertion coupled to periodic sampling. These
characterization and test procedures comply with section
4.6.2 of Bellcore TR-TSY-000357 Component Reliability
Assurance Requirements for Telecommunications
Equipment.
Current from A(TIP) or B(RING). . . . . . . . . . 150 mA
TESTOUT/RINGOUT/current. . . . . . . . . . . . . . 80 mA
TESTOUT/RINGOUT/voltage . . . . . . . BGND to +7 V
TESTOUT/RINGOUT/transient . . . . . BGND to +10 V
DA and DB inputs
Voltage on ring-trip inputs. . . . . . . . . . VBAT1 to 0 V
Current on ring-trip inputs. . . . . . . . . . . . . 10 mA
C4–C1, BSWEN, OVH, E1
Input voltage . . . . . . . . . . . . –0.4 V to VCC + 0.4 V
Maximum power dissipation, continuous
TA = 70°C, No heat sink (see note):
In 32-pin PLCC package. . . . . . . . . . . . . . . . 1.7 W
Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . .θJA
In 32-pin PLCC package. . . . . . . . . . . .43°C/W typ
ESD immunity/pin (HBM) . . . . . . . . . . . . . . . . . 1500 V
Note: Thermal limiting circuitry on chip will shut down the
circuit at a junction temperature of about 165°C. The device
should never be exposed to this temperature. Operation
above 145°C junction temperature may degrade device
reliability. See the SLIC Packaging Considerations section for
more information.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to Absolute Maximum
Ratings for extended periods may affect device reliability.
Le79489 Data Sheet
5
ELECTRICAL CHARACTERISTICS
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Transmission Performance
2-wire return loss
(See Test Circuit D)
200 Hz to 3.4 kHz
26
dB
4, 6
4
Analog output (VTX) impedance
Analog output (VTX) offset voltage
Overload level, 2-wire
3
20
Ω
–50
2.5
7
+50
mV
Active state
2a,
3
Vpk
Active state, OVH = 0
–5, –6*
–5, –6*
Overload level
Open loop, RLAC = 900 Ω,
OVH = 0
3.86
2b,
3
Vrms
THD, Total Harmonic Distortion
0 dBm
–64
–55
–50
–40
–36
3
4
+7 dBm
dB
THD, open loop
0 dBm, RLAC = 600 Ω
Longitudinal Capability (See Test Circuit C)
Longitudinal to metallic L-T
200 Hz to 1 kHz
Normal and reverse polarity
–1, –6*
–3, –5
52
52
60
58
54
Normal polarity
Normal polarity
0°C to +70°C –2, –4
Normal polarity –40°C to +85°C –2, –4
Reverse polarity –40°C to +85°C –2
dB
8
7
Longitudinal to metallic L-T
1 kHz to 3.4 kHz
Normal and reverse polarity
Normal polarity
–1, –6*
–3, –5
52
52
54
54
54
Normal polarity
0°C to +70°C –2, –4
Normal polarity –40°C to +85°C –2, –4
Reverse polarity –40°C to +85°C –2
Longitudinal signal generation 4-L 200 Hz to 3.4 kHz
40
15
dB
Longitudinal current per pin
(A or B)
Active state
27
25
mArms
Longitudinal impedance at A or B
Longitudinal Induction
0 to 100 Hz
Ω/pin
4
4
23
dBrnc
Idle Channel Noise
C-message weighted noise
Psophometric weighted noise
RL = 600 Ω
RL = 600 Ω
+7
+12
–78
dBrnC
dBmp
4, 8
8
–83
Insertion Loss (See Test Circuits A and B)
Gain, 4- to 2-wire
0 dBm, 1 kHz
0°C to 70°C
–40°C to 85°C
–0.15
–0.20
0
0
+0.15
+0.20
4
Gain, 2- to 4-wire, 4-to-4-wire
0 dBm, 1 kHz
0°C to 70°C
–40°C to 85°C
–6.05 –5.90 –5.75
–6.10 –5.90 –5.70
4
4
4
Gain, 4- to 2-wire
Open loop
Open loop
–0.35
+0.35
dB
µs
Gain, 2- to 4-wire, 4- to 4-wire
Gain over frequency
Gain tracking
–6.25 –5.90 –5.55
300 to 3.4 kHz, relative to 1 kHz
+3 dBm to –55 dBm relative to 0 dBm
0 dB to –15 dB
–0.10
–0.10
–0.35
+0.10
+0.10
+0.35
Gain tracking open loop
Group delay
4
0 dBm, 1 kHz
4
4, 6
Note:
* P.G. = Performance Grade
6
Le79489 Data Sheet
ELECTRICAL CHARACTERISTICS (CONTINUED)
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Line Characteristics
IL, Active
Short loop
Medium loop
Long loop
R
R
R
LDC = 250 Ω
LDC = 700 Ω
LDC = 2 kΩ
44.2
33.4
17.2
48.6
37.1
19.2
54.0
40.8
21.2
IL, Active
OVH = 0
Short loop
Medium loop
Long loop
RLDC = 250 Ω
RLDC = 700 Ω
RLDC = 2 kΩ
44.2
33.4
16.0
48.6
37.1
18.0
54.0
40.8
20.0
–5, –6*
mA
IL, Accuracy, Standby state
0.7 IL
IL
1.3 IL
VBAT1 – 3 V
IL = ----------------------------------
RL + 400
TA = 25°C
Current limited region
RL = 0
18
30
IL, Loop current, Disconnect state
ILLIM
100
135
µA
Active, A and B to GND
95
52
mA
Vapparent
4
VAB, Open loop voltage
Active, Normal
Reverse Polarity
OVH = 0
40.3
39.8
37
41.7
41.7
39
V
mV
V
BAT SW hysteresis
BAT SW threshold
1150
BAT2
+ 8.5
(from VBAT1 to VBAT2
)
OVH = 0
–5, –6*
BAT2
+ 11.7
IA, Leakage, Tip Open state
IB, Current, Tip Open state
VA, Active
RL = 0
100
56
µA
mA
V
B to GND
18
30
–5
RA to BAT1 = 7 kΩ, RB to
GND = 100 Ω
–7.5
4
Power Supply Rejection Ratio (Vripple = 100 mVrms), Active Normal State
VCC
50 Hz to 3.4 kHz
50 Hz to 3.4 kHz
50 Hz to 3.4 kHz
30
28
35
45
50
50
3
4
VBAT1
VBAT2
dB
VBAT1, Open loop, RLAC = 600 Ω
(Anti-sat region)
50 Hz
100 Hz
200 Hz
500 Hz to 3.4 kHz
8
14
22
29
40
15
20
28
4
4
Effective internal resistance
Device Power Dissipation
Open loop, Disconnect state
Open loop, Standby state
Open loop, Active state
Open loop, Active state
Off hook, Standby state
Off hook, Active state
85
170
255
kΩ
CAS pin to GND
35
50
70
85
OVH = 1
OVH = 0
RL = 600 Ω
150
550
1000
250
620
1300
mW
9
RL = 250 Ω
RL = 700 Ω
880
800
1200
1000
Le79489 Data Sheet
7
ELECTRICAL CHARACTERISTICS (CONTINUED)
Description
Test Conditions (See Note 1)
Min
Typ
Max
Unit
Note
Supply Currents, Battery
ICC
,
Disconnect state
Standby state
Active state
2.5
3.0
6.3
4.5
4.5
9.5
Open Loop VCC supply current
mA
mVrms
V
IBAT1
,
Disconnect state
Standby state
Active state
0.5
0.7
2.8
1.0
1.5
4.8
Open Loop VBAT1 supply current
RFI Rejection
RFI rejection
100 kHz to 30 MHz
(See Figure E)
0.7
4
Logic Inputs (C4–C1, E1, BSWEN, OVH [–5, –6 only])
VIH, Input High voltage
C3
C1, C2, C4, BSWEN, OVH, E1
2.5
2.0
VIL, Input Low voltage
0.8
40
IIH, Input High current C4–C1,
OVH, E1
–75
IIH, Input High current, BSWEN
IIL, Input Low current, except C1
IIL, Input Low current, C1
–75
–400
–600
1200
0.40
+50
µA
V
–300
Logic Output (DET, BSWOUT)
VOL, Output Low voltage
VOH, Output High voltage
IOUT = 0.3 mA
IOUT = –0.05 mA
2.4
Ring-Trip Comparator Input (DA, DB)
Bias current
–500
–50
–50
0
nA
Offset voltage
Source resistance = 2 MΩ
mV
5
Loop Detector
IT, Loop-detect threshold
tolerance
Active state, Off-hook to On-hook
RD = 35.4 kΩ, IT = 368/RD
On-hook to Off-hook
–15
–20
–15
–20
+15
+20
+15
+20
RD = 35.4 kΩ, IT = 414/RD
Standby state, Off-hook to On-hook
RD = 35.4 kΩ, IT = 425/RD
On-hook to Off-hook
%
RD = 35.4 kΩ, IT = 471/RD
Active state
Loop-detect threshold hysteresis
IGK, GND key-detector threshold
1.3
9
4
Standby state
mA
RL from BX to GND
Active, Standby, and Tip Open states
5
6
13
Relay Driver Output (RINGOUT/TESTOUT)
On voltage
IOL = 40 mA
+0.3
+0.7
100
V
Off leakage
VOH = +5 V
IZ = 100 µA
IZ = 40 mA
µA
Zener breakover
Zener On voltage
7.5
7.9
V
10
8
Le79489 Data Sheet
RELAY DRIVER SCHEMATICS
RINGOUT
TESTOUT
BGND
BGND
Notes:
1. Unless otherwise specified, test conditions are VCC = +5 V, BAT1 = –50 V, BAT2 = –34 V, RL = 600 Ω, RDC1 = RDC2 = 5.833 kΩ,
RTMG = 570 Ω, RD = 35.4 kΩ, RFA = 0 Ω, no fuse resistors, CHP = 0.22 µF, CDC = 0.5 µF, CCAS = 0.33 µF, CVBAT12 = 220 nF,
D1 = D2 = 1N400x, OVH = 1, two-wire AC input impedance is a 600 Ω resistance synthesized by the programming network
shown below.
VTX
RT1 =76 kΩ
CT1 =120 pF
RT2 =76 kΩ
RSN
RRX = 150 kΩ
VRX
2. a. Overload level exists when THD = 1%.
b. Overload level exists when THD = 1.5%.
3. This parameter is tested at 1 kHz in production. Performance at other frequencies is guaranteed by characterization.
4. Not tested in production. This parameter is guaranteed by characterization or correlation to other tests.
5. Tested with 0 Ω source impedance. 2 MΩ is specified for system design only.
6. Group delay can be greatly reduced by using a ZT network such as that shown in Note 1 above. The network reduces the
group delay to less than 2 µs and increases 2WRL. The effect of group delay on linecard performance also may be
compensated for by synthesizing complex impedance with the DSLAC™ or QSLAC™ device.
7. Minimum current level is guaranteed not to cause a false Loop Detect. The SLIC must be functional in this condition.
8. Four-wire performance is 5–9 dB better than the specified two-wire values.
9. Open loop, Active state, Metering mode power dissipation may be reduced from a typical of 550 mW to a typical of 150 mW
by connecting the DET pin to the OVH pin. This connection will force the SLIC into the nonmetering mode while on hook. With
this connection, a metering signal sent after the SLIC goes on hook may be distorted on the 2W line because the SLIC is
forced into the nonmetering mode. To eliminate this distortion, a delay can be added between the time the SLIC goes on hook
and the time the SLIC switches to nonmetering mode by using an RC circuit for the DET pin to OVH pin connection.
Le79489 Data Sheet
9
Table 1. SLIC Decoding
DET Output
E1 = 1
State
C3 C2 C1
2-Wire Status
Standby, Reverse Polarity
Reserved
E1 = 0
GK
0
1
2
3
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Loop detector
X
X
Active, Reverse Polarity
Tip Open
Loop detector
GK or loop detector
Ring trip
GK
GK
Disconnect
Ring trip
Ring trip
GK
Ringing
Ring trip
Active, Normal
Standby, Normal
Loop detector
Loop detector
GK
Table 2. User-Programmable Components
ZT = 253(Z2WIN – 2RF)
ZT is connected between the VTX and RSN pins. The fuse
resistors are RF, and Z2WIN is the desired two-wire AC input
impedance. When computing ZT, the internal current
amplifier pole and any external stray capacitance between
VTX and RSN must be taken into account. The internal
amplifier pole is:
22 kHz • RLAC
-------------------------------------
600 Ω 10%
Z
G
RX is connected from VRX to RSN. ZT is defined above, and
42L is the desired receive gain. ZL is the 2-wire load
impedance.
ZL
G42L
500(ZT)
ZT + 253(ZL + 2RF)
----------- ---------------------------------------------------
ZRX
=
•
R
DC1, RDC2, and CDC form the network connected to the RDC
625(GFA)
ILIMIT = ---------------------------------
pin. RDC1 and RDC2 are approximately equal. ILIMIT is the
desired loop current in the constant-current region.
R
DC1 + RDC2
R
DC1 + RDC2
DC1 • RDC2
-------------------------------
CDC = 1.5 ms •
R
(RFA + 30.1 kΩ)
------------------------------------------
GFA = 0.99 •
(RFA + 32 kΩ)
(RFA + 60 kΩ)
-----------------------------------------
RCL = 1.4 • (RDC1 + RDC2) •
(RFA + 100 kΩ)
RD and CD form the network connected from RD to AGND/
DGND and IT is the threshold current between on hook and
off hook in the Active state.
365
0.5 ms
--------
IT
RD
=
,
CD = ---------------
RD
C
CAS is the regulator filter capacitor and fc is the desired filter
1
CCAS = -----------------------------
3.4 • 105πfc
cutoff frequency.
Standby loop current (resistive region).
VBAT1 – 3 V
IS tandby = ----------------------------------
400 Ω+ RL
10
Le79489 Data Sheet
Table 2. User-Programmable Components (continued)
CBSWEN = 5 µmhos • TD(ms) CBSWEN is connected from BSWEN to GND for automatic
switching. TD is the delay in switching from BAT1 to BAT2.
The delay from BAT2 to BAT1 is about 0.1 TD.
The DC feed resistance can be adjusted with a resistance
(RFA) from the RFA pin to ground.
R
DC1 + RDC2
---------------------------------
GDC
RFEED = 2 • RFUSE
+
40 kΩ+ RFA
------------------------------------
GDC = 47.9
120 kΩ+ RFA
Thermal Management Equations (Active, Normal, and Reverse Polarity States)
RTMG is connected from TMG to VBAT2 and is used to limit
power dissipation within the SLIC in Active states only.
VBAT2 – 6 V
----------------------------------
ILOOPmax
RTMG
≥
≥
(OVH = 1)
(OVH = 0)
VBAT2 – 7.5 V
---------------------------------------
ILOOPmax
RTMG
Power dissipated in the thermal management resistor, RTMG
during the Active states.
,
( VBAT2 – 6 V – (IL • RL))2(RTMG
)
PRTMG = -------------------------------------------------------------------------------------------
(RTMG + 40)2
(OVH = 1)
( VBAT2 – 7.5 V – (IL • RL))2(RTMG
)
PRTMG = ------------------------------------------------------------------------------------------------
(RTMG + 40)2
(OVH = 0)
Power dissipated in the SLIC while in the Active states.
PSLIC = ( VBAT2 • IL ) – PRTMG – RL • (IL)2 + 0.22 W
Le79489 Data Sheet
11
DC FEED CHARACTERISTICS
RDC = RDC1 + RDC2 = 11.67 kΩ,
RFA = 0 Ω
No fuse resistors
18.8 mA, 38.8 V
OVH = 1
BAT1 = –50 V
60
3
41.5 V
48.0 mA, 18.5 V
VAB
(Volts)
2
1
0
50.0 mA
60
IL (mA)
0
Notes:
Graph is for illustration only.
1. VAB = ILIMIT • RCL – IL • RCL
RDC
------------
2. VAB = 52 V – IL
GDC
RDC
------------------------
VAB = 0.8 VBAT1 + 2.2 – IL
, OVH = 1
5 • GDC
3a.
RDC
------------------------
3b. VAB = 0.8 VBAT1 – 1.0 – IL
, OVH = 0
5 • GDC
a. Load Line (Typical)
A
a
RSN
RL
IL
SLIC
RDC1
b
CDC
RDC2
B
RDC
Feed current programmed by RDC1 and RDC2
b. Feed Programming
Figure 1. DC Feed Characteristics
12
Le79489 Data Sheet
TEST CIRCUITS
A(TIP)
A(TIP)
VTX
VTX
RL
2
SLIC
SLIC
AGND
AGND
RT
VAB
RT
VL
VAB
RL
RL
2
RRX
RRX
RSN
RSN
VRX
B(RING)
IL2-4 = –20 log (VTX / VAB
B(RING)
)
IL4-2 = –20 log (VAB / VRX)
A. Two- to Four-Wire Insertion Loss
B. Four- to Two-Wire Insertion Loss
1
<< RL
ωC
A(TIP)
RL
2
VTX
SLIC
AGND
S1
C
RT
VL
VAB
VL
S2
RRX
RL
2
RSN
VRX
B(RING)
S2 Open, S1 Closed
S2 Closed, S1 Open
L-T Long. Bal. = 20 log (VAB / VL)
L-4 Long. Bal. = 20 log (VTX / VL)
4-L Long. Sig. Gen. = 20 log (VL / VRX)
C. Longitudinal Balance
Le79489 Data Sheet
13
TEST CIRCUITS (continued)
ZD
A(TIP)
VTX
SLIC
RT1
R
AGND
VS
VM
CT1
R
RT2
ZIN
RSN
B(RING)
RRX
ZD is the specified nominal input impedance.
Return loss = –20 log (2 VM / VS)
D. Two-Wire Return Loss Test Circuit
L1
C1
RF1
A
CAX
33 nF
200 Ω
200 Ω
50 Ω
HF
GEN
50 Ω
B
CBX
VTX
C2
RF2
33 nF
L2
50 Ω
SLIC Under Test
1.5 Vrms
80% Amplitude
Modulated
100 kHz to 30 MHz
E. RFI Test Circuit
14
Le79489 Data Sheet
TEST CIRCUITS (continued)
+5 V
DA
DB
VCC
RD
CD
(optional)
2.2 nF
A(TIP)
A(TIP)
HPA
RD
VTX
VTX
CHP
RT
RRX
HPB
VRX
RSN
RDC
B(RING)
2.2 nF
B(RING)
RDC2
RDC1
TESTOUT
CDC
RINGOUT
BGND
AGND/
DGND
RFA
BSWOUT
RFA
BSWTH
VBAT2
OVH
BSWEN
C4
BAT2
BATTERY
GROUND
C
VBAT12
C3
C2
VBAT1
TMG
BAT1
D1
C1
E1
ANALOG
GROUND
RTMG
(optional)
DET
CAS
DIGITAL
GROUND
CCAS
F. Le79489 Test Circuit
Le79489 Data Sheet
15
PHYSICAL DIMENSIONS
32-Pin PLCC
16
Le79489 Data Sheet
REVISION SUMMARY
Revision C to Revision D
•
In the Electrical Characteristics table on page 8, some information was changed in the Test Conditions column
in the Loop Detector section and the “Loop-detect threshold hysteresis” row was added to this section.
Revision D to Revision E
•
•
The physical dimensions (PL032) were added to the Physical Dimensions section.
Updated the Pin Description table to correct inconsistencies.
Revision E to Revision F
•
•
•
•
•
Updated OPN (Ordering Part Number) throughout document.
Absolute Maximum Ratings: Notes updated to standard.
Operating Ranges: Temperature statement updated to standard.
Updated "Sales Office Listing."
Updated physical dimension drawings.
17
Le79489 Data Sheet
The contents of this document are provided in connection with Legerity, Inc. products. Legerity makes no representations or warranties with respect to the accuracy or completeness of the
contents of this publication and reserves the right to make changes to specifications and product descriptions at any time without notice. No license, whether express, implied, arising by estoppel
or otherwise, to any intellectual property rights is granted by this publication. Except as set forth in Legerity's Standard Terms and Conditions of Sale, Legerity assumes no liability whatsoever,
and disclaims any express or implied warranty, relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particular purpose, or infringement of any
intellectual property right.
Legerity's products are not designed, intended, authorized or warranted for use as components in systems intended for surgical implant into the body, or in other applications intended to support
or sustain life, or in any other application in which the failure of Legerity's product could create a situation where personal injury, death, or severe property or environmental damage may occur.
Legerity reserves the right to discontinue or make changes to its products at any time without notice.
© 2002 Legerity, Inc.
All rights reserved.
Trademarks
Legerity, the Legerity logo and combinations thereof, and QSLAC, DSLAC, are trademarks of Legerity, Inc.
Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies.
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Fax: (512) 228-5508
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nearest you, or to download or order
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