ZL40235LDG1 [MICROCHIP]
Clock Driver;
| 型号： | ZL40235LDG1 |
| 厂家： | 
MICROCHIP |
| 描述： | Clock Driver 驱动 逻辑集成电路 |
| 文件： | 总50页 (文件大小：1929K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
ZL40235
Low Skew, Low Additive Jitter 3 x 5 LVPECL/LVDS/HCSL
Fanout Buffer with one LVCMOS output
Ordering Information
Features
ZL40235LDG1
ZL40235LDF1
40 pin QFN
40 pin QFN
Trays
Tape and Reel
• 3 to 1 input Multiplexer: Two inputs accept any
differential (LVPECL, HCSL, LVDS, SSTL, CML,
LVCMOS) or a single ended signal and the third
input accepts a crystal or a single ended signal
Package size: 6 x 6 mm
-40 C to +85 C
• Five differential LVPECL/LVDS/HCSL outputs and
one LVCMOS output
Applications
• Ultra-low additive jitter: 24fs (integration band 12kHz
•
•
•
•
•
General purpose clock distribution
Low jitter clock trees
to 20MHz at 625MHz clock frequency)
• Supports clock frequencies from 0 to 1.6GHz
Logic translation
• Supports 2.5V or 3.3V power supplies for LVPECL,
Clock and data signal restoration
LVDS or HCSL outputs
Wired communications: OTN, SONET/SDH, GE, 10 GE,
FC and 10G FC
• Supports 1.5V, 1,8V, 2.5V or 3.3V power supplies
for LVCMOS output
•
•
•
•
PCI Express generation 1/2/3/4 clock distribution
Wireless communications
• Embedded Low Drop Out (LDO) Voltage regulator
provides superior Power Supply Noise Rejection
High performance microprocessor clock distribution
Test Equipment
• Maximum output to output skew of 40ps
• Device controlled via SPI or hardware pins
SEL
OE
SPI Slave
LVCMOS_OE/
SPI_CS_b
SPI_CS_b
Registers:
xtal_buf_gain[7:0]
Bank A
xtal_drive_level[7:0]
xtal_load_cap[7:0]
input_select[1:0]
IN_SEL0
SPI_CLK
IN_SEL0/
SPI_CLK
OUT0_p
OUT0_n
output_drive_low
driver_type[7:0] (diff)
driver_type[9:8] (diff)
cmos_div[2:0] (cmos)
output_enable (cmos)
driver_strength (cmos)
Device ID
IN_SEL1/
SPI_SDI
IN_SEL1
SPI_SDIO
OUT1_p
OUT1_n
SPI_SDO
Bank
B
OUT2_p
OUT2_n
OUT_TYPE_SEL0
OUT_TYPE_SEL1
OUT3_p
OUT3_n
IN0_p
IN0_n
OUT4_p
OUT4_n
IN1_p
IN1_n
DIV
OUT_LVCMOS
1to8
ZL40235
XOUT
XIN
Figure 1. Functional Block Diagram
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Data Sheet
ZL40235
Table of Contents
Features.....................................................................................................................................1
Applications................................................................................................................................1
Table of Contents ......................................................................................................................2
Pin Diagram ...............................................................................................................................5
Pin Descriptions.........................................................................................................................6
Functional Description ...............................................................................................................9
Clock Inputs ...............................................................................................................................9
Clock Outputs ..........................................................................................................................12
Crystal Oscillator Input.............................................................................................................13
Termination of unused inputs and outputs ..............................................................................13
Power Consumption ................................................................................................................13
Power Supply Filtering.............................................................................................................14
Power Supplies and Power-up Sequence...............................................................................14
Host Interface ..........................................................................................................................14
Typical device performance.....................................................................................................19
Register Map ...........................................................................................................................23
AC and DC Electrical Characteristics......................................................................................29
Absolute Maximum Ratings.....................................................................................................29
Recommended Operating Conditions .....................................................................................29
Change History........................................................................................................................48
Package Outline ......................................................................................................................49
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Data Sheet
ZL40235
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Functional Block Diagram........................................................................................................................................... 1
Pin Diagram ................................................................................................................................................................ 5
Input driven by a single ended output ........................................................................................................................ 9
Input driven by DC coupled LVPECL output................................................................................................................. 9
Input driven by DC coupled LVPECL output (alternative termination)...................................................................... 10
Input driven by AC coupled LVPECL output............................................................................................................... 10
Input driven by HCSL output ..................................................................................................................................... 10
Input driven by LVDS output ..................................................................................................................................... 11
Input driven by AC coupled LVDS .............................................................................................................................. 11
Input driven by an SSTL output ................................................................................................................................. 11
Termination for LVCMOS outputs............................................................................................................................. 12
Driving a load via transformer.................................................................................................................................. 12
Crystal Oscillator Circuit in Hardware Controlled Mode........................................................................................... 13
Power Supply Filtering .............................................................................................................................................. 14
SPI slave interface..................................................................................................................................................... 16
Serial Peripheral Interface Functional Waveform – LSB First Mode ......................................................................... 17
Serial Peripheral Interface Functional Waveform – MSB First Mode ....................................................................... 17
Example of the Burst Mode Operation ..................................................................................................................... 18
156.25MHz LVPECL................................................................................................................................................... 19
1.5GHz LVPECL.......................................................................................................................................................... 19
156.25MHz LVDS ...................................................................................................................................................... 19
1.5GHz LVDS ............................................................................................................................................................. 19
100MHz HCSL............................................................................................................................................................ 19
250MHz HCSL............................................................................................................................................................ 19
I/O delay vs temperature.......................................................................................................................................... 20
PSNR vs noise frequency........................................................................................................................................... 20
100MHz LVPECL Phase Noise................................................................................................................................... 20
100MHz LVDS Phase Noise ....................................................................................................................................... 20
156.25MHz LVDS Phase Noise in Xtal mode............................................................................................................. 20
100MHz HCSL Phase Noise ....................................................................................................................................... 20
156.25MHz LVPECL Phase Noise............................................................................................................................... 21
625MHz LVPECL Phase Noise.................................................................................................................................... 21
156.25MHz LVDS Phase Noise .................................................................................................................................. 21
625MHz LVDS Phase Noise ....................................................................................................................................... 21
Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate ................................................................................. 22
Output clock noise floor vs input clock slew-rate ..................................................................................................... 22
Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate ................................................................................. 22
Output clock noise floor vs input clock slew-rate ..................................................................................................... 22
Output RMS jitter (12kHz to 20MHz) vs input clock slew-rate ................................................................................. 22
Output clock noise floor vs input clock slew-rate ..................................................................................................... 22
Differential Input Voltage Levels .............................................................................................................................. 30
Differential Output Voltage Levels ........................................................................................................................... 34
SPI (Serial Peripheral Interface) Timing - LSB First Mode ......................................................................................... 46
SPI (Serial Peripheral Interface) Timing - MSB First Mode........................................................................................ 46
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
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Data Sheet
ZL40235
List of Tables
Table 1 Pin Description................................................................................................................................................................................... 6
Table 2 Input clock selection ........................................................................................................................................................................ 15
Table 3 Output Type Selection...................................................................................................................................................................... 15
Table 4 Register Map ................................................................................................................................................................................... 23
Table 5 Absolute Maximum Ratings*........................................................................................................................................................... 29
Table 6 Recommended Operating Conditions* ............................................................................................................................................ 29
Table 7 Current consumption ....................................................................................................................................................................... 29
Table 8 Input Characteristics* ...................................................................................................................................................................... 30
Table 9 Crystal Oscillator Characteristics* ................................................................................................................................................... 31
Table 10 Power Supply Rejection Ratio for VDD = VDDO = 3.3V* ................................................................................................................ 31
Table 11 Power Supply Rejection Ratio for VDD = VDDO = 2.5V* ................................................................................................................ 32
Table 12 LVCMOS Output Characteristics for VDDO = 3.3V* ....................................................................................................................... 32
Table 13 LVCMOS Output Characteristics for VDDO = 2.5V* ....................................................................................................................... 33
Table 14 LVPECL Output Characteristics for VDDO = 3.3V* ......................................................................................................................... 34
Table 15 LVPECL Output Characteristics for VDDO = 2.5V* ......................................................................................................................... 35
Table 16 LVDS Outputs for VDDO = 3.3V*.................................................................................................................................................... 36
Table 17 LVDS Outputs for VDDO = 2.5V*.................................................................................................................................................... 37
Table 18 HCSL Outputs for VDDO = 3.3V* .................................................................................................................................................... 38
Table 19 HCSL Outputs for VDDO = 2.5V* .................................................................................................................................................... 39
Table 20 LVCMOS Output Phase Noise with 25 MHz XTAL*......................................................................................................................... 40
Table 21 LVPECL Output Phase Noise with 25 MHz XTAL*........................................................................................................................... 40
Table 22 LVDS Output Phase Noise with 25 MHz XTAL ................................................................................................................................ 41
Table 23 HCSL Output Phase Noise with 25 MHz XTAL ................................................................................................................................ 41
Table 24 LVCMOS Output Phase Noise with 125 MHz XTAL*....................................................................................................................... 42
Table 25 LVPECL Output Phase Noise with 125 MHz XTAL*......................................................................................................................... 42
Table 26 LVDS Output Phase Noise with 125 MHz XTAL .............................................................................................................................. 43
Table 27 HCSL Output Phase Noise with 125 MHz XTAL .............................................................................................................................. 43
Table 28 LVCMOS Output Phase Noise with 156.25 MHz XTAL* ................................................................................................................. 44
Table 29 LVPECL Output Phase Noise with 156.25 MHz XTAL*.................................................................................................................... 44
Table 30 LVDS Output Phase Noise with 156.25 MHz XTAL ......................................................................................................................... 45
Table 31 HCSL Output Phase Noise with 156.25 MHz XTAL ......................................................................................................................... 45
Table 32 AC Electrical Characteristics* - SPI (Serial Peripheral Interface) Timing........................................................................................ 46
Table 33 6x6mm QFN Package Thermal Properties ..................................................................................................................................... 47
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Data Sheet
ZL40235
Pin Diagram
The device is packaged in a 6 x 6 mm 40-pin QFN.
Pin#1
Corner
40
39
38
37
36
35
34
33
32
31
1
2
30
GND
GND
NC1
29
OUT2_p
3
4
28
27
NC2
OUT2_n
VDDO_B
VDDO_A
OUT0_p
5
26
25
OUT3_p
OUT3_n
Exposed GND Pad 4.3 x 4.3 mm
6
7
OUT0_n
VDDO_A
24
23
VDDO_B
OUT4_p
8
OUT1_p
OUT1_n
GND
22
21
OUT4_n
GND
9
10
11
12
13
14
15
16
17
18
19
20
Figure 2. Pin Diagram
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Data Sheet
ZL40235
Pin Descriptions
All device inputs and outputs are LVPECL unless described otherwise. The I/O column uses the following symbols: I
– input, IPU – input with 300k internal pull-up resistor, IPD – input with 300k internal pull-down resistor, IAPU – input
with 31k internal pull-up resistor, IAPD – input with 30k internal pull-down resistor, IAPU/APD – input with 60k
internal pull-up and pull-down resistors (30 k equivalent), O – output, I/O – Input/Output pin, NC – No connect, P –
power supply pin.
Table 1 Pin Description
#
Name
I/O
Description
Input Reference
IAPD
IAPU/APD
IAPD
IN0_p
IN0_n
IN1_p
IN1_n
16
17
35
34
Input Differential or Single Ended References 0 and 1
Input frequency range 0Hz to 1.6GHz.
IAPU/APD
Non- inverting inputs (_p) are pulled down with internal 30k pull-down resistors.
Inverting inputs (_n) are biased at VDD/2 with 60k pull-up and pull-down resistors
to keep inverting input voltages at VDD/2 when inverting inputs are left floating
(device fed with a single ended reference).
Output Clocks
O
Ultra-Low Additive Jitter Differential LVPECL/HCSL/LVDS Outputs 0 to 4
5
6
8
9
29
28
26
25
23
22
OUT0_p
OUT0_n
OUT1_p
OUT1_n
OUT2_p
OUT2_n
OUT3_p
OUT3_n
OUT4_p
OUT4_n
Output frequency range 0 to 1.6GHz
In SPI bus controlled mode (SEL pin pulled high on the power up) type
(LVPECL/HCSL/LVDS/High-Z) of each output is programmable via SPI bus
In Hardware control mode (SEL pin pulled low on the power up) type
(LVPECL/HCSL/LVDS/High-Z) of each output bank is controlled via
OUTA/B_TYPE_SEL0/1 pins
O
Ultra-Low Additive Jitter LVCMOS Output
37
OUT_LVCMOS
Output frequency range 0 to 250MHz
Control
IPD
32
SEL
Select control.
When this pin is low, the device is controlled via hardware pins, IN_SEL0/1 and OE.
When this pin is high, the device is controlled via SPI port.
Any change of SEL pin value requires power cycle. Hence, SEL pin cannot be
changed on the fly.
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Data Sheet
ZL40235
IPD
15
IN_SEL0/SPI_CLK
Input Select 0 or Clock for Serial Interface. When SEL pin is low this pin is Input
Select 0 hardware control input pin and it is pulled-down with 300 k resistor. When
SEL pin is high this pin provides clock for serial micro-port interface and it is pulled-
up with 300 k resistor.
or
IPU
IN_SEL1 IN_SEL0
OUTN
Input 0 (IN0)
0
0
1
1
0
1
0
1
Input 1 (IN1)
Crystal Oscillator or overdrive
Crystal Bypass
IPD
18
19
33
39
IN_SEL1/SPI_SDI
IC1/SPI_SDO
IC2
Input Select 1 or Serial Interface Input. When SEL pin is low this pin is Input
Select 1 hardware control pin and it is pulled-down with 300 k resistor. When SEL
pin is high this pin is serial interface input stream and it is pulled-up with 300 k
resistor. The serial data stream holds the access command, the address and the
write data bits.
or
IPU
I/O
Internal Connection 1 or Serial Interface Output.
When SEL pin is low this pin in an internal connection. Leave open.
When SEL pin is high this pin is Serial interface output stream. As an output the
serial stream holds the read data bits.
IPD
Internal Connection 2. This pin should be left open.
IPD
LVCMOS_OE/
SPI_CS_b
LVCMOS Output Enable or Chip Select for Serial Interface.
or
IPU
When SEL pin is low this pin is LVCMOS Output Enable hardware control input and
it is pulled-down with 300 k resistor.
When SEL pin is high this pin is serial interface chip select and it is pulled-up with
300 k resistor--this is an active low signal.
IPD
11
40
OUT_TYPE_SEL0/
Output Signal Type:
IC3
OUT_TYPE_SEL1/
IC4
When SEL pin is low these two pins Selects Type for all outputs
OUT_TYPE_SEL1
OUT_TYPE_SEL0
Output 0 to 4
LVPECL
0
0
1
1
0
1
0
1
LVDS
HCSL
High-Z (Disabled)
When SEL pin is high these two pins are unused and should be left unconnected.
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Data Sheet
ZL40235
Crystal Oscillator
13
XIN
I
Crystal Oscillator Input or crystal bypass mode or crystal overdrive mode
If crystal oscillator is not used pull down this pin or connect it to ground.
14
XOUT
O
Crystal Oscillator Output
No Connect
2
3
NC1
NC2
NC
No Connect (not connected to the die) Leave unconnected or connect to GND for
mechanical support
Power and Ground
12
36
VDD
P
P
Positive Supply Voltage. Connect to 3.3V or 2.5V supply.
4
7
VDDO_A
VDDO_B
Positive Supply Voltage for Differential Outputs Bank A Connect 3.3V or 2.5V
power supply. VDDO_A does not have to be connected to the same voltage level as
VDD or VDDO_B.
These pins power up differential outputs OUT0_p/n and OUT1_p/n.
24
27
P
Positive Supply Voltage for Differential Outputs Bank B Connect 3.3V or 2.5V
power supply. VDDO_B does not have to be connected to the same voltage level as
VDD or VDDO_A.
These pins power up differential outputs OUT2_p/n, OUT3_p/n and OUT4_p/n.
38
VDD_LVCMOS
GND
P
P
Positive Supply Voltage for LVCMOS Output Connect 3.3V, 2.5V, 1.8V or 1.5V
power supply
1
Ground Connect to ground
10
20
21
30
31
E-Pad
GND
P
Ground. Connect to ground
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Data Sheet
ZL40235
Functional Description
The ZL40235 is a programmable or hardware pin controlled low additive jitter, low power 3 x 5 LVPECL/HCSL/LVDS
fanout buffer.
Two inputs can accept signal in differential (LVPECL, SSTL, LVDS, HSTL, CML) or single ended (LVPECL or
LVCMOS) format and the third input can accept a single ended signal or it can be used to build a crystal oscillator by
connecting an external crystal resonator between its XIN and XOUT pins. All the other components for building
crystal oscillator are built in device such as load capacitance, series and shunt resistors.
The ZL40235 has five LVPECL/HCSL/LVDS outputs which can be powered from 3.3V or 2.5V supply. Each output
can be independently enabled/disabled via SPI bus. The type of each output driver can be programmed to be
LVPECL, HCSL or LVDS. Hence, the device can be configured to support application where different signal formats
are needed.
The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature
range -40°C to +85°C.
Clock Inputs
The following blocks diagram shows how to terminate different signals fed to the ZL40235 inputs.
Figure 3 shows how to terminate a single ended output such as LVCMOS. Ideally, resistors R1 and R2 should be
100 each and Ro + Rs should be 50 so that the transmission line is terminated at both ends with characteristic
impedance. If the driving strength of the output driver is not sufficient to drive low impedance, the value of series
resistor RS should be increased. This will reduce the voltage swing at the input but this should be fine as long as the
input voltage swing requirement is not violated (Table 8). The source resistors of Rs = 270 could be used for
standard LVCMOS driver. This will provide 516mV of voltage swing for 3.3V LVCMOS driver with load current of
(3.3V/2) *(1/(270 + 50)) = 5.16mA.
For optimum performance both differential input pins (_p and _n) need to be DC biased to the same voltage. Hence,
the ratio R1/R2 should be equal to the ratio R3/R4.
Vdd
Vdd
Vdd
Vdd
Optional AC coupling
capacitor
R3
R1
0.1 µF
Rs
Ro
Z0 = 50 Ω
Ro + Rs = Z0
R1/R2 = R3/R4
Example:
R1 = R2 = 100Ω
R3 = R4 = 1kΩ
R2
MSCC Device
0.1 µF
R4
Rs = 270Ω for standard LVCMOS output
Figure 3. Input driven by a single ended output
VDD
VDD
VDD
VDD
RUP
RUP
Z0 = 50 Ω
Z0 = 50 Ω
LVPECL
RDWN
RDWN
MSCC Device
VDD
3.3V
RUP
127 Ω
RDWN
82 Ω
2.5V 250 Ω
62.5 Ω
Figure 4. Input driven by DC coupled LVPECL output
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Data Sheet
ZL40235
VDD
VDD
Z0 = 50 Ω
Z0 = 50 Ω
LVPECL
LVPECL
50 Ω
50 Ω
MSCC Device
VDD
3.3V
2.5V
RDWN
50 Ω
22 Ω
RDWN
Figure 5. Input driven by DC coupled LVPECL output (alternative termination)
VDD
VDD
VDD
100 Ω
VDD
100 Ω
10 nF
10 nF
Z0 = 50 Ω
Z0 = 50 Ω
LVPECL
200 Ω
200 Ω
100 Ω 100 Ω
MSCC Device
Figure 6. Input driven by AC coupled LVPECL output
VDD
VDD
VDD
1 kΩ
1 kΩ
VDD
33 Ω
33 Ω
1µF
1µF
Z0 = 50 Ω
Z0 = 50 Ω
HCSL
50 Ω
50 Ω
1 kΩ
1 kΩ
MSCC Device
50Ω resistors can be alternatively
connected at the source after 33Ω
series resistors.
Figure 7. Input driven by HCSL output
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Data Sheet
ZL40235
VDD
MSCC Device
VDD
Z0 = 50 Ω
Z0 = 50 Ω
100 Ω
LVDS
Figure 8. Input driven by LVDS output
VDD
VDD
10 kΩ
10 nF
VDD
10 kΩ
VDD
Z0 = 50 Ω
Z0 = 50 Ω
100 Ω
LVDS
10 nF
10 kΩ
MSCC Device
10 kΩ
Figure 9. Input driven by AC coupled LVDS
VDD
VDD
VDD
120 Ω
120 Ω
VDD
Z0 = 60 Ω
Z0 = 60 Ω
SSTL
120 Ω 120 Ω
MSCC Device
Input driven by SSTL driver
Figure 10.
Input driven by an SSTL output
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Data Sheet
ZL40235
Clock Outputs
LVCMOS output OUT10 require only series termination resistor whose value is depending on LVCMOS output
voltage as shown in Figure 11.
VDDO
3.3V
2.5V
1.8V
1.5V
Rs
VDDO
35Ω
30Ω
20Ω
10Ω
VDD = VDDO
Rs
LVCMOS
Z0 = 50 Ω
MSCC Device
Figure 11.
Termination for LVCMOS outputs
Differential outputs LVPECL and LVDS should have same termination as corresponding outputs described in
previous section. HCSL outputs should be terminated with 33Ω series resistors at the source and 50Ω shunt resistors
at the source or at the end on the transmission line. AC coupling and re-biasing is not required at the outputs when
driving native HCSL receivers.
The device is designed to drive differential input of semiconductor devices. In applications that use a transformer to
convert from the differential to the single ended output (for example driving an oscilloscope 50 input), a resistor
larger than 10 should be added at the center tap of the primary winding to achieve optimum jitter performance as
shown in Figure 12. This is to provide a nominal common mode impedance of 10 or higher which is typical for
differential terminations.
Add resistor to the ground or leave open
VDD
2 : 1
Z0 = 50 Ω
10 nF
Z0 = 50 Ω
Z0 = 50 Ω
24.9 Ω
LVPECL
10 nF
50 Ω
200 Ω
200 Ω
Figure 12.
Driving a load via transformer
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Data Sheet
ZL40235
Crystal Oscillator Input
The crystal oscillator circuit can work with crystal resonators from 8MHz to 160MHz. To be able support crystal
resonators with different characteristics all internal components are programmable.
The load capacitors can be programmed from 0 to 21.75 pF (4pF default) with resolution of 0.25pF which not only
meets load requirement for most crystal resonator but also allows for fine tuning of the crystal resonator frequency.
The amplifier gain can be adjusted in five steps and series resistor can be adjusted as parallel combination of seven
different resistors: 0Ω, 10.5Ω, 21Ω, 42Ω, 84Ω, 161Ω and 312Ω (84Ω default). Although the first resistor is 0Ω the
series resistance Rs will be slightly higher than 0Ω due to parasitic resistance of the switch which connects resistor.
Hence the minimum series resistance is achieved when all seven resistors are connected in parallel. The shunt
resistor is fixed and its value is 500k.
In Hardware Controlled mode the capacitive load is set at 4pF, internal series resistance to 84Ω and they cannot be
changed. For Crystal requiring higher load or series resistance additional capacitance and/or series resistance can be
added externally as shown in the Figure 13.
C1
XIN
Crystal
Rs
XOUT
C2
Load capacitors C1 and C2
should be as per crystal
specification
MSCC Device
Figure 13.
Crystal Oscillator Circuit in Hardware Controlled Mode
Termination of unused inputs and outputs
Unused inputs can be left unconnected or alternatively IN_0/1 can be pulled-down by 1kΩ resistor. Unused outputs
should be left unconnected.
Power Consumption
The device total power consumption can be calculated as:
P = P + PXTAL + P + P
+ P
T
S
C
O _ DIF
O _ LVCMOS
Where:
The core power when XTAL is not used. The
current is specified in Table 7. .If XTAL is running
this power should be set to zero.
P =VDD IS
S
The core power when XTAL is used. The current
is provided in Table 7. If XTAL is not used this
power should be set to zero.
PXTAL =VDD I DD_ XTAL
P =VDDO I DD _ CM
Common output power shared among all ten
outputs. The current IDD_CM is specified in Table 7.
C
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Data Sheet
Output power where output currents are specified
ZL40235
in Table 7.
P
=VDDO (IDD_ LVDS N1
O_ DIF
N1, N2 and N3 are number of enabled LVPECL,
LVDS and HSCL outputs respectively and
N1+N2+N3 is less or equal to 5.
+ IDD_ LVPECL N2 + IDD_ HCSL N3)
Dynamic LVCMOS output power. IDD is specified
in Table 7. If LVCMOS output is disabled this
term is equal to zero.
P
O_ LVCMOS =VDD_ LVCMOS (IDD f /100MHz
+VDD_ LVCMOS CLOAD f )
Power dissipated inside the device can be calculated by subtracting power dissipated in termination/biasing resistors
from the power consumption.
PD = P − N1 PLVPECL − N2 P
− N3 PHCSL
T
LVDS
Where N1, N2 and N3 are number of enabled LVPECL, LVDS and HSCL outputs respectively. Since there are five
differential outputs N1 + N2 + N3 is less or equal to 5.
2 /50 +
(
VOL −VB
)
2 /50
VB /50
VOH and VOL are the output high and low voltages
respectively for LVPECL output
P
=
(
VOH −VB
)
LVPECL
+
(
VOH −VB VB /50 +
)
(
VOL −VB
)
VB is LVPECL bias voltage equal to VDD – 2V
=VSW 2 /100
VSW is voltage swing of LVDS output.
P
LVDS
VSW is voltage swing of HCSL output. 50Ω is
termination resistance and 33Ω is series resistance
of the HCSL output.
P
=
(
VSW /50
)
2
(
33 + 50
)
HCSL
Power Supply Filtering
Each power pin (VDD and VDDO) should be decoupled with 0.1µF capacitor with minimum equivalent series
resistance (ESR) and minimum series inductance (ESL). For example, 0402 X5R Ceramic Capacitors with 6.3V
minimum rating could be used. These capacitors should be placed as close as possible to the power pins. To reduce
the power noise from adjacent digital components on the board each power supply could be further insulated with low
resistance ferrite bead with two capacitors. The ferrite bead will also insulate adjacent component from the noise
generated from the device. Following figure shows recommended decoupling for each power pin.
Board Supply
10uF
Ferrite Bead
1uF
VDD or VDDO
0.1uF
Figure 14.
Power Supply Filtering
Power Supplies and Power-up Sequence
The device has four different power supplies: VDD, VDDO_A, VDDO_B and VDD_LVCMOS which are mutually
independent. Voltages supported by each of these power supplies are specified in Table 1.
The device is not sensitive to the power-up sequence. For example, commonly used sequence where higher voltage
comes up before or at the same time as the lower voltages can be used (or any other sequence)
Host Interface
ZL30235 can be controlled via hardware pins (SEL pin tied low) or via SPI port (SEL pin tied high). The mode shall be
selected during power up and it cannot be changed on the fly.
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Data Sheet
ZL40235
Hardware Control Mode
In this mode, ZL40235 is controlled via Input Select (IN_SEL0/1) pins which select which one of three inputs is fed to
the output and show in Table 2 and OUT_TYPE_SEL0/1 pins which select signal level (LVPECL, LVDS, HCSL or Hi-
Z) as shown in Table 3.
All input control pins have low input threshold voltage so they can be driven from the device with low output voltage
(FPGA/CPLD). Supported voltages are between 1.2V and VDD (2.5V or 3.3V).
Table 2 Input clock selection
IN_SEL1
IN_SEL0
Selected Input
IN0_p, IN0_n
IN1_p, IN1_n
XIN
0
0
1
0
1
X
Table 3 Output Type Selection
OUT_TYPE_SEL1
OUT_TYPE_SEL0
Output
LVPECL
0
0
1
1
0
1
0
1
LVDS
HCSL
High-Z (Output Disabled)
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Data Sheet
ZL40235
SPI Control Mode
ZL40235 is controlled via four pin SPI slave interface as shown in the following figure.
SCK
SI
MSCC Device
SO
CS_b
Figure 15.
SPI slave interface
All SPI input pins have low threshold voltage so they can be driven from low output voltage SPI master device.
Supported voltages are between 1.2V and VDD (2.5V or 3.3V). This allows device to be controlled from an FPGA
with low voltage I/O supply.
The serial peripheral interface supports half-duplex processor mode which means that during a write cycle to the
device, output data from the SO pin must be ignored. Similarly, the input data on the SI pin is ignored by the device
during a read cycle.
The SPI interface supports two modes of access: Most Significant bit (MSb) first transmission or Least Significant bit
(LSb) first transmission. The mode is automatically selected based on the state of SCK pin when the CS_b pin is
active. If the SCK pin is low during CS_b activation, then MSb first timing is selected. If the SCK pin is high during
CS_b activation, then LSb first timing is assumed.
The SPI port expects 1-bit to differentiate between read and write operation followed by 7-bit addressing and 8-bit
data transmission. During SPI access, the CS_b pin must be held low until the operation is complete. Burst read/write
mode is also supported by leaving the chip select signal CS_b is low after a read or a write. The address will be
automatically incremented after each data byte is read or written.
Functional waveforms for the LSb and MSb first mode, and burst mode are shown in Figure 16 and Figure 17
respectively. Figure 18 shows an example of burst mode operation which allows user to read or write consecutive
location in the register map.
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© 2018 Microsemi Corporation
Data Sheet
ZL40235
cs_b
sck
Read from the device
si
Rd A0 A1 A2 A3 A4 A5 A6
X
X
X
X
X
X
X
X
so
D0 D1 D2 D3 D4 D5 D6 D7
Write to the device
D0 D1 D2 D3 D4 D5 D6 D7
Wr A0 A1 A2 A3 A4 A5 A6
si
X
X
X
X
X
X
X
X
so
Command/Address
Data
Figure 16.
Serial Peripheral Interface Functional Waveform – LSB First Mode
cs_b
sck
Read from the device
Rd A6 A5 A4 A3 A2 A1 A0
X
X
X
X
X
X
X
X
si
so
D7 D6 D5 D4 D3 D2 D1 D0
Write to the device
si
Wr A6 A5 A4 A3 A2 A1 A0
D7 D6 D5 D4 D3 D2 D1 D0
X
X
X
X
X
X
X
X
Command/Address
Data
so
Figure 17.
Serial Peripheral Interface Functional Waveform – MSB First Mode
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Data Sheet
ZL40235
cs_b
Address +0
Data
Address +1
Data
Address +2
Data
Address +N
Data
Address
Figure 18.
Example of the Burst Mode Operation
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Data Sheet
ZL40235
Typical device performance
The following plots show typical device performances
Figure 19.
156.25MHz LVPECL
Figure 20.
Figure 22.
Figure 24.
1.5GHz LVPECL
1.5GHz LVDS
250MHz HCSL
Figure 21.
156.25MHz LVDS
Figure 23.
100MHz HCSL
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Data Sheet
ZL40235
Figure 25.
I/O delay vs temperature
Figure 26.
PSNR vs noise frequency
Figure 28.
100MHz LVDS Phase Noise
Figure 27.
100MHz LVPECL Phase Noise
Figure 29.
156.25MHz LVDS Phase Noise in
Xtal mode
Figure 30.
100MHz HCSL Phase Noise
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Data Sheet
ZL40235
Figure 31.
156.25MHz LVPECL Phase Noise
Figure 32.
625MHz LVPECL Phase Noise
Figure 33.
156.25MHz LVDS Phase Noise
Figure 34.
625MHz LVDS Phase Noise
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Data Sheet
ZL40235
Figure 35.
Output RMS jitter (12kHz to
Figure 36.
Output clock noise floor vs input
clock slew-rate
20MHz) vs input clock slew-rate
Figure 37.
Output RMS jitter (12kHz to
Figure 38.
Output clock noise floor vs input
clock slew-rate
20MHz) vs input clock slew-rate
Figure 39.
Output RMS jitter (12kHz to
Figure 40.
Output clock noise floor vs input
clock slew-rate
20MHz) vs input clock slew-rate
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Data Sheet
ZL40235
Register Map
The device is controlled by accessing registers through the serial interface. The following table provides a summary
of the registers available for the configuration of the device.
Table 4 Register Map
Address
SPI A[6:0]
Hex (0x)
00
Name
Data D[7:0]
XTALBG
XTALDL
XTALLC
XTALNR
-
xtal_buf_gain[7:0]
xtal_drive_level[7:0]
xtal_load_cap[7:0]
xtal_normal_run
Not used
01
02
03
04
05
INSEL
input_select[1:0]
output_drive_low
06
OUTLOW
DRVTYPEA
-
07
{driver_type[5:4], 4’bxxxx} (differential output 1 and 0)
08
Not used
09
DRVTYPEB
-
{driver_type[17:12], 2’bxx} (differential output 4, 3, and 2)
0A
Not used
0B
CMOSDIV
cmos_div[2:0] (cmos)
0C
CMOSOUTEN output_enable (cmos)
CMOSDRVSTR driver_strength (cmos)
0D
0E
-
Not used
0F/11
11
Reserved
DEVID
Leave as default
Device ID
12 to 1F
Reserved
Leave as default
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Data Sheet
ZL40235
Address
XTALBG
Bit
0x00
Hex
XTAL Buffer Gain
Description
Name
Type Reset
7:0
Programs crystal buffer (inverting amplifier) gain.
RW
FF
xtal_buf_gain[7:0] Every bit pair (bits: 01, 23, 45, 67) of this register correspond to
additional equal gain block which can be added (bits set) or
removed (bits cleared).
Minimum gain is 0x00 (default) and 0xFF is maximum gain
When reference input mode is “bypass XTAL mode” or
“differential input modes” with HIGH xtal_normal_run bit, the
buffer is disabled and follows “Input Selection”.
When xtal_normal_run bit is LOW, XTAL buffer is in the “xtal
forced run” mode and keep running.
8’b0000_0000: default crystal buffer strength.
8’b0000_0011: enable additional buffer strength
8’b0000_1100: enable additional buffer strength
8’b0011_0000: enable additional buffer strength
8’b1100_0000: enable additional buffer strength
Address
XTALDL
Bit
0x01
Hex
XTAL Drive Level
Name
Description
Type Reset
RW 04
7:0
Internal damping resistance of crystal circuit to limit external
xtal_drive_level[7:0] crystal’s drive level uW.
The value of damping resistor is determined by crystal’s
motion resistance of crystal’s equivalent circuit.
Drive level should be lower than crystal manufacturer’s
specification.
Crystal’s equivalent values should be requested to the
manufacturer, (motion resistance and shunt capacitance).
The selected resistors are connected to XOUT.
Multiple bit combinations available by 7-bit control.
Because they use parallel connections, 0xFF is the smallest
resistance and 0x01 is the highest resistance.
8’b0000_0000: disable all resistors
8’b0000_0001: 312 Ohm resistor
8’b0000_0010: 161 Ohm resistor
8’b0000_0100: 84 Ohm resistor
8’b0000_1000: 42 Ohm resistor
8’b0001_0000: 21 Ohm resistor
8’b0010_0000: 10.5 Ohm resistor
8’b0100_0000: 0 Ohm connection
8’b1000_0000: not used
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Data Sheet
ZL40235
Address
XTALLC
Bit
0x02
Hex
XTAL Load Capacitance 0
Description
Name
Type Reset
7:0
xtal_load_cap[7:0]
Internal load capacitance of crystal circuit (0 pF to 21.75 pF
with the resolution of 0.25 pF).
RW
40
XIN and XOUT have each capacitor connected to GND.
Multiple bit combinations available between 8 capacitors.
8’b0000_0000: disable all xtal load capacitors
8’b0000_0001: enable capacitor 0.25 pF
8’b0000_0010: enable capacitor 0.5 pF
8’b0000_0100: enable capacitor 1 pF
8’b0000_1000: enable capacitor 2 pF
8’b0001_0000: enable capacitor 2 pF
8’b0010_0000: enable capacitor 4 pF
8’b0100_0000: enable capacitor 4 pF
8’b1000_0000: enable capacitor 8 pF
Address
XTALNR
Bit
0x03
Bin
XTAL Normal Run
Description
Name
Type
Reset
7:1
Reserved
Reserved
R
1111111
0
xtal_normal_run
When this bit is set high crystal oscillator circuit is running
only if input_select[1:0] register at address 0x05 selects
crystal mode (2’b10). This value is recommended because
it provides best jitter performance--XO circuit is running only
when it is needed.
RW
1
When this bit is set low the crystal oscillator will keep
running even if crystal oscillator is not selected in
input_select[1:0] register at address 0x05. This mode
should only be used when fast switching between input
references and crystal oscillator is required.
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Data Sheet
ZL40235
Address
INSEL
Bit
0x05
Bin
Input Select Register
Description
Name
Type
Reset
7:2
Reserved
Reserved
R
111111
1:0
input_select[1:0]
Input reference clock selection.
RW
00
Proper external coupling and termination are required.
2’b00: differential input from IN0_p and IN0_n
2’b01: differential input from IN1_p and IN1_n
2’b10: fundamental XTAL mode with XIN and
XOUT (Use internal crystal oscillator circuits)
or XTAL overdrive mode (single-ended clock
signal fed to XIN)
2’b11: XTAL bypass mode (single-ended clock signal
with XIN and disabled internal crystal buffer
circuit in the analog block)
Address
OUTLOW
Bit
0x06
Hex
Output Drive Low
Description
Reserved
Name
Type
Reset
7:1
0
Reserved
output_drive_low
R
1111111
0
Forces all disabled outputs to drive low in LVPECL mode. RW
1’b1: All differential outputs that are disabled in
DRVTYPE registers (addresses 0x07, 0x08, 0x09
and 0x0A) will drive low in LVPECL mode. Hence,
LVPECL biasing/termination resistors are required
for proper functionality of this feature.
1’b0: This feature is ignored and all outputs that are
disabled in DRVTYPE registers (addresses 0x07,
0x08, 0x09 and 0x0A) will stay in disabled (high-Z)
mode.
Address
DRVTYPEA
Bit
0x07
Bin
Output Type Select Bank-A
Name
Description
Type Reset
7:6
driver_type[7:6]
Output driver type of differential OUT1.
RW
11
The same description as for OUT0.
4:3
driver_type[5:4]
Output driver type of differential OUT0.
RW
11
2’b00: LVPECL outputs
2’b01: LVDS outputs
2’b10: HCSL outputs
2’b11: outputs disabled (Disabled state is dependent on
“out_drive_low” control bit of register OUTLOW.”)
3:0
Reserved
Reserved
RO
X
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Data Sheet
ZL40235
Address
DRVTYPEB
Bit
0x09
Bin
Output Type Select Bank-B
Description
Name
Type Reset
7:6
driver_type[17:16]
Output driver type of differential OUT4.
RW
RW
RW
11
11
11
The same description as for OUT0.
5:4
3:2
driver_type[15:14]
driver_type[13:12]
Output driver type of differential OUT3.
The same description as for OUT0.
Output driver type of differential OUT2.
The same description as for OUT0.
Reserved
1:0
Reserved
RO
X
Address
CMOSDIV
Bit
0x0B
Bin
Type Reset
CMOS Output Divider
Description
Name
7:3
Reserved
Reserved
R
11111
2:0
cmos_div[2:0]
Integer divider from a selected input reference clock for
OUT_LVCMOS (1 to 8).
RW
000
3’b000: division ratio = 1
3’b001: division ratio = 2
3’b010: division ratio = 3
3’b011: division ratio = 4
3’b100: division ratio = 5
3’b101: division ratio = 6
3’b110: division ratio = 7
3’b111: division ratio = 8
Address
CMOSOUTEN
Bit
0x0C
Bin
LVCMOS Output Enable
Description
Name
Type
Reset
7:1
Reserved
Reserved
R
1111111
0
output_enable
Output enable of OUT_LVCMOS.
RW
1
Disabled state is dependent on “out_drive_low” control
bit.
1’b0: Disable OUT_LVCMOS output
1’b1: Enable OUT_LVCMOS output
Address
0x0D
Bin
CMOSDRVSTR
CMOS Driver Strength
Description
Bit
Name
Type
Reset
7:1
Reserved
Reserved
R
1111111
0
driver_strength
OUT_LVCMOS output strength.
RW
0
1’b0: low strength
1’b1: high strength
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Data Sheet
ZL40235
Address
DEVID
0x11
Bin
Device Identification
Bit
Name
Description
Type Reset
7
Unused
Unused
R
0
6:5
4:0
Reserved
dev_id
Reserved
Device ID
R
11
RO
00010
5’h02: ZL40235
ZL40235
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Data Sheet
ZL40235
AC and DC Electrical Characteristics
Absolute Maximum Ratings
Table 5 Absolute Maximum Ratings*
Parameter
Sym.
VDD /VDDO
VDD /VDDO
TST
Min.
-0.5
-0.5
-55
Typ.
Max.
4.6
Units
V
Notes
1
2
3
Supply voltage (3.3V)
Supply voltage (2.5V)
Storage temperature
3.5
V
125
°C
* Exceeding these values may cause permanent damage
* Functional operation under these conditions is not implied
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions
Table 6 Recommended Operating Conditions*
Characteristics
Sym.
VDD /VDDO/VDD_LVCMOS
VDD /VDDO/VDD_LVCMOS
VDD_LVCMOS
Min.
3.135
2.375
1.6
Typ.
3.30
2.50
1.8V
1.5
Max.
Units Notes
1
2
3
4
5
6
Supply voltage 3.3V
Supply voltage 2.5V
Supply voltage 1.8V
Supply voltage 1.5V
3.465
2.625
2
V
V
V
VDD_LVCMOS
1.35
-40
1.65
V
Operating temperature
Input voltage
TA
25
85
°C
V
VDD-IN
- 0.3
VDD + 0.3
* Voltages are with respect to ground (GND) unless otherwise stated
* The device core supports two power supply modes (3.3V and 2.5V)
Table 7 Current consumption
Characteristics
Sym.
Is_3.3V
Min.
Typ.
163
Max.
197
Units
mA
mA
mA
mA
mA
mA
mA
Notes
VDD= 3.3V+5%
VDD = 2.5V+5%
VDD= 3.3V+5%
VDD= 2.5V+5%
VDDO= 3.3V+5%
VDDO= 2.5V+5%
VDDO= 3.3V+5%
1
2
3
Core device current (all outputs and XTAL disabled)
Is_2.5V
153
187
Core device current (all outputs disabled) XTAL circuit
enabled with 25MHz Crystal connected between XIN and
XOUT
IDD_XTAL_3.3V
IDD_XTAL_2.5V
IDD_CM_3.3V
IDD_CM_2.5V
IDD_3.3V
128
154
124
150
13.44
12.18
4.08
15.05
13.65
4.74
Common output current
Dynamic LVCMOS current for high strength output (f =
100MHz)
4
5
IDD_2.5V
IDD_3.3V
IDD_2.5V
mA
mA
mA
VDDO= 2.5V+5%
VDDO= 3.3V+5%
VDDO= 2.5V+5%
2.90
2.38
1.74
3.29
2.68
1.96
Needs to be scaled for different frequencies by f/100MHz
Dynamic LVCMOS current for low strength output (f =
100MHz)
Needs to be scaled for different frequencies by f/100MHz
IDD_LVPECL_3.3V
IDD_LVPECL_2.5V
IDD_LVDSL_3.3V
IDD_LVDS_2.5V
IDD_HCSL_3.3V
IDD_HCSL_2.5V
mA
mA
mA
mA
mA
mA
VDDO= 3.3V+5%
VDDO= 2.5V+5%
VDDO= 3.3V+5%
VDDO= 2.5V+5%
VDDO= 3.3V+5%
VDDO= 2.5V+5%
19.36
19.38
6.73
23.26
22.17
8.00
6
7
8
Current dissipation per LVPECL output
Current dissipation per LVDS output
Current dissipation per HCSL output
6.87
7.83
16.43
17.14
19.87
19.18
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© 2018 Microsemi Corporation
Data Sheet
ZL40235
Table 8 Input Characteristics*
Characteristics
CMOS high-level input voltage for control inputs
CMOS low-level input voltage for control inputs
Sym.
VCIH
VCIL
IIL
Min.
Typ.
Max.
Units
V
Notes
1
2
1.05
0.45
50
V
CMOS input leakage current for control inputs (includes current due to pull
down resistors)
-25
µA
VI = VDD or 0 V
3
4
5
Differential input common mode voltage for IN0_p/n and IN1_p/n
VCM
VID
1
2
V
V
Differential input voltage difference for IN0_p/n and IN1_p/n
f ≤ 1GHz **
0.15
1.3
Differential input voltage difference for IN0_p/n and IN1_p/n for
1GHz < f ≤ 1.6GHz **
VID
0.35
-150
1.3
V
6
Differential input leakage current for IN0_p/n and IN1_p/n (includes
current due to pull-up and pull-down resistors)
IIL
150
µA
VI = 2V or 0V
7
8
9
VSI
VSIC
VSID
-0.3
1
2.7
2
V
V
V
VDD = 3.3V or
2.5V
Single ended input voltage for IN0_p and IN1_p
VDD = 3.3V or
2.5V
Single ended input common mode voltage (IN0_p/n and IN1_p/n)
0.3
1.3
VDD = 3.3V or
2.5V
10 Single ended input voltage swing for IN0_p and IN1_p
11 Input frequency (differential)
12 Input frequency (LVCMOS)
13 Input duty cycle
fIN
fIN_CMOS
dc
0
0
1600
250
MHz
MHz
35%
65%
14 Input slew rate
slew
RPU/RPD
RPD
2
V/ns
dBc
15 Input pull-up/ pull-down resistance
16 Input pull-down resistance for INx_p
60kΩ
30kΩ
-84
fIN = 100 MHz
fIN = 200 MHz
fIN = 400 MHz
fIN = 800 MHz
-82
Input multiplexer isolation IN0_p/n to IN1_p/n and vice versa
Power on both inputs 0dBm, fOFFSET > 50kHz
17
Iso
-71
-67
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
* Input mux isolation is measured as amplitude of fOFFSET spur in dBc on the output clock phase noise plot
**Input differential voltage is calculated as VID = VIH-VIL where VIH and VIL are input voltage high and low respectively. It should not be confused with VID = 2 * (VIH
VIL) used in some datasheets. Please refer to Figure 41.
-
V
IH - VIL
VIH
VID = VIH - VIL
VCM
VIL
0
2 * VID
VIL - VIH
0
Figure 41.
Differential Input Voltage Levels
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Data Sheet
ZL40235
Table 9 Crystal Oscillator Characteristics*
Characteristics
Sym.
mode
f
Min.
Typ.
Max.
Units
Notes
1
2
3
4
5
6
7
Mode of oscillation
Frequency
Fundamental
8
0
160
MHz
pF
pF
Ω
On chip load capacitance in SPI controlled mode
On chip load capacitance in pin controlled mode
On chip series resistor in SPI controlled mode
On chip series resistor in pin controlled mode
On chip shunt resistor
CL
21.75
Programmable
Fixed
4
RS
R
0
312
Programmable
Fixed
84
Ω
500
kΩ
Functional but
may not meet
AC
parameters
Frequency in overdrive mode(1)
Frequency in bypass mode(2)
fOV
0.1
250
250
MHz
MHz
Minimum
depends on
AC coupling
Capacitor
(0.1uF
8
9
assumed)
Functional but
may not meet
AC
fBP
0
parameters
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
(1)
(2)
Maximum input level is 2V
Maximum output level is VDD
Table 10 Power Supply Rejection Ratio for VDD = VDDO = 3.3V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
-71.75
-84.45
-82.11
-95.16
-97.77
-79.23
-77.15
-76.75
-80.44
fIN = 156.25 MHz
fIN = 312.5 MHz
fIN = 625 MHz
fIN = 156.25 MHz
fIN = 312.5 MHz
fIN = 625 MHz
fIN = 100 MHz
fIN = 156.25 MHz
fIN = 312.5 MHz
1
2
3
PSRR for LVPECL output
PSRRLVPECL
dBc
PSRR for LVDS output
PSRR for HCSL output
PSRRLVDS
dBc
dBc
PSRRHCSL
* Values are over Recommended Operating Conditions
* Noise injected to VDDO power supply with frequency 100 kHz and amplitude 100 mVpp
* PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot
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Data Sheet
ZL40235
Table 11 Power Supply Rejection Ratio for VDD = VDDO = 2.5V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
-73.68
-78.88
-71.82
-90.04
-79.99
-73.45
-92.16
-74.08
-91.88
fIN = 156.25 MHz
fIN = 312.5 MHz
fIN = 625 MHz
fIN = 156.25 MHz
fIN = 312.5 MHz
fIN = 625 MHz
fIN = 100 MHz
fIN = 156.25 MHz
fIN = 312.5 MHz
1
2
3
PSRR for LVPECL output
PSRRLVPECL
dBc
PSRR for LVDS output
PSRR for HCSL output
PSRRLVDS
dBc
dBc
PSRRHCSL
* Values are over Recommended Operating Conditions
* Noise injected to VDDO power supply with frequency 100 kHz and amplitude 100 mVpp
* PSRR is measured as amplitude of 100 kHz spur in dBc on the output clock phase noise plot
Table 12 LVCMOS Output Characteristics for VDDO = 3.3V*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
DC
1
2
3
4
5
Output high voltage (1mA load)
VOH
VDDO-0.1
V
Measurement
DC
Output low voltage (1mA load)
VOL
IOH
IOL
0.1
V
Measurement
DC
Output High Current (Load adjusted to Vout = VDDO/2)
Output Low Current (Load adjusted to Vout = VDDO/2)
Output impedance
30
34
15
mA
mA
Ω
Measurement
DC
Measurement
DC
RO
Measurement
6
7
8
9
Rise time (20% to 80%)
Fall time (20% to 80%)
Output frequency
tr
tf
220
320
310
365
250
2.07
ps
ps
FO
tIOD
tEN
TDIS
0
MHz
ns
1.07
1.28
Input to output delay
10 Output enable time
11 Output disable time
3
3
cycles
cycles
46
56
80
Input Clock
25MHz
12 Additive RMS jitter in 1MHz to 5MHz band
13 Additive RMS jitter in 12kHz to 5MHz band
14 Additive RMS jitter in 1MHz to 20MHz band
15 Additive RMS jitter in 12kHz to 20MHz band
16 Additive RMS jitter in 1MHz to 20MHz band
17 Additive RMS jitter in 12kHz to 20MHz band
18
Tj_1M_5M
Tj_12K_5M
Tj_1M_20M
Tj_12k_20M
Tj_1M_20M
Tj_12k_20M
fs
fs
90
79
Input Clock
25MHz
60
Input Clock
125MHz
fs
65
86
Input Clock
125MHz
fs
61
94
Input Clock
156.25MHz
fs
66
100
-162
-156
-153
Input Clock
156.25MHz
fs
-165
-160
-158
Input clock:
25 MHz
dBc/Hz
dBc/Hz
dBc/Hz
Input clock:
125 MHz
19 Noise floor
NF
Input clock:
156.25 MHz
20
* Values are over Recommended Operating Conditions
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Data Sheet
ZL40235
Table 13 LVCMOS Output Characteristics for VDDO = 2.5V*
Characteristics
Output high voltage (1mA load)
Sym.
Min.
Typ.
Max.
Units
Notes
DC
1
2
3
4
5
VOH
VDDO-0.1
V
Measurement
DC
Output low voltage (1mA load)
VOL
IOH
IOL
0.1
V
Measurement
DC
Output High Current (Load adjusted to Vout = VDDO/2)
Output Low Current (Load adjusted to Vout = VDDO/2)
Output impedance
21
25
15
mA
mA
Ω
Measurement
DC
Measurement
DC
RO
Measurement
6
7
8
9
Rise time (20% to 80%)
Fall time (20% to 80%)
Output frequency
tr
tf
225
320
310
365
250
2.30
3
ps
ps
FO
tIOD
tEN
TDIS
0
MHz
ns
Input to output delay
1.10
1.41
10 Output enable time
11 Output disable time
cycles
cycles
3
51
62
104
Input Clock
25MHz
12 Additive RMS jitter in 1MHz to 5MHz band
13 Additive RMS jitter in 12kHz to 5MHz band
14 Additive RMS jitter in 1MHz to 20MHz band
15 Additive RMS jitter in 12kHz to 20MHz band
16 Additive RMS jitter in 1MHz to 20MHz band
17 Additive RMS jitter in 12kHz to 20MHz band
18
Tj_1M_5M
Tj_12k_5M
Tj_1M_20M
Tj_12k_20M
Tj_1M_20M
Tj_12k_20M
fs
111
81
Input Clock
25MHz
fs
fs
64
Input Clock
125MHz
70
88
Input Clock
125MHz
fs
62
94
Input Clock
156.25MHz
fs
68
100
-161
-155
-153
Input Clock
156.25MHz
fs
-164
-159
-158
Input clock:
25 MHz
dBc/Hz
dBc/Hz
dBc/Hz
Input clock:
125 MHz
19 Noise floor
NF
Input clock:
156.25 MHz
20
* Values are over Recommended Operating Conditions
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Data Sheet
ZL40235
Table 14 LVPECL Output Characteristics for VDDO = 3.3V*
Characteristics
Sym.
VLVPECL_OH
VLVPECL_OL
VLVPECL_SW
∆VLVPECL_SW
VCM
Min.
1.9
1.2
0.6
0
Typ.
2.08
1.36
0.72
0.02
1.72
Max.
2.4
1.7
0.9
0.07
2.1
800
1600
170
1600
40
Units
V
Notes
1
2
3
4
5
7
8
9
Output high voltage
Output low voltage
DC Measurement
DC Measurement
DC Measurement
V
Output differential swing**
V
Variation of VLVPECL_SW for complementary output states
Common mode output
V
1.6
V
Output frequency when VLVPECL_SW ≥ 0.6V
Output frequency when VLVPECL_SW ≥ 0.4V
Rise or fall time (20% to 80%)
FMAX_0.6VSW
FMAX_0.4VSW
tr, tf
MHz
MHz
ps
110
10 Output frequency
FO
0
MHz
ps
11 Output to output skew
12 Device to device output skew
13 Input to output delay
14 Output enable time
15 Output disable time
tOOSK
tDOOSK
120
1.1
3
ps
tIOD
0.73
0.87
ns
tEN
cycles
cycles
fs
tDIS
3
68
50
96
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 625 MHz
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 625 MHz
Input clock: 100 MHz
Input clock: 156.25 MHz
Input clock: 625 MHz
16 Additive RMS jitter in 1MHz to 20MHz band
17 Additive RMS jitter in 12kHz to 20MHz band
Tj_1M_20M
Tj_12k_20M
NF
64
fs
20
32
fs
71
101
70
fs
55
fs
25
39
fs
-161
-160
-155
-159
-155
-151
dBc/Hz
dBc/Hz
dBc/Hz
18 Noise floor
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. . Please refer to Figure 42.
VOH
V
OL
-
VOH
VCM
VOL
V
SW = VOH - VOL
0
2 * VSW
0
VOL - VOH
Figure 42.
Differential Output Voltage Levels
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October 2018
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34
Data Sheet
ZL40235
Table 15 LVPECL Output Characteristics for VDDO = 2.5V*
Characteristics
Sym.
VLVPECL_OH
VLVPECL_OL
VLVPECL_SW
∆VLVPECL_SW
VCM
Min.
1.1
0.4
0.6
0
Typ.
1.28
0.57
0.71
0.02
0.92
Max.
1.7
0.9
0.9
0.05
1.2
800
1600
170
1600
40
Units
V
Notes
1
2
3
4
5
7
8
9
Output high voltage
Output low voltage
DC Measurement
DC Measurement
DC Measurement
V
Output differential swing**
V
Variation of VLVPECL_SW for complementary output states
Common mode output
V
0.8
V
Output frequency when VLVPECL_SW ≥ 0.6V
Output frequency when VLVPECL_SW ≥ 0.4V
Rise or fall time (20% to 80%)
FMAX_0.6VSW
FMAX_0.4VSW
tr, tf
MHz
MHz
ps
120
10 Output frequency
FO
0
MHz
ps
11 Output to output skew
12 Device to device output skew
13 Input to output delay
14 Output enable time
15 Output disable time
tOOSK
tDOOSK
120
1.1
3
ps
tIOD
0.75
0.87
ns
tEN
cycles
cycles
fs
tDIS
3
65
50
91
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 625 MHz
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 625 MHz
Input clock: 100 MHz
Input clock: 156.25 MHz
Input clock: 625 MHz
16 Additive RMS jitter in 1MHz to 20MHz band
17 Additive RMS jitter in 12kHz to 20MHz band
Tj_1M_20M
Tj_12k_20M
NF
64
fs
20
30
fs
69
99
fs
54
75
fs
26
41
fs
-161
-160
-155
-159
-156
-151
dBc/Hz
dBc/Hz
dBc/Hz
18 Noise floor
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 42.
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© 2018 Microsemi Corporation
Data Sheet
ZL40235
Table 16 LVDS Outputs for VDDO = 3.3V*
Characteristics
Sym.
VLVDS_OH
VLVDS_OL
VLVDS_SW
∆VLVDS_SW
VCM
Min.
1.3
1.0
0.25
0
Typ.
1.39
Max.
1.47
1.15
0.39
0.01
1.3
Units
V
Notes
1
2
3
4
5
6
7
8
9
Output high voltage
Output low voltage
DC Measurement
DC Measurement
DC Measurement
1.07
V
Output differential swing**
0.32
V
Variation of VLVDS_SW for complementary output states
Common mode output
0.002
1.23
V
1.15
0
V
Variation of VCM for complementary output states
Output frequency when VLVDS_SW ≥ 250mV
Output frequency when VLVDS_SW ≥ 200mV
Rise or fall time (20% to 80%)
∆VCM
0.001
0.01
800
1600
170
1600
20
V
FMAX_0.25VSW
FMAX_0.2VSW
tr, tf
MHz
MHz
ps
110
10 Output frequency
FO
0
MHz
ps
11 Output to output skew
12 Device to device output skew
13 Input to output delay
tOOSK
tDOOSK
130
1.1
ps
tIOD
0.76
-24
0.86
ns
Single ended outputs
shorted to GND
14 Output Short Circuit Current Single Ended
15 Output Short Circuit Current Differential
IS
24
24
mA
mA
Complementary outputs
shorted
ISD
-24
16 Output enable time
17 Output disable time
tEN
3
cycles
cycles
fs
tDIS
3
110
63
144
81
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 625 MHz
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 625 MHz
Input clock: 100 MHz
Input clock: 156.25 MHz
Input clock: 625 MHz
18 Additive RMS jitter in 1MHz to 20MHz band
19 Additive RMS jitter in 12kHz to 20MHz band
Tj_1M_20M
Tj_12k_20M
NF
fs
21
33
fs
115
73
150
102
40
fs
fs
26
fs
-158
-158
-154
-156
-155
-151
dBc/Hz
dBc/Hz
dBc/Hz
20 Noise floor
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 42.
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October 2018
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© 2018 Microsemi Corporation
Data Sheet
ZL40235
Table 17 LVDS Outputs for VDDO = 2.5V*
Characteristics
Sym.
VLVDS_OH
VLVDS_OL
VLVDS_SW
∆VLVDS_SW
VCM
Min.
1.3
0.97
0.25
0
Typ.
1.4
Max.
1.5
Units
V
Notes
1
2
3
4
5
6
7
8
9
Output high voltage
Output low voltage
DC Measurement
DC Measurement
DC Measurement
1.05
0.35
0.001
1.23
0.001
1.13
0.44
0.01
1.3
V
Output differential swing**
V
Variation of VLVDS_SW for complementary output states
Common mode output
V
1.15
0
V
Variation of VCM for complementary output states
Output frequency when VLVDS_SW ≥ 250mV
Output frequency when VLVDS_SW ≥ 200mV
Rise or fall time (20% to 80%)
∆VCM
0.01
800
1600
170
1600
20
V
FMAX_0.25VSW
FMAX_0.2VSW
tr, tf
MHz
MHz
ps
110
10 Output frequency
FO
0
MHz
ps
11 Output to output skew
12 Device to device output skew
13 Input to output delay
tOOSK
tDOOSK
130
1.12
ps
tIOD
0.78
-24
0.86
ns
Single ended outputs
shorted to GND
14 Output Short Circuit Current Single Ended
15 Output Short Circuit Current Differential
IS
24
24
mA
mA
Complementary outputs
shorted
ISD
-24
16 Output enable time
17 Output disable time
tEN
3
cycles
cycles
fs
tDIS
3
107
62
140
77
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 625 MHz
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 625 MHz
Input clock: 100 MHz
Input clock: 156.25 MHz
Input clock: 625 MHz
18 Additive RMS jitter in 1MHz to 20MHz band
19 Additive RMS jitter in 12kHz to 20MHz band
Tj_1M_20M
Tj_12k_20M
NF
fs
20
31
fs
111
66
146
83
fs
fs
24
36
fs
-158
-159
-155
-156
-155
-151
dBc/Hz
dBc/Hz
dBc/Hz
20 Noise floor
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 42.
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© 2018 Microsemi Corporation
Data Sheet
ZL40235
Table 18 HCSL Outputs for VDDO = 3.3V*
Characteristics
Sym.
VHCSL_OH
VHCSL_OL
VHCSL_SW
∆VHCSL_SW
VCM
Min.
0.6
Typ.
0.85
0
Max.
1.1
Units
Notes
1
2
3
4
5
6
7
8
9
Output high voltage
Output low voltage
V
V
DC Measurement
DC Measurement
DC Measurement
-0.05
0.6
0.05
1.1
Output differential swing**
0.85
0.003
0.43
0.002
0.384
V
Variation of VHCSL_SW for complementary output states
Common mode output
0
0.05
0.55
0.05
0.447
0.127
400
309
21
V
0.28
0
V
Variation of VCM for complementary output states
Absolute Crossing Voltage
∆VCM
V
VCROSS
∆VCROSS
FMAX
0.320
V
Total Variation of VCROSS
V
Output frequency
0
MHz
ps
10 Rise or fall time (20% to 80%)
11 Output to output skew
12 Device to device output skew
13 Input to output delay
tr, tf
143
0.90
20
tOOSK
ps
tDOOSK
tIOD
129
1.08
3
ps
0.73
ns
14 Output enable time
tEN
cycles
cycles
15 Output disable time
tDIS
3
Additive Jitter as per PCIe 3.0 (PLL_BW = 2 to 5MHz,
40
16
TjPCIe_3.0
fs
Input clock: 100MHz
CDR = 10MHz)
73
53
104
69
fs
fs
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 100 MHz
Input clock: 156.25 MHz
17 Additive RMS jitter in 1MHz to 20MHz band
18 Additive RMS jitter in 12kHz to 20MHz band
Tj_1M_20M
77
112
100
-159
-155
fs
Tj_12k_20M
64
fs
-161
-159
dBc/Hz
dBc/Hz
19 Noise floor
NF
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 42.
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© 2018 Microsemi Corporation
Data Sheet
ZL40235
Table 19 HCSL Outputs for VDDO = 2.5V*
Characteristics
Sym.
VHCSL_OH
VHCSL_OL
VHCSL_SW
∆VHCSL_SW
VCM
Min.
0.6
Typ.
0.83
0
Max.
1.1
Units
Notes
1
2
3
4
5
6
7
8
9
Output high voltage
Output low voltage
V
V
DC Measurement
DC Measurement
DC Measurement
-0.05
0.5
0.05
1.1
Output differential swing**
0.83
0.003
0.42
0.002
0.316
V
Variation of VHCSL_SW for complementary output states
Common mode output
0
0.05
0.55
0.05
0.372
0.108
400
162
21
V
0.28
0
V
Variation of VCM for complementary output states
Absolute Crossing Voltage
∆VCM
V
VCROSS
∆VCROSS
FMAX
0.260
V
Total Variation of VCROSS
V
Output frequency
0
MHz
ps
10 Rise or fall time (20% to 80%)
11 Output to output skew
12 Device to device output skew
13 Input to output delay
tr, tf
125
0.92
20
tOOSK
ps
tDOOSK
tIOD
129
1.10
3
ps
0.76
ns
14 Output enable time
tEN
cycles
cycles
15 Output disable time
tDIS
3
Additive Jitter as per PCIe 3.0 (PLL_BW = 2 to 5MHz,
40
16
TjPCIe_3.0
fs
Input clock: 100MHz
CDR = 10MHz)
68
52
95
66
fs
fs
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 100 MHz
Input clock: 156.25MHz
Input clock: 100 MHz
Input clock: 156.25 MHz
17 Additive RMS jitter in 1MHz to 20MHz band
18 Additive RMS jitter in 12kHz to 20MHz band
Tj_1M_20M
72
102
71
fs
Tj_12k_20M
56
fs
-161
-160
-158
-153
dBc/Hz
dBc/Hz
19 Noise floor
NF
* Values are over Recommended Operating Conditions
**Output differential swing is calculated as VSW = VOH-VOL. It should not be confused with VSW = 2 * (VOH-VOL) used in some datasheets. Please refer to Figure 42.
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October 2018
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© 2018 Microsemi Corporation
Data Sheet
ZL40235
Table 20 LVCMOS Output Phase Noise with 25 MHz XTAL*
Characteristics
Min.
Typ.
103
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
1
Jitter RMS in 12kHz to 5MHz band
117
fs
VDD = 2.5V; VDDO = 2.5V
-75
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@5MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@5MHz, VDD = 2.5V; VDDO = 2.5V
-107
-132
-150
-162
-166
-166
-70
2
Noise floor
-102
-130
-149
-161
-165
-165
* Values are over Recommended Operating Conditions
Table 21 LVPECL Output Phase Noise with 25 MHz XTAL*
Characteristics
Min.
Typ.
265
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
1
Jitter RMS in 12kHz to 5MHz band
213
fs
VDD = 2.5V; VDDO = 2.5V
-75
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@5MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@5MHz, VDD = 2.5V; VDDO = 2.5V
-107
-133
-152
-157
-158
-157
-71
2
Noise floor
-103
-130
-151
-158
-160
-159
* Values are over Recommended Operating Conditions
ZL40235
October 2018
© 2018 Microsemi Corporation
40
Data Sheet
ZL40235
Table 22 LVDS Output Phase Noise with 25 MHz XTAL
Characteristics
Min.
Typ.
178
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
1
Jitter RMS in 12kHz to 5MHza band
190
fs
VDD = 2.5V; VDDO = 2.5V
-75
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@5MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@5MHz, VDD = 2.5V; VDDO = 2.5V
-107
-133
-154
-161
-161
-160
-68
2
Noise floor
-103
-130
-152
-161
-160
-159
* Values are over Recommended Operating Conditions
Table 23 HCSL Output Phase Noise with 25 MHz XTAL
Characteristics
Min.
Typ.
269
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
1
Jitter RMS in 12kHz to 20MHz band
228
fs
VDD = 2.5V; VDDO = 2.5V
-76
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@5MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@5MHz, VDD = 2.5V; VDDO = 2.5V
-107
-133
-152
-157
-157
-157
-73
2
Noise floor
-105
-131
-151
-158
-159
-159
* Values are over Recommended Operating Conditions
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© 2018 Microsemi Corporation
41
Data Sheet
ZL40235
Table 24 LVCMOS Output Phase Noise with 125 MHz XTAL*
Characteristics
Min.
Typ.
92
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
Jitter RMS in 12kHz to 20MHz
band
1
105
-58
fs
VDD = 2.5V; VDDO = 2.5V
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@10MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@10MHz, VDD = 2.5V; VDDO = 2.5V
-90
-118
-136
-150
-158
-159
-53
2
Noise floor
-86
-113
-134
-148
-157
-158
* Values are over Recommended Operating Conditions
Table 25 LVPECL Output Phase Noise with 125 MHz XTAL*
Characteristics
Min.
Typ.
76
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
Jitter RMS in 12kHz to 20MHz
band
1
86
fs
VDD = 2.5V; VDDO = 2.5V
-58
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@10MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@10MHz, VDD = 2.5V; VDDO = 2.5V
-90
-118
-140
-154
-159
-161
-54
2
Noise floor
-86
-114
-137
-152
-158
-160
* Values are over Recommended Operating Conditions
ZL40235
October 2018
© 2018 Microsemi Corporation
42
Data Sheet
ZL40235
Table 26 LVDS Output Phase Noise with 125 MHz XTAL
Characteristics
Min.
Typ.
98
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
Jitter RMS in 12kHz to 20MHz
band
1
100
-57
fs
VDD = 2.5V; VDDO = 2.5V
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@10MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@10MHz, VDD = 2.5V; VDDO = 2.5V
-90
-118
-140
-152
-157
-158
-54
2
Noise floor
-86
-114
-137
-153
-157
-158
* Values are over Recommended Operating Conditions
Table 27 HCSL Output Phase Noise with 125 MHz XTAL
Characteristics
Min.
Typ.
83
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
Jitter RMS in 12kHz to 20MHz
band
1
85
fs
VDD = 2.5V; VDDO = 2.5V
-58
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@10MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@10MHz, VDD = 2.5V; VDDO = 2.5V
-90
-118
-140
-152
-158
-160
-54
2
Noise floor
-86
-114
-137
-153
-158
-159
* Values are over Recommended Operating Conditions
ZL40235
October 2018
© 2018 Microsemi Corporation
43
Data Sheet
ZL40235
Table 28 LVCMOS Output Phase Noise with 156.25 MHz XTAL*
Characteristics
Min.
Typ.
79
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
Jitter RMS in 12kHz to 20MHz
band
1
88
fs
VDD = 2.5V; VDDO = 2.5V
-53
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@10MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@10MHz, VDD = 2.5V; VDDO = 2.5V
-81
-111
-135
-149
-157
-159
-53
2
Noise floor
-82
-113
-135
-148
-156
-158
* Values are over Recommended Operating Conditions
Table 29 LVPECL Output Phase Noise with 156.25 MHz XTAL*
Characteristics
Min.
Typ.
61
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
Jitter RMS in 12kHz to 20MHz
band
1
68
fs
VDD = 2.5V; VDDO = 2.5V
-52
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@10MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@10MHz, VDD = 2.5V; VDDO = 2.5V
-80
-111
-140
-153
-159
-161
-53
2
Noise floor
-81
-114
-140
-151
-158
-160
* Values are over Recommended Operating Conditions
ZL40235
October 2018
© 2018 Microsemi Corporation
44
Data Sheet
ZL40235
Table 30 LVDS Output Phase Noise with 156.25 MHz XTAL
Characteristics
Min.
Typ.
79
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
Jitter RMS in 12kHz to 20MHz
band
1
76
fs
VDD = 2.5V; VDDO = 2.5V
-52
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@10MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@10MHz, VDD = 2.5V; VDDO = 2.5V
-81
-111
-138
-148
-157
-159
-52
2
Noise floor
-82
-113
-140
-151
-157
-159
* Values are over Recommended Operating Conditions
Table 31 HCSL Output Phase Noise with 156.25 MHz XTAL
Characteristics
Min.
Typ.
72
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
Jitter RMS in 12kHz to 20MHz
band
1
72
fs
VDD = 2.5V; VDDO = 2.5V
-53
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@10MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@10MHz, VDD = 2.5V; VDDO = 2.5V
-86
-114
-139
-148
-157
-160
-53
2
Noise floor
-86
-115
-140
-151
-157
-160
* Values are over Recommended Operating Conditions
ZL40235
October 2018
© 2018 Microsemi Corporation
45
Data Sheet
ZL40235
Table 32 AC Electrical Characteristics* - SPI (Serial Peripheral Interface) Timing
Characteristics
Sym.
tcyc
Min.
124
62
Typ.
Max.
Units
ns
Notes
1
2
sck period
sck pulse width low
sck pulse width high
tclkl
ns
3
tclkh
trxs
62
ns
See
Figure 43&
Figure 44
4
si setup (write) from sck rising edge
si hold (write) from sck falling edge
10
ns
5
trxh
10
ns
6
so delay (read) from sck falling edge
cs_b to output high impedance
txd
25
60
ns
7
tohz
tcssi
tcshi
tcssm
tcshm
ns
8
cs_b setup from sck falling edge (LSB first)
cs_b hold from sck falling edge (LSB first)
cs_b setup from sck falling edge (MSB first)
cs_b hold from sck falling edge (MSB first)
20
10
20
10
ns
See Figure 43
See Figure 44
9
ns
10
11
ns
ns
* Values are over Recommended Operating Conditions
* For LSB first mode timing diagram, refer to Figure 43
* For MSB first mode timing diagram, refer to Figure 44
* Values shown are proposed for the data sheet, these values are to be confirmed
si
txrs
txrh
sck
cs_b
so
tcssi
tclkh
tclkl
tcyc
tcshi
txd
tohz
Figure 43.
SPI (Serial Peripheral Interface) Timing - LSB First Mode
si
sck
txrs
txrh
tcssm
tclkh
tclkl
tcyc
tcshm
cs_b
so
txd
tohz
Figure 44.
SPI (Serial Peripheral Interface) Timing - MSB First Mode
ZL40235
October 2018
© 2018 Microsemi Corporation
46
Data Sheet
ZL40235
Table 33 6x6mm QFN Package Thermal Properties
Parameter
Maximum Ambient Temperature
Symbol
Condition
Value
Units
TA
TJMAX
85
C
C
Maximum Junction Temperature
125
22.2
17.6
15.8
7.2
still air
1m/s airflow
2.5m/s airflow
Junction to Ambient Thermal Resistance(1) (Note 1)
JA
C/W
Junction to Board Thermal Resistance
Junction to Case Thermal Resistance
Junction to Pad Thermal Resistance(2)
JB
JC
JP
C/W
C/W
C/W
14.3
3.9
Still air
Still air
Junction to Top-Center Thermal Characterization Parameter
0.2
C/W
JT
(1)
(2)
Theta-JA (JA) is the thermal resistance from junction to ambient when the package is mounted on an 4-layer JEDEC standard test board and dissipating
maximum power
Theta-JP (JP) is the thermal resistance from junction to the center exposed pad on the bottom of the package)
ZL40235
October 2018
47
© 2018 Microsemi Corporation
Data Sheet
ZL40235
Change History
June 2017 was the first release of the document.
July 2017 release changes:
•
Modified power calculation in the Power Consumption section.
August 2017 release changes:
•
•
•
Modified “Input driven by HCSL output” figure.
Modified additive jitter for 156.25MHz input clock.
Added Figure 41 and Figure 42.
October 2018 release changes:
•
•
•
Added note in pinout to tie XIN pin when crystal circuit is not used
Removed Figures 13, 15 and 16 due to inaccuracy
Fixed typo in Table 3
ZL40235
October 2018
© 2018 Microsemi Corporation
48
Data Sheet
ZL40235
Package Outline
ZL40235
October 2018
© 2018 Microsemi Corporation
49
Data Sheet
ZL40235
Microsemi Corporation, a wholly owned subsidiary Microchip Technology Inc. (Nasdaq:
MCHP), offers a comprehensive portfolio of semiconductor and system solutions for
communications, defense & security, aerospace and industrial markets. Products include
high-performance and radiation-hardened analog mixed-signal integrated circuits, FPGAs,
SoCs and ASICs; power management products; timing and synchronization devices and
precise time solutions, setting the world's standard for time; voice processing devices; RF
solutions; discrete components; enterprise storage and communication solutions, security
technologies and scalable anti-tamper products; Ethernet solutions; Power-over-Ethernet ICs
and midspans; as well as custom design capabilities and services. Microsemi is
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Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
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ZL40235
October 2018
50
© 2018 Microsemi Corporation
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