ZL40241LDF1 [MICROSEMI]
Low Skew Clock Driver,;
| 型号： | ZL40241LDF1 |
| 厂家： | 
Microsemi |
| 描述： | Low Skew Clock Driver, 驱动 逻辑集成电路 |
| 文件： | 总23页 (文件大小：764K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
ZL40241
Ten LVCMOS Output Low Additive Jitter Fanout Buffer
Ordering Information
Features
ZL40241LDG1
ZL40241LDF1
32 Pin QFN
32 pin QFN
Trays
Tape and Reel
3 to 1 input Multiplexer: Two inputs accept any
differential (LVPECL, HCSL, LVDS, SSTL, CML,
LVCMOS) or a single ended signal and the third
input accepts a crystal or a single ended signal
Package size: 5 x 5 mm
-40 C to +85 C
Ten 1.5V/1.8V/2.5V/3.3V LVCMOS outputs
Supports frequencies from 0 to 200MHz
Supports crystals from 8MHz to 60MHz
Ultra-low additive jitter: 17fs (12kHz to 20MHz)
Ultra-low noise floor of -170dBc/Hz
Applications
General purpose clock distribution
Low jitter clock trees
Logic translation
Clock and data signal restoration
Wired and Wireless communications
High performance microprocessor clock distribution
Medical Imaging
Supports 2.5V or 3.3V power supplies
Output to output skew of 30ps (typical)
Input to output delay of 2ns (typical)
Test equipment
ZL40241
OUT0
Synchronous OE
OE
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
SEL0
SEL1
IN0_p
IN0_n
00
IN1_p
IN1_n
01
10
11
XOUT
XIN
Figure 1. Functional Block Diagram
ZL40241
Confidential
1
February 2017
© 2017 Microsemi Corporation
Data Sheet
ZL40241
Table of Contents
Features.....................................................................................................................................1
Table of Contents ......................................................................................................................2
Pin Diagram ...............................................................................................................................5
Pin Descriptions.........................................................................................................................6
Functional Description ...............................................................................................................8
Clock Inputs ...............................................................................................................................8
Clock Outputs ..........................................................................................................................11
Crystal Oscillator Input.............................................................................................................11
Termination of unused inputs and outputs ..............................................................................12
Power Consumption ................................................................................................................13
Power Supply Filtering.............................................................................................................15
Device Control .........................................................................................................................15
AC and DC Electrical Characteristics......................................................................................17
Absolute Maximum Ratings.....................................................................................................17
Recommended Operating Conditions .....................................................................................17
Package Outline ......................................................................................................................22
ZL40241
Confidential
2
February 2017
© 2017 Microsemi Corporation
Data Sheet
ZL40241
List of Figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Functional Block Diagram........................................................................................................................................... 1
Pin Diagram ................................................................................................................................................................ 5
Input driven by a single ended output ........................................................................................................................ 8
Input driven by DC coupled LVPEVCL output .............................................................................................................. 8
Input driven by DC coupled LVPEVCL output (alternative termination)...................................................................... 9
Input driven by AC coupled LVPECL output................................................................................................................. 9
Input driven by HCSL output ....................................................................................................................................... 9
Input driven by LVDS output ..................................................................................................................................... 10
Input driven by AC coupled LVDS .............................................................................................................................. 10
Input driven by an SSTL output ................................................................................................................................. 10
Termination for 3.3V LVPECL outputs....................................................................................................................... 11
Crystal Oscillator Circuit............................................................................................................................................ 11
Phase Noise Plot with 25MHz Crystal ....................................................................................................................... 12
Device power consumption per output for VDD = VDDO = 3.465V............................................................................... 13
Device power consumption per output for VDD = VDDO = 2.625V............................................................................... 14
Dynamic supply current per output for different output supply voltages ................................................................ 14
Power Supply Filtering .............................................................................................................................................. 15
OE Output Disable .................................................................................................................................................... 15
OE Output Enable ..................................................................................................................................................... 16
ZL40241
Confidential
3
February 2017
© 2017 Microsemi Corporation
Data Sheet
ZL40241
List of Tables
Table 1 · Pin Descriptions............................................................................................................................................................................... 6
Table 2 · Absolute Maximum Ratings*......................................................................................................................................................... 17
Table 3 · Recommended Operating Conditions* .......................................................................................................................................... 17
Table 4 · Current consumption ..................................................................................................................................................................... 17
Table 5 · Input Characteristics* .................................................................................................................................................................... 18
Table 6 · Crystal Oscillator Characteristics* ................................................................................................................................................. 18
Table 7 · LVCMOS Output Characteristics* .................................................................................................................................................. 19
Table 8 · LVCMOS Output Additive Jitter and Phase Noise*......................................................................................................................... 20
Table 9 · LVCMOS Output Jitter Phase Noise with 25MHz XTAL*................................................................................................................. 21
Table 10 · 5x5mm QFN Package Thermal Properties ................................................................................................................................... 21
ZL40241
Confidential
4
February 2017
© 2017 Microsemi Corporation
Preliminary Data Sheet
ZL40241
Pin Diagram
The device is packaged in a 5x5mm 32-pin QFN.
Pin#1
Corner
32
31
30
29
28
27
26
25
24
1
2
OUT9
VDDO
OUT0
VDDO
23
22
OUT1
GND
OUT8
GND
3
21
4
5
6
Exposed GND Pad 3.10 x 3.10 mm
OUT2
OUT7
VDDO
OUT6
OUT5
20
19
VDDO
OUT3
OUT4
7
8
18
17
9
10
11
12
13
14
15
16
Figure 2. Pin Diagram
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
5
Preliminary Data Sheet
ZL40241
Pin Descriptions
All device inputs and outputs are LVPECL unless described otherwise. The I/O column uses the following symbols: I
– input, IPU – input with 300k internal pull-up resistor, IPD – input with 300k internal pull-down resistor, IAPU – input
with 30k internal pull-up resistor, IAPD – input with 30k internal pull-down resistor, IAPU/APD – input biased at VDD/2
with 60k internal pull-up and 60k pull-down resistors, O – output, I/O – Input/Output pin, P – power supply pin.
Table 1 · Pin Descriptions
#
Name
I/O
Description
Input Reference
IAPD
IAPU/APD
IAPD
IN0_p
IN0_n
IN1_p
IN1_n
Input Differential or Single Ended References 0 and 1
13
14
28
27
Input frequency range 0Hz to 200MHz.
IAPU/APD
Non inverting inputs (_p) are pulled down with internal 30k pull-down resistors.
Inverting inputs (_n) are biased at VDD/2 with 60k pull-up and pull-down resistors
to keep inverting input voltages at VDD/2 when inverting inputs are left floating
(device fed with a single ended reference).
Output Clocks
Ultra Low Additive Jitter LVCMOS Outputs 0 to 9
O
1
3
5
7
8
17
18
20
22
24
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
OUT8
OUT9
Output frequency range 0 to 200MHz
Control
IPD
30
29
IN_SEL0
IN_SEL1
Input select pins. Logic level on these pins selects which input will be passed to
the output.
IN_SEL1 IN_SEL0
OUTN
Input 0 (IN0)
0
0
1
1
0
1
0
1
Input 1 (IN1)
Crystal Oscillator or overdrive
Crystal Bypass
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
6
Preliminary Data Sheet
ZL40241
IPD
31
OE
Output Enable When high outputs are enabled. When low outputs are high-Z.
Crystal Oscillator
11
XIN
I
Crystal Oscillator Input or crystal bypass mode or crystal overdrive mode
Crystal Oscillator Output
12
XOUT
O
Power and Ground
Positive Supply Voltage. Connect to 3.3V or 2.5V supply. VDD voltage must be
higher or equal to VDDO.
10
VDD
P
P
Positive Supply Voltage for LVCMOS Outputs Connect 3.3V, 2.5V, 1.8V or 1.5V
power supply
2
6
19
23
VDDO
GND
Ground Connect to ground
4
P
9
15
16
21
25
26
32
Ground. Connect to ground
E-Pad
GND
P
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
7
Preliminary Data Sheet
ZL40241
Functional Description
The ZL40241 is a pin controlled low additive jitter, low power 3 x 10 LVCMOS fanout buffer.
Two inputs can accept signal in differential (LVPECL, SSTL, LVDS, HSTL, CML ) or single ended (LVPECL or
LVCMOS) format and the third input can accept a single ended signal or it can be used to build a crystal oscillator by
connecting an external crystal resonator between its XIN and XOUT pins. .
The ZL40241 has ten LVCMOS outputs which can be powered from 3.3V, 2.5V, 1.8V or 1.5V supply. Output can be
synchronously enabled/disabled via OE pin.
The device operates from 2.5V+/-5% or 3.3V+/-5% supply. Its operation is guaranteed over the industrial temperature
range -40°C to +85°C.
Clock Inputs
The following blocks diagram shows how to terminate different signals fed to the ZL40241 inputs.
Figure 3 shows how to terminate a single ended output such as LVCMOS. Ideally, resistors R1 and R2 should be
100 each so that the transmission line is terminated with matched impedance (50). However, if the driving
strength of the output driver is not sufficient resistor values should be increased
VDD
VDD
VDD
VDD
1 k Ω
R1
Rs
Ro
Z0 = 50 Ω
Ro + Rs = Z0
R2
1 kΩ
MSCC Device
0.1 µF
Figure 3. Input driven by a single ended output
VDD
VDD
VDD
VDD
RUP
RUP
Z0 = 50 Ω
Z0 = 50 Ω
LVPECL
RDWN
RDWN
MSCC Device
VDD
3.3V
2.5V 250 Ω
RUP
125 Ω
RDWN
84 Ω
62.5 Ω
Figure 4. Input driven by DC coupled LVPEVCL output
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
8
Preliminary Data Sheet
ZL40241
VDD
VDD
Z0 = 50 Ω
Z0 = 50 Ω
LVPECL
LVPECL
50 Ω
50 Ω
MSCC Device
50 Ω
Figure 5. Input driven by DC coupled LVPEVCL output (alternative termination)
VDD
VDD
VDD
100 Ω
VDD
100 Ω
10 nF
10 nF
Z0 = 50 Ω
Z0 = 50 Ω
LVPECL
200 Ω
200 Ω
100 Ω 100 Ω
MSCC Device
Figure 6. Input driven by AC coupled LVPECL output
VDD
VDD
33 Ω
33 Ω
Z0 = 50 Ω
Z0 = 50 Ω
HCSL
50 Ω
50 Ω
MSCC Device
Figure 7. Input driven by HCSL output
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
9
Preliminary Data Sheet
ZL40241
VDD
MSCC Device
VDD
Z0 = 50 Ω
Z0 = 50 Ω
100 Ω
LVDS
Figure 8. Input driven by LVDS output
VDD
VDD
10 K Ω
10 nF
VDD
10 KΩ
VDD
Z0 = 50 Ω
Z0 = 50 Ω
100 Ω
LVDS
10 nF
10K Ω
MSCC Device
10 KΩ
Figure 9. Input driven by AC coupled LVDS
VDD
VDD
VDD
120 Ω
120 Ω
VDD
Z0 = 60 Ω
Z0 = 60 Ω
SSTL
120 Ω 120 Ω
MSCC Device
Input driven by SSTL driver
Figure 10.
Input driven by an SSTL output
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
10
Preliminary Data Sheet
ZL40241
Clock Outputs
LVCMOS outputs require only series termination resistor whose value is depending on LVCMOS output voltage as
shown in Figure 11.
VDDO
3.3V
2.5V
1.8V
1.5V
Rs
VDDO
33Ω
30Ω
20Ω
10Ω
VDD = VDDO
Rs
LVCMOS
Z0 = 50 Ω
MSCC Device
Figure 11.
Termination for 3.3V LVPECL outputs
Crystal Oscillator Input
The crystal oscillator circuit can work with crystal resonators from 8MHz to 60MHz. Load capacitors C1 and C2 shall
be selected as per crystal vendor recommendation. Shunt resistor is implemented inside the device.
C1
XIN
Crystal
XOUT
C2
Load capacitors C1 and C2
should be as per crystal
specification
MSCC Device
Figure 12.
Crystal Oscillator Circuit
The phase noise plot for 25MHz crystal is shown in Figure 13. The phase noise floor of the device is
below -170dBc/Hz as can be seen on the figure.
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
11
Preliminary Data Sheet
ZL40241
Figure 13.
Phase Noise Plot with 25MHz Crystal
Termination of unused inputs and outputs
Unused inputs can be left unconnected or alternatively IN_0/1 can be pulled-down by 1kΩ resistor. Unused outputs
should be left unconnected.
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
12
Preliminary Data Sheet
ZL40241
Power Consumption
The total device power consumption can be calculated as:
P P PXTAL P P
T
S
C
D
Where:
is static power consumed by input buffers. If
XTAL is running this power should be set to
zero. where the static current (IS) is specified
in Table 4 ·
P VDD IS
S
is power consumption of XTAL circuit. The
current of the XTAL circuit is provided in
Table 4 · If XTAL is not used the power
consumption is equal to zero.
P
VDD I DD _ XTAL
XTAL
Common output power shared among all ten
outputs. The current (IDDC is specified in
Table 4 · ,
P VDDO I DDC
C
P VDDO (IDD n f /100MHzVDDO CLOAD f n)
Dynamic power where dynamic current (IDD
)
D
is specified in Table 4 · , CLOAD is capacitive
load driven by an output, f is frequency of the
output clock and n is number of active
outputs.
The power consumption for different clock frequencies and power supply voltages can be quickly estimated from
Figure 14, Figure 15 and Figure 15.
45.0
CL=2 pF, P_avg (mW)
40.0
CL = 8 pF, P_avg (mW)
35.0
30.0
25.0
20.0
15.0
10.0
5.0
0
20
40
60
80 100 120 140 160 180 200
Freq (MHz)
Figure 14.
Device power consumption per output for VDD = VDDO = 3.465V
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
13
Preliminary Data Sheet
ZL40241
25.0
20.0
15.0
10.0
5.0
CL=2 pF, P_avg (mW)
CL = 8 pF, P_avg (mW)
0.0
0
20
40
60
80 100 120 140 160 180 200
Freq (MHz)
Figure 15.
Device power consumption per output for VDD = VDDO = 2.625V
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
VDDO=3.465 V
VDDO=2.625 V
VDDO=2.00 V
VDDO=1.65 V
0.0
0
20
40
60
80
100
120
140
160
180
200
Frequency (MHz)
Figure 16.
Dynamic supply current per output for different output supply voltages
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
14
Preliminary Data Sheet
ZL40241
Power Supply Filtering
Each power pin (VDD and VDDO) should be decoupled with 0.1µF capacitor with minimum equivalent series
resistance (ESR) and minimum series inductance (ESL). For example 0402 X5R Ceramic Capacitors with 6.3V
minimum rating could be used. These capacitors should be placed as close as possible to the power pins. To reduce
the power noise from adjacent digital components on the board each power supply could be further insulted with low
resistance ferrite bead with two capacitors. The ferrite bead will also insulate adjacent component from the noise
generated from the device. Following figure shows recommended decoupling for each power pin.
Board Supply
10uF
Ferrite Bead
1uF
VDD or VDDO
0.1uF
Figure 17.
Power Supply Filtering
Device Control
ZL40241 is controlled via Output Enable (OE) and Input Select (SEL0/1) input pins. Output is disabled synchronously
on the falling edge of the input (t2) as shown in Figure 18.
INX_n
INX_p
INX_p - INX_n
OE
OUT[9:0]
t1
t2
Figure 18.
OE Output Disable
Outputs can be enabled by toggling OE pin high. As soon as OE pin goes high (t1) the outputs will go from high-Z to
low and will start to track the input after the first falling edge (t2) of the input signal as shown in Figure 19.
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
15
Preliminary Data Sheet
ZL40241
INX_n
INX_p
INX_p - INX_n
OE
OUT[9:0]
t1
t2
Figure 19.
OE Output Enable
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
16
Preliminary Data Sheet
ZL40241
AC and DC Electrical Characteristics
Absolute Maximum Ratings
Table 2 · Absolute Maximum Ratings*
Parameter
Sym.
VDD /VDDO
VDD /VDDO
VDDO
Min.
-0.5
-0.5
-0.5
-0.5
-55
Typ.
Max.
4.6
Units
Notes
1
2
3
4
5
Supply voltage (3.3V)
Supply voltage (2.5V)
Supply voltage (1.8V)
Supply voltage (1.5V)
Storage temperature
V
V
4.6
2.5
V
VDDO
2.0
V
TST
125
°C
* Exceeding these values may cause permanent damage
* Functional operation under these conditions is not implied
* Voltages are with respect to ground (GND) unless otherwise stated
Recommended Operating Conditions
Table 3 · Recommended Operating Conditions*
Characteristics
Sym.
VDD /VDDO
VDD /VDDO
VDDO
Min.
3.135
2.375
1.6
Typ.
3.30
2.50
1.8V
1.5
Max.
3.465
2.625
2
Units
Notes
1
2
3
4
5
6
Supply voltage 3.3V
Supply voltage 2.5V
Supply voltage 1.8V
Supply voltage 1.5V
V
V
V
VDDO
1.35
-40
1.65
Operating temperature
Input voltage
TA
25
85
°C
V
VDD-IN
- 0.3
VDD + 0.3
* Voltages are with respect to ground (GND) unless otherwise stated
* The device supports two power supply modes (3.3V and 2.5V)
Table 4 · Current consumption
Characteristics
Static device current
Sym.
Is_3.3V
Min.
Typ.
15
Max.
18
Units
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Notes
VDD= 3.465V
VDD = 2.625V
VDD= 3.465V
VDD= 2.625V
VDDO= 3.465V
VDDO= 2.625V
VDDO= 2V
1
2
Is_2.5V
12
15
IDD_XTAL_3.3V
IDD_XTAL_2.5V
IDD_3.3V
24
27
Device current with 25MHz XTAL input
18
20
4.2
3.0
2.1
1.6
2.3
1.7
1.2
0.9
3.8
1.9
1.2
1
4.7
3.5
2.4
1.8
3.0
1.8
1.3
1.0
8.0
3.3
1.7
1.4
Dynamic current per output (f = 100MHz) (1)(2)
Needs to be scaled for different frequencies by
f/100MHz, Driving Strength = 1 (registers 0x09, 0x0A)
IDD_2.5V
3
4
5
IDD_1.8V
IDD_1.5V
VDDO= 1.65V
VDDO= 3.465V
VDDO= 2.625V
VDDO= 2V
IDD_3.3V
Dynamic current per output (f = 100MHz) (1)(2)
Needs to be scaled for different frequencies by
f/100MHz, Driving Strength = 0 (registers 0x09, 0x0A)
IDD_2.5V
IDD_1.8V
IDD_1.5V
VDDO= 1.65V
VDDO= 3.465V
VDDO= 2.625V
VDDO= 2V
IDDC_3.3V
IDDC_2.5V
IDDC_1.8V
IDDC_1.5V
Common output current(3)
VDDO= 1.65V
(1)
(2)
Needs to be scaled for different frequencies by f/100MHz
To calculate total power consumption use following formula: P = (Is + IDD_XTAL ) * VDD + (IDDC + IDD * n * f/100MHz + VDDO * CLOAD * f * n) * VDDO, where
IDD_XTAL: should be set to zero if XTAL is not used or Is should be set to zero if XTAL is used.
n: number of active outputs
f: frequency of the clock
CLOAD: is capacitive load driven by an output.
(3)
This current is consumed by device whenever one or more outputs are enabled. It is independent of the number of active outputs
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
17
Preliminary Data Sheet
ZL40241
Table 5 · Input Characteristics*
Characteristics
Sym.
VCIH
VCIL
IIL
Min.
Typ.
Max.
Units
Notes
1
2
3
CMOS high-level input voltage for SEL0/1 and OE
CMOS low-level input voltage for SEL0/1 and OE
CMOS input leakage current for SEL0/1 and OE(1)
Differential input common mode voltage for IN0_p/n and IN1_p/n
1.20
V
V
0.45
10
-40
0.5
µA
V
VI = VDD or 0 V
VCM
VDD –
0.85
4
5
6
Differential input voltage difference for IN0_p/n and IN1_p/n
Differential input leakage current for IN0_p/n and IN1_p/n(2)
VID
IIL
0.15
-200
2
1.3
V
µA
V
100
VI = VDD or 0 V
VSIH
VDD +
0.3V
VDD = 3.3V+/-
5%
7
Single ended input high voltage for IN_0_p and IN_1_p
VSIH
VSIL
VSIL
1.6
-0.3
-0.3
VDD +
0.3V
V
V
VDD = 2.5V+/-
5%
1.3
0.9
VDD = 3.3V+/-
5%
8
9
Single ended input high voltage for IN_0_p and IN_1_p
Input frequency
V
VDD = 2.5V+/-
5%
fIN
0
200
MHz
dc
35%
65%
@200MHz; for
lower
frequencies
duty cycle can
be scaled
10 Input duty cycle
proportionally
11 Input slew rate
slew
2
V/ns
12
13
Input pull-up/ pull-down resistance (INx_n)
Input pull-down resistance (INx_p)
RPU/RPD
RPD
60kΩ
30kΩ
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
(1) CMOS input leakage is due to 300kΩ pull-up/pull-down resistors
(2) Differential Input leakage is due to 60kΩ pull-up/pull-down resistors INx_n and due to 30kΩ pull-down resistor for INx_p
Table 6 · Crystal Oscillator Characteristics*
Characteristics
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
3
4
Mode of oscillation
Frequency
mode
Fundamental
f
8
60
MHz
MΩ
pF
On chip shunt resistor
On chip capacitance
R
C
0.5
12
Functional but
may not meet AC
parameters
Minimum depends
on AC coupling
Capacitor (0.1uF
assumed)
5
6
Frequency in overdrive mode(1)
Frequency in bypass mode(2)
fOV
0.1
200
200
MHz
MHz
Functional but
may not meet AC
parameters
fBP
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
(1)
(2)
Maximum input level is 2V
Maximum output level is VDD
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
18
Preliminary Data Sheet
ZL40241
Table 7 · LVCMOS Output Characteristics*
Characteristics
Sym.
VOH
VOH
VOH
VOH
VOL
VOL
VOL
VOL
RO
Min.
Typ.
Max.
Units
V
Notes
0.8*VDDO
0.8*VDDO
0.7*VDDO
0.7*VDDO
VDDO = 3.3V±5%
VDDO = 2.5V±5%
VDDO = 1.8V±10%
VDDO = 1.5V±10%
VDDO = 3.3V±5%
VDDO = 2.5V±5%
VDDO = 1.8V±10%
VDDO = 1.5V±10%
VDDO = 3.3V
V
1
2
3
4
Output high voltage
V
V
0.2*VDDO
0.2*VDDO
0.3*VDDO
0.3*VDDO
V
V
Output low voltage
V
V
17
21
Ω
RO
Ω
VDDO = 2.5V
Output impedance
RO
30
Ω
VDDO = 1.8V
RO
42
Ω
VDDO = 1.5V
tr, tf
tr, tf
tr, tf
tr, tf
FO
3.19
1.72
1.64
1.20
0
5.14
3.74
2.52
1.96
6.33
4.61
3.32
2.54
200
V/ns
V/ns
V/ns
V/ns
MHz
VDDO = 3.3V±5%
VDDO = 2.5V±5%
VDDO = 1.8V±10%
VDDO = 1.5V±10%
Output slew rate-- rise or fall (20% to 80%)
5
6
7
8
9
Output frequency
Output Duty Cycle
50.26%
53.18%
2
Input. duty-cycle 50%
Output enable or disable time
Output to output skew
Device to device output skew
Cycle
ps
tOOSK
tDOOSK
tIOD
27
1.6
ns
1.15
1.57
75
2.09
2.27
2.54
2.77
ns
VDD = 3.3V
VDD = 2.5V
10 Input to output delay
tIOD
ns
11 Input multiplexer isolation
iso
dB
tested with 125MHz clocks
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
* Load 50 Ohm to VDDO/2
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
19
Preliminary Data Sheet
ZL40241
Table 8 · LVCMOS Output Additive Jitter and Phase Noise*
Characteristics
Min.
Typ.
Max.
Units
Notes
VDD = 3.3V, VDDO = 3.3V
fin = 125MHz, single ended input
17
fs-RMS
VDD = 2.5V, VDDO = 1.5V to 2.5V
fin = 125MHz, single ended input
31
fs-RMS
fs-RMS
fs-RMS
fs-RMS
fs-RMS
fs-RMS
fs-RMS
1
System level additive jitter(1)
VDD = 3.3V, VDDO = 3.3V
fin = 125MHz, differential input
22
VDD = 2.5V, VDDO = 1.5V to 2.5V
fin = 125MHz, differential input
37
VDD = 3.3V, VDDO = 3.3V
fin = 125MHz, single ended input
45.18
80.46
39.95
67.18
93.11
126.92
68.98
VDD = 2.5V, VDDO = 1.5V to 2.5V
fin = 125MHz, single ended input
2
Additive jitter(2) (3)
VDD = 3.3V, VDDO = 3.3V
fin = 125MHz, differential input
VDD = 2.5V, VDDO = 1.5V to 2.5V
fin = 125MHz, differential input
117.26
-145.08
-152.46
-160.67
-162.66
-162.71
-145.34
-152.60
-161.06
-163.22
-163.38
-139.93
-147.22
-157.11
-160.58
-160.78
-141.69
-149.19
-158.66
-161.60
-161.85
-138.67
-145.82
-155.66
-160.55
-160.19
-137.83
-146.93
-156.99
-160.84
-161.42
-134.59
-144.21
-154.78
-158.21
-158.19
-134.26
-144.73
-156.22
-159.32
-159.36
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10kHz, fin = 125MHz, single ended input
@100kHz, fin = 125MHz, single ended input
@1MHz, fin = 125MHz, single ended input
@10MHz, fin = 125MHz, single ended input
@20MHz, fin = 125MHz, single ended input
@10kHz, fin = 125MHz, differential input
@100kHz, fin = 125MHz, differential input
@1MHz, fin = 125MHz, differential input
@10MHz, fin = 125MHz, differential input
@20MHz, fin = 125MHz, differential input
@10kHz, fin = 125MHz, single ended input
@100kHz, fin = 125MHz, single ended input
@1MHz, fin = 125MHz, single ended input
@10MHz, fin = 125MHz, single ended input
@20MHz, fin = 125MHz, single ended input
@10kHz, fin = 125MHz, differential input
@100kHz, fin = 125MHz, differential input
@1MHz, fin = 125MHz, differential input
@10MHz, fin = 125MHz, differential input
@20MHz, fin = 125MHz, differential input
Phase Noise floor
3
(VDD = 3.3V, VDDO = 3.3V)
Phase Noise floor
(VDD = 2.5V, VDDO = 2.5V)
4
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
(1)
(2)
System level additive jitter is calculated as JRMS_SYS_AJ = JRMS_OUT - JRMS_IN
Additive jitter is calculated as JRMS__AJ = sqrt (JRMS_OUT2 - JRMS_IN2) where jitter is integrated in 12 kHz to 20 MHz band
Tester measures jitter at 156.25MHz. Since this freq won’t appear in the data sheet, it should be removed from the PPGT. Data sheet jitter is guaranteed by lab
char. The ATE jitter measurement will be used to screen outliers only, with limits based on ATE distribution
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
20
Preliminary Data Sheet
ZL40241
Table 9 · LVCMOS Output Jitter Phase Noise with 25MHz XTAL*
Characteristics
Min.
Typ.
Max.
Units
fs
Notes
VDD = 3.3V, VDDO = 3.3V
72.63
Jitter RMS in 12kHz to 20MHz
band
1
fs
VDD = 2.5V; VDDO = 2.5V
87.59
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
@10Hz , VDD = 3.3V, VDDO = 3.3V
@100Hz, VDD = 3.3V, VDDO = 3.3V
@1kHz, VDD = 3.3V, VDDO = 3.3V
@10kHz, VDD = 3.3V, VDDO = 3.3V
@100kHz, VDD = 3.3V, VDDO = 3.3V
@1MHz, VDD = 3.3V, VDDO = 3.3V
@5MHz, VDD = 3.3V, VDDO = 3.3V
@10Hz, VDD = 2.5V; VDDO = 2.5V
@100Hz, VDD = 2.5V; VDDO = 2.5V
@1kHz, VDD = 2.5V; VDDO = 2.5V
@10kHz, VDD = 2.5V; VDDO = 2.5V
@100kHz, VDD = 2.5V; VDDO = 2.5V
@1MHz, VDD = 2.5V; VDDO = 2.5V
@5MHz, VDD = 2.5V; VDDO = 2.5V
-75.96
-107.50
-132.34
-157.36
-165.82
-168.85
-168.88
-70.52
2
Phase Noise floor
-102.60
-129.14
-153.93
-164.00
-167.34
-167.41
* Values are over Recommended Operating Conditions
* Values are over all two power supply modes (VDD = 3.3V and VDD = 2.5V)
* Xtal frequency is 25 MHz
Table 10 · 5x5mm QFN Package Thermal Properties
Parameter
Symbol
Conditions
Value
Units
TA
TJMAX
Maximum Ambient Temperature
Maximum Junction Temperature
85
C
C
125
26.8
21.8
19.9
10.8
19.5
6.5
still air
1m/s airflow
2.5m/s airflow
Junction to Ambient Thermal Resistance(1) (Note 1)
JA
C/W
Junction to Board Thermal Resistance
Junction to Case Thermal Resistance
Junction to Pad Thermal Resistance(2)
JB
JC
JP
C/W
C/W
C/W
Still air
Still air
Junction to Top-Center Thermal Characterization
Parameter
0.6
C/W
JT
(1)
Theta-JA (JA) is the thermal resistance from junction to ambient when the package is mounted on an 4-layer JEDEC standard test board and dissipating
maximum power
(2)
Theta-JP (JP) is the thermal resistance from junction to the center exposed pad on the bottom of the package)
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
21
Preliminary Data Sheet
ZL40241
Package Outline
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
22
Preliminary Data Sheet
ZL40241
Microsemi Corporation (Nasdaq: MSCC) offers a comprehensive portfolio of semiconductor
and system solutions for aerospace & defense, communications, data center and industrial
markets. Products include high-performance and radiation-hardened analog mixed-signal
integrated circuits, FPGAs, SoCs and ASICs; power management products; timing and
synchronization devices and precise time solutions, setting the world's standard for time; voice
processing devices; RF solutions; discrete components; enterprise storage and
communication solutions, security technologies and scalable anti-tamper products; Ethernet
solutions; Power-over-Ethernet ICs and midspans; as well as custom design capabilities and
services. Microsemi is headquartered in Aliso Viejo, California, and has approximately 4,800
employees globally. Learn more at www.microsemi.com.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo,
CA 92656 USA
Microsemi makes no warranty, representation, or guarantee regarding the information contained herein or
the suitability of its products and services for any particular purpose, nor does Microsemi assume any
liability whatsoever arising out of the application or use of any product or circuit. The products sold
hereunder and any other products sold by Microsemi have been subject to limited testing and should not
be used in conjunction with mission-critical equipment or applications. Any performance specifications are
believed to be reliable but are not verified, and Buyer must conduct and complete all performance and
other testing of the products, alone and together with, or installed in, any end-products. Buyer shall not
rely on any data and performance specifications or parameters provided by Microsemi. It is the Buyer’s
responsibility to independently determine suitability of any products and to test and verify the same. The
information provided by Microsemi hereunder is provided “as is, where is” and with all faults, and the
entire risk associated with such information is entirely with the Buyer. Microsemi does not grant, explicitly
or implicitly, to any party any patent rights, licenses, or any other IP rights, whether with regard to such
Within the USA: +1 (800) 713-4113
Outside the USA: +1 (949) 380-6100
Sales: +1 (949) 380-6136
Fax: +1 (949) 215-4996
E-mail: sales.support@microsemi.com
©
2017 Microsemi Corporation. All information itself or anything described by such information. Information provided in this document is
rights reserved. Microsemi and the proprietary to Microsemi, and Microsemi reserves the right to make any changes to the information in this
Microsemi logo are trademarks of document or to any products and services at any time without notice.
Microsemi Corporation. All other
trademarks and service marks are the
property of their respective owners.
ZL40241
Confidential
February 2017
© 2017 Microsemi Corporation
23
相关型号：
ZL40272
Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/ LVPECL Fanout Buffer with Per-Output Enable Control
MICROCHIP
ZL40272LDF1
Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/ LVPECL Fanout Buffer with Per-Output Enable Control
MICROCHIP
ZL40272LDG1
Low-Skew, Low Additive Jitter, 12 Output HCSL/LVDS/ LVPECL Fanout Buffer with Per-Output Enable Control
MICROCHIP
ZL40293LDF1
Low Skew Clock Driver, 4000/14000/40000 Series, 40 True Output(s), 0 Inverted Output(s), CMOS
MICROCHIP
©2020 ICPDF网 联系我们和版权申明