ATA6622C-PGQW-1 [MICROCHIP]
IC TXRX LIN BUS REG 20QFN;
| 型号： | ATA6622C-PGQW-1 |
| 厂家： | 
MICROCHIP |
| 描述： | IC TXRX LIN BUS REG 20QFN 电信 电信集成电路 |
| 文件： | 总29页 (文件大小：2284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Atmel ATA6622C/ATA6624C/ATA6626C
LIN Bus Transceiver with 3.3V (5V) Regulator and
Watchdog
DATASHEET
Features
● Master and slave operation possible
● Supply voltage up to 40V
● Operating voltage VS = 5V to 27V
● Typically 10µA supply current during Sleep Mode
● Typically 57µA supply current in Silent Mode
● Linear low-drop voltage regulator, 85mA current capability:
● Normal, Fail-safe, and Silent Mode
● Atmel ATA6622C VCC = 3.3V ±2%
● Atmel ATA6624C VCC = 5.0V ±2%
● Atmel ATA6626C VCC = 5.0V ±2%, TXD time-out timer disabled
● In Sleep Mode VCC is switched off
● VCC- undervoltage detection (4ms reset time) and watchdog reset logical
combined at open drain output NRES
● Negative trigger input for watchdog
● Boosting the voltage regulator possible with an external NPN transistor
● LIN physical layer according to LIN 2.0, 2.1 and SAEJ2602-2
● Wake-up capability via LIN-bus, wake pin, or Kl_15 pin
● INH output to control an external voltage regulator or to switch off the master pull
up resistor
● TXD time-out timer; Atmel ATA6626C: TXD time-out timer Is disabled
● Bus pin is overtemperature and short circuit protected versus GND and battery
● Adjustable watchdog time via external resistor
● Advanced EMC and ESD performance
● Fulfills the OEM “Hardware Requirements for LIN in automotive Applications
Rev.1.0”
● Interference and damage protection according to ISO7637
● Package: QFN 5mm x 5mm with 20 pins
4986M–AUTO–02/13
1.
Description
The Atmel® ATA6622C is a fully integrated LIN transceiver, which complies with the LIN 2.0, 2.1 and SAEJ2602-2
specifications. It has a low-drop voltage regulator for 3.3V/85mA output and a window watchdog. The Atmel ATA6624C has the
same functionality as the Atmel ATA6622C; however, it uses a 5V/85mA regulator. The Atmel ATA6626C has the same
functionality as Atmel ATA6624C without a TXD time-out timer. The voltage regulator is able to source 85mA, but the output
current can be boosted by using an external NPN transistor. This chip combination makes it possible to develop inexpensive,
simple, yet powerful slave and master nodes for LIN-bus systems. Atmel ATA6622C/ATA6624C/ATA6626C are designed to
handle the low-speed data communication in vehicles, e.g., in convenience electronics. Improved slope control at the LIN-driver
ensures secure data communication up to 20kBaud. Sleep Mode and Silent Mode guarantee very low current consumption. The
Atmel ATA6626C is able to switch the LIN unlimited to dominant level via TXD for low data rates.
Figure 1-1. Block Diagram
20
VS
Normal and
Fail-safe
Mode
10
INH
PVCC
Normal
Mode
Receiver
-
9
RXD
+
7
RF Filter
LIN
4
WAKE
KL_15
16
Edge
Detection
Wake-up
Bus Timer
Short Circuit and
Overtemperature
Protection
PVCC
Slew Rate Control
TXD
Time-out
Timer
11
TXD
*)
19
18
Normal/Silent/
Fail-safe Mode
3.3/5V
VCC
PVCC
Control Unit
12
1
5
Undervoltage
Reset
NRES
EN
OUT
Watchdog
Adjustable
Watchdog
Oscillator
13
Internal Testing
WD_OSC
Unit
GND
PVCC
15
14
3
MODE TM
NTRIG
*) Not in ATA6626
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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4986M–AUTO–02/13
2.
Pin Configuration
Figure 2-1. Pinning QFN20
20 19 18 17 16
EN
GND
1
2
3
4
5
15
14
13
12
11
MODE
TM
ATA6622C
ATA6624C
ATA6626C
NTRIG
WAKE
GND
WD_OSC
NRES
TXD
QFN 5mm x 5mm
0.65mm pitch
20 lead
6
7
8
9
10
Table 2-1. Pin Description
Pin
Symbol
EN
Function
1
Enables the device in Normal Mode
System ground (optional)
2
GND
NTRIG
WAKE
GND
GND
LIN
3
Low-level watchdog trigger input from microcontroller
High-voltage input for local wake-up request; if not needed, connect directly to VS
System ground (mandatory)
4
5
6
7
System ground (optional)
LIN-bus line input/output
8
GND
RXD
INH
System ground (optional)
9
Receive data output
10
Battery related output for controlling an external voltage regulator
Transmit data input; active low output (strong pull down) after a local wake-up request
Output undervoltage and watchdog reset (open drain)
11
TXD
12
NRES
13
WD_OSC External resistor for adjustable watchdog timing
14
TM
MODE
KL_15
GND
PVCC
VCC
For factory testing only (tie to ground)
Low, watchdog is on; high, watchdog is off
Ignition detection (edge sensitive)
System ground (optional)
15
16
17
18
3.3V/5V regulator sense input pin
3.3V/5V regulator output/driver pin
Battery supply
19
20
VS
Backside
Heat slug is connected to all GND pins
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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3.
Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., the LIN protocol layer), all nodes with a LIN physical
layer according to revision 2.x can be mixed with LIN physical layer nodes, which, according to older versions (i.e., LIN 1.0, LIN
1.1, LIN 1.2, LIN 1.3), are without any restrictions.
3.2
Supply Pin (VS)
The LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable data transmission if VS falls
below VSth < 4V in order to avoid false bus messages. After switching on VS, the IC starts in Fail-safe Mode, and the voltage
regulator is switched on.
The supply current is typically 10µA in Sleep Mode and 57µA in Silent Mode.
3.3
3.4
Ground Pin (GND)
The IC does not affect the LIN Bus in the event of GND disconnection. It is able to handle a ground shift up to 11.5% of VS. The
mandatory system ground is pin 5.
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads up to 85mA. It is able to supply the microcontroller and other
ICs on the PCB and is protected against overloads by means of current limitation and overtemperature shut-down. Furthermore,
the output voltage is monitored and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun
.
To boost up the maximum load current, an external NPN transistor may be used, with its base connected to the VCC pin and its
emitter connected to PVCC.
3.5
3.6
Voltage Regulator Sense Pin (PVCC)
The PVCC is the sense input pin of the 3.3V/5V voltage regulator. For normal applications (i.e., when only using the internal
output transistor), this pin is connected to the VCC pin. If an external boosting transistor is used, the PVCC pin must be
connected to the output of this transistor, i.e., its emitter terminal.
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown and an internal pull-up resistor compliant with the LIN 2.x
specification are implemented. The allowed voltage range is between –27V and +40V. Reverse currents from the LIN bus to VS
are suppressed, even in the event of GND shifts or battery disconnection. LIN receiver thresholds are compatible with the LIN
protocol specification. The fall time from recessive to dominant bus state and the rise time from dominant to recessive bus state
are slope controlled.
3.7
3.8
Input/Output Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface used to control the state of the LIN output. TXD must be pulled to
ground in order to have a low LIN-bus. If TXD is high or unconnected (internal pull-up resistor), the LIN output transistor is
turned off, and the bus is in recessive state. During Fail-safe Mode, this pin is used as output. It is current-limited to < 8mA. and
is latched to low if the last wake-up event was from pin WAKE or KL_15.
TXD Dominant Time-out Function
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being driven permanently in
dominant state. If TXD is forced to low for longer than tDOM > 6ms, the LIN-bus driver is switched to recessive state.
To reactivate the LIN bus driver, switch TXD to high (> 10µs).
The time-out function is disabled in the ATA6626C. Switching to dominant level on the LIN bus occurs without any time
limitations.
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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3.9
Output Pin (RXD)
This output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state) is reported by a high level at
RXD; LIN low (dominant state) is reported by a low level at RXD. The output has an internal pull-up resistor with typically 5kΩ to
VCC. The AC characteristics can be defined with an external load capacitor of 20pF.
The output is short-circuit protected. RXD is switched off in Unpowered Mode (i.e., VS = 0V).
3.10 Enable Input Pin (EN)
The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in Normal Mode, with transmission
paths from TXD to LIN and from LIN to RXD both active. The VCC voltage regulator operates with 3.3V/5V/85mA output
capability.
If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data transmission is then possible, and
the current consumption is reduced to IVS typ. 57µA. The VCC regulator has its full functionality.
If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmission is possible, and the voltage
regulator is switched off.
3.11 Wake Input Pin (WAKE)
The Wake Input pin is a high-voltage input used to wake up the device from Sleep Mode or Silent Mode. It is usually connected
to an external switch in the application to generate a local wake-up. A pull-up current source, typically 10µA, is implemented.
If a local wake-up is not needed in the application, connect the Wake pin directly to the VS pin.
3.12 Mode Input Pin (MODE)
Connect the MODE pin directly or via an external resistor to GND for normal watchdog operation. To debug the software of the
connected microcontroller, connect MODE pin to 3.3V/5V and the watchdog is switched off.
3.13 TM Input Pin
The TM pin is used for final production measurements at Atmel®. In normal application, it has to be always connected to GND.
3.14 KL_15 Pin
The KL_15 pin is a high-voltage input used to wake up the device from Sleep or Silent Mode. It is an edge sensitive pin (low-to-
high transition). It is usually connected to ignition to generate a local wake-up in the application when the ignition is switched on.
Although KL_15 pin is at high voltage (VBatt), it is possible to switch the IC into Sleep or Silent Mode. Connect the KL_15 pin
directly to GND if you do not need it. A debounce timer with a typical TdbKl_15 of 160µs is implemented.
The input voltage threshold can be adjusted by varying the external resistor due to the input current IKL_15. To protect this pin
against voltage transients, a serial resistor of 47kΩ and a ceramic capacitor of 100nF are recommended. With this RC
combination you can increase the wake-up time TwKL_15 and, therefore, the sensitivity against transients on the ignition Kl.15.
You can also increase the wake-up time using external capacitors with higher values.
3.15 INH Output Pin
The INH Output pin is used to switch an external voltage regulator on during Normal or Fail-safe Mode. The INH pin is switched
off in Sleep or Silent Mode. It is possible to switch off the external 1kΩ master resistor via the INH pin for master node
applications. The INH pin is switched off during VCC undervoltage reset.
3.16 Reset Output Pin (NRES)
The Reset Output pin, an open drain output, switches to low during VCC undervoltage or a watchdog failure.
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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4986M–AUTO–02/13
3.17 WD_OSC Output Pin
The WD_OSC Output pin provides a typical voltage of 1.2V, which supplies an external resistor with values between 34kΩ and
120kΩ to adjust the watchdog oscillator time.
3.18 NTRIG Input Pin
The NTRIG Input pin is the trigger input for the window watchdog. A pull-up resistor is implemented. A negative edge triggers
the watchdog. The trigger signal (low) must exceed a minimum time ttrigmin to generate a watchdog trigger.
3.19 Wake-up Events from Sleep or Silent Mode
●
●
●
●
LIN-bus
WAKE pin
EN pin
KL_15
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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4986M–AUTO–02/13
4.
Modes of Operation
Figure 4-1. Modes of Operation
a: VS > 5V
b: VS < 3.7V
Unpowered Mode
Batt = 0V
V
c: Bus wake-up event
d: Wake up from WAKE or KL_15 pin
e: NRES switches to low
b
a
b
Fail-safe Mode
VCC: 3.3V/5V
with undervoltage monitoring
Communication: OFF
Watchdog: ON
b
b
c + d + e
e
EN = 1
EN = 1
c + d
Go to silent command
Local wake-up event
EN = 0
TXD = 1
Silent Mode
VCC: 3.3V/5V
with undervoltage monitoring
Communication: OFF
Watchdog: OFF
Normal Mode
EN = 1
VCC: 3.3V/5V
with undervoltage
monitoring
Go to sleep command
EN = 0
TXD = 0
Sleep Mode
Communication: ON
Watchdog: ON
VCC: switched off
Communication: OFF
Watchdog: OFF
Table 4-1. Table of Modes
Mode of
Operation
Transceiver
VCC
Watchdog
WD_OSC INH
RXD
LIN
High,
except after wake-up
Fail-safe
Off
3.3V/5V
On
1.23V
On
Recessive
Normal
Silent
On
Off
Off
3.3V/5V
3.3V/5V
0V
On
Off
Off
1.23V
0V
On
Off
Off
LIN depending
TXD depending
Recessive
High
0V
Sleep
0V
Recessive
4.1
Normal Mode
This is the normal transmitting and receiving mode of the LIN Interface in accordance with the LIN specification LIN 2.x. The
voltage regulator is active and can source up to 85mA. The undervoltage detection is activated. The watchdog needs a trigger
signal from NTRIG to avoid resets at NRES. If NRES is switched to low, the IC changes its state to Fail-safe Mode.
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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4986M–AUTO–02/13
4.2
Silent Mode
A falling edge at EN when TXD is high switches the IC into Silent Mode. The TXD Signal has to be logic high during the Mode
Select window (see Figure 4-2). The transmission path is disabled in Silent Mode. The overall supply current from VBatt is a
combination of the IVSsi = 57µA plus the VCC regulator output current IVCC
.
The internal slave termination between the LIN pin and the VS pin is disabled in Silent Mode, only a weak pull-up current
(typically 10µA) between the LIN pin and the VS pin is present. Silent Mode can be activated independently from the actual level
on the LIN, WAKE, or KL_15 pins.
If an undervoltage condition occurs, NRES is switched to low, and the IC changes its state to Fail-safe Mode.
A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on the
internal slave termination between the LIN pin and the VS pin.
Figure 4-2. Switch to Silent Mode
Normal Mode
Silent Mode
EN
Mode select window
TXD
t
d = 3.2μs
NRES
VCC
LIN
Delay time silent mode
td_silent maximum 20μs
LIN switches directly to recessive mode
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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4986M–AUTO–02/13
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and the following rising
edge at the LIN pin (see Figure 4-3 on page 9) results in a remote wake-up request. The device switches from Silent Mode to
Fail-safe Mode. The remote wake-up request is indicated by a low level at the RXD pin to interrupt the microcontroller (see
Figure 4-3 on page 9). EN high can be used to switch directly to Normal Mode.
Figure 4-3. LIN Wake Up from Silent Mode
Bus wake-up filtering time
tbus
Fail-safe mode
Normal mode
LIN bus
RXD
Node in silent mode
High
Low
High
TXD
Watchdog off
Start watchdog lead time td
Fail safe mode 3.3V/5V
Watchdog
VCC
voltage
regulator
Silent mode 3.3V/5V
Normal mode
EN High
EN
Undervoltage detection active
NRES
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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4986M–AUTO–02/13
4.3
Sleep Mode
A falling edge at EN when TXD is low switches the IC into Sleep Mode. The TXD Signal has to be logic low during the Mode
Select window (Figure 4-4 on page 10). In order to avoid any influence to the LIN-pin during switching into sleep mode it is
possible to switch the EN up to 3.2 µs earlier to LOW than the TXD. Therefore, the best and easiest way are two falling edges at
TXD and EN at the same time.The transmission path is disabled in Sleep Mode. The supply current IVSsleep from VBatt is typically
10µA.
The VCC regulator is switched off. NRES and RXD are low. The internal slave termination between the LIN pin and VS pin is
disabled, only a weak pull-up current (typically 10µA) between the LIN pin and the VS pin is present. Sleep Mode can be
activated independently from the current level on the LIN, WAKE, or KL_15 pin.
A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver and switches on the
internal slave termination between the LIN pin and the VS pin.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time period (> tbus) and a following rising
edge at pin LIN results in a remote wake-up request. The device switches from Sleep Mode to Fail-safe Mode.
The VCC regulator is activated, and the remote wake-up request is indicated by a low level at the RXD pin to interrupt the
microcontroller (see Figure 4-5 on page 11).
EN high can be used to switch directly from Sleep/Silent to Fail-safe Mode. If EN is still high after VCC ramp up and
undervoltage reset time, the IC switches to the Normal Mode.
Figure 4-4. Switch to Sleep Mode
Normal Mode
Sleep Mode
EN
Mode select window
TXD
t
d = 3.2μs
NRES
VCC
Delay time sleep mode
d_sleep = maximum 20μs
t
LIN
LIN switches directly to recessive mode
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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4986M–AUTO–02/13
4.4
4.5
Fail-safe Mode
The device automatically switches to Fail-safe Mode at system power-up. The voltage regulator is switched on (see Figure 5-1
on page 13). The NRES output switches to low for tres = 4ms and gives a reset to the microcontroller. LIN communication is
switched off. The IC stays in this mode until EN is switched to high. The IC then changes to Normal Mode. A power down of VBatt
(VS < 3.7V) during Silent or Sleep Mode switches the IC into Fail-safe Mode after power up. A low at NRES switches into Fail-
safe Mode directly. During Fail-safe Mode the TXD pin is an output and signals the last wake-up source.
Unpowered Mode
If you connect battery voltage to the application circuit, the voltage at the VS pin increases according to the block capacitor (see
Figure 5-1 on page 13). After VS is higher than the VS undervoltage threshold VSth, the IC mode changes from Unpowered
Mode to Fail-safe Mode. The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the VCC
capacitor and the load.
The NRES is low for the reset time delay treset. During this time, treset, no mode change is possible.
Figure 4-5. LIN Wake Up from Sleep Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
Normal Mode
LIN bus
RXD
Low
Low
TXD
On state
VCC
voltage
regulator
Off state
Regulator wake-up time
EN High
EN
Reset
time
NRES
Low
Microcontroller
start-up time delay
Watchdog off
Start watchdog lead time td
Watchdog
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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5.
Wake-up Scenarios from Silent or Sleep Mode
5.1
Remote Wake-up via Dominant Bus State
A voltage less than the LIN Pre_Wake detection VLINL at the LIN pin activates the internal LIN receiver.
A falling edge at the LIN pin followed by a dominant bus level VBUSdom maintained for a certain time period (> tBUS) and a rising
edge at pin LIN result in a remote wake-up request. The device switches from Silent or Sleep Mode to Fail-safe Mode. The VCC
voltage regulator is/remains activated, the INH pin is switched to high, and the remote wake-up request is indicated by a low
level at the RXD pin to generate an interrupt for the microcontroller. A low level at the LIN pin in the Normal Mode starts the bus
wake-up filtering time, and if the IC is switched to Silent or Sleep Mode, it will receive a wake-up after a positive edge at the LIN
pin.
5.2
5.3
Local Wake-up via Pin WAKE
A falling edge at the WAKE pin followed by a low level maintained for a certain time period (> tWAKE) results in a local wake-up
request. The device switches to Fail-safe Mode. The local wake-up request is indicated by a low level at the RXD pin to
generate an interrupt in the microcontroller and a strong pull down at TXD. When the Wake pin is low, it is possible to switch to
Silent or Sleep Mode via pin EN. In this case, the wake-up signal has to be switched to high > 10µs before the negative edge at
WAKE starts a new local wake-up request.
Local Wake-up via Pin KL_15
A positive edge at pin KL_15 followed by a high voltage level for a certain time period (> tKL_15) results in a local wake-up
request. The device switches into the Fail-safe Mode. The extra long wake-up time ensures that no transients at KL_15 create a
wake up. The local wake-up request is indicated by a low level at the RXD pin to generate an interrupt for the microcontroller
and a strong pull down at TXD. During high-level voltage at pin KL_15, it is possible to switch to Silent or Sleep Mode via pin
EN. In this case, the wake-up signal has to be switched to low > 250µs before the positive edge at KL_15 starts a new local
wake-up request. With external RC combination, the time is even longer.
5.4
5.5
Wake-up Source Recognition
The device can distinguish between a local wake-up request (Wake or KL_15 pins) and a remote wake-up request (dominant
LIN bus state). The wake-up source can be read on the TXD pin in Fail-safe Mode. A high level indicates a remote wake-up
request (weak pull up at the TXD pin); a low level indicates a local wake-up request (strong pull down at the TXD pin). The
wake-up request flag (signalled on the RXD pin), as well as the wake-up source flag (signalled on the TXD pin), is immediately
reset if the microcontroller sets the EN pin to high (see Figure 4-2 on page 8 and Figure 4-3 on page 9) and the IC is in Normal
Mode. The last wake-up source flag is stored and signalled in Fail-safe Mode at the TXD pin.
Fail-safe Features
●
During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to the power dissipation, the chip
temperature exceeds TLINoff, and the LIN output is switched off. The chip cools down and after a hysteresis of Thys
,
switches the output on again. RXD stays on high because LIN is high. During LIN overtemperature switch-off, the VCC
regulator works independently.
●
●
●
During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode. If the short-circuit disappears,
the IC starts with a remote wake-up.
The reverse current is very low < 2µA at the LIN pin during loss of VBatt. This is optimal behavior for bus systems where
some slave nodes are supplied from battery or ignition.
During a short circuit at VCC, the output limits the output current to IVCClim. Because of undervoltage, NRES switches to
low and sends a reset to the microcontroller. The IC switches into Fail-safe Mode. If the chip temperature exceeds the
value TVCCoff, the VCC output switches off. The chip cools down and after a hysteresis of Thys, switches the output on
again. Because of the Fail-safe Mode, the VCC voltage will switch on again although EN is switched off from the
microcontroller. The microcontroller can start with its normal operation.
●
●
●
EN pin provides a pull-down resistor to force the transceiver into recessive mode if EN is disconnected.
RXD pin is set floating if VBatt is disconnected.
TXD pin provides a pull-up resistor to force the transceiver into recessive mode if TXD is disconnected.
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4986M–AUTO–02/13
●
●
●
If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE after tdom > 20ms (only for Atmel®
ATA6622C/ATA6624C).
If the WD_OSC pin has a short-circuit to GND and the NTRIG Signal has a period time > 27ms, the watchdog runs with
an internal oscillator and guarantees a reset after the second NTRIG signal at the latest.
If the resistor at WO_OSC pin is disconnected, the watchdog runs with an internal oscillator and guarantees a reseet
after the second NTRIG signal at the latest.
5.6
Voltage Regulator
The voltage regulator needs an external capacitor for compensation and for smoothing the disturbances from the
microcontroller. It is recommended to use an electrolythic capacitor with C > 1.8µF and a ceramic capacitor with C = 100nF.
The values of these capacitors can be varied by the customer, depending on the application.
The main power dissipation of the IC is created from the VCC output current IVCC, which is needed for the application. In Figure
5-2 on page 13 the safe operating area of the Atmel ATA6624C/ATA6626C is shown.
Figure 5-1. VCC Voltage Regulator: Ramp-up and Undervoltage Detection
VS
12V
5.5V/3.8V
t
VCC
5V/3.3V
Vthun
t
t
Tres_f
TVCC
TReset
NRES
5V/3.3V
Figure 5-2. Power Dissipation: Safe Operating Area: VCC Output Current versus Supply Voltage VS at Different Ambi-
ent Temperatures Due to Rthja = 35K/W
90
T
= 105°C
amb
80
70
T
T
= 115°C
= 125°C
amb
amb
60
50
40
30
20
10
0
5
6
7
8
9
10 11 12 13 14 15 16 17 18
VS (V)
For programming purposes of the microcontroller it is potentially necessary to supply the VCC output via an external power
supply while the VS Pin of the system basis chip is disconnected. This will not affect the system basis chip.
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6.
Watchdog
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative edge) input within a time window of
Twd. The trigger signal must exceed a minimum time ttrigmin > 200ns. If a triggering signal is not received, a reset signal will be
generated at output NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period, Tosc, is
adjustable via the external resistor Rwd_osc (34kΩ to 120kΩ).
During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at NRES disappears. It is defined as lead
time td. After wake up from Sleep or Silent Mode, the lead time td starts with the negative edge of the RXD output.
6.1
Typical Timing Sequence with RWD_OSC = 51kΩ
The trigger signal Twd is adjustable between 20ms and 64ms using the external resistor RWD_OSC
.
For example, with an external resistor of RWD_OSC = 51kΩ ±1%, the typical parameters of the watchdog are as follows:
t
t
osc = 0.405 × RWD_OSC – 0.0004 × (RWD_OSC)2 (RWD_OSC in kΩ; tosc in µs)
OSC = 19.6µs due to 51kΩ
td = 7895 × 19.6µs = 155ms
t1 = 1053 × 19.6µs = 20.6ms
t2 = 1105 × 19.6µs = 21.6ms
tnres = constant = 4ms
After ramping up the battery voltage, the 3.3V/5V regulator is switched on. The reset output NRES stays low for the time treset
(typically 4ms), then it switches to high, and the watchdog waits for the trigger sequence from the microcontroller. The lead time,
td, follows the reset and is td = 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the trigger
pulse NTRIG occurs during this time, the time t1 starts immediately. If no trigger signal occurs during the time td, a watchdog
reset with tNRES = 4ms will reset the microcontroller after td = 155ms. The times t1 and t2 have a fixed relationship between each
other. A triggering signal from the microcontroller is anticipated within the time frame of t2 = 21.6ms. To avoid false triggering
from glitches, the trigger pulse must be longer than tTRIG,min > 200ns. This slope serves to restart the watchdog sequence. If the
triggering signal fails in this open window t2, the NRES output will be drawn to ground. A triggering signal during the closed
window t1 immediately switches NRES to low.
Figure 6-1. Timing Sequence with RWD_OSC = 51kΩ
VCC
3.3V/5V
Undervoltage Reset
reset = 4ms
Watchdog Reset
tnres = 4ms
t
NRES
td = 155ms
t1 = 20.6ms
t1
t2
t2 = 21ms
twd
NTRIG
ttrig > 200ns
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
14
4986M–AUTO–02/13
6.2
Worst Case Calculation with RWD_OSC = 51kΩ
The internal oscillator has a tolerance of 20%. This means that t1 and t2 can also vary by 20%. The worst case calculation for
the watchdog period twd is calculated as follows.
The ideal watchdog time twd is between the maximum t1 and the minimum t1 plus the minimum t2.
t1,min = 0.8 × t1 = 16.5ms, t1,max = 1.2 × t1 = 24.8ms
t
2,min = 0.8 × t2 = 17.3ms, t2,max = 1.2 × t2 = 26ms
t
t
wdmax = t1min + t2min = 16.5ms + 17.3ms = 33.8ms
wdmin = t1max = 24.8ms
twd = 29.3ms ±4.5ms (±15%)
A microcontroller with an oscillator tolerance of ±15% is sufficient to supply the trigger inputs correctly.
Table 6-1.
Typical Watchdog Timings
Oscillator
Period
tosc/µs
Lead
Time
td/ms
Closed
Window
t1/ms
RWD_OSC
Open Window
t2/ms
Trigger Period from
Microcontroller twd/ms
Reset Time
tnres/ms
kΩ
34
51
13.3
19.61
33.54
42.84
105
14.0
20.64
35.32
45.11
14.7
21.67
37.06
47.34
19.9
29.32
50.14
64.05
4
4
4
4
154.8
264.80
338.22
91
120
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
15
4986M–AUTO–02/13
7.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
Supply voltage VS
VS
–0.3
+40
V
Pulse time ≤ 500ms; Ta = 25°C
Output current IVCC ≤ 85mA
VS
VS
+40
27
V
V
Pulse time ≤ 2min; Ta = 25°C
Output current IVCC ≤ 85mA
WAKE (with 33kΩ serial resistor)
KL_15 (with 47kΩ/100nF)
DC voltage
–1
–150
+40
+100
V
V
Transient voltage due to ISO7637 (coupling 1nF)
INH
- DC voltage
–0.3
–27
VS + 0.3
+40
V
LIN
- DC voltage
V
V
Logic pins (RxD, TxD, EN, NRES, NTRIG,
WD_OSC, MODE, TM)
–0.3
+5.5
+2
Output current NRES
INRES
mA
PVCC DC voltage
VCC DC voltage
–0.3
–0.3
+5.5
+6.5
V
V
ESD according to IBEE LIN EMC
Test Spec. 1.0 following IEC 61000-4-2
- Pin VS, LIN, KL_15 (47kΩ/100nF) to GND
- Pin WAKE (33kΩ serial resistor) to GND
±6
±5
KV
KV
ESD HBM following STM5.1 with 1.5kΩ 100pF
- Pin VS, LIN, KL_15, WAKE to GND
±6
KV
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
±3
KV
CDM ESD STM 5.3.1
±750
±200
–40
V
V
Machine Model ESD AEC-Q100-RevF(003)
Junction temperature
Tj
+150
+150
°C
°C
Storage temperature
Ts
–55
8.
Thermal Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Thermal resistance junction to heat slug
Rthjc
10
K/W
Thermal resistance junction to ambient, where heat
slug is soldered to PCB
Rthja
35
K/W
Thermal shutdown of VCC regulator
Thermal shutdown of LIN output
Thermal shutdown hysteresis
150
150
165
165
10
170
170
°C
°C
°C
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
16
4986M–AUTO–02/13
9.
Electrical Characteristics
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
VS Pin
Nominal DC voltage
range
1.1
VS
VS
VS
5
3
27
14
V
A
B
Sleep Mode
VLIN > VS – 0.5V
IVSsleep
10
11
57
66
µA
VS < 14V (Tj = 25°C)
Supply current in Sleep
Mode
1.2
1.3
Sleep Mode
VLIN > VS – 0.5V
VS < 14V (Tj = 125°C)
VS
VS
VS
VS
VS
VS
IVSsleep
5
16
67
76
0.8
53
µA
µA
µA
mA
mA
µA
A
B
A
A
A
A
Bus recessive
VS < 14V (Tj = 25°C)
Without load at VCC
IVSsi
47
56
0.3
50
Supply current in Silent
Mode
Bus recessive
VS < 14V (Tj = 125°C)
Without load at VCC
IVSsi
Bus recessive
VS < 14V
Without load at VCC
Supply current in Normal
Mode
1.4
1.5
IVSrec
IVSdom
IVSfail
Bus dominant
VS < 14V
VCC load current 50 mA
Supply current in Normal
Mode
Bus recessive
VS < 14V
Without load at VCC
Supply current in Fail-
safe Mode
1.6
1.7
250
3.7
550
5
VS undervoltage
threshold
VS
VS
VSth
4.4
0.2
V
V
A
A
VS undervoltage
threshold hysteresis
1.8
2
VSth_hys
RXD Output Pin
Normal Mode
VLIN = 0V
VRXD = 0.4V
Low-level output sink
current
2.1
RXD
IRXD
1.3
3
2.5
5
8
mA
A
2.2
2.3
3
Low-level output voltage IRXD = 1mA
Internal resistor to VCC
RXD
RXD
VRXDL
RRXD
0.4
7
V
A
A
kΩ
TXD Input/Output Pin
3.1
Low-level voltage input
TXD
TXD
TXD
TXD
VTXDL
VTXDH
RTXD
ITXD
–0.3
2
+0.8
V
V
A
A
A
A
VCC
+
3.2
3.3
3.4
High-level voltage input
0.3V
Pull-up resistor
VTXD = 0V
125
–3
250
2.5
400
kΩ
µA
High-level leakage
current
VTXD = VCC
+3
Fail-safe Mode
VLIN = VS
VWAKE = 0V
VTXD = 0.4V
Low-level output sink
current at local wake-up
request
3.5
4
TXD
ITXDwake
2
8
mA
A
EN Input Pin
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
17
4986M–AUTO–02/13
9.
Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
4.1
Low-level voltage input
EN
VENL
–0.3
+0.8
V
A
VCC
0.3V
+
4.2
High-level voltage input
Pull-down resistor
EN
VENH
2
V
A
4.3
4.4
5
VEN = VCC
EN
EN
REN
IEN
50
–3
125
200
+3
kΩ
A
A
Low-level input current VEN = 0V
NTRIG Watchdog Input Pin
Low-level voltage input
µA
5.1
NTRIG
NTRIG
NTRIG
NTRIG
VNTRIGL
VNTRIGH
RNTRIG
INTRIG
–0.3
2
+0.8
V
V
A
A
A
A
VCC
0.3V
+
5.2
5.3
5.4
High-level voltage input
Pull-up resistor
VNTRIG = 0V
VNTRIG = VCC
125
–3
250
400
kΩ
µA
High-level leakage
current
+3
6
Mode Input Pin
6.1
Low-level voltage input
MODE
MODE
VMODEL
VMODEH
–0.3
2
+0.8
V
V
A
A
VCC
+
6.2
6.3
High-level voltage input
Leakage current
0.3V
VMODE = VCC or
VMODE = 0V
MODE
IMODE
–3
+3
µA
A
7
INH Output Pin
7.1
High-level voltage
IINH = –15mA
INH
INH
VINHH
RINH
VS – 0.75
VS
50
V
A
A
Switch-on resistance
between VS and INH
7.2
7.3
30
Ω
Sleep Mode
VINH = 0V/27V, VS = 27V
Leakage current
INH
IINHL
–3
+3
µA
A
LIN Bus Driver: Bus Load Conditions:
Load 1 (Small): 1nF, 1kΩ; Load 2 (Large): 10nF, 500Ω; Internal Pull-up RRXD = 5kΩ; CRXD = 20pF
Load 3 (Medium): 6.8nF, 660Ω, Characterized on Samples
8
10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20kBit/s and 10.8 and 10.9 at 10.4kBit/s
Driver recessive output
voltage
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Load1/Load2
LIN
LIN
LIN
LIN
LIN
LIN
LIN
LIN
VBUSrec
V_LoSUP
V_HiSUP
V_LoSUP_1k
V_HiSUP_1k
RLIN
0.9 × VS
VS
1.2
2
V
V
A
A
A
A
A
A
D
A
VVS = 7V
Rload = 500Ω
Driver dominant voltage
VVS = 18V
Rload = 500Ω
Driver dominant voltage
Driver dominant voltage
Driver dominant voltage
Pull-up resistor to VS
V
VVS = 7.0V
Rload = 1000Ω
0.6
0.8
20
V
VVS = 18V
Rload = 1000Ω
V
The serial diode is
mandatory
30
60
1.0
200
kΩ
V
Voltage drop at the serial In pull-up path with Rslave
diodes
VSerDiode
IBUS_LIM
0.4
40
ISerDiode = 10mA
LIN current limitation
VBUS = VBatt_max
120
mA
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
18
4986M–AUTO–02/13
9.
Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Input leakage current at Input leakage current
the receiver including
pull-up resistor as
specified
Driver off
VBUS = 0V
VBatt = 12V
8.9
LIN IBUS_PAS_dom
–1
–0.35
mA
A
Driver off
Leakage current LIN
recessive
8V < VBatt < 18V
8V < VBUS < 18V
8.10
LIN
LIN
IBUS_PAS_rec
10
20
µA
µA
A
A
VBUS ≥ VBatt
Leakage current when
control unit disconnected
from ground.
GNDDevice = VS
VBatt = 12V
0V < VBUS < 18V
8.11 Loss of local ground
must not affect
IBUS_NO_gnd
–10
+0.5
+10
communication in the
residual network.
Leakage current at a
disconnected battery.
Node has to sustain the VBatt disconnected
8.12 current that can flow
VSUP_Device = GND
under this condition. Bus 0V < VBUS < 18V
must remain operational
LIN
IBUS_NO_bat
0.1
2
µA
A
under this condition.
Capacitance on pin LIN
to GND
8.13
9
LIN
LIN
CLIN
20
pF
V
D
A
LIN Bus Receiver
Center of receiver
threshold
VBUS_CNT
(Vth_dom + Vth_rec)/2
=
0.475 ×
VS
0.5 ×
VS
0.525 ×
VS
9.1
VBUS_CNT
9.2
9.3
Receiver dominant state VEN = 5V
Receiver recessive state VEN = 5V
Receiver input
LIN
LIN
VBUSdom
VBUSrec
0.4 × VS
V
V
A
A
0.6 × VS
0.028 ×
VS
0.175 ×
VS
9.4
9.5
Vhys = Vth_rec – Vth_dom
LIN
LIN
LIN
VBUShys
VLINH
0.1 × VS
V
V
V
A
A
A
hysteresis
Pre_Wake detection LIN
High-level input voltage
VS +
0.3V
VS – 2V
–27
Pre_Wake detection LIN
Low-level input voltage
VS –
3.3V
9.6
10
Activates the LIN receiver
VLINL
Internal Timers
Dominant time for wake-
up via LIN bus
10.1
VLIN = 0V
VEN = 5V
LIN
EN
tbus
30
5
90
15
150
20
µs
µs
A
A
Time delay for mode
change from Fail-safe
into Normal Mode via EN
pin
10.2
10.3
tnorm
Time delay for mode
change from Normal
Mode to Sleep Mode via
EN pin
VEN = 0V
EN
tsleep
2
7
12
µs
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
19
4986M–AUTO–02/13
9.
Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
TXD dominant time-out
10.4 time (ATA6626C
disabled)
VTXD = 0V
TXD
tdom
6
13
20
ms
A
Time delay for mode
change from Silent
Mode into Normal Mode
via EN
10.5
VEN = 5V
EN
ts_n
5
15
40
µs
A
A
THRec(max) = 0.744 × VS
THDom(max) = 0.581 × VS
VS = 7.0V to 18V
10.6 Duty cycle 1
LIN
D1
0.396
tBit = 50µs
D1 = tbus_rec(min)/(2 × tBit)
THRec(min) = 0.422 × VS
THDom(min) = 0.284 × VS
VS = 7.6V to 18V
10.7 Duty cycle 2
10.8 Duty cycle 3
10.9 Duty cycle 4
LIN
LIN
D2
D3
D4
0.581
A
A
tBit = 50µs
D2 = tbus_rec(max)/(2 × tBit)
THRec(max) = 0.778 × VS
THDom(max) = 0.616 × VS
VS = 7.0V to 18V
tBit = 96µs
D3 = tbus_rec(min)/(2 × tBit)
0.417
THRec(min) = 0.389 × VS
THDom(min) = 0.251 × VS
VS = 7.6V to 18V
tBit = 96µs
D4 = tbus_rec(max)/(2 × tBit)
LIN
LIN
0.590
22.5
A
A
Slope time falling and
10.10
tSLOPE_fall
tSLOPE_rise
VS = 7.0V to 18V
3.5
µs
rising edge at LIN
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions: CRXD = 20pF
11
Propagation delay of
VS = 7.0V to 18V
11.1 receiver (Figure 9-1 on
RXD
RXD
trx_pd
6
µs
µs
A
A
trx_pd = max(trx_pdr , trx_pdf
)
page 23)
Symmetry of receiver
11.2 propagation delay rising
edge minus falling edge
VS = 7.0V to 18V
trx_sym = trx_pdr – trx_pdf
trx_sym
–2
+2
12
NRES Open Drain Output Pin
VS ≥ 5.5V
INRES = 1mA
12.1 Low-level output voltage
NRES
NRES
NRES
NRES
VNRESL
VNRESLL
treset
A
A
A
A
0.14
0.14
V
V
10kΩ to 5V
VCC = 0V
12.2 Low-level output low
VS ≥ 5.5V
CNRES = 20pF
12.3 Undervoltage reset time
2
4
6
ms
µs
Reset debounce time for VS ≥ 5.5V
12.4
13
tres_f
1.5
10
falling edge
CNRES = 20pF
Watchdog Oscillator
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
20
4986M–AUTO–02/13
9.
Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Voltage at WD_OSC in IWD_OSC = –200µA
WD_
OSC
13.1
13.2
VWD_OSC
1.13
1.23
1.33
V
A
Normal Mode
VVS ≥ 4V
Possible values of
resistor
WD_
OSC
ROSC
34
120
kΩ
A
13.3 Oscillator period
13.4 Oscillator period
13.5 Oscillator period
13.6 Oscillator period
ROSC = 34kΩ
ROSC = 51kΩ
ROSC = 91kΩ
ROSC = 120kΩ
tOSC
tOSC
tOSC
tOSC
10.65
15.68
26.83
34.2
13.3
19.6
33.5
42.8
15.97
23.52
40.24
51.4
µs
µs
µs
µs
A
A
A
A
14
Watchdog Timing Relative to tOSC
Watchdog lead time after
Reset
14.1
td
7895
cycles
A
Watchdog closed
window
14.2
t1
t2
1053
1105
4
cycles
cycles
ms
A
A
A
14.3 Watchdog open window
Watchdog reset time
NRES
14.4
NRES
tnres
3.2
4.8
15
KL_15 Pin
High-level input voltage Positive edge initializes a
VS +
0.3V
15.1
KL_15
KL_15
KL_15
VKL_15H
VKL_15L
IKL_15
4
V
V
A
A
A
RV = 47kΩ
wake-up
Low-level input voltage
RV = 47kΩ
15.2
–1
+2
65
VS < 27V
VKL_15 = 27V
15.3 KL_15 pull-down current
50
µA
15.4 Internal debounce time Without external capacitor KL_15
TdbKL_15
TwKL_15
80
160
2
250
4.5
µs
A
C
15.5 KL_15 wake-up time
16 WAKE Pin
RV = 47kΩ, C = 100nF
KL_15
WAKE
0.4
ms
VS +
0.3V
16.1 High-level input voltage
VWAKEH
VWAKEL
IWAKE
VS – 1V
–1
V
V
A
A
A
A
A
VS –
3.3V
16.2 Low-level input voltage Initializes a wake-up signal WAKE
VS < 27V
16.3 WAKE pull-up current
WAKE
WAKE
WAKE
–30
–5
–10
70
µA
µA
µs
VWAKE = 0V
High-level leakage
current
VS = 27V
VWAKE = 27V
16.4
IWAKEL
IWAKEL
+5
Time of low pulse for
16.5
VWAKE = 0V
30
150
wake-up via WAKE pin
17
VCC Voltage Regulator ATA6622C, PVCC = VCC
4V < VS < 18V
(0mA to 50mA)
VCC
VCC
VCC
VCCnor
VCCnor
VCClow
3.234
3.234
3.366
3.366
3.366
V
V
V
A
C
A
17.1 Output voltage VCC
4.5V < VS < 18V
(0mA to 85mA)
Output voltage VCC at
17.2
3V < VS < 4V
VS – VD
low VS
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
21
4986M–AUTO–02/13
9.
Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VS > 3V
IVCC = –15mA
VS,
VCC
17.3 Regulator drop voltage
VD1
200
mV
A
VS > 3V
IVCC = –50mA
VS,
VCC
17.4 Regulator drop voltage
VD2
500
700
mV
A
17.5 Line regulation
17.6 Load regulation
4V < VS < 18V
VCC
VCC
VCCline
VCCload
0.1
0.1
0.2
0.5
%
%
A
A
5mA < IVCC < 50mA
10Hz to 100kHz
Power supply ripple
rejection
17.7
CVCC = 10µF
VCC
VCC
50
dB
D
A
VS = 14V, IVCC = –15mA
17.8 Output current limitation VS > 4V
0.2Ω < ESR < 5Ω at 100kHz
IVCClim
–240
–160
10
–85
mA
for phase margin ≥ 60°
17.9 External load capacity
VCC
Cload
1.8
2.8
µF
D
ESR < 0.2Ω at 100kHz
for phase margin ≥ 30°
VCC undervoltage
threshold
Referred to VCC
VS > 4V
17.10
VCC
VCC
VCC
VthunN
Vhysthun
TVCC
3.2
V
A
A
A
Hysteresis of
17.11
Referred to VCC
undervoltage threshold VS > 4V
150
100
mV
µs
Ramp-up time VS > 4V to CVCC = 2.2µF
17.12
18
250
VCC = 3.3V
Iload = –5mA at VCC
VCC Voltage Regulator ATA6624C/ATA6626C, PVCC = VCC
5.5V < VS < 18V
VCC
VCCnor
VCCnor
VCClow
VD1
4.9
4.9
5.1
5.1
V
V
A
C
A
A
A
A
(0mA to 50mA)
18.1 Output voltage VCC
6V < VS < 18V
(0mA to 85mA)
VCC
VCC
Output voltage VCC at
low VS
18.2
4V < VS < 5.5V
VS – VD
5.1
V
VS > 4V
VS,
18.3 Regulator drop voltage
18.4 Regulator drop voltage
18.5 Regulator drop voltage
250
600
200
mV
mV
mV
IVCC = –20mA
VCC
VS > 4V
VS,
VD2
400
IVCC = –50mA
VCC
VS > 3.3V
VS,
VD3
IVCC = –15mA
VCC
18.6 Line regulation
18.7 Load regulation
5.5V < VS < 18V
VCC
VCC
VCCline
VCCload
0.1
0.1
0.2
0.5
%
%
A
A
5mA < IVCC < 50mA
10Hz to 100kHz
CVCC = 10µF
VS = 14V, IVCC = –15mA
Power supply ripple
rejection
18.8
VCC
VCC
50
dB
D
A
18.9 Output current limitation VS > 5.5V
IVCClim
–240
–130
10
–85
mA
0.2Ω < ESR < 5Ω at 100kHz
for phase margin ≥ 60°
18.10 External load capacity
VCC
Cload
1.8
µF
D
ESR < 0.2Ω at 100kHz
for phase margin ≥ 30°
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
22
4986M–AUTO–02/13
9.
Electrical Characteristics (Continued)
5V < VS < 27V, -40°C < Tj < 150°C, unless otherwise specified. All values refer to GND pins
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
VCC undervoltage
threshold
Referred to VCC
VS > 5.5V
18.11
18.12
18.13
VCC
VthunN
4.2
4.8
V
A
Hysteresis of
undervoltage threshold VS > 5.5V
Referred to VCC
VCC
VCC
Vhysthun
tVCC
250
130
mV
µs
A
A
Ramp-up time VS > 5.5V CVCC = 2.2µF
to VCC = 5V
300
Iload = –5mA at VCC
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 9-1. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
receiving node1
THRec(max)
VS
THDom(max)
(Transceiver supply
of transmitting node)
LIN Bus Signal
Thresholds of
receiving node2
THRec(min)
THDom(min)
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
trx_pdf(2)
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
23
4986M–AUTO–02/13
Figure 9-2. Typical Application Circuit
Ignition
KL15
VBattery
KL30
22μF
100nF
+
47kΩ
Master node
pull-up
100nF
+
1kΩ
10kΩ
Debug
100nF 10μF
20 19 18 17 16
10kΩ
51kΩ
EN
MODE
TM
1
2
3
4
5
15
14
13
12
11
VCC
ATA6622C
ATA6624C
ATA6626C
10kΩ
WD_OSC
NTRIG
WAKE
GND
33kΩ
NRES
TXD
Microcontroller
MLP 5mm x 5mm
0.65mm pitch
20 lead
Wake
switch
EN
6
7
8
9
10
NTRIG
RXD
220pF
TXD
RESET
GND
INH
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
24
4986M–AUTO–02/13
Figure 9-3. Application Circuit with External NPN-Transistor
Ignition
KL15
VBattery
KL30
*)
22μF
10kΩ
100nF
+
MJD31C
47kΩ
+
Master node
pull-up
2.2μF
100nF
3.3Ω
+
1kΩ
Debug
100nF 10μF
20 19 18 17 16
10kΩ
51kΩ
EN
MODE
TM
1
2
3
4
5
15
14
13
12
11
ATA6622C
ATA6624C
ATA6626C
VCC
10kΩ
WD_OSC
NTRIG
WAKE
GND
33kΩ
NRES
TXD
Microcontroller
MLP 5mm x 5mm
0.65mm pitch
20 lead
Wake
switch
EN
6
7
8
9
10
NTRIG
RXD
220pF
TXD
RESET
GND
INH
*) Note that the output voltage PVCC is no longer short-ciruit protected when boosting the output current by an external NPN-transistor.
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
25
4986M–AUTO–02/13
Figure 9-4. LIN Slave Application with Minimum External Devices
VBAT
C2
+
22μF/50V
VCC
C5
C3
C1
100nF
+
100nF
10μF
20 19 18 17 16
EN
1
MODE
TM
15
14
13
12
11
GND
2
ATA6622C
ATA6624C
ATA6626C
WD_OSC
NTRIG
WAKE
GND
VCC
3
4
5
VCC
NRES
TXD
Microcontroller
6
7
8
9
10
EN
NTRIG
C4
RXD
TXD
220pF
R9
10kΩ
VCC
RESET
GND
Note: No watchdog, INH output not used, no local wake-up
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
26
4986M–AUTO–02/13
10. Ordering Information
Extended Type Number
ATA6622C-PGQW
Package
QFN20
QFN20
QFN20
Remarks
3.3V LIN system-basis-chip, Pb-free, 6k, taped and reeled
5V LIN system-basis-chip, Pb-free, 6k, taped and reeled
5V LIN system-basis-chip, Pb-free, 6k, taped and reeled
ATA6624C-PGQW
ATA6626C-PGQW
11. Package Information
Bottom
0
3.1 0.15
0.05-0.05
Top
20
16
20
1
15
1
5
Pin 1 identification
11
5
10
6
0.2
0.9 0.1
0.65 nom.
5
2.6
technical drawings
according to DIN
specifications
0.28 0.07
Dimensions in mm
Not indicated tolerances 0.05
09/02/07
TITLE
DRAWING NO.
6.543-5129.01-4
REV.
GPC
Package Drawing Contact:
packagedrawings@atmel.com
Package: VQFN_5x5_20L
Exposed pad 3.1x3.1
2
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
27
4986M–AUTO–02/13
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this
document.
Revision No.
History
4986M-AUTO-02/13
4986L-AUTO-11/12
4986K-AUTO-01/12
• Section 10 “Ordering Information” on page 27 updated
• Section 10 “Ordering Information” on page 27 updated
• Table 2-1 “Pin Description” on page 3 changed
• Features on page 1 changed
• Section 1 “Description” on pages 1 to 2 changed
• Table 2-1 “Pin Description” on page 3 changed
• Section 3 “Functional Description” on pages 4 to 6 changed
• Section 4 “Modes of Operation” on pages 7 to 11 changed
• Section 5 “Wake-up Scenarios from Silent to Sleep Mode” on pages 12 to 14 changed
• Section 7 “Absolute Maximum Ratings” on page 17 changed
• Section 9 “Electrical Characteristics” on pages 18 to 26 changed
• Section 6 “Watchdog” on pages 15 to 16 changed
• New Part numbers ATA6622C, ATA6624C and ATA6626C added
• Features on page 1 changed
4986J-AUTO-03/11
4986I-AUTO-07/10
• Pin Description table: rows Pin 4 and Pin 15 changed
• Text under headings 3.3, 3.9, 3.11, 5.5 and 6 changed
• Figures 4-5, 6-1 and 9-3 changed
• Abs.Max.Rat.Table -> Values in row “ESD HBM following....” changed
4986H-AUTO-05/10
• El.Char.Table -> rows changed: 7.1, 12.1, 12.2, 17.5, 17.6, 17.7, 17.8, 18.6, 18.7, 18.8,
18.9
• El.Char.Table -> row 8.13 added
• Figures 9-2 and 9-3 figure title changed
• Figure 9-4 on page 27 added
• Ord.Info.Table -> new part numbers added
• complete datasheet: “LIN 2.0 specification” changed in “LIN 2.1 specification”
• Figures changed: 1-1, 4-2, 4-3, 4-4, 4-5, 5-1, 9-2, 9-3
• Sections changed: 3.1, 3.6, 3.8, 3.9, 3.10, 3.14, 4.1, 4.2, 4,3, 5.1, 5.2, 5.3, 5.5, 5.6
• Features and Description changed
4986G-AUTO-08/09
• Table 4-1 changed
• Abs. Max. Ratings table changed
• Thermal Characteristics table inserted
• El. Characteristics table changed
• Section 3.15 “INH Output Pin” on page 6 changed
• Section 5.5 “Fail-safe Features” on page 13 changed
• Section 6.1 “Typical Timing Sequence with RWD_OSC = 51 kΩ” on page 15 changed
• Section 8 “Electrical Characteristics” numbers 1.6 to 1.8 on page 18 changed
• Figure 2-1 on page 3 renamed
4986F-AUTO-05/08
4986E-AUTO-02/08
• Figure 6-1 “Timing Sequence with RWD_OSC = 51 kΩ” on page 16 changed
• Figure 8-3 “Application Circuit with External NPN” on page 26 added
Atmel ATA6622C/ATA6624C/ATA6626C [DATASHEET]
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4986M–AUTO–02/13
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© 2013 Atmel Corporation. All rights reserved. / Rev.: 4986M–AUTO–02/13
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