ATA6623C [ATMEL]
Linear Low-drop Voltage Regulator; 线性低压降稳压器
| 型号： | ATA6623C |
| 厂家： | 
ATMEL |
| 描述： | Linear Low-drop Voltage Regulator |
| 文件： | 总24页 (文件大小：681K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage up to 40V
• Operating Voltage VS = 5V to 27V
• Typically 10 µA Supply Current During Sleep Mode
• Typically 57 µA Supply Current in Silent Mode
• Linear Low-drop Voltage Regulator:
– Normal, Fail-safe, and Silent Mode
– ATA6623: VCC = 3.3V ±2%
– ATA6625: VCC = 5.0V ±2%
LIN Bus
– Sleep Mode: VCC is Switched Off
• VCC Undervoltage Detection with Reset Open Drain Output NRES (4 ms Reset Time)
• Voltage Regulator is Short-circuit and Over-temperature Protected
• LIN Physical Layer According to LIN 2.0, 2.1 and SAEJ2602-2
• Wake-up Capability via LIN Bus (90 µs Dominant)
• TXD Time-out Timer
• Bus Pin is Overtemperature and Short-circuit Protected versus GND and Battery
• Advanced EMC and ESD Performance
• Fulfills the OEM “Hardware Requirements for LIN in Automotive Applications Rev1.0”
• Interference and Damage Protection According to ISO7637
• Package: SO8
Transceiver
with Integrated
Voltage
Regulator
ATA6623
ATA6625
ATA6623C
ATA6625C
1. Description
ATA6623/ATA6625 is a fully integrated LIN transceiver, designed according to the LIN
specification 2.0 and 2.1, with a low-drop voltage regulator (3.3V/5V/50 mA). The
combination of voltage regulator and bus transceiver makes it possible to develop
simple, but powerful, slave nodes in LIN Bus systems. ATA6623/ATA6625 is
designed to handle the low-speed data communication in vehicles (for example, in
convenience electronics). Improved slope control at the LIN driver ensures secure
data communication up to 20 kBaud with an RC oscillator for the protocol handling.
The bus output is designed to withstand high voltage. Sleep Mode (voltage regulator
switched off) and Silent Mode (communication off; VCC voltage on) guarantee mini-
mized current consumption.
4957H–AUTO–05/10
Figure 1-1. Block Diagram
1
VS
ATA6623/25
VCC
Normal
Mode
RXD
Receiver
5
-
+
4
LIN
RF-filter
VCC
Wake-up bus timer
Slew rate control
Short circuit and
overtemperature
protection
TXD
TXD
Time-out
timer
6
8
VCC
Normal/Silent/
Fail-safe Mode
3.3V/50 mA/±2%
5V/50 mA/±2%
Sleep
mode
VCC
switched
EN
7
2
NRES
Control
unit
GND
3
off
Undervoltage reset
2. Pin Configuration
Figure 2-1. Pinning SO8
VS
EN
1
2
3
4
8
VCC
NRES
TXD
7
6
5
GND
LIN
RXD
Table 2-1.
Pin Description
Pin
1
Symbol
VS
Function
Battery supply
2
EN
Enables Normal Mode if the input is high
Ground, heat sink
3
GND
LIN
4
LIN bus line input/output
5
RXD
TXD
NRES
VCC
Receive data output
6
Transmit data input
7
Output undervoltage reset, low at reset
Output voltage regulator 3.3V/5V/50 mA
8
2
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
3. Functional Description
3.1
Physical Layer Compatibility
Since the LIN physical layer is independent from higher LIN layers (e.g., LIN protocol layer), all
nodes with a LIN physical layer according to revision 2.x can be mixed with LIN physical layer
nodes, which are according to older versions (i.e., LIN 1.0, LIN 1.1, LIN 1.2, LIN 1.3) without any
restrictions.
3.2
Supply Pin (VS)
LIN operating voltage is VS = 5V to 27V. An undervoltage detection is implemented to disable
transmission if VS falls below 5V, in order to avoid false bus messages. After switching on VS,
the IC starts with the Fail-safe Mode and the voltage regulator is switched on (i.e.,
3.3V/5V/50 mA).
The supply current in Sleep Mode is typically 10 µA and 57 µA in Silent Mode.
3.3
3.4
Ground Pin (GND)
The IC does not affect the LIN Bus in the event of GND disconnection. It is able to handle a
ground shift up to 11.5% of VS.
Voltage Regulator Output Pin (VCC)
The internal 3.3V/5V voltage regulator is capable of driving loads with up to 50 mA, supplying
the microcontroller and other ICs on the PCB and is protected against overload by means of cur-
rent limitation and overtemperature shut-down. Furthermore, the output voltage is monitored
and will cause a reset signal at the NRES output pin if it drops below a defined threshold Vthun
.
3.5
3.6
Undervoltage Reset Output (NRES)
If the VCC voltage falls below the undervoltage detection threshold of Vthun, NRES switches to
low after tres_f (Figure 6-1 on page 11). Even if VCC = 0V the NRES stays low, because it is
internally driven from the VS voltage. If VS voltage ramps down, NRES stays low until VS < 1.5V
and then becomes highly resistant.
The implemented undervoltage delay keeps NRES low for tReset = 4 ms after VCC reaches its
nominal value.
Bus Pin (LIN)
A low-side driver with internal current limitation and thermal shutdown as well as an internal
pull-up resistor according to LIN specification 2.x is implemented. The voltage range is from
–27V to +40V. This pin exhibits no reverse current from the LIN bus to VS, even in the event of a
GND shift or VBatt disconnection. The LIN receiver thresholds are compatible with the LIN proto-
col specification.
The fall time (from recessive to dominant) and the rise time (from dominant to recessive) are
slope controlled.
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4957H–AUTO–05/10
3.7
3.8
Input Pin (TXD)
In Normal Mode the TXD pin is the microcontroller interface to control the state of the LIN output.
TXD must be pulled to ground in order to drive the LIN bus low. If TXD is high or unconnected
(internal pull-up resistor), the LIN output transistor is turned off and the bus is in the recessive
state.
Dominant Time-out Function (TXD)
The TXD input has an internal pull-up resistor. An internal timer prevents the bus line from being
driven permanently in the dominant state. If TXD is forced to low longer than tDOM > 6 ms, the
LIN bus driver is switched to the recessive state.
To reactivate the LIN bus driver, switch TXD to high (> 10 µs).
3.9
Output Pin (RXD)
This output pin reports the state of the LIN-bus to the microcontroller. LIN high (recessive state)
is reported by a high level at RXD; LIN low (dominant state) is reported by a low level at RXD.
The output has an internal pull-up resistor with typically 5 kΩ to VCC. The AC characteristics are
measured with an external load capacitor of 20 pF.
The output is short-circuit protected. In Unpowered Mode (that is, VS = 0V), RXD is switched off.
3.10 Enable Input Pin (EN)
The Enable Input pin controls the operation mode of the device. If EN is high, the circuit is in
Normal Mode, with transmission paths from TXD to LIN and from LIN to RXD both active. The
VCC voltage regulator operates with 3.3V/5V/50 mA output capability.
If EN is switched to low while TXD is still high, the device is forced to Silent Mode. No data trans-
mission is then possible, and the current consumption is reduced to IVS typ. 57 µA. The VCC
regulator has its full functionality.
If EN is switched to low while TXD is low, the device is forced to Sleep Mode. No data transmis-
sion is possible, and the voltage regulator is switched off.
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ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
4. Mode of Operation
Figure 4-1. Mode of Operation
a: VS > 5V
b: VS < 4V
Unpowered Mode
VBatt = 0V
c: Bus wake-up event
d: NRES switches to low
b
a
Fail-safe Mode
b
b
VCC: 3.3V/5V/50 mA
with undervoltage monitoring
Communication: OFF
c + d
d
EN = 1
EN = 1
c
b
Go to silent command
Local wake-up event
EN = 0
Silent Mode
TXD = 1
VCC: 3.3V/5V/50 mA
with undervoltage monitoring
Normal Mode
EN = 1
Communication: OFF
VCC: 3.3V/5V/50 mA
with undervoltage
monitoring
Go to sleep command
EN = 0
Communication: ON
Sleep Mode
VCC: switched off
Communication: OFF
TXD = 0
Table 4-1.
Mode of
Mode of Operation
Operation
Transceiver
VCC
RXD
LIN
High,
Fail safe
OFF
3.3V/5V
Recessive
Except after wake-up
Normal
Silent
ON
OFF
OFF
3.3V/5V
3.3V/5V
0V
LIN depending
TXD depending
Recessive
High
0V
Sleep
Recessive
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4957H–AUTO–05/10
4.1
4.2
Normal Mode
Silent Mode
This is the normal transmitting and receiving Mode of the LIN Interface, in accordance with LIN
specification 2.x. The VCC voltage regulator operates with a 3.3V/5V output voltage, with a low
tolerance of ±2% and a maximum output current of 50 mA.
If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to
Fail-safe Mode.
A falling edge at EN while TXD is high switches the IC into Silent Mode. The TXD Signal has to
be logic high during the Mode Select window (Figure 4-2 on page 7). The transmission path is
disabled in Silent Mode. The overall supply current from VBatt is a combination of the
IVSsi = 57 µA plus the VCC regulator output current IVCC
.
The 3.3V/5V regulator with 2% tolerance can source up to 50 mA. In Silent Mode the internal
slave termination between pin LIN and pin VS is disabled, and only a weak pull-up current (typi-
cally 10 µA) between pin LIN and pin VS is present. The Silent Mode can be activated
independently from the current level on pin LIN.
If an undervoltage condition occurs, NRES is switched to low and the IC changes its state to
Fail-safe Mode.
A voltage less than the LIN Pre-wake detection VLINL at pin LIN activates the internal LIN
receiver and switches on the internal slave termination between the LIN pin and the VS pin.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time
period (tbus) and the following rising edge at pin LIN (see Figure 4-3 on page 7) results in a
remote wake-up request.
The device switches from Silent Mode to Fail-safe Mode, and the remote wake-up request is
indicated by a low level at pin RXD to interrupt the microcontroller (Figure 4-3 on page 7). EN
high can be used to switch directly to Normal Mode.
6
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
Figure 4-2. Switch to Silent Mode
Normal Mode
Silent Mode
EN
Mode select window
TXD
td = 3.2 µs
NRES
VCC
Delay time silent mode
td_silent = maximum 20 µs
LIN
LIN switches directly to recessive mode
Figure 4-3. LIN Wake-up Waveform Diagram from Silent Mode
Bus wake-up filtering time
tbus
Fail-safe mode
Normal mode
LIN bus
RXD
High
Low
VCC
Silent mode 3.3V/5V/50 mA
Fail-safe mode 3.3V/5V/50 mA
Normal mode
EN High
EN
Undervoltage detection active
NRES
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4957H–AUTO–05/10
4.3
Sleep Mode
A falling edge at EN while TXD is low switches the IC into Sleep Mode. The TXD Signal has to
be logic low during the Mode Select window (Figure 4-4 on page 8). To avoid influencing the
LIN-pin during the switch to sleep mode, it is possible to switch the EN up to 3.2 µs earlier to
LOW than the TXD. Even if the two falling edges at TXD and EN occur at the same time, the LIN
line will remain uninfluenced.
In Sleep Mode the transmission path is disabled. The supply current IVSsleep from VBatt is typically
10 µA. The VCC regulator is switched off, NRES and RXD are low. The internal slave termination
between pin LIN and pin VS is disabled, only a weak pull-up current (typically 10 µA) between
pin LIN and pin VS is present. Sleep Mode can be activated independently from the current level
on pin LIN.
A voltage less than the LIN Pre-wake detection VLINL at pin LIN activates the internal LIN
receiver and switches on the internal slave termination between the LIN pin and the VS pin.
A falling edge at the LIN pin followed by a dominant bus level maintained for a certain time
period (tbus) and a following rising edge at pin LIN results in a remote wake-up request. The
device switches from Sleep Mode to Fail-safe Mode.
The VCC regulator is activated, and the remote wake-up request is indicated by a low level at the
RXD pin to interrupt the microcontroller (Figure 4-5 on page 9).
EN high can be used to switch directly from Sleep to Fail-safe Mode. If EN is still high after VCC
ramp up and undervoltage reset time, the IC switches to Normal Mode.
Figure 4-4. Switch to Sleep Mode
Normal Mode
Sleep Mode
EN
Mode select window
TXD
t
d = 3.2 µs
NRES
VCC
Delay time sleep mode
td_sleep = maximum 20 µs
LIN
LIN switches directly to recessive mode
8
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
Figure 4-5. LIN Wake-up Diagram from Sleep Mode
Bus wake-up filtering time
tbus
Fail-safe Mode
Normal Mode
LIN bus
RXD
VCC
Low or floating
Low
On state
voltage
regulator
Off state
Regulator wake-up time
EN High
EN
Reset
time
NRES
Low or floating
Microcontroller
start-up time delay
4.4
4.5
Fail-safe Mode
At system power-up the device automatically switches to Fail-safe Mode. The voltage regulator
is switched on (VCC = 3.3V/5V/50 mA), (see Figure 6-1 on page 11). The NRES output switches
to low for tres = 4 ms and gives a reset to the microcontroller. LIN communication is switched off.
The IC stays in this mode until EN is switched to high, and changes then to the Normal Mode. A
power down of VBatt (VS < 4V) during Silent- or Sleep Mode switches the IC into the Fail-safe
Mode after power up. A logic low at NRES switches the IC into Fail-safe Mode directly.
Unpowered Mode
If you connect battery voltage to the application circuit, the voltage at the VS pin increases
according to the block capacitor (see Figure 6-1 on page 11). After VS is higher than the VS
undervoltage threshold VSth, the IC mode changes from Unpowered Mode to Fail-safe Mode.
The VCC output voltage reaches its nominal value after tVCC. This time, tVCC, depends on the
VCC capacitor and the load.
NRES is low for the reset time delay tReset; no mode change is possible during this time.
9
4957H–AUTO–05/10
5. Fail-safe Features
• During a short-circuit at LIN to VBattery, the output limits the output current to IBUS_lim. Due to
the power dissipation, the chip temperature exceeds TLINoff and the LIN output is switched off.
The chip cools down and after a hysteresis of Thys, switches the output on again. RXD stays
on high because LIN is high. During LIN overtemperature switch-off, the VCC regulator is
working independently.
• During a short-circuit from LIN to GND the IC can be switched into Sleep or Silent Mode. If
the short-circuit disappears, the IC starts with a remote wake-up.
• The reverse current is very low < 2 µA at pin LIN during loss of VBatt. This is optimal behavior
for bus systems where some slave nodes are supplied from battery or ignition.
• During a short circuit at VCC, the output limits the output current to IVCClim. Because of
undervoltage, NRES switches to low and sends a reset to the microcontroller. The IC
switches into Fail-safe Mode. If the chip temperature exceeds the value TVCCoff, the VCC
output switches off. The chip cools down and after a hysteresis of Thys, switches the output on
again. Because of Fail-safe Mode, the VCC voltage will switch on again although EN is
switched off from the microcontroller. The microcontroller can then start with normal
operation.
• Pin EN provides a pull-down resistor to force the transceiver into Recessive Mode if EN is
disconnected.
• Pin RXD is set floating if VBatt is disconnected.
• Pin TXD provides a pull-up resistor to force the transceiver into Recessive Mode if TXD is
disconnected.
• If TXD is short-circuited to GND, it is possible to switch to Sleep Mode via ENABLE after
tdom > 20 ms.
10
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
6. Voltage Regulator
Figure 6-1. VCC Voltage Regulator: Ramp Up and Undervoltage
VS
12V
5.5V/3.8V
VCC
5V/3.3V
Vthun
tVCC
tReset
tres_f
NRES
5V/3.3V
The voltage regulator needs an external capacitor for compensation and to smooth the distur-
bances from the microcontroller. It is recommended to use an electrolythic capacitor with
C > 1.8 µF and a ceramic capacitor with C = 100 nF. The values of these capacitors can be var-
ied by the customer, depending on the application.
With this special SO8 package (fused lead frame to pin 3) an Rthja of 80 K/W is achieved.
Therefore, it is recommended to connect pin 3 with a wide GND plate on the printed board to get
a good heat sink.
The main power dissipation of the IC is created from the VCC output current IVCC, which is
needed for the application.
Figure 6-2 shows the safe operating area of the ATA6623/ATA6625.
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4957H–AUTO–05/10
Figure 6-2. Power Dissipation: Save Operating Area versus VCC Output Current and Supply
Voltage VS at Different Ambient Temperatures Due to Rthja = 80 K/W
60.00
T
T
= 85°C
= 95°C
50.00
40.00
amb
amb
T
= 105°C
amb
30.00
20.00
10.00
0.00
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19
VS (V)
To program the microcontroller it may be necessary to supply the VCC output via an external
power supply while the VS Pin of the system basis chip is disconnected. This issue does not
occur with the system basis chip.
12
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
7. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Min.
Typ.
Max.
Unit
Supply voltage VS
VS
–0.3
+40
V
Pulse time ≤ 500 ms
Ta = 25°C
Output current IVCC ≤ 50 mA
VS
VS
+40
27
V
V
Pulse time ≤ 2 min
Ta = 25°C
Output current IVCC ≤ 50 mA
Logic pins (RxD, TxD, EN, NRES)
Output current NRES
–0.3
+5.5
+2
V
INRES
mA
LIN
- DC voltage
–27
+40
V
V
VCC
- DC voltage
–0.3
+5.5
ESD according to IBEE LIN EMC
Test specification 1.0 following IEC 61000-4-2
- Pin VS, LIN to GND
±6
KV
ESD HBM following STM5.1
with 1.5 kΩ/100 pF
- Pin VS, LIN to GND
±6
±3
KV
KV
HBM ESD
ANSI/ESD-STM5.1
JESD22-A114
AEC-Q100 (002)
CDM ESD STM 5.3.1
±750
±200
V
V
Machine Model ESD
AEC-Q100-RevF(003)
Junction temperature
Storage temperature
Tj
–40
–55
+150
+150
°C
°C
Ts
8. Thermal Characteristics
Parameters
Symbol
Min.
Typ.
Max.
Unit
Thermal resistance junction to ambient
(free air)
Rthja
145
K/W
Special heat sink at GND (pin 3) on PCB
Thermal shutdown of VCC regulator
Thermal shutdown of LIN output
Thermal shutdown hysteresis
Rthja
TVCCoff
TLINoff
Thys
80
160
160
10
K/W
°C
150
150
170
170
°C
°C
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4957H–AUTO–05/10
9. Electrical Characteristics
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
VS Pin
Nominal DC voltage
range
1.1
VS
VS
VS
5
3
13.5
10
27
14
V
A
A
Sleep Mode
VLIN > VS – 0.5V
IVSsleep
µA
VS < 14V (Tj = 25°C)
Supply current in Sleep
Mode
1.2
1.3
Sleep Mode
VLIN > VS – 0.5V
VS < 14V (Tj = 125°C)
VS
VS
VS
VS
VS
VS
IVSsleep
5
11
57
66
16
67
76
0.8
53
µA
µA
µA
mA
mA
µA
A
A
A
A
A
A
Bus recessive
VS < 14V (Tj = 25°C)
Without load at VCC
IVSsi
47
56
0.3
50
Supply current in Silent
Mode
Bus recessive
VS < 14V (Tj = 125°C)
Without load at VCC
IVSsi
Bus recessive
VS < 14V
Without load at VCC
Supply current in Normal
Mode
1.4
1.5
IVSrec
IVSdom
IVSspeed
Bus dominant
VS < 14V
VCC load current 50 mA
Supply current in Normal
Mode
Bus recessive
VS < 14V
Without load at VCC
Supply current in
Fail-safe Mode
1.6
1.7
200
4.0
500
5
VS undervoltage
threshold
VS
VS
VSth
4.5
0.2
V
V
A
A
VS undervoltage
threshold hysteresis
1.8
VSth_hys
2
RXD Output Pin
Normal Mode
VLIN = 0V
VRXD = 0.4V
Low level output sink
current
2.1
RXD
IRXD
1.3
3
2.5
5
8
mA
A
2.2
2.3
3
Low level output voltage IRXD = 1 mA
Internal resistor to VCC
TXD Input Pin
RXD
RXD
VRXDL
RRXD
0.4
7
V
A
A
kΩ
3.1
Low level voltage input
TXD
TXD
TXD
TXD
VTXDL
VTXDH
RTXD
ITXD
–0.3
2
+0.8
V
V
A
A
A
A
VCC
+
3.2
3.3
3.4
High level voltage input
0.3V
Pull-up resistor
V
TXD = 0V
125
–3
250
400
kΩ
µA
High level leakage
current
VTXD = VCC
+3
*) Type means: A = 100% tested, B = 100% correlation tested, C = Charact1
erized on samples, D = Design parameter
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4957H–AUTO–05/10
ATA6623/ATA6625
9. Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
4
EN Input Pin
4.1
Low level voltage input
EN
EN
VENL
VENH
–0.3
2
+0.8
V
V
A
A
VCC
+
4.2
High level voltage input
0.3V
4.3
4.4
5
Pull-down resistor
VEN = VCC
VEN = 0V
EN
EN
REN
IEN
50
–3
125
200
+3
kΩ
A
A
Low level input current
µA
NRES Open Drain Output Pin
VS ≥ 5.5V
5.1
5.2
5.3
Low level output voltage
Low level output low
NRES
NRES
NRES
NRES
I
NRES = 1 mA
VNRESL
0.14
0.14
V
V
A
A
10 kΩ to 5V
VCC = 0V
VNRESLL
VS ≥ 5.5V
CNRES = 20 pF
Undervoltage reset time
tReset
tres_f
2
4
6
ms
µs
A
A
Reset debounce time for VS ≥ 5.5V
5.4
6
1.5
10
falling edge
CNRES = 20 pF
VCC Voltage Regulator ATA6623
4V < VS < 18V
(0 mA to 50 mA)
6.1
Output voltage VCC
VCC
VCC
VCCnor
VCClow
3.234
3.366
3.366
V
V
A
A
Output voltage VCC at
low VS
VS –
VDrop
6.2
3V < VS < 4V
6.3
6.4
6.5
6.6
Regulator drop voltage VS > 3V, IVCC = –15 mA
Regulator drop voltage VS > 3V, IVCC = –50 mA
VCC
VCC
VCC
VCC
VD1
VD2
200
700
0.2
mV
mV
%
A
A
A
A
500
0.1
0.1
Line regulation
Load regulation
4V < VS < 18V
VCCline
VCCload
5 mA < IVCC < 50 mA
0.5
%
10 Hz to 100 kHz
CVCC = 10 µF
VS = 14V, IVCC = –15 mA
Power supply ripple
rejection
6.7
VCC
VCC
50
dB
D
6.8
6.9
Output current limitation VS > 4V
IVCClim
Cload
–240
1.8
–160
10
–85
3.2
mA
µF
A
D
Load capacity
0.2Ω< ESR < 5Ωat 100 kHz VCC
VCC undervoltage
threshold
Referred to VCC
VCC
6.10
6.11
VthunN
Vhysthun
tVCC
2.8
V
A
A
A
VS > 4V
Hysteresis of
Referred to VCC
VCC
150
100
mV
µs
undervoltage threshold VS > 4V
Ramp up time VS > 4V
to VCC = 3.3V
CVCC = 2.2 µF
6.12
7
VCC
250
Iload = –5 mA at VCC
VCC Voltage Regulator ATA6625
5.5V < VS < 18V
(0 mA to 50 mA)
7.1
Output voltage VCC
VCC
VCC
VCCnor
VCClow
4.9
5.1
5.1
V
V
A
A
Output voltage VCC at
low VS
7.2
4V < VS < 5.5V
VS – VD
7.3
7.4
Regulator drop voltage VS > 4V, IVCC = –20 mA
Regulator drop voltage VS > 4V, IVCC = –50 mA
VCC
VCC
VD1
VD2
250
600
mV
mV
A
A
400
*) Type means: A = 100% tested, B = 100% correlation tested, C = Charact1
erized on samples, D = Design parameter
15
4957H–AUTO–05/10
9. Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
VD3
Min.
Typ.
Max.
200
0.2
Unit
mV
%
Type*
7.5
7.6
7.7
Regulator drop voltage VS > 3.3V, IVCC = –15 mA
VCC
VCC
VCC
A
A
A
Line regulation
Load regulation
5.5V < VS < 18V
VCCline
VCCload
0.1
0.1
5 mA < IVCC < 50 mA
0.5
%
10 Hz to 100 kHz
CVCC = 10 µF
VS = 14V, IVCC = –15 mA
Power supply ripple
rejection
7.8
VCC
50
dB
D
7.9
Output current limitation VS > 5.5V
VCC
IVCClim
Cload
–240
1.8
–160
10
–85
4.8
mA
µF
A
D
7.10 Load capacity
0.2Ω< ESR < 5Ωat 100 kHz VCC
VCC undervoltage
threshold
Referred to VCC
VCC
7.11
VthunN
Vhysthun
tVCC
4.2
V
A
A
A
VS > 5.5V
Hysteresis of
7.12
Referred to VCC
VCC
250
130
mV
µs
undervoltage threshold VS > 5.5V
Ramp up time VS > 5.5V CVCC = 2.2 µF
to VCC = 5V load = –5 mA at VCC
7.13
8
VCC
300
I
LIN Bus Driver: Bus Load Conditions:
Load 1 (Small): 1 nF, 1 kΩ, Load 2 (Large): 10 nF, 500Ω, Internal Pull-up RRXD = 5 kΩ, CRXD = 20 pF,
Load 3 (Medium): 6.8 nF, 660Ω, Characterized on Samples
10.6 and 10.7 Specifies the Timing Parameters for Proper Operation at 20 kBit/s and 10.8 and 10.9 at 10.4 kBit/s
Driver recessive output
voltage
8.1
Load1/Load2
LIN
VBUSrec
0.9 × VS
VS
V
A
8.2
8.3
8.4
8.5
Driver dominant voltage VVS = 7V, Rload = 500Ω
Driver dominant voltage VVS = 18V, Rload = 500Ω
Driver dominant voltage VVS = 7V, Rload = 1000Ω
Driver dominant voltage VVS = 18V, Rload = 1000Ω
LIN
LIN
LIN
LIN
V_LoSUP
V_HiSUP
V_LoSUP_1k
V_HiSUP_1k
1.2
2
V
V
V
V
A
A
A
A
0.6
0.8
The serial diode is
Pull–up resistor to VS
8.6
8.7
8.8
LIN
LIN
LIN
RLIN
20
0.4
40
30
60
1.0
200
kΩ
V
A
D
A
mandatory
Voltage drop at the serial In pull-up path with Rslave
VSerDiode
IBUS_lim
diodes
ISerDiode = 10 mA
LIN current limitation
120
mA
VBUS = VBatt_max
Input leakage current at Input Leakage current
the receiver including
pull-up resistor as
specified
Driver off
VBUS = 0V
VBatt = 12V
8.9
LIN IBUS_PAS_dom
–1
–0.35
mA
µA
A
A
Driver off
8V < VBatt < 18V
8V < VBUS < 18V
Leakage current LIN
recessive
8.10
LIN
LIN
IBUS_PAS_rec
10
20
VBUS ≥ VBatt
Leakage current when
control unit disconnected
from ground. Loss of
local ground must not
affect communication in
the residual network
GNDDevice = VS
VBatt = 12V
0V < VBUS < 18V
8.11
IBUS_NO_gnd
–10
+0.5
+10
µA
A
*) Type means: A = 100% tested, B = 100% correlation tested, C = Charact1
erized on samples, D = Design parameter
16
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
9. Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Leakage current at
disconnected battery.
Node has to sustain the VBatt disconnected
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
8.12 current that can flow
VSUP_Device = GND
under this condition. Bus 0V < VBUS < 18V
must remain operational
LIN
IBUS_NO_bat
0.1
2
µA
A
under this condition.
Capacitance on Pin LIN
to GND
8.13
9
LIN
LIN
CLIN
20
pF
V
D
A
LIN Bus Receiver
Center of receiver
threshold
VBUS_CNT
(Vth_dom + Vth_rec)/2
=
0.475 ×
0.5 ×
VS
0.525 ×
9.1
VBUS_CNT
VS
VS
9.2
9.3
Receiver dominant state VEN = 5V
Receiver recessive state VEN = 5V
Receiver input
LIN
LIN
VBUSdom
VBUSrec
–27
0.4 × VS
V
V
A
A
0.6 × VS
40
0.028 ×
0.175 ×
9.4
9.5
Vhys = Vth_rec – Vth_dom
LIN
LIN
LIN
VBUShys
VLINH
0.1 x VS
V
V
V
A
A
A
hysteresis
VS
VS
Pre-wake detection LIN
High level input voltage
VS +
0.3V
VS – 2V
–27
Pre-wake detection LIN
Low level input voltage
9.6
10
Activates the LIN receiver
VLINL
VS – 3.3V
Internal Timers
Dominant time for
wake–up via LIN bus
10.1
VLIN = 0V
VEN = 5V
LIN
EN
tbus
30
5
90
150
20
µs
µs
A
A
Time delay for mode
change from Fail-safe
into Normal Mode via pin
EN
10.2
tnorm
Time delay for mode
change from Normal
Mode to Sleep Mode via
pin EN
10.3
10.4
VEN = 0V
EN
tsleep
2
7
15
µs
A
TXD dominant time out
time
VTXD = 0V
TXD
EN
tdom
6
5
13
15
20
40
ms
µs
A
A
Time delay for mode
10.5 change from Silent Mode VEN = 5V
into Normal Mode via EN
ts_n
THRec(max) = 0.744 × VS
THDom(max) = 0.581 × VS
VS = 7.0V to 18V
tBit = 50 µs
10.6 Duty cycle 1
10.7 Duty cycle 2
LIN
LIN
D1
D2
0.396
A
A
D1 = tbus_rec(min)/(2 × tBit)
THRec(min) = 0.422 × VS
THDom(min) = 0.284 × VS
VS = 7.6V to 18V
0.581
tBit = 50 µs
D2 = tbus_rec(max)/(2 × tBit)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Charact1
erized on samples, D = Design parameter
17
4957H–AUTO–05/10
9. Electrical Characteristics (Continued)
5V < VS < 27V, –40°C < Tj < 150°C; unless otherwise specified all values refer to GND pins.
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
THRec(max) = 0.778 × VS
THDom(max) = 0.616 × VS
VS = 7.0V to 18V
10.8 Duty cycle 3
LIN
D3
0.417
A
tBit = 96 µs
D3 = tbus_rec(min)/(2 × tBit)
THRec(min) = 0.389 × VS
THDom(min) = 0.251 × VS
VS = 7.6V to 18V
tBit = 96 µs
D4 = tbus_rec(max)/(2 × tBit)
10.9 Duty cycle 4
LIN
LIN
D4
0.590
22.5
A
A
Slope time falling and
tSLOPE_fall
tSLOPE_rise
10.10
11
VS = 7.0V to 18V
3.5
µs
rising edge at LIN
Receiver Electrical AC Parameters of the LIN Physical Layer
LIN Receiver, RXD Load Conditions: CRXD = 20 pF
Propagation delay of
receiver Figure 9-1
VS = 7.0V to 18V
trx_pd = max(trx_pdr , trx_pdf
11.1
RXD
trx_pd
6
µs
µs
A
A
)
Symmetry of receiver
11.2 propagation delay rising
edge minus falling edge
VS = 7.0V to 18V
trx_sym = trx_pdr – trx_pdf
RXD
trx_sym
–2
+2
*) Type means: A = 100% tested, B = 100% correlation tested, C = Charact1
erized on samples, D = Design parameter
18
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
Figure 9-1. Definition of Bus Timing Characteristics
tBit
tBit
tBit
TXD
(Input to transmitting node)
tBus_dom(max)
tBus_rec(min)
Thresholds of
THRec(max)
THDom(max)
receiving node1
VS
(Transceiver supply
of transmitting node)
LIN Bus Signal
Thresholds of
THRec(min)
THDom(min)
receiving node2
tBus_dom(min)
tBus_rec(max)
RXD
(Output of receiving node1)
trx_pdf(1)
trx_pdr(1)
RXD
(Output of receiving node2)
trx_pdr(2)
trx_pdf(2)
19
4957H–AUTO–05/10
Figure 9-2. Application Circuit
VCC
VBAT
1
VS
ATA6623/25
VCC
Master
node
+
pull-up
Normal
Mode
RXD
Receiver
-
100 nF 22 µF
5
1 kΩ
+
4
LIN-BUS
RF filter
LIN
220 pF
VCC
Micro-
controller
Wake-up bus timer
Slew rate control
Short circuit and
overtemperature
protection
TXD
TXD
Time-out
timer
6
8
VCC
Normal/Silent/
Fail-safe Mode
3.3V/50 mA/±2%
5V/50 mA/±2%
Sleep
mode
VCC
switched
EN
2
Control
unit
NRES
10 kΩ
7
GND
3
off
Undervoltage reset
100 nF 10 µF
GND
20
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
10. Ordering Information
Extended Type Number
Package
SO8
Remarks
ATA6623-TAPY
3.3V LIN system basis chip, Pb-free, 1k, taped and reeled
5V LIN system basis chip, Pb-free, 1k, taped and reeled
3.3V LIN system basis chip, Pb-free, 4k, taped and reeled
5V LIN system basis chip, Pb-free, 4k, taped and reeled
3.3V LIN system basis chip, Pb-free, 1k, taped and reeled
5V LIN system basis chip, Pb-free, 1k, taped and reeled
3.3V LIN system basis chip, Pb-free, 4k, taped and reeled
5V LIN system basis chip, Pb-free, 4k, taped and reeled
ATA6625-TAPY
SO8
ATA6623-TAQY
SO8
ATA6625-TAQY
SO8
ATA6623C-TAPY
ATA6625C-TAPY
ATA6623C-TAQY
ATA6625C-TAQY
SO8
SO8
SO8
SO8
11. Package Information
Package: SO 8
Dimensions in mm
5±0.2
4.9±0.1
3.7±0.1
3.8±0.1
6±0.2
0.4
1.27
3.81
8
5
technical drawings
according to DIN
specifications
1
4
Drawing-No.: 6.541-5031.01-4
Issue: 1; 15.08.06
21
4957H–AUTO–05/10
12. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• New Part numbers ATA6623C and ATA6625C added
• Features on page 1 changed
• Text under heading 3.3 on page 3 changed
• Text under heading 3.9 on page 4 changed
• Abs.Max.Rat.Table -> Values in row “ESD HBM following....” changed
4957H-AUTO-05/10
• El.Char.Table -> rows changed: 5.1, 5.2, 6.5, 6.6, 6.7, 6.8, 7.6, 7.7,
7.8,7.9, 10.2
• El.Char.Table -> row 8.13 added
• Ord.Info.Table -> Part numbers ATA6623C and ATA6625C added
• Figures changed: 1-1, 4-2, 4-3, 4-4, 4-5, 6-2, 9-2
• Sections changed: 3.1, 3.6, 3.8, 3.9, 3.10, 4.1, 4.2, 4.3, 5
• Description Text changed
4957G-AUTO-09/09
• Table 4-1 changed
• Abs. Max. Ratings table changed
• El. Characteristics table changed
• “Pre-normal Mode” in “Fail-safe Mode” changed
• Section 7 “Absolute Maximum Ratings” on page 13 changed
4957F-AUTO-02/08
4957E-AUTO-10/07
• Section 8 “Electrical Characteristics” numbers 10.5 to 10.10 on pages 17
to 18 changed
• Section 9 “Ordering Information” on page 20 changed
• Features changed
• Block diagram changed
• Application diagram changed
• Text changed under the headings:
3.2, 3.3, 3.4, 3.6, 3.7, 3.8, 3.9, 4, 4.1, 4.2, 4.3, 4.4, 4.5, 5.5, 5.6, 6
4957D-AUTO-07/07
• Figure 4-2, 4-3, 4-4, 4-5, 8-2: changed
• Figure title 6-1: text changed
• Abs. Max. Ratings: row “Output current NRES” added
• El. Char. table: values changed in the following rows:
1.3, 5.1, 5.3, 5.4, 6.9, 6.12, 7.9, 11.1
22
ATA6623/ATA6625
4957H–AUTO–05/10
ATA6623/ATA6625
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Features on page 1 changed
• Table 2-1 “Pin Description” on page 2 changed
• Section 3-1 “Physical Layer Compatibility” on page 3 added
• Section 3-2 “Supply Pin (VS) on page 3 changed
• Section 3-3 “Ground Pin (GND) on page 3 changed
• Section 3-8 “Dominant Time-out Function (TXD)” on page 4 changed
• Section 4-1 “Normal Mode” on page 5 changed
• Section 4-2 “Silent Mode” on page 5 changed
• Figure 4-3 “LIN Wake-up Waveform Diagram from Silent Mode” on page
6 changed
4957C-AUTO-02/07
• Section 4.3 “Sleep Mode” on page 7 changed
• Section 4-5 “Unpowered Mode” on page 7 changed
• Figure 4-4 “Switch to Sleep Mode” on page 8 changed
• Figure 4-6 “VCC Voltage Regulator: Ramp up and Undervoltage” on page
9 changed
• Section 5 “Fail-safe Features on page 9 changed
• Section 6 “Voltage Regulator” on page 10 changed
• Section 7 “Absolute Maximum Ratings” on page 11 changed
• Section 8 “Electrical Characteristics” on pages 12 to 16 changed
• Section 9 “Ordering Information” on page 18 changed
23
4957H–AUTO–05/10
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4957H–AUTO–05/10
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