SY100S834LZC [MICREL]
(±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION CHIP; （ ÷ 1 ÷ 2 ÷4 ）OR （ ÷ 2 ÷ 4 ÷8 ）时钟发生芯片
| 型号： | SY100S834LZC |
| 厂家： | 
MICREL SEMICONDUCTOR |
| 描述： | (±1, ±2, ±4) OR (±2, ±4, ±8) CLOCK GENERATION CHIP |
| 文件： | 总4页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ClockWorks™
SY100S834
SY100S834L
(÷1, ÷2, ÷4) OR (÷2, ÷4, ÷8)
CLOCK GENERATION CHIP
FEATURES
DESCRIPTION
■ 3.3V and 5V power supply options
■ 50ps output-to-output skew
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2,
÷4, ÷8) clock generation chip designed explicitly for low
skew clock generation applications. The internal dividers
are synchronous to each other, therefore, the common
output edges are all precisely aligned. The devices can
be driven by either a differential or single-ended ECL or,
if positive power supplies are used, PECL input signal.
In addition, by using the VBB output, a sinusoidal source
can be AC-coupled into the device. If a single-ended
input is to be used, the VBB output should be connected
to the CLK input and bypassed to ground via a 0.01µF
capacitor. The VBB output is designed to act as the
switching reference for the input of the SY100S834/L
under single-ended input conditions. As a result, this pin
can only source/sink up to 0.5mA of current.
The Function Select (FSEL) input is used to determine
what clock generation chip function is. When FSEL input
is LOW, SY100S834/L functions as a divide by 2, by 4
and by 8 clock generation chip. However, if FSEL input
is HIGH, it functions as a divide by 1, by 2 and by 4
clock generation chip. This latter feature will increase
the clock frequency by two folds.
■ Synchronous enable/disable
■ Master Reset for synchronization
■ Internal 75KΩ input pull-down resistors
■ Available in 16-pin SOIC package
PIN CONFIGURATION/BLOCK DIAGRAM
1
2
16
15
Q
Q
0
0
V
CC
Q
÷1 or ÷2
EN
R
Q
D
V
CC
3
4
14
13
R
F
SEL
Q
1
CLK
Q
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids
any chance of generating a runt clock pulse on the
internal clock when the device is enabled/disabled as
can happen with an asynchronous control. An internal
runt pulse could lead to losing synchronization between
the internal divider stages. The internal enable flip-flop is
clocked on the falling edge of the input clock, therefore,
all associated specification limits are referenced to the
negative edge of the clock input.
÷2 or ÷4
5
6
12
11
Q
1
CLK
R
VCC
VBB
Q
2
2
7
8
10 MR
9
Q
÷4 or ÷8
Q
VEE
R
SOIC
TOP VIEW
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S834/Ls in a system.
PIN NAMES
TRUTH TABLE
Pin
CLK
FSEL
EN
Function
CLK
Z
EN
L
MR
L
Function
Divide
Differential Clock Inputs
Function Select
ZZ
X
H
L
Hold Q0–2
Synchronous Enable
Master Reset
X
H
Reset Q0–2
MR
VBB
Q0
NOTES:
Reference Output
Z = LOW-to-HIGH transition
ZZ = HIGH-to-LOW transition
Differential ÷1 or ÷2 Outputs
Differential ÷2 or ÷4 Outputs
Differential ÷4 or ÷8 Outputs
Q1
FSEL
L
Q0 Outputs
Divide by 2
Divide by 1
Q1 Outputs
Divide by 4
Divide by 2
Q2 Outputs
Q2
Divide by 8
Divide by 4
H
Rev.: F
Amendment:/0
IssueDate: September,1999
1
ClockWorks™
SY100S834
SY100S834L
Micrel
(1)
DC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°C
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
IEE
Parameter
Power Supply Current
—
—
—
—
49
-1.26 -1.38
150
—
—
—
—
49
-1.26 -1.38
150
—
—
—
—
49
-1.26 -1.38
150
—
—
—
—
54
mA
V
VBB
Output Reference Voltage -1.38
Input HIGH Current
-1.26
150
IIH
—
—
—
—
µA
NOTE:
1. Parametric values specified at:
5 volt Power Supply Range 100S834 Series:
-4.2V to -5.5V.
3 volt Power Supply Range 100S834L Series -3.0V to -3.8V.
(1)
AC ELECTRICAL CHARACTERISTICS
VEE = VEE (Min.) to VEE (Max.); VCC = GND
TA = –40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
tPLH
tPHL
Propagation Delay CLK 960 1100 1200 960 1100 1200 960 1100 1200 960 1100 1200
ps
to Output
MR 650
—
800
—
1010 650
800 1010 650
800 1010 650 800 1010
tskew
tS
Within-Device Skew(2)
Set-up Time EN
Hold Time EN
50
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
—
—
50
—
—
—
ps
ps
400
—
400
200
250
400
200
250
400
200
250
tH
200
—
ps
VPP
VCMR
Minimum Input Swing
250
—
mV
Common Mode Range(3)
CLK –1.3
—
–0.4 –1.4
525 275
—
–0.4 –1.4
525 275
—
–0.4 –1.4
525
—
–0.4
V
tr
tf
Output Rise/Fall Times
275
400
400
400
275 400
525
ps
Q (20% – 80%)
NOTES:
1. Parametric values specified at:
5 volt Power Supply Range 100S834 Series:
3 volt Power Supply Range 100S834L Series -3.0V to -3.8V.
2. Within-Device Skew is specified for identical transition.
-4.2V to -5.5V.
3. TheCMRrangeisreferencedtothemostpositivesideofthedifferentialinputsignal. NormaloperationisobtainediftheHIGHlevelfallswithinthespecified
range and the peak-to-peak voltage lies between VPP min. and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in the spec table
assume a nominal VEE = –3.3V. Note for PECL operation, the VCMR (min) will be fixed at 3.3V – IVCMR (min)I.
2
ClockWorks™
SY100S834
SY100S834L
Micrel
TIMING DIAGRAM
Internal Clock
Disabled
Internal Clock
Enabled
CLK
F
SEL = 0
Q
0
1
2
Q
Q
F
SEL = 1
Q
Q
Q
0
1
2
EN
TheENsignalwillfreezetheinternalclockstotheflip-flopsonthefirstfallingedgeofCLKafteritsassertion. Theinternaldividerswillmaintain
their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will transition to their
next states in the same manner, time and relationship as they would have had the EN signal not been asserted.
PRODUCT ORDERING CODE
Ordering
Code
Package
Type
Operating
Range
VEE Range
(V)
Ordering
Code
Package
Type
Operating
Range
VEE Range
(V)
SY100S834ZC
Z16-2
Z16-2
Z16-2
Z16-2
Commercial
Commercial
Commercial
Commercial
-4.2 to -5.5
-4.2 to -5.5
-3.0 to -3.8
-3.0 to -3.8
SY100S834ZI
Z16-2
Z16-2
Z16-2
Z16-2
Industrial
Industrial
Industrial
Industrial
-4.2 to -5.5
-4.2 to -5.5
-3.0 to -3.8
-3.0 to -3.8
SY100S834ZITR
SY100S834LZI
SY100S834LZITR
SY100S834ZCTR
SY100S834LZC
SY100S834LZCTR
3
ClockWorks™
SY100S834
SY100S834L
Micrel
16 LEAD SOIC .150" WIDE (Z16-2)
Rev. 02
MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA
TEL + 1 (408) 980-9191 FAX + 1 (408) 914-7878 WEB http://www.micrel.com
This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or
other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc.
© 2000 Micrel Incorporated
4
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