SY100S834LZG [MICROCHIP]
100S SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16;
| 型号： | SY100S834LZG |
| 厂家： | 
MICROCHIP |
| 描述： | 100S SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：185K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SY100S834/SY100S834L
(÷1, ÷2, ÷4) or (÷2, ÷4, ÷8) Clock
Generation Chip
Precision Edge®
General Description
The SY100S834/L is low skew (÷1, ÷2, ÷4) or (÷2, ÷4, ÷8)
clock generation chip designed explicitly for low skew
clock generation applications. The internal dividers are
synchronous to each other, therefore, the common output
edges are all precisely aligned. The devices can be driven
by either a differential or single-ended ECL or, if positive
power supplies are used, PECL input signal. In addition,
by using the VBB output, a sinusoidal source can be AC-
coupled into the device. If a single-ended input is to be
used, the VBB output should be connected to the CLK
input and bypassed to ground via a 0.01µF capacitor. The
VBB output is designed to act as the switching reference
for the input of the SY100S834/L under single-ended input
conditions. As a result, this pin can only source/sink up to
0.5mA of current.
Precision Edge®
Features
•
3.3V (SY100S834L) and 5V (SY100S834) power
supply options
•
•
•
•
•
50ps output-to-output skew
Synchronous enable/disable
Master reset for synchronization
Internal 75KΩ input pulldown resistors
Available in 16-pin SOIC package
Truth Table
The Function Select (FSEL) input is used to determine
what clock generation chip function is. When FSEL input is
LOW, SY100S834/L functions as a divide by 2, by 4 and
by 8 clock generation chip. However, if FSEL input is
HIGH, it functions as a divide by 1, by 2 and by 4 clock
generation chip. This latter feature will increase the clock
frequency by two folds.
CLK
MR
L
Function
Divide
EN
L
Z
ZZ
H
L
Hold Q0−2
Reset Q0−2
X
X
H
Notes:
Z = LOW-to-HIGH transition.
ZZ = HIGH-to-LOW transition.
The common enable (EN) is synchronous so that the
internal dividers will only be enabled/disabled when the
internal clock is already in the LOW state. This avoids any
chance of generating a runt clock pulse on the internal
clock when the device is enabled/disabled as can happen
with an asynchronous control. An internal runt pulse could
lead to losing synchronization between the internal divider
stages. The internal enable flip-flop is clocked on the
falling edge of the input clock, therefore, all associated
specification limits are referenced to the negative edge of
the clock input.
FSEL
L
Q0 Outputs
Q1 Outputs
Divide by 4
Divide by 2
Q2 Outputs
Divide by 8
Divide by 4
Divide by 2
Divide by 1
H
Upon start-up, the internal flip-flops will attain a random
state; the master reset (MR) input allows for the
synchronization of the internal dividers, as well as for
multiple SY100S834/Ls in a system.
Data sheets and support documentation can be found on
Micrel’s web site at www.micrel.com.
Precision Edge is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
M9999-060911
June 2011
hbwhelp@micrel.com or (408) 955-1690
Micrel, Inc.
SY100S834/SY100S834L
Ordering Information
Part Number
Package Type
Z16-2
Operating Range
Commercial
Commercial
Commercial
Commercial
Industrial
Package Marking
SY100S834ZC
SY100S834ZC
SY100S834LZC
SY100S834LZC
SY100S834ZI
Lead Finish
Sn-Pb
SY100S834ZC
SY100S834ZCTR(1)
SY100S834LZC
SY100S834LZCTR(1)
SY100834ZI
Z16-2
Sn-Pb
Z16-2
Sn-Pb
Z16-2
Sn-Pb
Z16-2
Sn-Pb
SY100834ZITR(1)
Z16-2
Industrial
SY100S834ZI
Sn-Pb
SY100834LZI
SY100834LZITR(1)
Z16-2
Industrial
SY100S834LZI
SY100S834LZI
Sn-Pb
Z16-2
Industrial
Sn-Pb
SY100S834ZG with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY100834ZG(2)
Z16-2
Z16-2
Z16-2
Z16-2
Industrial
Industrial
Industrial
Industrial
SY100S834ZG with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY100834ZGTR(1, 2)
SY100834LZG(2)
SY100S834LZG with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY100S834LZG with
Pb-Free bar-line indicator
NiPdAu
Pb-Free
SY100834LZGTR(1, 2)
Notes:
1. Tape and reel.
2. Pb-Free package is recommended for new designs.
Pin Configuration
16-Pin SOIC (Z16-2)
M9999-060911
hbwhelp@micrel.com or (408) 955-1690
June 2011
2
Micrel, Inc.
SY100S834/SY100S834L
Pin Description
Pin Name
CLK
Pin Function
Differential clock inputs.
FSEL
Function select, single-sided ECL logic.
Synchronous enable, single-sided ECL logic.
EN
MR
VBB
Q0
Q1
Q2
Master reset, single-sided ECL logic.
Reference output.
Differential ÷1 or ÷2 outputs.
Differential ÷2 or ÷4 outputs.
Differential ÷4 or ÷8 outputs.
3.3V PECL Output DC Electrical Characteristics(1)
VCC = 3.3V ±10%; RL = 50Ω to VCC −2V; VEE = GND.
TA = −40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Power Supply
Current
IEE
49
49
49
54
mA
V
−
−
−
−
2.235
1.595
−
−
−
2.345
1.595
−
−
−
Output HIGH
Voltage
VCH
VOL
VIH
VIL
2.215 2.295
2.42
1.745
2.42
2.275
1.49
2.42
1.68
2.275
1.49
2.42
1.68
2.275
1.49
2.345
1.595
−
2.42
1.68
Output LOW
Voltage
1.47
2.135
1.49
1.605
V
Input HIGH
Voltage
2.135
1.49
2.42
2.135
1.49
2.42
2.135
1.49
2.42
V
−
−
Input LOW
Voltage
1.825
1.825
1.825
1.825
V
−
−
−
Output
VBB
Reference
Voltage
1.92
2.04
1.92
2.04
1.92
2.04
1.92
2.04
V
−
−
−
−
Common
VCMR
IIH
2
−
2.9
150
−
1.9
−
2.9
150
−
1.9
−
2.9
150
−
1.9
−
2.9
150
−
V
−
−
−
−
−
−
−
−
−
−
−
−
Mode Range(2)
Input HIGH
Current
µA
µA
Input LOW
Current
IIL
0.5
0.5
0.5
0.5
Notes:
1. These values are for VCC = 3.3V. Level specifications will vary 1:1 with VCC
.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the
specified range and the peak-to-peak voltage lies between VPP (min.) and 1V. The lower end of the CMR range varies 1:1 with VEE. Note for PECL
operation that the VCMR (min.) will be fixed at 3.3V − IVCMR (min.)I.
M9999-060911
hbwhelp@micrel.com or (408) 955-1690
June 2011
3
Micrel, Inc.
SY100S834/SY100S834L
5V PECL Output DC Electrical Characteristics(2)
VCC = 3.3V ±10%; RL = 50Ω to VCC −2V; VEE = GND.
TA = −40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Power Supply
Current
IEE
49
49
49
54
mA
V
−
−
−
−
4.045
3.295
−
−
−
4.045
3.295
−
−
−
Output HIGH
Voltage
VCH
VOL
VIH
VIL
3.915 3.995
4.12
3.445
4.12
3.975
3.19
4.12
3.38
3.975
3.19
4.12
3.38
3.975
3.19
4.045
3.295
−
4.12
3.38
Output LOW
Voltage
3.17
3.835
3.19
3.305
V
Input HIGH
Voltage
3.835
3.19
4.12
3.835
3.19
4.12
3.835
3.19
4.12
V
−
−
Input LOW
Voltage
3.525
3.525
3.525
3.525
V
−
−
−
Output
VBB
Reference
Voltage
3.62
3.74
3.62
3.74
3.62
3.74
3.62
3.74
V
−
−
−
−
Common
VCMR
IIH
2
−
4.6
150
−
1.9
−
4.6
150
−
1.9
−
4.6
150
−
1.9
−
4.6
150
−
V
−
−
−
−
−
−
−
−
−
−
−
−
Mode Range(2)
Input HIGH
Current
µA
µA
Input LOW
Current
IIL
0.5
0.5
0.5
0.5
Notes:
1. These values are for VCC = 5V. Level specifications will vary 1:1 with VCC
.
2. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the
specified range and the peak-to-peak voltage lies between VPP (min.) and 1V. The lower end of the CMR range varies 1:1 with VEE. Note for PECL
operation that the VCMR (min.) will be fixed at 3.3V − IVCMR (min.)I.
M9999-060911
hbwhelp@micrel.com or (408) 955-1690
June 2011
4
Micrel, Inc.
SY100S834/SY100S834L
NECL Output DC Electrical Characteristics
VCC = GND; RL = 50Ω to VCC −2V; VEE = −3.0V to −5.5V.
TA = −40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol Parameter
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Power
IEE
Supply
Current
49
49
49
54
mA
−
−
−
−
−
−
−
−
Output
HIGH
Voltage
VCH
V
V
−1085
−1830
−1005
−880
−1025
−1830
−955
−880
−1025
−1810
−955
−880
−1025
−1810
−955
−880
Output
LOW
Voltage
VOL
−1695
−1555
−1705
−1620
−1705
−1620
−1705
−1620
Input
VIH
VIL
HIGH
Voltage
V
V
V
−
−1165
−1810
−1.38
−880
−1475
−1.26
−1165
−1810
−1.38
−
−
−
−880
−1475
−1.26
−1165
−1810
−1.38
−
−
−
−880
−1475
−1.26
−1165
−1810
−1.38
−
−
−
−880
−1475
−1.26
Input LOW
Voltage
−
−
Output
Reference
Voltage
VBB
Common
Mode
VCMR
V
−1.3
−
−0.4
−1.4
−
−0.4
−1.4
−
−0.4
−1.4
−
−0.4
Range(1)
Input
IIH
HIGH
Current
150
150
150
150
µA
µA
−
−
−
−
−
−
−
−
−
−
−
−
Input LOW
Current
IIL
0.5
0.5
0.5
0.5
−
−
−
−
Note:
1. The CMR range is referenced to the most positive side of the differential input signal. Normal operation is obtained if the HIGH level falls within the
specified range and the peak-to-peak voltage lies between VPP (min.) and 1V. The lower end of the CMR range varies 1:1 with VEE. The numbers in
the spec table assume a nominal VEE = −3.3V. Note for PECL operation, the VCMR (min.) will be fixed at 3.3V − IVCMR (min.)I.
M9999-060911
hbwhelp@micrel.com or (408) 955-1690
June 2011
5
Micrel, Inc.
SY100S834/SY100S834L
AC Electrical Characteristics(1)
VEE = VEE (min.) to VEE (max.); VCC = GND.
TA = −40°C
TA = 0°C
TA = +25°C
TA = +85°C
Symbol
Parameter
Unit
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Min.
Typ.
Max.
Propagation Delay
tPLH
960
1100
1200
960
1100
800
−
1200
960
1100
800
−
1200
960
1100
1200
ps
ps
ps
to Output
CLK
tPHL
MR
650
800
1010
50
650
1010
50
650
1010
50
650
800
1010
50
Within-Device
Skew(2)
tSKEW
−
−
−
−
−
−
tS
tH
ps
ps
400
200
400
200
400
200
400
200
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
Set-Up Time EN
Hold Time EN
Minimum Input
Swing
VPP
mV
ps
250
275
250
275
250
275
250
275
−
−
−
−
−
−
−
−
Output Rise/Fall
Times
tr
tf
400
525
400
525
400
525
400
525
Q (20% − 80%)
Notes:
1. Parametric values specified at:
−
−
5V power supply range, 100S834 series: −4.2V to −5.5V
3V power supply range, 100S834L series: −3.0V to −3.8V
2. Within-Device Skew is specified for identical transition.
M9999-060911
hbwhelp@micrel.com or (408) 955-1690
June 2011
6
Micrel, Inc.
SY100S834/SY100S834L
Timing Diagram
The EN signal will freeze the internal clocks to the flip-flops on the first falling edge of CLK after its assertion. The internal dividers will
maintain their state during the internal clock freeze and will return to clocking once the internal clocks are unfrozen. The outputs will
transition to their next states in the same manner, time, and relationship as they would have had the EN signal not been asserted.
M9999-060911
hbwhelp@micrel.com or (408) 955-1690
June 2011
7
Micrel, Inc.
SY100S834/SY100S834L
Package Information
xx-Pin Package Type (code)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com
Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This
information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry,
specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual
property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability
whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties
relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right.
Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product
can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant
into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A
Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully
indemnify Micrel for any damages resulting from such use or sale.
© 2006 Micrel, Incorporated.
M9999-060911
hbwhelp@micrel.com or (408) 955-1690
June 2011
8
相关型号：
SY100S834LZG-TR
100S SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MICROCHIP
SY100S834ZG
100S SERIES, LOW SKEW CLOCK DRIVER, 3 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MICROCHIP
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