33LV408RPFS-30 [MAXWELL]
4 Megabit (512K x 8-Bit) CMOS SRAM; 4兆位（ 512K ×8位） CMOS SRAM
| 型号： | 33LV408RPFS-30 |
| 厂家： | 
MAXWELL TECHNOLOGIES |
| 描述： | 4 Megabit (512K x 8-Bit) CMOS SRAM |
| 文件： | 总12页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
33LV408
4 Megabit (512K x 8-Bit)
CMOS SRAM
33LV408
Logic Diagram
FEATURES:
DESCRIPTION:
• RAD-PAK® Technology radiation-hardened against natural
space radiation
• 524,288 x 8 bit organization
Maxwell Technologies’ 33LV408 high-density 4 Megabit
SRAM microcircuit features a greater than 100 krad (Si) total
dose tolerance, depending upon space mission. Using Max-
well’s radiation-hardened RAD-PAK® packaging technology, the
33LV408 realizes a high density, high performance, and low
power consumption. Its fully static design eliminates the need
for external clocks, while the CMOS circuitry reduces power
consumption and provides higher reliability. The 33LV408 is
equipped with eight common input/output lines, chip select
and output enable, allowing for greater system flexibility and
eliminating bus contention. The 33LV408 features the same
advanced 512K x 8-bit SRAM, high-speed, and low-power
demand as the commercial counterpart.
· Total dose hardness:
- > 100 krad (Si), depending upon space mission
• Excellent Single Event Effect
· - SEL : > 101 MeV/mg/cm2
TH
· - SEUTH: = 3 MeV/mg/cm2
- SEU saturated cross section: 6E-9 cm2/bit
• Package:
- 32-Pin RAD-PAK® flat pack
• Fast access time:
- 20, 25, 30 ns maximum times available
• Single 3.3V + 10% power supply
• Fully static operation
Maxwell Technologies' patented RAD-PAK® packaging technol-
ogy incorporates radiation shielding in the microcircuit pack-
age. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, RAD-PAK® provides greater than 100
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
- No clock or refresh required
• Three state outputs
• TTL compatible inputs and outputs
• Low power:
- Standby: 60 mA (TTL); 10 mA (CMOS)
- Operation: 150 mA (20 ns); 140 mA (25 ns);
130 mA (30 ns)
04.02.04 REV 2
1
All data sheets are subject to change without notice
(858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 1. PINOUT DESCRIPTION
PIN
SYMBOL
DESCRIPTION
12-5, 27, 26, 23, 25, 4,
28, 3, 31, 2, 30, 1
A0-A18
Address Inputs
29
WE
CS
Write Enable
Chip Select
22
24
OE
Output Enable
13-15, 17-21
I/O 1-I/O 8 Data Inputs/Outputs
32
16
V
Power
CC
V
Ground
SS
TABLE 2. 33LV408 ABSOLUTE MAXIMUM RATINGS
PARAMETER
SYMBOL
MIN
MAX
UNIT
Voltage on VCC supply relative to V
V
-0.5
-0.5
--
7.0
V
V
SS
CC
Voltage on any pin relative to V
V , V
V +0.5
SS
IN OUT
CC
Power Dissipation
PD
TS
1.0
W
°C
°C
Storage Temperature
Operating Temperature
-65
-55
+150
+125
T
A
TABLE 3. DELTA LIMITS
PARAMETER
VARIATION
ICC
ISB
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
±10% of stated vaule in Table 6
ISB1
04.02.04 REV 2
All data sheets are subject to change without notice
2
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 4. 33LV408 RECOMMENDED OPERATING CONDITIONS
(VCC = 3.3 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)
PARAMETER
SYMBOL
MIN
MAX
UNIT
Supply Voltage
Ground
V
3.0
0
3.6
0
V
V
CC
V
SS
Input High Voltage 1
Input Low Voltage 2
Thermal Impedance
Weight
V
2.2
-0.3
--
V +0.3
V
IH
CC
V
0.8
1.21
12
V
IL
ΘJC
°C/W
Grams
1. V (max) = VCC +2.0V ac (pulse width < 10 ns) for I < 20 mA
IH
2. V (min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA
IL
TABLE 5. 33LV408 CAPACITANCE
(f = 1.0 MHZ, VCC = 3.3 V, T = 25 °C)
A
TEST
CONDITIONS
PARAMETER
SYMBOL
MAX
UNITS
Input Capacitance1
CS1 - CS4,
OE, WE
CIN
V = 0 V
pF
IN
7
28
7
I/O0-7, I/O8-15, I/O16-23, I/O24-31
Input / Output Capacitance1
COUT
V = 0 V
8
pF
I/O
1. Guaranteed by design.
TABLE 6. 33LV408 DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL CONDITION
SUBGROUPS
MIN
MAX
UNIT
Input Leakage Current
Output Leakage Current
ILI
V = V to V
CC
1, 2, 3
1, 2, 3
-2
-2
2
2
µA
µA
IN
SS
ILO
CS=V or OE=V or WE=V ,
IH IH IL
V
OUT =V to V
SS CC
Output Low Voltage
Output High Voltage
V
IOL = 8mA
1, 2, 3
1, 2, 3
1, 2, 3
--
0.4
--
V
V
OL
V
IOH = -4mA
2.4
OH
Operating Current
ICC
Min cycle, 100% Duty, CS=V , IOUT=0mA,
mA
IL
-20
-25
-30
V = V or V
--
--
--
150
140
130
IN
IH
IL
Standby Power Supply
Current
ISB
CS = V , Min Cycle
1, 2, 3
--
60
mA
IH
04.02.04 REV 2
All data sheets are subject to change without notice
3
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 6. 33LV408 DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL CONDITION
SUBGROUPS
MIN
MAX
UNIT
Standby Power Supply
Current - CMOS
ISB1 CS > VCC - 0.2V; V > VCC - 0.2V
1, 2, 3
--
10
mA
IN
or V < 0.2V
IN
Input Capacitance 1
Output Capacitance 1
C
V = 0V, f = 1MHz, T = 25 °C
1, 2, 3
1, 2, 3
--
--
7
8
pF
pF
IN
IN
A
C
V = 0V
I/O
I/O
1. Guaranteed by design.
TABLE 7. 33LV408 AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 3.3 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)
PARAMETER
MIN
TYP
MAX
UNITS
Input Pulse Level
0.0
--
--
--
--
--
3.0
1.5
3.0
1.5
V
V
ns
V
Output Timing Measurement Reference Level
Input Rise/Fall Time
--
Input Timing Measurement Reference Level
--
TABLE 8. 33LV408 AC CHARACTERISTICS FOR READ CYCLE
(VCC = 3.3V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYP
MAX
UNIT
Read Cycle Time
tRC
9, 10, 11
ns
-20
-25
-30
20
25
30
--
--
--
--
--
--
Address Access Time
tAA
tCO
tOE
tLZ
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
ns
ns
-20
-25
-30
--
--
--
--
--
--
20
25
30
Chip Select Access Time
-20
-25
-30
--
--
--
--
--
--
20
25
30
Output Enable to Output Valid
-20
-25
-30
--
--
--
--
--
--
10
12
14
ns
ns
Chip Enable to Output in Low-Z
-20
-25
-30
--
--
--
3
3
3
--
--
--
04.02.04 REV 2
All data sheets are subject to change without notice
4
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 8. 33LV408 AC CHARACTERISTICS FOR READ CYCLE
(VCC = 3.3V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYP
MAX
UNIT
Output Enable to Output in Low-Z
tOLZ
9, 10, 11
ns
-20
-25
-30
--
--
--
0
0
0
--
--
--
Chip Deselect to Output in High-Z
tHZ
tOHZ
tOH
tPU
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
ns
ns
ns
ns
ns
-20
-25
-30
--
--
--
5
6
8
--
--
--
Output Disable to Output in High-Z
-20
-25
-30
--
--
--
5
6
8
--
--
--
Output Hold from Address Change
-20
-25
-30
3
5
6
--
--
--
--
--
--
Chip Select to Power Up Time
-20
-25
-30
--
--
--
0
0
0
--
--
--
Chip Select to Power Down Time
tPD
-20
-25
-30
--
--
--
10
15
20
--
--
--
TABLE 9. 33LV408 FUNCTIONAL DESCRIPTION
CS
WE
OE
MODE
I/O PIN
SUPPLY CURRENT
1
1
H
L
L
L
X
X
Not Select
Output Disable
Read
High-Z
High-Z
DOUT
ISB, ISB1
ICC
H
H
L
H
L
ICC
1
X
Write
D
ICC
IN
1. X = don’t care.
04.02.04 REV 2
All data sheets are subject to change without notice
5
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 10. 33LV408 AC CHARACTERISTICS FOR WRITE CYCLE
(VCC = 3.3V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYP
MAX
UNIT
Write Cycle Time
tWC
9, 10, 11
ns
-20
-25
-30
20
25
30
--
--
--
--
--
--
Chip Select to End of Write
tCW
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
9, 10, 11
ns
ns
ns
ns
ns
ns
ns
ns
ns
-20
-25
-30
14
15
17
--
--
--
--
--
--
Address Setup Time
tAS
-20
-25
-30
0
0
0
--
--
--
--
--
--
Address Valid to End of Write
tAW
-20
-25
-30
14
15
17
--
--
--
--
--
--
Write Pulse Width (OE High)
tWP
-20
-25
-30
14
15
17
--
--
--
--
--
--
Write Recovery Time
tWR
tWHZ
tWP1
tDW
tOW
-20
-25
-30
0
0
0
--
--
--
--
--
--
Write to Output in High-Z
-20
-25
-30
--
--
--
5
5
6
--
--
--
Write Pulse Width (OE Low)
-20
-25
-30
--
--
--
20
25
30
--
--
--
Data to Write Time Overlap
-20
-25
-30
9
10
11
--
--
--
--
--
--
End Write to Output Low-Z
-20
-25
-30
--
--
--
6
7
8
--
--
--
04.02.04 REV 2
All data sheets are subject to change without notice
6
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
TABLE 10. 33LV408 AC CHARACTERISTICS FOR WRITE CYCLE
(VCC = 3.3V + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE SPECIFIED)
PARAMETER
SYMBOL
SUBGROUPS
MIN
TYP
MAX
UNIT
Data Hold from Write Time
tDH
9, 10, 11
ns
-20
-25
-30
0
0
0
--
--
--
--
--
--
FIGURE 1: TIMING WAVEFORM OF READ CYCLE(1)
FIGURE 2: TIMING WAVEFORM OF READ CYCLE (2)
Read Cycle Notes:
1. WE is high for read cycle.
2. All read cycle timing is referenced form the last valid address to the first transition address.
3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
V levels.
OL
4. At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and from device to device.
5. Transition is measured + 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS = V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention condition is necessary during read and write cycle.
04.02.04 REV 2
All data sheets are subject to change without notice
7
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
FIGURE 3: TIMING WAVEFORM OF WRITE CYCLE(1)
FIGURE 4: TIMING WAVEFORM OF WRITE CYCLE(2)
04.02.04 REV 2
All data sheets are subject to change without notice
8
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
FIGURE 5: TIMING WAVEFORM OF WRITE CYCLE (3)
WRITE CYCLE NOTE:
1.
2.
All write cycle timing is referenced from the last valid address to the first transition address.
A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and
WE going low: A write ends at the earliest transition among CS going high and WE going high. tWP is measured from begin-
ning of write to the end of write.
3.
4.
5.
6.
tCW is measured from the later of CS going low to end of write.
tAS is measured from the address valid to the beginning of write.
tWR is measured form the end of write to the address change. TWR applied in case a write ends as CS, or WR going high.
If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite
phase of the output must not be applied because bus contention can occur.
7.
For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.
8.
9.
IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
D is the read data of the new address.
OUT
10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should
not be applied.
04.02.04 REV 2
All data sheets are subject to change without notice
9
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
32 PIN RAD-PAK® FLAT PACKAGE
DIMENSION
SYMBOL
MIN
NOM
MAX
A
b
0.122
0.015
0.008
--
0.135
0.017
0.010
0.930
0.645
--
0.155
0.019
0.012
0.940
0.655
0.690
--
c
D
E
0.635
--
E1
E2
E3
e
0.550
--
0.565
0.040
0.050 BSC
0.400
0.098
0.082
32
--
L
0.390
0.088
--
0.410
.108
--
Q
S1
N
Note: All dimensions in inches
04.02.04 REV 2
All data sheets are subject to change without notice 10
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
Important Notice:
These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech-
nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
04.02.04 REV 2
All data sheets are subject to change without notice 11
©2004 Maxwell Technologies
All rights reserved.
33LV408
4 Megabit (512K x 8-Bit) CMOS SRAM
Product Ordering Options
Model Number
33LV408
XX
F
X
-XX
Option Details
20 = 20 ns
Feature
Access Time
25 = 25 ns
30 = 30 ns
Monolithic
Screening Flow
S = Maxwell Class S
B = Maxwell Class B
I = Industrial (testing @ -55°C,
+25°C, +125°C)
E = Engineering (testing @ +25°C)
F = Flat Pack
Package
RP = RAD-PAK® package
Radiation Feature
4 Megabit CMOS SRAM
Base Product
Nomenclature
04.02.04 REV 2
All data sheets are subject to change without notice 12
©2004 Maxwell Technologies
All rights reserved.
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