MAX9324EUP+ [MAXIM]
暂无描述;
| 型号： | MAX9324EUP+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 暂无描述 驱动器 时钟 |
| 文件： | 总12页 (文件大小：274K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2576; Rev 0; 10/02
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
General Description
Features
The MAX9324 low-skew, low-jitter, clock and data driver
distributes a differential LVPECL input to four differential
LVPECL outputs and one single-ended LVCMOS output.
All outputs default to logic low when the differential inputs
equal GND or are left open. The MAX9324 operates from
3.0V to 3.6V, making it ideal for 3.3V systems, and con-
sumes only 25mA (max) of supply current.
ꢀ 15ps Differential Output-to-Output Skew
ꢀ 1.7ps Added Random Jitter
RMS
ꢀ 150ps (max) Part-to-Part Skew
ꢀ 450ps Propagation Delay
ꢀ Synchronous Output Enable/Disable
ꢀ Single-Ended Monitor Output
The MAX9324 features low 150ps (max) part-to-part
skew, low 15ps output-to-output skew, and low 1.7ps
RMS jitter, making the device ideal for clock and data
distribution across a backplane or board. CLK_EN and
SEOUT_Z control the status of the various outputs.
Asserting CLK_EN low configures the differential (Q_,
Q_) outputs to a differential low condition and SEOUT to
a single-ended logic-low state. CLK_EN operation is
synchronous with the CLK_ inputs. A logic high on
SEOUT_Z places SEOUT in a high-impedance state.
SEOUT_Z is asynchronous with the CLK (CLK) inputs.
ꢀ Outputs Assert Low when CLK, CLK are Open or
at GND
ꢀ 3.0V to 3.6V Supply Voltage Range
ꢀ -40°C to +85°C Operating Temperature Range
Ordering Information
The MAX9324 is available in space-saving 20-pin
TSSOP and ultra-small 20-pin 4mm ✕ 4mm thin QFN
packages and operates over the extended (-40°C to
+85°C) temperature range.
PART
MAX9324EUP
MAX9324ETP*
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
20 TSSOP
20 Thin QFN-EP**
Applications
*Future product—Contact factory for availability.
**EP = Exposed paddle.
Precision Clock Distribution
Low-Jitter Data Repeater
Data and Clock Driver and Buffer
Central-Office Backplane Clock Distribution
DSLAM Backplane
Functional Diagram and Typical Operating Circuit appear at
end of data sheet.
Base Station
ATE
Pin Configurations
TOP VIEW
20 19 18 17 16
GND
CLK_EN
N.C.
1
2
20 Q0
19 Q0
V
1
2
3
4
5
15
14
13
12
11
SEOUT
GND
CC
3
18 V
CC
Q1
Q1
Q2
Q2
SEOUT
GND
4
17 Q1
16 Q1
15 Q2
MAX9324
N.C.
MAX9324
5
**EXPOSED PADDLE
SEOUT_Z
CLK
N.C.
6
SEOUT_Z
CLK
7
14
13
Q2
8
V
CC
6
7
8
9
10
CLK
9
12 Q3
11 Q3
V
10
CC
THIN QFN-EP** (4mm x 4mm)
**CONNECT EXPOSED PADDLE TO GND.
TSSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
ABSOLUTE MAXIMUM RATINGS
CC
V
to GND...........................................................-0.3V to +4.0V
Junction-to-Ambient Thermal Resistance in Still Air
Q_, Q_, CLK, CLK, SEOUT_Z, CLK_EN,
SEOUT to GND.......................................-0.3V to (V
CLK to CLK............................................................................±3V
SEOUT Short to GND .................................................Continuous
Continuous Output Current (Q_, Q_) ..................................50mA
Surge Output Current (Q_, Q_).........................................±00mA
20-Pin TSSOP ............................................................+9±°C/W
20-Pin 4mm ✕ 4mm Thin QFN.................................+59.3°C/W
Junction-to-Case Thermal Resistance
20-Pin TSSOP ............................................................+20°C/W
20-Pin 4mm ✕ 4mm Thin QFN......................................+2°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+±50°C
Storage Temperature Range.............................-65°C to +±50°C
Soldering Temperature (±0s)...........................................+300°C
+ 0.3V)
CC
Continuous Power Dissipation (T = +70°C)
A
20-Pin TSSOP (derate ±±mW/°C)..............................879.±mW
20-Pin 4mm ✕ 4mm Thin QFN (derate ±6.9mW/°C)..±349.±mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
CC
(V
= 3.0V to 3.6V, differential outputs terminated with 50Ω ±±1 to (V
- 2V), SEOUT_Z = GND, CLK_EN = V , T = -40°C to
CC CC A
= 3.3V, T = +25°C.) (Notes ±, 2, and 3)
+85°C, unless otherwise noted. Typical values are at V
CC
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SINGLE-ENDED INPUTS (CLK_EN, SEOUT_Z)
Input High Voltage
Input Low Voltage
V
2
0
V
V
V
IH
CC
V
0.8
+5
IL
CLK_EN = V
-5
CC
Input High Current
Input Low Current
I
µA
µA
IH
SEOUT_Z = V
±50
CC
CLK_EN = GND
SEOUT_Z = GND
-±50
-5
I
IL
+5
DIFFERENTIAL INPUT (CLK, CLK)
Differential Input High Voltage
Differential Input Low Voltage
Differential Input Voltage
Input Current
V
Figure ±
Figure ±
±.5
0
V
V
V
IHD
CC
V
V
- 0.±5
±.5
ILD
- V
CC
V
0.±5
-5
V
IHD
ILD
I
V
, V
IHD ILD
+±50
µA
CLK
DIFFERENTIAL OUTPUTS (Q_, Q_)
Single-Ended Output High
V
Figure ±
Figure ±
Figure ±
V
V
- ±.4
V
- ±.0
V
V
V
OH
CC
CC
CC
CC
Single-Ended Output Low
V
- 2.0
V
- ±.7
OL
- V
Differential Output Voltage
SINGLE-ENDED OUTPUT (SEOUT)
Output High Voltage
V
0.6
0.85
OH
OL
V
I
I
= -4mA
= 4mA
2.4
-±0
V
V
OH
OH
OL
Output Low Voltage
V
0.4
+±0
75
OL
OZ
OS
Output High-Impedance Current
Output Short-Circuit Current
SUPPLY
I
I
SEOUT_Z = V , SEOUT = V
or GND
CC
µA
mA
CC
V
= V , SEOUT = GND
CC
CLK
Supply Current
I
(Note 4)
25
mA
CC
2
_______________________________________________________________________________________
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
AC ELECTRICAL CHARACTERISTICS
(V
= 3.0V to 3.6V, differential outputs terminated with 50Ω ±±1 to (V
- 2V), f
≤ 266MHz, input duty cycle = 501, input transi-
CLK
CC
CC
tion time = ±25ps (201 to 801), V
= ±.5V to V , V
= GND to (V
- 0.±5V), V
- V
= 0.±5V to ±.5V, CLK_EN = V
,
IHD
CC ILD
CC
IHD
ILD
CC
SEOUT_Z = GND, T = -40°C to +85°C, unless otherwise noted. Typical values are at V
= 3.3V, V
= (V
- ±V), V
= (V
-
A
CC
IHD
CC
ILD
CC
±.5V), T = +25°C.) (Note 5)
A
PARAMETER
SYMBOL
CONDITIONS
- V ≥ 0.6V, SEOUT_Z = V
CC
MIN
650
±25
±00
TYP
MAX
UNITS
V
800
200
450
OH
OL
Switching Frequency
f
MHz
MAX
SEOUT_Z = GND, SEOUT
Propagation Delay
Output-to-Output Skew
Part-to-Part Skew
t
, t
CLK, CLK to Q_, Q_, Figure ± (Note 6)
(Note 7)
600
30
ps
ps
ps
ps
ps
1
PHL PLH
t
SKOO
t
(Note 8)
±50
300
300
52
SKPP
Output Rise Time
t
201 to 801, Figure ±
801 to 201, Figure ±
±00
±00
48
2±7
207
50
R
Output Fall Time
t
F
Output Duty Cycle
Added Random Jitter
Added Deterministic Jitter
ODC
t
t
f
= 650MHz (Note 9)
2e23 - ± PRBS pattern, f = 650Mbps (Note 9)
±.7
83
3
ps
(RMS)
RJ
CLK
±00
ps
(P-P)
DJ
V
= 3.3V with 25mV superimposed
CC
Added Jitter
t
8.5
±2
ps
(P-P)
AJ
sinusoidal noise at ±00kHz (Note 9)
Single-Ended Output Rise Time
Single-Ended Output Fall Time
Single-Ended Output Duty Cycle
t
C = ±5pF, 201 to 801, Figure ±
±.6
±.6
52
2
2
ns
ns
1
R
L
t
C = ±5pF, 801 to 201, Figure ±
L
F
ODC
(Note ±0)
40
60
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters are production tested at T = +25°C and guaranteed by design over the full operating temperature range.
A
Note 4: All pins open except V
and GND.
CC
Note 5: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 6: Measured from the differential input signal crosspoint to the differential output signal crosspoint.
Note 7: Measured between the differential outputs of the same part at the differential signal crosspoint for a same-edge transition.
Note 8: Measured between the differential outputs of different parts at the differential signal crosspoint under identical conditions
for a same-edge transition.
Note 9: Jitter added to the input signal.
Note 10: Measured at 501 of V
.
CC
_______________________________________________________________________________________
3
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Typical Operating Characteristics
(V
= 3.3V, outputs terminated to (V
- 2V) through 50Ω, SEOUT_Z = V , CLK_EN = V , T = +25°C.)
CC
CC CC CC A
DIFFERENTIAL OUTPUT AMPLITUDE
(V - V ) vs. FREQUENCY
SUPPLY CURRENT vs. TEMPERATURE
OH
OL
800
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
700
600
500
400
300
200
100
0
0
200 400 600 800 1000 1200 1400 1600
FREQUENCY (MHz)
-40
-15
10
35
60
85
TEMPERATURE (°C)
DIFFERENTIAL OUTPUT RISE/FALL TIME
vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
250
240
230
220
210
200
190
180
170
160
150
510
500
490
480
470
460
450
440
430
420
410
t
R
t
PLH
t
F
t
PHL
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
4
_______________________________________________________________________________________
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Pin Description
PIN
NAME
FUNCTION
TSSOP
QFN
±, 5
2, ±8
GND
Ground. Provide a low-impedance connection to the ground plane.
Synchronous Output Enable. Connect CLK_EN to V
or leave floating to enable the
CC
differential outputs. Connect CLK_EN to GND to disable the differential outputs. When
disabled, Q_ asserts low, Q_ asserts high, and SEOUT asserts low. A 5±kΩ pullup resistor to
2
±9
CLK_EN
V
allows CLK_EN to be left floating.
CC
3, 6
4
3, 20
±
N.C.
No Connect. Not internally connected.
LVCMOS/LVTTL Clock Output. SEOUT reproduces CLK when SEOUT_Z = GND. SEOUT
goes high impedance when SEOUT_Z = V . The maximum output frequency of SEOUT is
CC
SEOUT
±25MHz.
Single-Ended Clock Output Enable/Disable. Connect SEOUT_Z to GND to enable the single-
ended clock output. Connect SEOUT_Z to V
5±kΩ pulldown resistor to GND allows SEOUT_Z to be left floating.
to disable the single-ended clock output. A
7
4
SEOUT_Z
CLK
CC
Noninverting Differential LVPECL Input. An internal 5±kΩ pulldown resistor to GND forces the
outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or
at GND and the outputs are enabled.
8
9
5
6
Inverting Differential LVPECL Input. An internal 5±kΩ pulldown resistor to GND forces the
outputs (Q_, Q_) to differential low and logic low (SEOUT) when CLK and CLK are left open or
at GND and the outputs are enabled.
CLK
Positive Supply Voltage. Bypass V
to GND with three 0.0±µF and one 0.±µF ceramic
CC
±0, ±3, ±8
7, ±0, ±5
V
capacitors. Place the 0.0±µF capacitors as close to each V input as possible (one per V
CC CC
CC
input). Connect all V
inputs together, and bypass to GND with a 0.±µF ceramic capacitor.
CC
±±
±2
±4
±5
±6
±7
±9
20
8
Q3
Q3
Q2
Q2
Q1
Q±
Q0
Q0
Inverting Differential LVPECL Output. Terminate Q3 to (V
- 2V) with a 50Ω ±±1 resistor.
CC
9
Noninverting Differential LVPECL Output. Terminate Q3 to (V
- 2V) with a 50Ω ±±1 resistor.
CC
±±
±2
±3
±4
±6
±7
Inverting Differential LVPECL Output. Terminate Q2 to (V
- 2V) with a 50Ω ±±1 resistor.
CC
Noninverting Differential LVPECL Output. Terminate Q2 to (V
- 2V) with a 50Ω ±±1 resistor.
CC
Inverting Differential LVPECL Output. Terminate Q1 to (V
- 2V) with a 50Ω ±±1 resistor.
CC
Noninverting Differential LVPECL Output. Terminate Q± to (V
- 2V) with a 50Ω ±±1 resistor.
CC
Inverting Differential LVPECL Output. Terminate Q0 to (V
- 2V) with a 50Ω ±±1 resistor.
CC
Noninverting Differential LVPECL Output. Terminate Q0 to (V
- 2V) with a 50Ω ±±1 resistor.
CC
_______________________________________________________________________________________
5
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
signal. Terminate CLK and CLK through 50Ω to (V
-
CC
Detailed Description
2V) to minimize input signal reflections. Internal 5±kΩ
pulldown resistors to GND ensure the outputs default to
differential low (Q_, Q_) or logic low (SEOUT) when the
CLK inputs are left open.
The MAX9324 low-skew, low-jitter, clock and data dri-
ver distributes a differential LVPECL input signal to four
differential LVPECL outputs and a single-ended LVC-
MOS output. The differential output drivers operate at
frequencies up to 800MHz. When SEOUT_Z = GND,
the single-ended LVCMOS output driver operates with
frequencies as high as 200MHz. The MAX9324 oper-
ates from 3.0V to 3.6V, making the device ideal for 3.3V
systems.
CLK_EN Input
CLK_EN enables/disables the differential outputs of the
MAX9324. Connect CLK_EN to V
to enable the dif-
CC
ferential outputs. The (Q_, Q_) outputs are driven to a
differential low condition when CLK_EN = GND. Each
differential output pair disables following successive
rising and falling edges on CLK (falling and rising
edges on CLK), after CLK_EN connects to GND. Both a
rising and falling edge on CLK are required to com-
plete the enable/disable function (Figure 2).
Data Inputs
Differential LVPECL Inputs
The MAX9324 accepts a differential LVPECL input.
Each differential output duplicates the differential input
CLK
V
IHD
V
ILD
CLK
Q_
V
OH
V
- V
OH OL
V
OL
Q_
t
t
PHL
PLH
80%
80%
Q_ - Q_
t
t
F
R
20%
20%
80%
80%
SEOUT
t
t
F
R
20%
20%
Figure 1. MAX9324 Clock Input-to-Output Delay and Rise/Fall Time
_______________________________________________________________________________________
6
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
CLK
CLK
ENABLED
DISABLED
CLK_EN
Q_
Q_
HIGH
IMPEDANCE
SEOUT
SEOUT_Z
Figure 2. MAX9324 CLK_EN Timing Diagram
SEOUT_Z
Applications Information
SEOUT_Z enables/disables the single-ended LVCMOS
output (Table ±). Connect SEOUT_Z to GND to enable
Output Termination
Terminate both outputs of each differential pair through
the single-ended output. Connect SEOUT_Z to V
to
CC
50Ω to (V
- 2V) or use an equivalent Thevenin termi-
CC
force the single-ended output to a high-impedance
state. SEOUT provides a single-ended monitor for oper-
ating frequencies as high as 200MHz.
nation. Use identical termination on each output for the
lowest output-to-output skew. Terminate both outputs
when deriving a single-ended signal from a differential
output. For example, using Q0 as a single-ended out-
put requires termination for both Q0 and Q0.
Table 1. Control Input Table
INPUTS
OUTPUTS
Q0 Q3
CLK_EN
SEOUT_Z
Q0–Q3
Disabled, pulled to logic low
Disabled, pulled to logic low
Enabled
–
SEOUT
0
0
±
±
0
±
0
±
Disabled, pulled to logic high
Disabled, pulled to logic high
Enabled
Enabled, logic low
Disabled, high impedance
Enabled
Enabled
Enabled
Disabled, high impedance
_______________________________________________________________________________________
7
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
SEOUT provides a single-ended LVCMOS monitor out-
put. SEOUT operates with a maximum output frequency
of 200MHz.
Circuit Board Traces
Input and output trace characteristics affect the perfor-
mance of the MAX9324. Connect each input and output
to a 50Ω characteristic impedance trace to minimize
reflections. Avoid discontinuities in differential imped-
ance and maximize common-mode noise immunity by
maintaining the distance between differential traces
and avoiding sharp corners. Minimize the number of
vias to prevent impedance discontinuities. Minimize
skew by matching the electrical length of the traces.
Ensure that the output currents do not violate the cur-
rent limits as specified in the Absolute Maximum
Ratings table. Observe the device’s total thermal limits
under all operating conditions.
Power-Supply Bypassing
Bypass V
to GND using three 0.0±µF ceramic capaci-
CC
tors and one 0.±µF ceramic capacitor. Place the 0.0±µF
capacitors (one per V
input) as close to V
as possi-
CC
CC
ble (see the Typical Operating Circuit). Use multiple
Chip Information
TRANSISTOR COUNT: 4430
bypass vias to minimize parasitic inductance.
PROCESS: BiCMOS
Functional Diagram
V
V
V
CC
CC
CC
SEOUT_Z
MAX9324
SEOUT
V
CC
Q0
Q0
D
CLK_EN
Q
Q1
Q1
CLK
CLK
CLK
Q2
Q2
Q3
Q3
GND
GND
8
_______________________________________________________________________________________
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Typical Operating Circuit
3.0V TO
3.6V
0.01µF
0.01µF
0.01µF
0.1µF
V
V
V
CC
CC
CC
Z
= 50Ω
O
Q0
Q0
Z
Z
= 50Ω
= 50Ω
O
O
MAX9324
50Ω
50Ω
LVPECL
RECEIVER
Z
Z
= 50Ω
= 50Ω
CLK
CLK
O
O
Q1
Q1
V
- 2V
CC
Z
Z
= 50Ω
= 50Ω
O
O
50Ω
50Ω
Q2
Q2
V
- 2V
CC
Z
Z
= 50Ω
= 50Ω
O
O
ON
CLK_EN
Q3
Q3
OFF
ON
LVCMOS/
LVTTL
INPUT
OFF
Z
= 50Ω
O
SEOUT_Z
SEOUT
GND
_______________________________________________________________________________________
9
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
10 ______________________________________________________________________________________
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
12,16,20,24L QFN THIN, 4x4x0.8 mm
21-0139
A
______________________________________________________________________________________ 11
One-to-Five LVPECL/LVCMOS Output Clock and
Data Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
相关型号：
MAX9324EUP+T
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), BICMOS, PDSO20, 4.40 MM, TSSOP-20
MAXIM
MAX9324EUP-T
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), BICMOS, PDSO20, 4.40 MM, TSSOP-20
MAXIM
MAX9325EGI
9325 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC28, 5 X 5 MM, QFN-28
ROCHESTER
MAX9325EQI
9325 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTIC, MO-047AB, LCC-28
ROCHESTER
MAX9325EQI+
9325 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC28, PLASTIC, MO-047AB, LCC-28
ROCHESTER
MAX9325EQI+T
Low Skew Clock Driver, 9325 Series, 8 True Output(s), 0 Inverted Output(s), Bipolar, PQCC28, PLASTIC, MO-047AB, LCC-28
MAXIM
MAX9326EGI
LOW SKEW CLOCK DRIVER, 9 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC28, 5 X 5 MM, QFN-28
ROCHESTER
MAX9326EGI-T
Low Skew Clock Driver, 9 True Output(s), 0 Inverted Output(s), Bipolar, 5 X 5 MM, QFN-28
MAXIM
©2020 ICPDF网 联系我们和版权申明