MAX9325EGI [ROCHESTER]
9325 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC28, 5 X 5 MM, QFN-28;
| 型号： | MAX9325EGI |
| 厂家： | 
Rochester Electronics |
| 描述： | 9325 SERIES, LOW SKEW CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC28, 5 X 5 MM, QFN-28 驱动 输出元件 逻辑集成电路 |
| 文件： | 总13页 (文件大小：1413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2511; Rev 3; 11/04
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
General Description
Features
The MAX9325 low-skew, 2:8 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make
the device ideal for clock and data distribution across a
backplane or board. The device selects one of the two
differential HSTL or LVECL/LVPECL inputs and repeats
them at eight differential outputs. Outputs are compati-
ble with LVECL and LVPECL, and can directly drive
50Ω terminated transmission lines.
♦ 50ps (max) Output-to-Output Skew
♦ 1.5ps (max) Random Jitter
♦ Guaranteed 300mV Differential Output at 700MHz
RMS
♦ +2.375V to +3.8V Supplies for Differential
HSTL/LVPECL
♦ -2.375V to -3.8V Supplies for Differential LVECL
♦ Two Selectable Differential Inputs
♦ On-Chip Reference for Single-Ended Inputs
♦ Outputs Low for Inputs Open or at V
♦ Pin Compatible with MC100LVE310
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output volt-
EE
age V
EE.
All inputs have internal pulldown resistors to
BB.
V
The internal pulldowns and a fail-safe circuit
ensure differential low default outputs when the inputs
are left open or at V
.
EE
The MAX9325 operates over a 2.375V to 3.8V supply
range for interfacing to differential HSTL and LVPECL
signals. This allows high-performance clock or data dis-
tribution in systems with a nominal +2.5V or +3.3V sup-
ply. For LVECL operation, the device operates with a
-2.375V to -3.8V supply.
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 PLCC
MAX9325EQI
MAX9325EGI
The MAX9325 is offered in 28-lead PLCC and space-
saving 28-lead QFN packages. The MAX9325 is speci-
fied for operation from -40°C to +85°C.
28 QFN 5mm x 5mm
Applications
Precision Clock Distribution
Functional Diagram appears at end of data sheet.
Low-Jitter Data Repeaters
Pin Configurations
TOP VIEW
INPUT SELECT TRUTH TABLE
25 24 23 22 21 20 19
CLK_SEL
INPUT CLOCK
*
*
L
CLK0, CLK0 SELECTED
CLK1, CLK1 SELECTED
V
EE
Q3
Q3
Q4
V
26
27
28
1
18
17
16
15
14
13
12
H
V
1
2
3
4
5
6
7
21 Q3
20 Q3
19 Q4
EE
CLK_SEL
CLKO
CLK_SEL
CLKO
V
CC
CC
MAX9325
V
CC
18
V
CC
CLKO
2
Q4
Q5
Q5
MAX9325
V
3
CLKO
17 Q4
16 Q5
15 Q5
BB
4
CLK1
V
BB
CLK1
5
6
7
8
9
10 11
*
*
PLCC
QFN
*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO V
.
EE
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
ABSOLUTE MAXIMUM RATINGS
V
- V ...............................................................-0.3V to +4.1V
28-Lead QFN (derate 20.8mW/°C above +70°C) ....1667mW
CC
EE
Inputs (CLK_, CLK_, CLK_SEL) to V ......-0.3V to (V + 0.3V)
θ
θ
in Still Air............................................................+48°C/W
..............................................................................+2°C/W
EE
CC
JA
JC
CLK_ to CLK_ .....................................................................±3.0V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
V
Sink/Source Current................................................±0.65mA
BB
Continuous Power Dissipation (T = +70°C)
A
28-Lead PLCC (derate 10.5mW/°C above +70°C) .....842mW
Human Body Model (CLK_, CLK_, Q_, Q_)....................≥2kV
Soldering Temperature (10s)...........................................+300°C
θ
JA
JC
in Still Air.............................................................+95°C/W
.............................................................................+25°C/W
θ
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
((V - V ) = 2.375V to 3.8V, R = 50Ω ±1% to V - 2V. Typical values are at (V - V ) = 3.3V, V = (V - 1V), V = (V - 1.5V).)
CC
EE
L
CC
CC
EE
IH
CC
IL
CC
(Notes 1–4)
-40°C
TYP
+25°C
+85°C
PARAMETER SYMBOL CONDITIONS
UNITS
MIN
MAX
MIN
TYP
MAX
MIN
TYP
MAX
SINGLE-ENDED INPUT (CLK_SEL)
Single-Ended
Input High
Voltage
V
V
V
CC
- 1.165
CC
CC
V
Figure 1
Figure 1
V
V
V
V
CC
V
IH
CC
CC
CC
- 1.165
- 1.165
Single-Ended
Input Low
Voltage
V
V
CC
- 1.475
CC
V
V
V
V
EE
V
IL
EE
EE
- 1.475
- 1.475
Input Current
I
V
, V
IH IL
-10.0
+150
-10.0
+150 -10.0
+150
µA
IN
DIFFERENTIAL INPUT (CLK_, CLK_)
Single-Ended
Input High
Voltage
V
V
V
CC
- 1.165
CC
CC
V
Figure 1
V
V
V
V
V
CC
V
IH
CC
CC
CC
CC
- 1.165
- 1.165
Single-Ended
Input Low
Voltage
VCC
- 1.475
V
Figure 1
Figure 1
V
V
V
V
V
V
V
V
IL
EE
EE
EE
EE
EE
EE
- 1.475
- 1.475
Differential Input
High Voltage
V
V
V
V
CC
IHD
CC
CC
+ 1.2
+ 1.2
+ 1.2
2
_______________________________________________________________________________________
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
DC ELECTRICAL CHARACTERISTICS (continued)
((V - V ) = 2.375V to 3.8V, R = 50Ω ±1% to V - 2V. Typical values are at (V - V ) = 3.3V, V = (V - 1V), V = (V - 1.5V).)
CC
EE
L
CC
CC
EE
IH
CC
IL
CC
(Notes 1–4)
-40°C
+25°C
+85°C
PARAMETER SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Differential Input
Low Voltage
V
V
V
CC
- 0.095
CC
CC
V
Figure 1
(V - V ) <
V
V
V
EE
V
ILD
EE
EE
- 0.095
- 0.095
V
- V
V
- V
V
CC
- VEE
CC
EE
CC
CC
0.095
0.095
-10.0
0.095
0.095
0.095
0.095
3.0V, Figure 1
EE
EE
Differential Input
Voltage
V
-
IHD
V
V
ILD
(V - V ) ≥
CC
EE
3.0
3.0
3.0
3.0V, Figure 1
V
V
V
, V
,
IH, IL IHD
Input Current
I
+150.0 -10.0
+150.0 -10.0
+150.0
µA
IN
ILD
OUTPUT (Q_, Q_)
Single-Ended
Output High
Voltage
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
Figure 2
V
OH
- 1.085 - 0.977 - 0.880 - 1.025 - 0.949 - 0.88 - 1.025 - 0.929 - 0.88
Single-Ended
Output Low
Voltage
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
Figure 2
Figure 2
V
OL
- V
- 1.810 - 1.695 - 1.620 - 1.810 - 1.697 - 1.62 - 1.810 - 1.698 - 1.62
Differential
Output Voltage
V
535
718
595
749
595
769
mV
OH
OL
REFERENCE VOLTAGE OUTPUT (VBB)
Reference
Voltage Output
IBB = 0.5mA
(Note 5)
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
V
BB
- 1.38 - 1.318 - 1.26 - 1.38 - 1.325 - 1.26 - 1.38 - 1.328 - 1.26
SUPPLY
Supply Current
I
EE
(Note 6)
35
50
39
55
42
65
mA
_______________________________________________________________________________________
3
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
AC ELECTRICAL CHARACTERISTICS—PLCC Package
((V
are at (V
- V ) = 2.375V to 3.8V, R = 50Ω ±1% to V
- 2V, f ≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values
CC
EE
L
CC
IN
- V ) = 3.3V, V = (V
- 1V), V = (V
- 1.5V).) (Note 7)
CC
EE
IH
CC
IL
CC
-40°C
+25°C
+85°C
PARAMETER SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Differential
Input-to-Output
Delay
t
t
PLHD
Figure 2
525
725
550
750
575
775
ps
PHLD
Single-Ended
Input-to-Output
Delay
t
t
PLH
PHL
Figure 3 (Note 8)
(Note 9)
500
750
550
800
600
850
ps
Output-to-
Output Skew
t
50
50
50
ps
ps
SKOO
Part-to-Part
Skew
Differential input
(Note 10)
t
160
190
225
SKPP
f
= 0.5GHz
IN
Added Random
Jitter
t
clock pattern
(Note 11)
1.5
1.5
1.5
ps
RMS
RJ
Added
Deterministic
Jitter
f
= 1.0Gbps,
IN
2E23 - 1 PRBS
t
DJ
100
100
100
ps
P-P
pattern (Note 11)
V
- V
≥
OH
OL
Switching
Frequency
f
300mV clock
pattern
1.5
1.5
1.5
GHz
ps
MAX
Output Rise/Fall
Time (20% to
80%)
t , t
Figure 2
140
440
140
440
140
440
R
F
4
_______________________________________________________________________________________
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
AC ELECTRICAL CHARACTERISTICS—QFN Package
((V
are at (V
- V ) = 2.375V to 3.8V, R = 50Ω ±1% to V
- 2V, f ≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values
CC
EE
L
CC
IN
- V ) = 3.3V, V = (V
- 1V), V = (V
- 1.5V).) (Note 7)
CC
EE
IH
CC
IL
CC
-40°C
+25°C
+85°C
PARAMETER SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Differential
Input-to-Output
Delay
t
t
PLHD
Figure 2
250
575
298
553
309
576
ps
PHLD
Single-Ended
Input-to-Output
Delay
t
t
PLH
PHL
Figure 3 (Note 8)
(Note 9)
253
581
310
586
324
606
ps
Output-to-
Output Skew
t
50
50
50
ps
ps
SKOO
Part-to-Part
Skew
Differential input
(Note 10)
t
192
215
218
SKPP
f
= 0.5GHz
IN
Added Random
Jitter
t
clock pattern
(Note 11)
1.5
95
1.5
95
1.5
95
ps
RMS
RJ
Added
Deterministic
Jitter
f
= 1.0Gbps,
IN
2E23 - 1 PRBS
t
DJ
ps
P-P
pattern (Note 11)
V
- V
≥
OH
OL
Switching
Frequency
f
300mV clock
pattern
1.5
97
1.5
1.5
GHz
ps
MAX
Output Rise/Fall
Time (20% to
80%)
t , t
Figure 2
411
104
210
111
232
R
F
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters production tested at T = +25°C and guaranteed by design over the full operating temperature range.
A
Note 4: Single-ended input operation using V is limited to (V
- V ) = 3.0V to 3.8V.
EE
BB
CC
Note 5: Use V only for inputs that are on the same device as the V reference.
BB
BB
Note 6: All pins open except V
and V
.
EE
CC
Note 7: Guaranteed by design and characterization. Limits are set at ±6 sigma.
Note 8: Measured from the 50% point of the input signal with the 50% point equal to V , to the 50% point of the output signal.
BB
Note 9: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal.
Note 10: Measured between outputs of different parts under identical condition for same-edge transition.
Note 11: Device jitter added to the input signal. Differential input signal.
_______________________________________________________________________________________
5
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
Typical Operating Characteristics
(PLCC package, typical values are at (V
- V ) = 3.3V, V = (V
- 1V), V = (V
- 1.5V), R = 50Ω ±1% to V
- 2V, f
=
CC
EE
IH
CC
IL
CC
L
CC
IN
500MHz, input transition time = 125ps (20% to 80%).)
OUTPUT AMPLITUDE (V - V
)
SUPPLY CURRENT (I
vs. TEMPERATURE
)
OH
OL
EE
vs. FREQUENCY
50
45
40
35
30
25
20
800
700
600
500
400
300
-40
-15
10
35
60
85
0
500
1000
1500
TEMPERATURE (°C)
FREQUENCY (MHz)
PROPAGATION DELAY
vs. TEMPERATURE
TRANSITION TIME vs. TEMPERATURE
750
650
550
450
400
360
320
280
240
200
160
t
PHLD
t
R
t
F
t
PLHD
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
Pin Description
PIN
NAME
FUNCTION
Positive Supply Voltage. Bypass each V to V with 0.1µF and 0.01µF ceramic
PLCC
QFN
CC
EE
capacitors. Place the capacitors as close to the device as possible, with the smaller
value capacitor closest to the device.
1, 8, 15, 22 4, 11, 18, 25
V
CC
2
3
5
6
CLK0
Inverting Differential Clock Input 0. Internal 105kΩ pulldown to V
.
EE
Reference Output Voltage. Connect to the inverting or noninverting clock input to
provide a reference for single-ended operation. When used, bypass V to V
BB
with a
V
CC
BB
0.01µF ceramic capacitor. Otherwise leave open.
4
7
CLK1
CLK1
N.C.
Q7
Noninverting Differential Clock Input 1. Internal 105kΩ pulldown to V
.
EE
5
8
Inverting Differential Clock Input 1. Internal 105kΩ pulldown to V
.
EE
6
9
Not Connected
7
10
12
13
14
15
16
17
19
20
21
22
23
24
26
27
28
1
Inverting Q7 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
9
Q7
Noninverting Q7 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
10
11
12
13
14
16
17
18
19
20
21
23
24
25
26
Q6
Inverting Q6 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Q6
Noninverting Q6 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Q5
Inverting Q5 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Q5
Noninverting Q5 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Q4
Inverting Q4 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Q4
Noninverting Q4 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Q3
Inverting Q3 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Q3
Noninverting Q3 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Q2
Inverting Q2 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Q2
Noninverting Q2 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Q1
Inverting Q1 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Q1
Noninverting Q1 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Q0
Inverting Q0 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Q0
Noninverting Q0 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
V
Negative Supply Voltage
EE
Clock Select Input. When driven low, the CLK0 input is selected. Drive high to select
the CLK1 Input. The CLK_SEL threshold is equal to V . Internal 75kΩ pulldown to V
27
28
2
CLK_SEL
CLK0
—
.
EE
BB
3
Noninverting Differential Clock Input 0. Internal 105kΩ pulldown to V
.
EE
Exposed
Pad
Exposed
Internally Connected to V
EE
_______________________________________________________________________________________
7
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
V
CC
V
CC
V
IHD
V
ILD
V
IHD
V
ILD
(MAX)
(MAX)
(MIN)
(MIN)
V
- V
ILD
IHD
V
V
IH
IL
V
BB
V
- V
ILD
IHD
V
EE
V
EE
DIFFERENTIAL INPUT VOLTAGE DEFINITION
SINGLE-ENDED INPUT VOLTAGE DEFINITION
Figure 1. Input Voltage Definitions
CLK
V
IHD
V
- V
ILD
IHD
V
V
CLK
Q_
ILD
OH
t
t
PHLD
PLHD
V
- V
OH OL
Q_
V
OL
80%
80%
V
V
- V
OH OL
0V (DIFFERENTIAL)
- V
OH OL
20%
20%
DIFFERENTIAL OUTPUT WAVEFORM
Q_ - Q_
t
t
F
R
Figure 2. Differential Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram
8
_______________________________________________________________________________________
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
CLK_ WHEN CLK_ = V
BB
V
IH
V
V
BB
BB
V
V
OR
IL
IH
V
V
t
BB
BB
CLK_ WHEN CLK_ = V
BB
V
IL
t
PLH
PHL
Q_
Q_
V
V
OH
OL
V
- V
OL
OH
Figure 3. Single-Ended Input (CLK_, CLK_) to Output (Q_, Q_) Delay Timing Diagram
±(V
- V ), whichever is less. This limit also applies
EE
CC
Detailed Description
to the difference between a single-ended input and any
reference voltage input.
The MAX9325 low-skew, 2:8 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make the
device ideal for clock and data distribution across a
backplane or board. The device selects one of the two
differential HSTL or LVECL/LVPECL inputs, and repeats
them at eight differential outputs. Outputs are compati-
ble with LVECL and LVPECL, and can directly drive 50Ω
terminated transmission lines.
The single-ended CLK_SEL input has a 75kΩ pulldown
to V that selects the default input, CLK0, CLK0, when
EE
CLK_SEL is left open or at V . All the differential inputs
EE
EE
have 105kΩ pulldowns to V . Internal pulldowns and a
fail-safe circuit ensure differential low default outputs
when the inputs are left open or at V
.
EE
Specifications for the high and low voltages of a differ-
ential input (V and V ) and the differential input
voltage (V
IHD
ILD
A 2:1 mux selects between the two differential inputs,
CLK0, CLK0 and CLK1, CLK1. The 2:1 mux is switched
by the single-ended CLK_SEL input. A logic low selects
the CLK0, CLK0 input. A logic high selects the CLK1,
CLK1 input. The logic threshold for CLK_SEL is set by
an internal V voltage reference. The selected input is
BB
reproduced at eight differential outputs at speeds up to
700MHz.
- V ) apply simultaneously.
IHD
ILD
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a +2.375V to +3.8V supply
range, allowing high-performance clock or data distrib-
ution in systems with a nominal +2.5V or +3.3V supply.
For differential LVECL operation, these devices operate
from a -2.375V to -3.8V supply.
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output volt-
Single-Ended Operation
CLK_SEL is a single-ended input with the input threshold
internally set to V , and can be driven to V
or V or
EE
BB
CC
age (V ). A single-ended input of at least V
95mV
or a differential input of at least 95mV switches the out-
puts to the V and V levels specified in the DC
BB
BB
by a single-ended LVPECL/LVECL signal. The CLK_,
CLK_ are differential inputs but can be configured to
accept single-ended inputs when operating at supply
voltages greater than 2.58V. The recommended supply
voltage for single-ended operation is 3.0V to 3.8V. A dif-
OH
OL
Electrical Characteristics. The maximum magnitude of
the differential input from CLK_ to CLK_ is ±3.0V or
_______________________________________________________________________________________
9
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
ferential input is configured for single-ended operation
Traces
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
by connecting the on-chip reference voltage, V , to an
BB
unused complementary input as a reference. For exam-
ple, the differential CLK0, CLK0 input is converted to a
noninverting, single-ended input by connecting V
to
BB
CLK0 and connecting the single-ended input to CLK0.
Similarly, an inverting input is obtained by connecting
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
V
BB
to CLK0 and connecting the single-ended input to
CLK0. With a differential input configured as single-
ended (using V ), the single-ended input can be driven
BB
to V
or V or with a single-ended LVPECL/LVECL
CC
EE
signal.
When configuring a differential input as a single-ended
input, a user must ensure that the supply voltage (V
-
CC
V
) is greater than 2.58V. This is because the input
EE
Exposed-Pad Package
The 28-lead QFN package (MAX9325EGI) has the
exposed paddle on the bottom of the package that pro-
vides the primary heat removal path from the IC to the
PC board, as well as excellent electrical grounding to
the PC board. The MAX9325EGI’s exposed pad is
high minimum level must be at (V + 1.2V) or higher
EE
for proper operation. The reference voltage V
must
BB
be at least (V + 1.2V) or higher for the same reason
EE
because it becomes the high-level input when the other
single-ended input swings below it. The minimum V
BB
output for the MAX9325 is (V
the minimum V
in a minimum supply (V
- 1.38V). Substituting
CC
internally connected to V . Do not connect the
EE
output for (V = V + 1.2V) results
BB
BB EE
exposed pad to a separate circuit ground plane
- V ) of 2.58V. Rounding up
EE
CC
unless V and the circuit ground are the same.
EE
to standard supplies gives the single-ended operating
supply ranges (V
MAX9325.
- V
) of 3.0V to 3.8V for the
EE
CC
Chip Information
TRANSISTOR COUNT: 1030
When using the V
reference output, bypass it with a
BB
PROCESS: Bipolar
0.01µF ceramic capacitor to V . If not used, leave it
CC
open. The V
reference can source or sink 0.5mA,
BB
which is sufficient to drive two inputs.
Functional Diagram
Applications Information
Q0
Q0
Output Termination
MAX9325
Terminate the outputs through 50Ω to (V - 2V) or use
CC
Q1
CLK0
equivalent Thevenin terminations. Terminate each Q and
Q output with identical termination on each for low output
distortion. When a single-ended signal is taken from the
differential output, terminate both Q_ and Q_.
Q1
CLK0
Q2
105kΩ
Q2
Ensure that output currents do not exceed the current
limits as specified in the Absolute Maximum Ratings
table. Under all operating conditions, the device’s total
thermal limits should be observed.
Q3
0
1
V
EE
Q3
Q4
CLK1
CLK1
Supply Bypassing
to V with high-frequency surface-
EE
Q4
Q5
Bypass each V
CC
105kΩ
mount ceramic 0.1µF and 0.01µF capacitors. Place the
capacitors as close to the device as possible with the
0.01µF capacitor closest to the device pins.
Q5
Q6
V
EE
CLK_SEL
Use multiple vias when connecting the bypass capaci-
Q6
Q7
75kΩ
tors to ground. When using the V
reference output,
BB
bypass it with a 0.01µF ceramic capacitor to V . If the
CC
V
V
BB
reference is not used, it can be left open.
EE
Q7
10 ______________________________________________________________________________________
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
e
INCHES
MIN MAX MIN
D 0.385 0.395 9.78
D1 0.350 0.356 8.89
D2 0.290 0.330 7.37
INCHES
MIN MAX MIN
0.165 0.180 4.20
MAX
10.03
9.04
N
MAX
4.57
3.04
3.96
---
0.53
0.81
0.28
20 AA
A
A1 0.090 0.120 2.29
A2 0.145 0.156 3.69
8.38
D D1 D3
A3 0.020 ---
0.013 0.021 0.33
B1 0.026 0.032 0.66
0.51
D3 0.200 REF
5.08 REF
B
N
28 AB
44 AC
52 AD
68 AE
D
0.485 0.495 12.32 12.57
D1 0.450 0.456 11.43 11.58
D2 0.390 0.430 9.91 10.92
D3 0.300 REF 7.62 REF
C
e
0.009 0.011 0.23
0.050 1.27
D3
D1
D
D
0.685 0.695 17.40 17.65
D1 0.650 0.656 16.51 16.66
D2 0.590 0.630 14.99 16.00
D3 0.500 REF
12.70 REF
D
0.785 0.795 19.94 20.19
D1 0.750 0.756 19.05 19.20
D2 0.690 0.730 17.53 18.54
A2
A
A1
D3 0.600 REF
15.24 REF
B1
B
D
0.985 0.995 25.02 25.27
D1 0.950 0.958 24.13 24.33
D2 0.890 0.930 22.61 23.62
C
D2
A3
D3 0.800 REF
20.32 REF
NOTES:
1. D1 DOES NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED
.20mm (.008") PER SIDE.
3. LEADS TO BE COPLANAR WITHIN .10mm.
4. CONTROLLING DIMENSION: MILLIMETER
5. MEETS JEDEC MO047-XX AS SHOWN IN TABLE.
6. N = NUMBER OF PINS.
PROPRIETARY INFORMATION
TITLE:
FAMILY PACKAGE OUTLINE:
20L, 28L, 44L, 52L, 68L PLCC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0049
D
1
______________________________________________________________________________________ 11
2:8 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2004 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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