MAX9326EQI [MAXIM]
1:9 Differential LVPECL/LVECL/HSTL Clock and Data Driver; 1 ： 9差分LVPECL / LVECL / HSTL时钟和数据驱动
| 型号： | MAX9326EQI |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 1:9 Differential LVPECL/LVECL/HSTL Clock and Data Driver |
| 文件： | 总12页 (文件大小：311K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2538; Rev 2; 10/02
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
General Description
Features
The MAX9326 low-skew, 1:9 differential driver features
extremely low output-to-output skew (50ps max) and
part-to-part skew (225ps max). These features make
the device ideal for clock and data distribution across a
backplane or board. The device repeats an HSTL or
LVECL/LVPECL differential input at nine differential out-
puts. Outputs are compatible with LVECL and LVPECL,
and directly drive 50Ω terminated transmission lines.
ꢀ 50ps (max) Output-to-Output Skew
ꢀ 1.5ps (max) Random Jitter
RMS
ꢀ Guaranteed 300mV Differential Output at 1.0GHz
ꢀ +2.375V to +3.8V Supplies for Differential
HSTL/LVPECL
ꢀ -2.375V to -3.8V Supplies for Differential LVECL
ꢀ On-Chip Reference for Single-Ended Inputs
The differential inputs can be configured to accept a
single-ended signal when the unused complementary
input is connected to the on-chip reference output volt-
ꢀ Outputs Low for Inputs Open or at V
ꢀ Pin Compatible with MC100LVE111
EE
age V
EE.
All inputs have internal pulldown resistors to
BB.
V
The internal pulldowns and a fail-safe circuit
ensure differential low default outputs when the inputs
are left open or at V
.
EE
The MAX9326 operates over a +2.375V to +3.8V supply
range for interfacing to differential HSTL and LVPECL
signals. This allows high-performance clock or data dis-
tribution in systems with a nominal +2.5V or +3.3V sup-
ply. For LVECL operation, the device operates with a
-2.375V to -3.8V supply.
Ordering Information
PART
MAX9326EQI
MAX9326EGI
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
28 PLCC
The MAX9326 is offered in 28-lead PLCC and space-
saving 28-lead QFN packages. The MAX9326 is speci-
fied for operation from -40°C to +85°C.
28 QFN 5mm x 5mm
Functional Diagram appears at end of data sheet.
Applications
Precision Clock Distribution
Low-Jitter Data Repeaters
Pin Configurations
TOP VIEW
25 24 23 22 21 20 19
Q3
Q3
Q4
V
V
18
17
16
15
14
13
12
EE
26
27
28
1
V
1
2
3
4
5
6
7
21 Q3
EE
N.C.
CLK
N.C.
CLK
20 Q3
19 Q4
V
CC
CC
MAX9326
MAX9326
V
CC
18
V
CC
Q4
Q5
Q5
CLK
2
V
BB
3
CLK
17 Q4
16 Q5
15 Q5
4
N.C.
V
BB
N.C.
5
6
7
8
9
10 11
PLCC
QFN*
*CORNER PINS AND EXPOSED PAD ARE CONNECTED TO V
EE
.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
ABSOLUTE MAXIMUM RATINGS
V
- V ...............................................................-0.3V to +4.1V
28-Lead QFN (derate 20.8mW/°C above +70°C) .....1667mW
CC
EE
Inputs (CLK, CLK) to V ...........................-0.3V to (V + 0.3V)
θ
in Still Air.............................................................+48°C/W
...............................................................................+2°C/W
EE
CC
JA
CLK to CLK ........................................................................ 3.0V
Continuous Output Current.................................................50mA
Surge Output Current........................................................100mA
θ
JC
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +150°C
ESD Protection
V
Sink/Source Current................................................ 0.65mA
BB
Continuous Power Dissipation (T = +70°C)
A
28-Lead PLCC (derate 10.5mW/°C above +70°C) .....842mW
Human Body Model (CLK, CLK, Q_, Q_).........................≥2kV
Soldering Temperature (10s)...........................................+300°C
θ
JA
JC
in Still Air.............................................................+95°C/W
.............................................................................+25°C/W
θ
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
((V
- V ) = 2.375V to 3.8V, R = 50Ω 1% to V
- 2V. Typical values are at (V
- V ) = 3.3V, V = (V
- 1V), V = (V
-
CC
CC
EE
L
CC
CC
EE
IH
CC
IL
1.5V).) (Notes 1–4)
-40°C
TYP
+25°C
+85°C
PARAMETER SYMBOL CONDITIONS
UNITS
MIN
MAX
MIN
TYP
MAX
MIN
TYP
MAX
DIFFERENTIAL INPUT (CLK_, CLK_)
Single-Ended
Input High
Voltage
V
V
V
CC
- 1.165
CC
CC
V
Figure 1
Figure 1
V
V
V
V
V
CC
V
V
IH
CC
CC
CC
CC
- 1.165
- 1.165
Single-Ended
Input Low
Voltage
VCC
- 1.475
V
V
V
V
V
V
V
IL
EE
EE
EE
EE
EE
EE
- 1.475
- 1.475
Differential Input
High Voltage
V
Figure 1
Figure 1
V
V
V
V
V
V
V
V
IHD
CC
CC
CC
CC
CC
CC
+ 1.2
+ 1.2
+ 1.2
Differential Input
Low Voltage
V
V
V
V
EE
ILD
EE
EE
- 0.095
- 0.095
- 0.095
(V - V ) <
3.0V, Figure 1
V
- V
V
- V
V
CC
- VEE
CC
EE
CC
CC
0.095
0.095
-10.0
0.095
0.095
0.095
0.095
EE
EE
Differential Input
Voltage
V
V
-
IHD
V
ILD
(V - V ) ≥
CC
EE
3.0
3.0
3.0
3.0V, Figure 1
V
V
V
, V
,
IH, IL IHD
Input Current
I
+150.0 -10.0
+150.0 -10.0
+150.0
µA
IN
ILD
2
_______________________________________________________________________________________
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
DC ELECTRICAL CHARACTERISTICS (continued)
((V
- V ) = 2.375V to 3.8V, R = 50Ω 1% to V
- 2V. Typical values are at (V
- V ) = 3.3V, V = (V
- 1V), V = (V
-
CC
CC
EE
L
CC
CC
EE
IH
CC
IL
1.5V).) (Notes 1–4)
-40°C
+25°C
+85°C
PARAMETER SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
OUTPUT (Q_,
)
Single-Ended
Output High
Voltage
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
Figure 2
V
OH
- 1.085 - 0.977 - 0.880 - 1.025 - 0.949 - 0.88 - 1.025 - 0.929 - 0.88
Single-Ended
Output Low
Voltage
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
Figure 2
Figure 2
V
OL
- V
- 1.810 - 1.695 - 1.620 - 1.810 - 1.697 - 1.62 - 1.810 - 1.698 - 1.62
Differential
Output Voltage
V
535
718
595
749
595
769
mV
OH
OL
REFERENCE VOLTAGE OUTPUT (VBB)
Reference
Voltage Output
IBB = 0.5mA
(Note 5)
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC
CC
CC
CC
CC
CC
V
V
BB
- 1.38 - 1.318 - 1.26 - 1.38 - 1.325 - 1.26 - 1.38 - 1.328 - 1.26
SUPPLY
Supply Current
I
EE
(Note 6)
35
50
39
55
42
65
mA
_______________________________________________________________________________________
3
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
AC ELECTRICAL CHARACTERISTICS–PLCC Package
((V
are at (V
- V ) = 2.375V to 3.8V, R = 50Ω 1% to V
- 2V, f ≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values
CC
CC
EE
L
CC IN
- V ) = 3.3V, V = V(V
- 1V), V = (V
- 1.5V).) (Note 7)
CC
EE
IH
CC
IL
-40°C
+25°C
+85°C
PARAMETER SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Differential
Input-to-Output
Delay
t
t
PLHD
PHLD
Figure 2
365
615
375
605
383
653
ps
Single-Ended
Input-to-Output
Delay
t
t
PLH
PHL
Figure 3 (Note 8)
(Note 9)
350
635
360
685
360
705
ps
Output-to-
Output Skew
t
50
50
50
ps
ps
SKOO
Part-to-Part
Skew
Differential input
(Note 10)
t
190
125
240
SKPP
f
= 0.5GHz
IN
Added Random
Jitter
t
clock pattern
(Note 11)
1.5
95
1.5
95
1.5
95
ps
RMS
RJ
Added
Deterministic
Jitter
f
= 1.0Gbps,
IN
2E23 - 1 PRBS
t
DJ
ps
P-P
pattern (Note 11)
V
- V
≥
OH
OL
Switching
Frequency
f
300mV clock
pattern
1.5
1.5
1.5
GHz
ps
MAX
Output Rise/Fall
Time (20% to
80%)
t , t
R
Figure 2
140
440
140
440
140
440
F
4
_______________________________________________________________________________________
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
AC ELECTRICAL CHARACTERISTICS–QFN Package
((V
are at (V
- V ) = 2.375V to 3.8V, R = 50Ω 1% to V
- 2V, f ≤ 500MHz, input transition time = 125ps (20% to 80%). Typical values
CC
CC
EE
L
CC IN
- V ) = 3.3V, V = V(V
- 1V), V = (V
- 1.5V).) (Note 7)
CC
EE
IH
CC
IL
-40°C
+25°C
+85°C
PARAMETER SYMBOL
CONDITIONS
UNITS
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
Differential
Input-to-Output
Delay
t
t
PLHD
PHLD
Figure 2
217
541
238
448
249
486
ps
Single-Ended
Input-to-Output
Delay
t
t
PLH
PHL
Figure 3 (Note 8)
(Note 9)
213
558
230
506
244
503
ps
Output-to-
Output Skew
t
50
50
50
ps
ps
SKOO
Part-to-Part
Skew
Differential input
(Note 10)
t
192
215
218
SKPP
f
= 0.5GHz
IN
Added Random
Jitter
t
clock pattern
(Note 11)
1.5
95
1.5
95
1.5
95
ps
RMS
RJ
Added
Deterministic
Jitter
f
= 1.0Gbps,
IN
2E23 - 1 PRBS
t
DJ
ps
P-P
pattern (Note 11)
V
- V
≥
OH
OL
Switching
Frequency
f
300mV clock
pattern
1.5
97
1.5
1.5
GHz
ps
MAX
Output Rise/Fall
Time (20% to
80%)
t , t
R
Figure 2
411
104
210
111
232
F
Note 1: Measurements are made with the device in thermal equilibrium.
Note 2: Current into a pin is defined as positive. Current out of a pin is defined as negative.
Note 3: DC parameters production tested at T = +25°C and guaranteed by design over the full operating temperature range.
A
Note 4: Single-ended input operation using V is limited to (V
- V ) = 3.0V to 3.8V.
BB
CC
EE
Note 5: Use V only for inputs that are on the same device as the V reference.
BB
BB
Note 6: All pins open except V
and V
.
EE
CC
Note 7: Guaranteed by design and characterization. Limits are set at 6 sigma.
Note 8: Measured from the 50% point of the input signal with the 50% point equal to V , to the 50% point of the output signal.
BB
Note 9: Measured between outputs of the same part at the signal crossing points for a same-edge transition. Differential input signal.
Note 10: Measured between outputs of different parts under identical conditions for same-edge transition.
Note 11: Device jitter added to the input signal. Differential input signal.
_______________________________________________________________________________________
5
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
Typical Operating Characteristics
(PLCC package, typical values are at (V
500MHz, input transition time = 125ps (20% to 80%).)
- V ) = 3.3V, V = (V
- 1V), V = (V
- 1.5V), R = 50Ω 1% to V
- 2V, f
=
CC
EE
IH
CC
IL
CC
L
CC
IN
OUTPUT AMPLITUDE (V - V
OH
)
SUPPLY CURRENT (I
vs. TEMPERATURE
)
OL
EE
vs. FREQUENCY
50
45
40
35
30
25
20
800
700
600
500
400
300
-40
-15
10
35
60
85
0
500
1000
1500
TEMPERATURE (°C)
FREQUENCY (MHz)
PROPAGATION DELAY
vs. TEMPERATURE
OUTPUT TRANSITION TIME
vs. TEMPERATURE
750
650
550
450
400
360
320
280
240
200
160
t
PHLD
t
R
t
PLHD
t
F
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
Pin Description
PIN
NAME
FUNCTION
Positive Supply Voltage. Bypass each V to V with 0.1µF and 0.01µF ceramic
PLCC
QFN
CC
EE
capacitors. Place the capacitors as close to the device as possible with the smaller
value capacitor closest to the device.
1, 8, 15, 22 4, 11, 18, 25
V
CC
2
3
5
6
CLK
Inverting Differential Clock Input. Internal 105kΩ pulldown to V
.
EE
Reference Output Voltage. Connect to the inverting or noninverting clock input to
provide a reference for single-ended operation. When used, bypass V to V
BB
with a
V
CC
BB
0.01µF ceramic capacitor. Otherwise leave open.
4, 27
5
2, 7
8
N.C.
Q8
Q8
Q7
Q7
Q6
Q6
Q5
Q5
Q4
Q4
Q3
Q3
Q2
Q2
Q1
Q1
Q0
Q0
Not Connected
Inverting Q8 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
6
9
Noninverting Q8 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
7
10
12
13
14
15
16
17
19
20
21
22
23
24
26
27
28
1
Inverting Q7 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
9
Noninverting Q7 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
10
11
12
13
14
16
17
18
19
20
21
23
24
25
26
28
Inverting Q6 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q6 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q5 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q5 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q4 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q4 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q3 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q3 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q2 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q2 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q1 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q1 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
Inverting Q0 Output. Typically terminate with 50Ω resistor to V
- 2V.
CC
Noninverting Q0 Output. Typically terminate with 50Ω resistor to V - 2V.
CC
V
Negative Supply Voltage
EE
3
CLK
Noninverting Differential Clock Input. Internal 105kΩ pulldown to V
.
EE
Exposed
Pad
—
—
Internally Connected to V
EE
_______________________________________________________________________________________
7
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
V
CC
V
CC
V
IHD
V
ILD
V
IHD
V
ILD
(MAX)
(MAX)
(MIN)
(MIN)
V
- V
ILD
IHD
V
V
IH
IL
V
BB
V
- V
ILD
IHD
V
V
EE
EE
DIFFERENTIAL INPUT VOLTAGE DEFINITION
SINGLE-ENDED INPUT VOLTAGE DEFINITION
Figure 1. Input Voltage Definitions
CLK
V
IHD
V
IHD
- V
ILD
V
CLK
Q_
ILD
t
t
PHLD
PLHD
V
V
OH
OL
V
- V
OH OL
Q_
80%
80%
V
V
- V
OH OL
0V (DIFFERENTIAL)
- V
OH OL
20%
20%
DIFFERENTIAL OUTPUT WAVEFORM
Q_ - Q_
t
R
t
F
Figure 2. Differential Input (CLK, CLK) to Output (Q_, Q_) Delay Timing Diagram
8
_______________________________________________________________________________________
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
CLK WHEN CLK = V
BB
V
IH
V
V
BB
BB
V
V
OR
IL
IH
V
V
t
BB
BB
CLK WHEN CLK = V
BB
V
IL
t
PLH
PHL
Q_
Q_
V
V
OH
V
- V
OL
OH
OL
Figure 3. Single-Ended Input (CLK, CLK) to Output (Q_, Q_) Delay Timing Diagram
Specifications for the high and low voltages of a differ-
ential input (V and V ) and the differential input
Detailed Description
IHD
ILD
The MAX9326 low-skew, 1:9 differential driver features
extremely low output-to-output skew (50ps max) and part-
to-part skew (225ps max). These features make the
device ideal for clock and data distribution across a
backplane or board. The device repeats an HSTL or
LVECL/LVPECL differential input at nine differential out-
puts. Outputs are compatible with LVECL and LVPECL,
and can directly drive 50Ω terminated transmission lines.
voltage (V
- V ) apply simultaneously.
IHD
ILD
For interfacing to differential HSTL and LVPECL signals,
these devices operate over a 2.375V to 3.8V supply
range, allowing high-performance clock or data distrib-
ution in systems with a nominal 2.5V or 3.3V supply. For
differential LVECL operation, these devices operate
from a -2.375V to -3.8V supply.
The differential inputs (CLK, CLK) can be configured to
accept a single-ended signal when the unused com-
plementary input is connected to the on-chip reference
Single-Ended Operation
The differential inputs (CLK, CLK) can be configured to
accept single-ended inputs when operating at supply
voltages greater than 2.58V. The recommended supply
voltage for single-ended operation is 3.0V to 3.8V. A dif-
ferential input is configured for single-ended operation
output voltage (V ). A single-ended input of at least
BB
V
95mV or a differential input of at least 95mV
and V levels speci-
BB
switches the outputs to the V
OH
OL
fied in the DC Electrical Characteristics. The maximum
magnitude of the differential input from CLK to CLK is
by connecting the on-chip reference voltage, V , to an
BB
unused complementary input as a reference. For exam-
ple, the differential CLK, CLK input is converted to a non-
3.0V or (V
- V ), whichever is less. This limit also
EE
CC
applies to the difference between a single-ended input
and any reference voltage input.
inverting, single-ended input by connecting V
to CLK
BB
and connecting the single-ended input to CLK. Similarly,
an inverting input is obtained by connecting V to CLK
BB
All the differential inputs have 105kΩ pulldowns to V
.
EE
and connecting the single-ended input to CLK. With a
Internal pulldowns and a fail-safe circuit ensure differ-
ential low default outputs when the inputs are left open
differential input configured as single ended (using V ),
BB
the single-ended input can be driven to V
with a single-ended LVPECL/LVECL signal.
or V or
CC
EE
or at V
.
EE
_______________________________________________________________________________________
9
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
When configuring a differential input as a single-ended
input, a user must ensure that the supply voltage (V
EE
Signal reflections are caused by discontinuities in the
50Ω characteristic impedance of the traces. Avoid dis-
continuities by maintaining the distance between differ-
ential traces, not using sharp corners or using vias.
Maintaining distance between the traces also increases
common-mode noise immunity. Reducing signal skew
is accomplished by matching the electrical length of
the differential traces.
-
CC
V
) is greater than 2.58V. This is because the input high
minimum level must be at (V + 1.2V) or higher for prop-
EE
er operation. The reference voltage V must be at least
BB
(V + 1.2V) or higher for the same reason because it
EE
becomes the high-level input when the other single-
ended input swings below it. The minimum V output for
BB
the MAX9326 is (V
- 1.38V). Substituting the minimum
CC
Exposed-Pad Package
The 28-lead QFN package (MAX9326EGI) has the
exposed paddle on the bottom of the package that pro-
vides the primary heat removal path from the IC to the
PC board, as well as excellent electrical grounding to
the PC board. The MAX9326EGI’s exposed pad is
V
output for (V = V + 1.2V) results in a minimum
BB
BB EE
supply (V
- V ) of 2.58V. Rounding up to standard
EE
CC
supplies gives the single-ended operating supply ranges
(V - V ) of 3.0V to 3.8V for the MAX9326.
CC
EE
When using the V
reference output, bypass it with a
BB
0.01µF ceramic capacitor to V . If not used, leave it
CC
internally connected to V . Do not connect the
EE
open. The V
reference can source or sink 0.5mA,
BB
exposed pad to a separate circuit ground plane
which is sufficient to drive two inputs.
unless V and the circuit ground are the same.
EE
Applications Information
Chip Information
TRANSISTOR COUNT: 1030
Output Termination
Terminate the outputs through 50Ω to V - 2V or use
CC
PROCESS: Bipolar
equivalent Thevenin terminations. Terminate each Q and
Q output with identical termination on each for the lowest
output distortion. When a single-ended signal is taken
from the differential output, terminate both Q_ and Q_.
Functional Diagram
Ensure that output currents do not exceed the current
limits as specified in the Absolute Maximum Ratings.
Under all operating conditions, the device’s total ther-
mal limits should be observed.
Q0
Q0
Q1
Q1
Supply Bypassing
Bypass each V
to V with high-frequency surface-
EE
CC
Q2
Q2
Q3
Q3
mount ceramic 0.1µF and 0.01µF capacitors. Place the
capacitors as close to the device as possible with the
0.01µF capacitor closest to the device pins.
Use multiple vias when connecting the bypass capaci-
tors to ground. When using the V
reference output,
BB
bypass it with a 0.01µF ceramic capacitor to V . If the
CLK
CLK
CC
Q4
V
BB
reference is not used, it can be left open.
Q4
Q5
Q5
Q6
Q6
Q7
Q7
Q8
Q8
Traces
105kΩ
Circuit board trace layout is very important to maintain
the signal integrity of high-speed differential signals.
Maintaining integrity is accomplished in part by reduc-
ing signal reflections and skew, and increasing com-
mon-mode noise immunity.
V
EE
10 ______________________________________________________________________________________
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
e
INCHES
MIN MAX MIN
D 0.385 0.395 9.78
D1 0.350 0.356 8.89
D2 0.290 0.330 7.37
INCHES
MIN MAX MIN
0.165 0.180 4.20
MAX
10.03
9.04
N
MAX
4.57
3.04
3.96
---
0.53
0.81
0.28
20 AA
A
A1 0.090 0.120 2.29
A2 0.145 0.156 3.69
8.38
D D1 D3
A3 0.020 ---
0.013 0.021 0.33
B1 0.026 0.032 0.66
0.51
D3 0.200 REF
5.08 REF
B
N
28 AB
44 AC
52 AD
68 AE
D
0.485 0.495 12.32 12.57
D1 0.450 0.456 11.43 11.58
D2 0.390 0.430 9.91 10.92
D3 0.300 REF 7.62 REF
C
e
0.009 0.011 0.23
0.050 1.27
D3
D1
D
D
0.685 0.695 17.40 17.65
D1 0.650 0.656 16.51 16.66
D2 0.590 0.630 14.99 16.00
D3 0.500 REF
12.70 REF
D
0.785 0.795 19.94 20.19
D1 0.750 0.756 19.05 19.20
D2 0.690 0.730 17.53 18.54
A2
A
A1
D3 0.600 REF
15.24 REF
B1
B
D
0.985 0.995 25.02 25.27
D1 0.950 0.958 24.13 24.33
D2 0.890 0.930 22.61 23.62
C
D2
A3
D3 0.800 REF
20.32 REF
NOTES:
1. D1 DOES NOT INCLUDE MOLD FLASH.
2. MOLD FLASH OR PROTRUSIONS NOT TO EXCEED
.20mm (.008") PER SIDE.
3. LEADS TO BE COPLANAR WITHIN .10mm.
4. CONTROLLING DIMENSION: MILLIMETER
5. MEETS JEDEC MO047-XX AS SHOWN IN TABLE.
6. N = NUMBER OF PINS.
PROPRIETARY INFORMATION
TITLE:
FAMILY PACKAGE OUTLINE:
20L, 28L, 44L, 52L, 68L PLCC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0049
D
1
______________________________________________________________________________________ 11
1:9 Differential LVPECL/LVECL/HSTL Clock and
Data Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2002 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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