MAX4938CTN [MAXIM]
Octal High-Voltage Transmit/Receive Switches; 八通道高压发送/接收开关
| 型号： | MAX4938CTN |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Octal High-Voltage Transmit/Receive Switches |
| 文件： | 总19页 (文件大小：1636K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5541; Rev 1; 3/11
Octal High-Voltage Transmit/Receive Switches
General Description
Features
S Low Power: Low Impedance (5ω) with 1.5mA Bias
The MAX4936–MAX4939 are octal, high-voltage, transmit/
receive (T/R) switches. The T/R switches are based on
a diode bridge topology, and the amount of current
in the diode bridges can be programmed through an
SPIK interface. All devices feature a latch-clear input
to asynchronously turn off all T/R switches and put the
device into a low-power shutdown mode. The MAX4936/
MAX4938 include the T/R switch and grass-clipping
diodes, performing both transmit and receive operations.
The MAX4937/MAX4939 include just the T/R switch and
perform the receive operation only.
Current Only
S Low Noise < 0.5nV/√Hz (typ) with 1.5mA Bias
Current Only
S Wide -3dB Bandwidth 65MHz (typ)
S Easy Programming with SPI Interface
S High Density (8 Channels per Package)
S Grass-Clipping Diodes with Low-Voltage Isolation
(MAX4936/MAX4938)
S Output Clamp Diodes for Receiver Protection
The MAX4936/MAX4938 transmit path is low impedance
during high-voltage transmit and high impedance during
low-voltage receive, providing isolation between transmit
and receive circuitry. The high-voltage transmit path is
high bandwidth, low distortion, and low jitter.
(MAX4936/MAX4937)
S Global Shutdown Control (CLR)
S Each T/R Switch Can Be Individually Programmed
On or Off
The receive path for all devices is low impedance dur-
ing low-voltage receive and high impedance during
high-voltage transmit, providing protection to the receive
circuitry. The low-voltage receive path is high bandwidth,
low noise, low distortion, and low jitter. Each T/R switch
can be individually programmed on or off, allowing these
devices to also be used as receive path multiplexers.
S Low-Voltage Receive Path with High-Voltage
Protection
S Space-Saving, 5mm x 11mm, 56-Pin TQFN Package
Applications
Medical/Industrial Imaging
Ultrasound
The MAX4936/MAX4937 feature clamping diodes to
protect the receiver input from voltage spikes due to
leakage currents flowing through the T/R switches dur-
ing transmission. The MAX4938/MAX4939 do not have
clamping diodes and rely on clamping diodes integrated
in the receiver front end.
High-Voltage Transmit and Low-Voltage Isolation
All devices are available in a small, 56-pin, 5mm x 11mm
TQFN package, and are specified over the commercial
0NC to +70NC temperature range.
Ordering Information/Selector Guide
LOW-VOLTAGE
ISOLATION
HIGH-VOLTAGE
PROTECTION
PART
OUTPUT CLAMP
TEMP RANGE
PIN-PACKAGE
MAX4936CTN+
MAX4937CTN+
MAX4938CTN+**
MAX4939CTN+**
Yes
No
Yes
Yes
Yes
Yes
Yes
Yes
No
0NC to +70NC
0NC to +70NC
0NC to +70NC
0NC to +70NC
56 TQFN-EP*
56 TQFN-EP*
56 TQFN-EP*
56 TQFN-EP*
Yes
No
No
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
**Future product—contact factory for availability.
SPI is a trademark of Motorola, Inc.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Octal High-Voltage Transmit/Receive Switches
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND, unless otherwise noted.)
Voltage Difference Across Any or All COM_ .................. Q230V
Continuous Current (HV_ to COM_ ) (MAX4936/MAX4938)..Q250mA
Continuous Current (Any Other Terminal)..................... Q100mA
Peak Current (HV_ to COM_ ) (MAX4936/MAX4938)
V
V
V
Positive Supply Voltage...................................-0.3V to +6V
, LVCC_ Positive Supply Voltage ....................-0.3V to +6V
, LVEE_ Negative Supply Voltage ....................-6V to +0.3V
DD
CC
EE
CLK, DIN, CLR, LE Input Voltage ..........................-0.3V to +6V
DOUT Output Voltage ..............................-0.3V to (V + 0.3V)
(Pulsed at 1ms, 0.1% Duty Cycle) ................................ Q2.5A
Continuous Power Dissipation (T = +70NC)
DD
A
HV_ Input Voltage (MAX4936/MAX4938) ..........-120V to +120V
COM_ Input/Output Voltage...............................-120V to +120V
NO_ Output Voltage (MAX4936/MAX4937) ...................... Q1.5V
NO_ Output Voltage (MAX4938/MAX4939) ......................... Q6V
Voltage Difference Across Any or
TQFN (derate 41.0mW/NC above +70NC) .................3279mW
Operating Temperature Range............................. 0NC to +70NC
Storage Temperature Range............................ -65NC to +150NC
Junction Temperature ................................................... +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
All HV_ (MAX4936/MAX4938) ...................................... Q230V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
TQFN
Junction-to-Ambient Thermal Resistance (q )...........44°C/W
JA
Junction-to-Case Thermal Resistance (q ).................10°C/W
JC
Note 1: Package thermal resistance were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
ELECTRICAL CHARACTERISTICS
(V
DD
= +1.62V to +5.5V, V
= +2.7V to +5.5V, V = -2.7V to -5.5V, V
= 0V, LVCC_ = V , LVEE_ = V , T = T
to T
,
CC
EE
CLR
CC
EE
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MAX4936/MAX4938 only
MAX4936/MAX4938 only
|V | R +2V, I = Q100mA (MAX4936/
MIN
TYP
MAX UNITS
STATIC CHARACTERISTICS
HV_ Input Voltage Range
V
-115
+115
220
V
V
IRHV_
|Difference Across Any or All
HV_ |
V
HV_
V
HV_
Q
V
HV_
+ 1
HV_
HV_
COM_ Output Voltage Range
COM_ Input Voltage Range
V
V
V
V
ORCM_
MAX4938 only)
- 1
0.85
V
-115
+115
IRCM_
|Difference Across Any or All
COM_ |
220
V
CC
= +5V, V = -5V, |V
| R +2V,
COM_
EE
R = 200I, C = 30pF, I = 10mA
CH_
-1
Q0.75
+1
L
L
(MAX4936/MAX4937 only)
NO_ Output Voltage Range
V
V
ORNO_
V
= +5V, V = -5V, |V
| < +0.4V,
= 1.5mA
V
V
Q 0.1
V
CC
EE
COM_
COM_
- 0.2
COM_
COM_
+ 0.2
R = 200I, C = 30pF, I
L
L
CH_
HV_ to COM_ Continuous
Current
I
V
= 0V (MAX4936/MAX4938 only)
-200
+200
mA
V
CN_
COM_
V
= 0V, I
= Q2A
COM_
CN_
HV_ to COM_ Drop
V
Q2
CN_
(MAX4936/MAX4938 only)
V
= +5V, V = -5V, COM_ = unconnected,
CC
EE
Diode Bridge Voltage Offset
V
OFF_
-200
+200
mV
NO_ = unconnected, I
= 1.5mA
CH
2
______________________________________________________________________________________
Octal High-Voltage Transmit/Receive Switches
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +1.62V to +5.5V, V
= +2.7V to +5.5V, V = -2.7V to -5.5V, V
= 0V, LVCC_ = V , LVEE_ = V , T = T
to T
,
CC
EE
CLR
CC
EE
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
| < +0.3V, V
(MAX4936/MAX4938 only)
|V - V | < +0.3V, V = 0V,
HV_
MIN
TYP
MAX UNITS
|V
- V
= 0V
COM_
HV_
COM_
HV_ Off-Leakage Current
I
-3
+3
+3
+1
FA
FA
LHV_
HV_
COM_
-3
-1
switch is off (MAX4936/MAX4938 only)
COM_ Off-Leakage Current
I
LCOM_
HV_ = unconnected, switch is off
(MAX4936/MAX4938 only)
FA
FA
FA
Switch is off (MAX4937/MAX4939 only)
-1
-2
-1
+1
+2
+1
MAX4936/MAX4937
MAX4938/MAX4939
|V
NO_
| < +0.3V,
NO_ Off-Leakage Current
I
LNO_
switch is off
DYNAMIC CHARACTERISTICS
V
CC
= +5V, V = -5V, R = 200I,
EE L
Diode Bridge Turn-On Time
Diode Bridge Turn-Off Time
t
I
= 1.5mA, C = 30pF, V = Q0.4V,
COM_
200
5
ns
ON
CH
L
Figure 1
V
= +5V, V = -5V, R = 200I,
CC
EE
L
t
I
= 1.5mA, C = 30pF, V
= Q0.4V,
OFF
CH
L
COM_
ms
Figure 1
= I = 10mA
RVR
Reverse Recovery Time
SPI Power-Up Delay
t
I
450
4.5
65
ns
RR
FWD
t
500
Fs
DLY
Small-Signal COM_ to NO_ On
Impedance
V
CC
= +5V, V = -5V, V
= 0V,
NO_
EE
R
I
ICOM_
I
= 1.5mA, f = 5MHz
CH
COM_ to NO_, switch is on,
|V | < +0.4V, V = +5V, V = -5V,
-3dB Bandwidth
Off-Isolation
BW
MHz
COM_
CC
EE
R = 200I, C = 30pF, I
= 1.5mA
L
L
CH
HV_ to COM_, |V
- V
| < +0.3V,
HV_
COM_
V
CC
= +5V, V = -5V, R = 100I,
EE L
-50
-75
-60
C = 100pF, f = 1MHz
L
V
dB
dB
ISO
(MAX4936/MAX4938 only)
COM_ to NO_, switch is off, V
= +5V,
CC
V
EE
= -5V, R = 200I, C = 30pF, f = 1MHz
L L
Between any two HV_ to COM_ channels,
|V | R +2V, V = +5V,
HV_
CC
V
= -5V, R = 100I, C = 100pF,
L L
EE
f = 5MHz (MAX4936/MAX4938 only)
Crosstalk
V
CT
Between any two COM_ to NO_ channels,
switch is on, |V
| < +0.4V, V
= +5V,
COM_
CC
-71
V
EE
= -5V, R = 200I, C = 30pF,
L
L
I
= 1.5mA, f = 5MHz
CH
_______________________________________________________________________________________
3
Octal High-Voltage Transmit/Receive Switches
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +1.62V to +5.5V, V
= +2.7V to +5.5V, V = -2.7V to -5.5V, V
= 0V, LVCC_ = V , LVEE_ = V , T = T
to T
,
CC
EE
CLR
CC
EE
TYP
-90
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
HV_ to COM_, |V | R +2V, V
MIN
MAX UNITS
= +5V,
CC
COM_
V
EE
= -5V, R = 100I, C = 100pF,
L L
f = 5MHz (MAX4936/MAX4938 only)
2nd Harmonic Distortion
HD2
dBc
COM_ to NO_, switch is on, |V | < +0.4V,
COM_
V
= +5V, V = -5V, R = 200I,
-95
-90
CC
EE
L
C = 30pF, I
= 1.5mA, f = 5MHz
L
CH
HV_ to COM_, |V
| R +2V, V
= +5V,
COM_
CC
V
EE
= -5V, R = 100I, C = 100pF,
L L
f = 5MHz (MAX4936/MAX4938 only)
3rd Harmonic Distortion
HD3
dBc
dBc
COM_ to NO_, switch is on, |V | < +0.4V,
COM_
V
CC
= +5V, V = -5V, R = 200I,
-115
EE
L
C = 30pF, I
= 1.5mA, f = 5MHz
L
CH
COM_ to NO_, switch is on,
|V | < +0.4V, V = +5V, V = -5V,
Two-Tone Intermodulation
Distortion (Note 3)
COM_
CC
EE
IMD3
-77
R = 200I, C = 30pF, I = 1.5mA,
CH
L
L
f = 5MHz, f = 5.01MHz
1
2
|V
- V
| < +0.3V
HV_
COM_
HV_ Off Capacitance
C
12
17
pF
pF
HV_(OFF)
(MAX4936/MAX4938 only)
|V - V | < +0.3V, switch is off
HV_
COM_
(MAX4936/MAX4938 only)
COM_ Off Capacitance
C
COM_(OFF)
Switch is off (MAX4937/MAX4939 only)
12
20
NO_ On Capacitance
NO_ Off Capacitance
C
|V | < +0.4V, switch is on
NO_
NO_
pF
pF
NO_(ON)
C
|V
| < +0.4V, switch is off
7.5
NO_(OFF)
DIGITAL I/Os (CLR, DIN, DOUT, CLK, LE)
V
DD
0.5
-
V
DD
= +2.25V to +5.5V
Input High Voltage
V
V
IH
V
DD
V
DD
V
DD
V
DD
V
DD
= +1.62V to +1.98V
= +2.25V to +5.5V
= +1.62V to +1.98V
= +3V
1.4
0.6
V
Input Low Voltage
Input Hysteresis
V
IL
0.4
50
90
V
mV
HYST
= +1.8V
Input Leakage Current
Input Capacitance
DOUT Low Voltage
I
-1
+1
FA
pF
V
CLR, DIN, CLK, LE = GND or V
IL
DD
C
5
IN
V
OL
I
I
= 5mA
0.4
SINK
V
-
DD
0.4
DOUT High Voltage
V
= 5mA
V
OH
SOURCE
POWER SUPPLY (V , V , V
)
DD CC EE
Positive Logic Supply Voltage
Positive Analog Supply Voltage
V
V
+1.62
+2.7
+5.5
+5.5
V
V
DD
CC
Negative Analog Supply
Voltage
V
EE
-5.5
-2.7
V
4
______________________________________________________________________________________
Octal High-Voltage Transmit/Receive Switches
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +1.62V to +5.5V, V
= +2.7V to +5.5V, V = -2.7V to -5.5V, V
= 0V, LVCC_ = V , LVEE_ = V , T = T
to T
,
CC
EE
CLR
CC
EE
A
MIN
MAX
unless otherwise noted. Typical values are at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS
Positive Logic Supply Current
I
+1
FA
CLR, DIN, CLK, LE = GND or V
DD
DD
Per channel, switch is on, V
= +5V,
CC
Positive Analog Supply Current
I
+1.15
+1.5
-1.5
+2
mA
CC
V
EE
= -5V, I
= 1.5mA
CH
Positive Analog Shutdown
Supply Current
I
CLR = high
+1
FA
mA
FA
CC_SHDN
Negative Analog Supply
Current
Per channel, switch is on, V
= -5V, I = 1.5mA
= +5V,
CC
I
-2
-1
-1.15
EE
V
EE
CH
Negative Analog Shutdown
Supply Current
I
CLR = high
EE_SHDN
V
V
to NO_ or V to NO_, switch is on,
EE
CC
On Power-Supply Rejection
Ratio
PSRR
= +5V, V = -5V, R = 200I,
-77
-80
dB
dB
ON
CC
EE
L
C = 30pF, I
= 1.5mA, f = 1MHz
L
CH
V
V
to NO_ or V to NO_, switch is off,
EE
= +5V, V = -5V, R = 200I,
EE L
CC
Off Power-Supply Rejection
Ratio
PSRR
OFF
CC
C = 30pF, f = 1MHz
L
LOGIC TIMING (CLR, DIN, DOUT, CLK, LE) (Figure 1)
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
V
DD
= 3V Q10%
= 1.8V Q10%
= 3V Q10%
= 1.8V Q10%
= 3V Q10%
= 1.8V Q10%
50
100
20
45
20
45
3
CLK Period
t
ns
ns
ns
ns
ns
ns
ns
ns
ns
CP
CLK High Time
t
CH
CLK Low Time
t
CL
= 3V Q10%, C P 20pF
30
70
L
CLK to DOUT Delay
DIN to CLK Setup Time
DIN to CLK Hold Time
t
DO
= 1.8V Q10%, C P 20pF
7
L
= 3V Q10%
= 1.8V Q10%
= 3V Q10%
= 1.8V Q10%
= 3V Q10%
= 1.8V Q10%
= 3V Q10%
= 1.8V Q10%
= 3V Q10%
= 1.8V Q10%
10
16
4
t
DS
t
DH
4
36
65
14
22
20
40
t
t
CLK to LE Setup Time
LE Low Pulse Width
CLR High Pulse Width
CS
WL
t
WC
Note 2: All specifications are 100% production tested at T = +70NC, unless otherwise noted. Specifications at 0NC are guaran-
A
teed by design.
Note 3: See the Ultrasound-Specific IMD3 Specification section.
_______________________________________________________________________________________
5
Octal High-Voltage Transmit/Receive Switches
D
D
D
N - 1
DIN
LE
50%
50%
50%
N + 1
N
50%
t
WL
t
CS
50%
50%
CLK
t
t
DH
DS
t
DO
50%
t
DOUT
T/R SWITCH
CLR
t
OFF
ON
OFF
ON
90%
10%
50%
50%
t
WC
Figure 1. Serial Interface Timing
6
______________________________________________________________________________________
Octal High-Voltage Transmit/Receive Switches
Typical Operating Characteristics
(V
= +3V, V
= +5V, V = -5V, I
= 1.5mA, R
= 200I, R
= 200I, f = 5MHz, V
= 0V, T = +25NC, unless other-
CLR A
DD
CC
EE
CH
COM_
NO_
wise noted.)
I
, I SUPPLY CURRENT
I
, I SUPPLY CURRENT
vs. TEMPERATURE
CC EE
CC EE
vs. V , V SUPPLY VOLTAGE
CC
EE
2.0
1.5
1.0
0.5
0
2.00
1.75
1.50
1.25
1.00
ONE CHANNEL ON
ONE CHANNEL ON
2.5
3.0
V
3.5
4.0
4.5
5.0
5.5
-40
-15
10
35
60
85
, V SUPPLY VOLTAGE (V)
EE
TEMPERATURE (°C)
CC
I
, I
SUPPLY SHUTDOWN CURRENT
vs. TEMPERATURE
COM_ TO NO_ SMALL-SIGNAL TRANSFER
FUNCTION vs. FREQUENCY
CC_SHDN EE_SHDN
0.20
0.15
0.10
0.05
0
0
-0.5
-1.0
-1.5
R
= 50Ω
NO_
I
= 1.5mA
CH
I
= 3mA
CH
0
14
28
42
56
70
0
5
10
FREQUENCY (MHz)
15
20
TEMPERATURE (°C)
COM_ TO NO_ IMPEDANCE
vs. FREQUENCY
COM_ TO NO_ CROSSTALK
vs. FREQUENCY
9
8
7
6
5
4
3
2
1
0
-60
-70
R
R
= 200Ω
NO_
= 200Ω
COM_
I
= 1.5mA
CH
-80
I
= 3mA
CH
-90
-100
0
5
10
FREQUENCY (MHz)
15
20
1
10
FREQUENCY (MHz)
_______________________________________________________________________________________
7
Octal High-Voltage Transmit/Receive Switches
Typical Operating Characteristics (continued)
(V
= +3V, V
= +5V, V = -5V, I
= 1.5mA, R
= 200I, R
= 200I, f = 5MHz, V
= 0V, T = +25NC, unless other-
DD
CC
EE
CH
COM_
NO_
CLR
A
wise noted.)
COM_/NO_ SMALL SIGNAL vs. TIME
(2MHz GAUSSIAN SIGNAL AT COM_)
COM_/NO_ FFT vs. FREQUENCY
(2MHz GAUSSIAN SIGNAL AT COM_)
PSRR vs. FREQUENCY
-70
0.08
0.06
0.04
0.02
0
0
-20
-40
-60
-80
R
= 50Ω
R
R
= 200Ω
R
= 50Ω
NO_
NO_
NO_
NO_
COM_
COM_
NO_
= 200Ω
COM_
PSRR_V
EE
-75
-80
-85
-0.02
-0.04
-0.06
-0.08
PSRR_V
CC
1
10
-5 -4 -3 -2 -1
0
1
2
3
4
5
0
5
10
15
FREQUENCY (MHz)
TIME (ms)
FREQUENCY (MHz)
COM_/NO_ vs. TIME
HV_/COM_ vs. TIME
FOR CLR TOGGLING FROM V TO GND TO V
DD
DD
MAX4936-39 toc11
MAX4936-39 toc10
COM_LOAD = 200Ω
V
HV_
V
50V/div
COM_
5mV/div
NO_LOAD = 200Ω30pF
COM_LOAD = 100Ω100pF
V
COM_
50V/div
V
NO_
5mV/div
200µs/div
100ns/div
8
______________________________________________________________________________________
Octal High-Voltage Transmit/Receive Switches
Pin Configuration
TOP VIEW
40 39 38 37 36 35 34 33 32 31 30 29
48 47 46 45 44 43 42 41
NO1 49
LVCC1 50
LE 51
28 NO8
27 LVCC8
26 DOUT
25 DIN
CLR 52
GND 53
N.C. 54
COM1 55
HV1 56
MAX4936/MAX4938
24 CLK
23 GND
22 COM8
21 HV8
*EP
+
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29
48 47 46 45 44 43 42 41
NO1 49
LVCC1 50
LE 51
28 NO8
27 LVCC8
26 DOUT
25 DIN
CLR 52
GND 53
N.C. 54
COM1 55
N.C. 56
MAX4937/MAX4939
24 CLK
23 GND
22 COM8
21 N.C.
*EP
+
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20
TQFN
(5mm × 11mm)
*CONNECT EP TO GND.
Pin Description
PIN
NAME
FUNCTION
MAX4936/
MAX4938
MAX4937/
MAX4939
T/R Switch 2 Input. When the switch is on, low-voltage signals are passed
through from COM2 to NO2, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked.
1
2
1
COM2
HV2
T/R Switch 2 Input. COM2 follows HV2 when high-voltage signals are present on
HV2. HV2 is isolated from COM2 when low-voltage signals are present on COM2.
—
_______________________________________________________________________________________
9
Octal High-Voltage Transmit/Receive Switches
Pin Description (continued)
PIN
NAME
FUNCTION
MAX4936/
MAX4938
MAX4937/
MAX4939
2, 3, 5, 6, 8,
3, 6, 15, 18, 54 13, 15, 16, 18,
19, 21, 54, 56
N.C.
No Connection. Not internally connected.
T/R Switch 3 Input. When the switch is on, low-voltage signals are passed
through from COM3 to NO3, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked.
4
5
7
4
—
7
COM3
HV3
T/R Switch 3 Input. COM3 follows HV3 when high-voltage signals are present on
HV3. HV3 is isolated from COM3 when low-voltage signals are present on COM3.
T/R Switch 4 Input. When the switch is on, low-voltage signals are passed
through from COM4 to NO4, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked.
COM4
HV4
T/R Switch 4 Input. COM4 follows HV4 when high-voltage signals are present on
HV4. HV4 is isolated from COM4 when low-voltage signals are present on COM4.
8
9
—
9
Positive Logic Supply. Bypass V
to GND with a 1FF or greater ceramic
DD
V
V
DD
capacitor as close as possible to the device.
Positive Analog Supply. Bypass V to GND with a 1FF or greater ceramic
CC
10
10
CC
capacitor as close as possible to the device.
Negative Analog Supply. Bypass V to GND with a 1FF or greater ceramic
capacitor as close as possible to the device.
EE
11
12, 23, 53
13
11
12, 23, 53
—
V
EE
GND
HV5
Ground
T/R Switch 5 Input. COM5 follows HV5 when high-voltage signals are present on
HV5. HV5 is isolated from COM5 when low-voltage signals are present on COM5.
T/R Switch 5 Input. When the switch is on, low-voltage signals are passed
through from COM5 to NO5, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked.
14
16
17
19
20
21
22
14
—
17
—
20
—
22
COM5
HV6
T/R Switch 6 Input. COM6 follows HV6 when high-voltage signals are present on
HV6. HV6 is isolated from COM6 when low-voltage signals are present on COM6.
T/R Switch 6 Input. When the switch is on, low-voltage signals are passed
through from COM6 to NO6, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked.
COM6
HV7
T/R Switch 7 Input. COM7 follows HV7 when high-voltage signals are present on
HV7. HV7 is isolated from COM7 when low-voltage signals are present on COM7.
T/R Switch 7 Input. When the switch is on, low-voltage signals are passed
through from COM7 to NO7, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked.
COM7
HV8
T/R Switch 8 Input. COM8 follows HV8 when high-voltage signals are present on
HV8. HV8 is isolated from COM8 when low-voltage signals are present on COM8.
T/R Switch 8 Input. When the switch is on, low-voltage signals are passed
through from COM8 to NO8, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked.
COM8
10 _____________________________________________________________________________________
Octal High-Voltage Transmit/Receive Switches
Pin Description (continued)
PIN
NAME
FUNCTION
MAX4936/
MAX4938
MAX4937/
MAX4939
24
25
26
24
25
26
CLK
DIN
Serial-Clock Input
Serial-Data Input
Serial-Data Output
DOUT
Inductor V
Connection. Connect an inductor between LVCC8 and V
to
CC
CC
27
27
LVCC8
NO8
improve noise performance, otherwise connect LVCC8 to V
.
CC
T/R Switch 8 Output. When the switch is on, low-voltage signals are passed
through from COM8 to NO8, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked. NO8 is
limited with clamping diodes on MAX4936/MAX4937.
28
28
Inductor V Connection. Connect an inductor between LVEE8 and V to
EE
EE
29
30
29
30
LVEE8
LVCC7
improve noise performance; otherwise, connect LVEE8 to V
.
EE
Inductor V
Connection. Connect an inductor between LVCC7 and V
to
CC
CC
improve noise performance; otherwise, connect LVCC7 to V
.
CC
T/R Switch 7 Output. When the switch is on, low-voltage signals are passed
through from COM7 to NO7, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked. NO7 is
limited with clamping diodes on MAX4936/MAX4937.
31
31
NO7
Inductor V Connection. Connect an inductor between LVEE7 and V to
EE
EE
32
33
32
33
LVEE7
LVCC6
improve noise performance; otherwise, connect LVEE7 to V
.
EE
Inductor V
Connection. Connect an inductor between LVCC6 and V
to
CC
CC
improve noise performance; otherwise, connect LVCC6 to V
.
CC
T/R Switch 6 Output. When the switch is on, low-voltage signals are passed
through from COM6 to NO6, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked. NO6 is
limited with clamping diodes on MAX4936/MAX4937.
34
34
NO6
Inductor V Connection. Connect an inductor between LVEE6 and V to
EE
EE
35
36
35
36
LVEE6
LVCC5
improve noise performance; otherwise, connect LVEE6 to V
.
EE
Inductor V
Connection. Connect an inductor between LVCC5 and V
to
CC
CC
improve noise performance; otherwise, connect LVCC5 to V
.
CC
T/R Switch 5 Output. When the switch is on, low-voltage signals are passed
through from COM5 to NO5, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked. NO5 is
limited with clamping diodes on MAX4936/MAX4937.
37
37
NO5
Inductor V Connection. Connect an inductor between LVEE5 and V to
EE
EE
38
39
38
39
LVEE5
LVEE4
improve noise performance; otherwise, connect LVEE5 to V
.
EE
Inductor V Connection. Connect an inductor between LVEE4 and V to
EE
EE
improve noise performance; otherwise, connect LVEE4 to V
.
EE
T/R Switch 4 Output. When the switch is on, low-voltage signals are passed
through from COM4 to NO4, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked. NO4 is
limited with clamping diodes on MAX4936/MAX4937.
40
40
NO4
______________________________________________________________________________________ 11
Octal High-Voltage Transmit/Receive Switches
Pin Description (continued)
PIN
NAME
FUNCTION
MAX4936/
MAX4938
MAX4937/
MAX4939
Inductor V
Connection. Connect an inductor between LVCC4 and V
to
CC
CC
41
42
41
42
LVCC4
LVEE3
improve noise performance; otherwise, connect LVCC4 to V
.
CC
Inductor V Connection. Connect an inductor between LVEE3 and V to
EE
EE
improve noise performance; otherwise, connect LVEE3 to V
.
EE
T/R Switch 3 Output. When the switch is on, low-voltage signals are passed
through from COM3 to NO3, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked. NO3 is
limited with clamping diodes on MAX4936/MAX4937.
43
43
NO3
Inductor V
Connection. Connect an inductor between LVCC3 and V
to
CC
CC
44
45
44
45
LVCC3
LVEE2
improve noise performance; otherwise, connect LVCC3 to V
.
CC
Inductor V Connection. Connect an inductor between LVEE2 and V to
EE
EE
improve noise performance; otherwise, connect LVEE2 to V
.
EE
T/R Switch 2 Output. When the switch is on, low-voltage signals are passed
through from COM2 to NO2, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked. NO2 is
limited with clamping diodes on MAX4936/MAX4937.
46
46
NO2
Inductor V
Connection. Connect an inductor between LVCC2 and V
to
CC
CC
47
48
47
48
LVCC2
LVEE1
improve noise performance; otherwise, connect LVCC2 to V
.
CC
Inductor V Connection. Connect an inductor between LVEE1 and V to
EE
EE
improve noise performance; otherwise, connect LVEE1 to V
.
EE
T/R Switch 1 Output. When the switch is on, low-voltage signals are passed
through from COM1 to NO1, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked. NO1 is
limited with clamping diodes on MAX4936/MAX4937.
49
49
NO1
Inductor V
Connection. Connect an inductor between LVCC1 and V
to
CC
CC
50
51
50
51
LVCC1
improve noise performance; otherwise, connect LVCC1 to V
.
CC
Active-Low Latch-Enable Input. Drive LE low to change the contents of the latch
and update the state of the switches. Drive LE high to hold the contents of the
latch.
LE
Active-High Latch-Clear Input. Drive CLR high to clear the contents of the latch
and disable all the switches. When CLR is driven high, the device enters
shutdown mode. CLR does not affect the contents of the register.
52
55
52
55
CLR
T/R Switch 1 Input. When the switch is on, low-voltage signals are passed
through from COM1 to NO1, while high-voltage signals are blocked. When the
switch is off, both low-voltage and high-voltage signals are blocked.
COM1
T/R Switch 1 Input. COM1 follows HV1 when high-voltage signals are present on
HV1. HV1 is isolated from COM1 when low-voltage signals are present on COM1.
56
—
—
—
HV1
EP
Exposed Pad. Internally connected to GND. Connect EP to a large ground plane
to maximize thermal performance. Do not use EP as the only GND connection.
12 _____________________________________________________________________________________
Octal High-Voltage Transmit/Receive Switches
MAX4938 include the T/R switch and grass-clipping
diodes, performing both transmit and receive operations.
The MAX4937/MAX4939 include just the T/R switch and
Functional Diagram
V
V
CC
DD
perform the receive operation only.
The MAX4936/MAX4938 transmit path is low impedance
during high-voltage transmit and high impedance during
low-voltage receive, providing isolation between transmit
and receive circuitry. The high-voltage transmit path is
high bandwidth, low distortion, and low jitter.
MAX4936−MAX4939
(SINGLE CHANNEL)
*
HV_
LVCC_
NO_
V
EE
The receive path for all devices is low impedance dur-
ing low-voltage receive and high impedance during
high-voltage transmit, providing protection to the receive
circuitry. The low-voltage receive path is high bandwidth,
low noise, low distortion, and low jitter. Each T/R switch
can be individually programmed on or off, allowing these
devices to also be used as receive path multiplexers.
COM_
**
V
CC
LVEE_
SPI LOGIC
The MAX4936/MAX4937 feature clamping diodes to
protect the receiver input from voltage spikes due to
leakage currents flowing through the T/R switches dur-
ing transmission. The MAX4938/MAX4939 do not have
clamping diodes and rely on clamping diodes integrated
in the receiver front-end.
GND
CLK DIN DOUT LE CLR
V
EE
*LOW-VOLTAGE ISOLATION DIODES AVAILABLE ON MAX4936/MAX4938 ONLY.
**OUTPUT CLAMP DIODES AVAILABLE ON MAX4936/MAX4937 ONLY.
Serial Interface
All the devices are controlled by a serial interface with a
12-bit serial shift register and transparent latch (Figure 2).
Each of the first 4 data bits controls the bias current into
the diode bridges (see Figure 3 and Table 2), while the
remaining 8 data bits control a T/R switch (Table 1). Data
on DIN is clocked with the most significant bit (MSB) first
into the shift register on the rising edge of CLK. Data is
clocked out of the shift register onto DOUT on the rising
edge of CLK. DOUT reflects the status of DIN, delayed
by 12 clock cycles (Figure 4).
Detailed Description
The MAX4936–MAX4939 are octal, high-voltage trans-
mit/receive (T/R) switches. The T/R switches are based
on a diode bridge topology, and the amount of current
in the diode bridges can be programmed through an
SPI interface. All devices feature a latch-clear input to
asynchronously turn off all T/R switches and put the
device into a low-power shutdown mode. The MAX4936/
SPI LOGIC
Transmit/Receive Switch
The T/R switch is based on a diode bridge topology. The
amount of bias current into each diode bridge is adjust-
able by setting the S0–S3 switches through the serial
interface (see Figure 3 and Table 2).
REGISTER
CLK
D0
D1
D10
S2
D11
S3
DOUT
DIN
Latch Enable (LE)
Drive LE logic-low to change the contents of the latch
and update the state of the T/R switches (Figure 4).
Drive LE logic-high to hold the contents of the latch and
prevent changes to the switches’ states. To reduce noise
due to clock feedthrough, drive LE logic-high while data
is clocked into the shift register. After the data shift reg-
ister is loaded with valid data, pulse LE logic-low to load
the contents of the shift register into the latch.
LATCH
CLR
LE
ON1
ON2
Figure 2. SPI Logic
______________________________________________________________________________________ 13
Octal High-Voltage Transmit/Receive Switches
Latch Clear (CLR)
LVCC (LVEE)
Drive CLR logic-high to reset the contents of the latch to
zero and open all T/R switches. CLR does not affect the
contents of the shift register. Once CLR is high again,
and LE is driven low, the contents of the shift register are
loaded into the latch.
S3
S2
S1
S0
R3
R2
R1
R0
Power-On Reset
The devices feature a power-on-reset circuit to ensure
all switches are off at power-on. The internal 12-bit serial
shift register and latch are set to zero on power-up.
DIODE BRIDGE
Figure 3. Diode Bias Current Control
LE
CLK
D9
D1
D0
DIN
D11
MSB
D10
LSB
D10'
D1'
D0'
D11
D11'
D9'
DOUT
D11'–D0' FROM PREVIOUS DATA
POWER-UP DEFAULT: D11–D0 = 0
Figure 4. Latch-Enable Interface Timing
14 _____________________________________________________________________________________
Octal High-Voltage Transmit/Receive Switches
Table 1. Serial Interface Programming
CONTROL
BITS
DATA BITS
FUNCTION
D0
(LSB)
D11
(MSB)
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
CLR
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
S0
S1
S2
S3
LE
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
Off
On
H
L
H
X
X
Off
On
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Hold Previous State
Off Off Off
Off
Off
Off
Off
Off
Off
Off
Off
Off
L = Low, H = High, X = Don’t care.
Table 2. Diode Bias Current
RESISTOR
COMBINATION
TYPICAL DIODE BRIDGE CURRENT
(mA) vs. S[3:0] CONTROL BITS (*)
SWITCHES
RESISTORS (I)
S3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
R3
R2
R1
R0
(I)
V
CC
= 3.0V
V
CC
= 5.0V
350
350
350
350
350
350
350
350
350
350
350
350
350
350
350
350
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
700
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
1400
2800
2800
2800
2800
2800
2800
2800
2800
2800
2800
2800
2800
2800
2800
2800
2800
—
0
0
2800
1400
933
0.78
1.50
1.58
2.36
3.14
3.98
4.72
5.50
6.28
7.08
7.86
8.64
9.42
10.22
11.00
11.78
3.00
4.50
700
6.00
560
7.50
467
9.00
400
10.50
12.00
13.50
15.00
16.50
18.00
19.50
21.00
22.50
350
311
280
255
233
215
200
187
*V = -V
EE
CC
______________________________________________________________________________________ 15
Octal High-Voltage Transmit/Receive Switches
all devices, and drive LE logic-low to update all devices
simultaneously. Drive CLR high to open all the switches
simultaneously. Additional shift registers can be includ-
ed anywhere in series with the device data chain.
Applications Information
For medical ultrasound applications, see Figures 5, 6,
and 7.
Ultrasound-Specific IMD3 Specification
Supply Sequencing and Bypassing
Unlike typical communications applications, the two input
The devices do not require special sequencing of the
tones are not equal in magnitude for the ultrasound-spe-
V
DD
, V
and V
supply voltages; however, analog
CC,
EE
cific IMD3 two-tone specification. In this measurement,
F1 represents reflections from tissue and F2 represents
reflections from blood. The latter reflections are typically
25dB lower in magnitude, and hence the measurement
is defined with one input tone 25dB lower than the other.
The IMD3 product of interest (F1 - (F2 - F1)) presents
itself as an undesired Doppler error signal in ultrasound
applications. See Figure 8.
switch inputs must be unconnected, or satisfy V
P
EE
(V
, V
, V
) P V
during power up and power
HV_ COM_ NO_
CC
down. Bypass V , V , and V
to GND with a 1FF
DD CC
EE
ceramic capacitor as close as possible to the device.
PCB Layout
The pin configuration is optimized to facilitate a very
compact physical layout of the device and its associated
discrete components. A typical application for this device
might incorporate several devices in close proximity to
handle multiple channels of signal processing.
Logic Levels
The digital interface inputs CLK, DIN, LE, and CLR are
tolerant of up to +5.5V, independent of the V
supply
DD
The exposed pad (EP) of the TQFN-EP package provides
a low thermal resistance path to the die. It is important that
the PCB on which the device is mounted be designed to
conduct heat from the EP. In addition, provide the EP with
a low-inductance path to electrical ground. The EP must
be soldered to a ground plane on the PCB, either directly
or through an array of plated through holes.
voltage, allowing compatibility with higher voltage con-
trollers.
Daisy-Chaining Multiple Devices
Digital output DOUT is provided to allow the connec-
tion of multiple devices by daisy-chaining (Figure 9).
Connect each DOUT to the DIN of the subsequent
device in the chain. Connect CLK, LE, and CLR inputs of
Application Diagrams
+3V
+5V
HV
MUX
XMT
V
V
CC
DD
TRANSDUCERS
COM_
MAX4936/MAX4938
HV_
NO_
HV
MUX
RELAY
MUX
CLK
DIN
DOUT
CLR
LE
SPI
CONTROL
RCV
GND
V
EE
HV
MUX
CONNECTORS
-5V
Figure 5. Ultrasound T/R Path with One Transmit per Receive Channel (One Channel Only)
16 _____________________________________________________________________________________
Octal High-Voltage Transmit/Receive Switches
Application Diagrams (continued)
XMT
+3V
+5V
TRANSDUCERS
HV
MUX
V
V
CC
DD
COM_
MAX4937/MAX4939
HV
MUX
RELAY
MUX
RCV
NO_
CLK
DIN
DOUT
CLR
LE
SPI
CONTROL
GND
V
EE
HV
MUX
CONNECTORS
-5V
Figure 6. Ultrasound T/R Path with One Transmit per Receive Channel and External Isolation (One Channel Only)
MAX4936
HV_
DRIVER
< ±±11V
TRANSMIT PATH
HV_
DRIVER
< ±±11V
TRANSDUCERS
V
V
CC
HV
MUX
EE
COM_
COM_
NO_ < 511mV
HV
MUX
RELAY
MUX
V
V
CC
EE
LNA
V
V
CC
EE
HV
MUX
RECEIVE PATH
NO_ < 511mV
CONNECTORS
V
V
CC
EE
Figure 7. Ultrasound T/R Path with Multiple Transmits per Receive Channel
______________________________________________________________________________________ 17
Octal High-Voltage Transmit/Receive Switches
Application Diagrams (continued)
-25dB
ULTRASOUND IMD3
F1 - (F2 - F1)
F1
F2
F2 + (F2 - F1)
Figure 8. Ultrasound IMD3 Measurement Technique
U1
DOUT
U2
U_
DOUT
DIN
DIN
DIN
DIN
DOUT
MAX4936-
MAX4939
MAX4936-
MAX4939
MAX4936-
MAX4939
CLK
LE
CLK
LE
CLK
LE
CLK
LE
CLR
CLR
CLR
CLR
Figure 9. Interfacing Multiple Devices by Daisy-Chaining
Chip Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/packages. Note that a
“+”, “#”, or “-“ in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BCDMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
56 TQFN-EP
T56511+1
21-0187
90-0087
18 _____________________________________________________________________________________
Octal High-Voltage Transmit/Receive Switches
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
9/10
Initial release
—
Updated the Diode Bridge Turn-Off Time and the NO_ On Capacitance in the
Electrical Characteristics, updated Figure 7
1
3/11
3, 4, 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
19
©
2011 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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