MAX4940A [MAXIM]
Dual/Quad, Unipolar/Bipolar, High-Voltage Digital Pulsers;
| 型号： | MAX4940A |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Dual/Quad, Unipolar/Bipolar, High-Voltage Digital Pulsers |
| 文件： | 总18页 (文件大小：1714K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4591; Rev 0; 4/09
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
General Description
Features
S High-Density Quad-Channel Pulser in One
The MAX4940/MAX4940A integrated circuits generate
high-voltage, high-frequency, unipolar or bipolar pulses
from low-voltage logic inputs. These quad/dual pulsers
feature independent logic inputs, independent high-volt-
age pulser outputs with active clamps and independent
high-voltage supply inputs.
Package
S 0 to +220V Unipolar or Q110V Bipolar Outputs
S 8.5I (typ) Output Impedance and 2.0A (typ)
Output Current
S 21I (typ) Always-On Active Clamp with Integrated
The MAX4940/MAX4940A feature quad, high-voltage puls-
ers with 8.5I output impedance for the high-voltage
outputs and a 21I impedance for the active clamp. The
high-voltage outputs can provide 2.0A (typ) output current.
Blocking Diodes
S Integrated Output Diodes (MAX4940A Only)
S No Special Power-Supply Sequencing Required
for Trilevel Applications
All devices use two logic inputs per channel to con-
trol the positive and negative pulses. The MAX4940/
MAX4940A have a dedicated input to control the active
clamp. All devices feature an independent enable input
EN. All digital inputs are CMOS compatible (see the
Ordering Information/Selector Guide).
S Matched Rise/Fall Times and Matched
Propagation Delays
S CMOS-Compatible Logic Inputs
S 56-Pin, 8mm x 8mm, TQFN Package
The MAX4940/MAX4940A are available in a 56-pin, 8mm x
8mm, TQFN exposed pad package and are specified over
the 0NC to +70NC commercial temperature range.
Ordering Information/
Selector Guide
Warning: Exercise caution. The MAX4940/MAX4940A are
OUTPUT
BLOCKING CURRENT
DIODE
OUTPUT
PIN-
PACKAGE
designed to operate with high voltages.
PART
(A)
Applications
Ultrasound Medical Imaging
Flaw Detection
MAX4940CTN+
MAX4940ACTN+
None
2.0 (typ)
56 TQFN-EP*
56 TQFN-EP*
OUT2A,
OUT2B
2.0 (typ)
Piezoelectric Drivers
Note: Devices operate over the 0°C to +70°C temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Test Instruments
Cleaning Equipment
Pin Configuration
TOP VIEW
42 41 40 39 38 37 36 35 34 33 32 31 30 29
28
27
26
25
24
23
22
21
20
19
18
17
OUT1A
GND
OUT1B
GND
43
44
45
46
47
48
49
50
51
52
53
54
V
V
PP1
PP1
C
C
C
C
C
C
C
C
C
GP1A
GN1A
GN2A
GP1B
GN1B
GN2B
GP2B
DP2B
DN2B
DN1B
DP1B
CC
C
C
C
C
GP2A
DP2A
DN2A
DN1A
MAX4940
MAX4940A
C
C
C
DP1A
V
V
CC
GND 55
56
*EP
16 GND
15
+
V
DD
V
EE
1
2
3
4
5
6
7
8
9
10 11 12 13 14
TQFN
*EP = EXPOSED PAD. CONNECT EP TO V
.
NN1
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
ABSOLUTE MAXIMUM RATINGS
(Voltages referenced to GND.)
C
, C
Voltage................................................-0.3V to V
DP_ DN_ CC
V
V
V
V
V
V
Logic Supply Voltage......................................-0.3V to +6V
Output Driver Positive Supply Voltage..........-0.3V to +15V
Output Driver Negative Supply Voltage ........-15V to +0.3V
Continuous Power Dissipation (T = +70NC)
56-Pin TQFN (derate 47.6mW/NC above +70NC).......3809mW
Thermal Resistance (Note 1)
DD
A
CC
EE
B
................................................................................21NC/W
.................................................................................1NC/W
High-Positive Supply Voltage........-0.3V to (V
+ 220V)
JA
PP_
NN_
PP1
NN_
B
Low-Negative Supply Voltage ...................-220V to +0.3V
- V , V - V Supply Voltage .........-0.6V to +250V
JC
Operating Temperature Range............................. 0NC to +70NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
NN1 PP2
NN2
INP_, INN_, CLP_, EN Logic Input........... -0.3V to (V
C
C
+ 0.3V)
DD
Voltage ......................... (-0.3V + V
Voltage............................(+0.3V + V
) to (+15V + V
)
)
GN_
GP_
NN_
NN_
) to (-15V + V
PP_ PP_
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= +3V, V
= +12V, V = -12V, V
= +100V, V
= -100V, T = T
to T
, unless otherwise noted. Typical values are
MAX
CC
EE
PP_
NN_
A
MIN
at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
, V
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY (V , V , V , V
)
DD CC EE PP_ NN_
Logic Supply Voltage
V
V
2.37
4.75
3
6
V
V
DD
CC
Positive Drive Supply Voltage
12
12.6
1.05 x
0.95 x
Negative Drive Supply Voltage
V
EE
-V
CC
V
(-V )
CC
(-V )
CC
High-Side Supply Voltage
Low-Side Supply Voltage
High-Side Supply Voltage
Low-Side Supply Voltage
V
0
-200
0
+200
0
V
V
V
V
V
PP1
V
NN1
V
PP2
V
PP1
V
V
NN1
0
NN2
V
- V
Supply Voltage
0
+200
PP_
NN_
SUPPLY CURRENT (for single channel)
V
/V
/V
= 0 or V , V = 0
1
FA
FA
INN_ INP_ CLP_
DD EN
V
Supply Current
I
DD
DD
V
EN
V
= V , V
, f = 5MHz, one channel switching
= 0 or V , V
=
DD CLP_
DD INN_
100
200
INP_
V
V
= 0 (static)
1
EN
EN
FA
= V
(static)
10
DD
V
V
= V , V
= 0 or V , V
DD INN_
=
EN
DD CLP_
, f = 5MHz, V
INP_
= +12V, V = +3V,
DD
36
15
CC
V
Supply Current
I
CC
CC_
one channel switching
mA
V
EN
V
= V , V
= 0 or V , V
=
DD CLP_
DD INN_
, f = 5MHz, V
INP_
= +5V, V
= +3V,
CC
DD
one channel switching
2
______________________________________________________________________________________
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3V, V
= +12V, V = -12V, V
= +100V, V
= -100V, T = T
to T
, unless otherwise noted. Typical values are
MAX
CC
EE
PP_
NN_
A
MIN
at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
(static)
DD
MIN
TYP
MAX
UNITS
V
V
= 0 or V
1
EN
= -5V, V = V , V
= V
,
EE
EN
DD CLP_
DD
PRF = 10kHz, f = 5MHz, four pulses,
no load, one channel switching
100
V
EE_
Supply Current
I
EE_
FA
V
= -12V, V = V , V
= V
,
EE
EN
DD CLP_
DD
PRF = 10kHz, f = 5MHz, four pulses,
no load, one channel switching
200
1
V
= 0 or V
(static)
FA
EN
DD
V
V
= V , V
= 0 or V , V
DD INN_
=
EN
DD CLP_
, f = 5MHz, V
INP_
= +5V, V = -5V,
NN_
9
PP_
no load, one channel switching
V
Supply Current
I
PP_
PP_
mA
FA
V
V
= V , V
= 0 or V
,
EN
DD CLP_
DD
= +80V, V
= -80V, PRF = 10kHz,
PP_
NN_
0.6
f = 10MHz, four pulses, no load,
one channel switching
V
= 0 or V
(static)
1
EN
DD
V
V
= V , V
= 0 or V , V
DD INN_
=
EN
DD CLP_
, f = 5MHz, V
INP_
= +5V, V = -5V,
NN_
9
PP_
no load, one channel switching
V
Supply Current
I
NN_
NN_
mA
V
V
= V , V
= 0 or V
,
EN
DD INC_
DD
= +80V, V
= -80V, PRF = 10kHz,
PP_
NN_
0.6
f = 10MHz, four pulses, no load,
one channel switching
LOGIC INPUTS (EN, INN_, INP_, CLP_)
0.25 x
Low-Level Input Voltage
High-Level Input Voltage
V
V
V
IL
V
DD
0.75 x
V
IH
V
DD
Logic-Input Capacitance
Logic-Input Leakage
OUTPUT (OUT_)
C
5
0
pF
IN
I
V
IN
= 0 or V
DD
Q1
FA
IN
No load at OUT_
V
V
V
V
NN_
PP_
V
NN_
1.5
+
V
PP_
1.5
-
100mA load (MAX4940), V
= +12V Q5%
CC
OUT_ Output-Voltage Range
V
OUT_
V
NN_
2.5
+
V
-
PP_
2.5
100mA load (MAX4940A), V
= +12V Q5%
V
I
I
CC
V
CC
V
CC
V
CC
V
CC
= +12V Q5%
= +5V Q5%
= +12V Q5%
= +5V Q5%
7.5
8
14
18
14
18
Low-Side Output Impedance
(MAX4940)
R
OLS
I
I
= -50mA
= -50mA
OUT_
OUT_
9
High-Side Output Impedance
(MAX4940)
R
OHS
10.5
_______________________________________________________________________________________
3
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3V, V
= +12V, V = -12V, V
= +100V, V
= -100V, T = T
to T
, unless otherwise noted. Typical values are
MAX
CC
EE
PP_
NN_
A
MIN
at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
8.5
MAX
17
UNITS
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= +12V Q5%
= +5V Q5%
= +12V Q5%
= +5V Q5%
= +12V Q5%
= +5V Q5%
= +12V Q5%
= +5V Q5%
Low-Side Output Impedance
(MAX4940A)
R
I
I
I
I
= -50mA
= -50mA
= -50mA
= -50mA
I
OLS
OUT_
OUT_
OUT_
OUT_
10.0
11.5
13.0
18.7
20
21
17
High-Side Output Impedance
(MAX4940A)
R
OHS
I
I
I
21
45
Low-Side Signal CLAMP Output
Impedance
R
OLSC
60
26.5
37.0
45
High-Side Signal CLAMP Output
Impedance
R
OHSC
60
PEAK CURRENT
Low-Side Output Current
High-Side Output Current
Low-Side Output Current Clamp
High-Side Output Current Clamp
I
V
V
V
V
= +12V Q5%, V
= +12V Q5%, V
= +12V Q5%, V
= +12V Q5%, V
- V
- V
= 100V
= 100V
1.3
1.3
2.0
2.0
0.9
0.9
75
A
A
OL
CC
CC
CC
CC
OUT_
OUT_
OUT_
OUT_
NN_
I
OH
PP_
I
= +40V
= +40V
0.47
0.47
OLC
OHC
A
I
MAX4940, MAX4940A (OUT1_)
MAX4940A (OUT2_)
Off-Output Capacitance
C
pF
FA
O(OFF)
45
V
V
= -100V, V
= +100V, V = 0,
NN_
PP_ EN
Off-Output Leakage Current
I
Q1
LK
= -100V to +100V
OUT_
GATE-SOURCE RESISTANCE
Gate-Source Resistance
R
V
EN
= V
5
7.5
10
kI
GS
DD
DYNAMIC CHARACTERISTICS (R = 100I, C = 100pF, unless otherwise noted)
L
L
Logic Input-to-Output Rise
Propagation Delay (Figure 1)
INN_/INP_ at 50% to OUT_ 10/90%,
= +12V, V = +5V, V = -5V
t
15
15
ns
ns
PLH
PHL
V
CC
PP_
NN_
Logic Input-to-Output Fall
Propagation Delay (Figure 1)
INN_/INP_ at 50% to OUT_ 10/90%,
V = +12V, V = +5V, V = -5V
CC
t
PP_
NN_
Logic Input-to-Output Rise
Propagation Delay Clamp
(Figure 1)
INN_/INP_ at 50% to OUT_ 10/90%,
= +12V, V = +5V, V = -5V
t
15
15
ns
ns
PLO
V
CC
PP_
NN_
Logic Input-to-Output Fall
Propagation Delay Clamp
(Figure 1)
INN_/INP_ at 50% to OUT_ 10/90%,
t
PHO
V
CC
= +12V, V
= +5V, V
= -5V
PP_
NN_
OUT_ Rise Time (GND to V
(Figure 1)
)
V
V
= +100V, V
= -100V, 10% to 90%,
PP_
PP_
NN_
t
9
10.5
9
20
35
20
35
35
ns
ns
ns
ns
ns
ROP
= +12V Q5%, V
= -V
CC_
CC_
EE_
OUT_ Rise Time (V
(Figure 1)
to V
)
V
V
= +100V, V
= -100V, 10% to 90%,
NN_
PP_
PP_
NN_
t
RNP
FON
= +12V Q5%, V
= -V
CC_
CC_
EE_
OUT_ Fall Time (GND to V
(Figure 1)
)
V
V
= +100V, V
= -100V, 10% to 90%,
NN_
PP_
NN_
t
= +12V Q5%, V
= -V
CC_
CC_
EE_
OUT_ Fall Time (V
(Figure 1)
to V
)
V
V
= +100V, V
= -100V, 10% to 90%,
PP_
NN_
PP_
NN_
t
10.5
17
FPN
= +12V Q5%, V
= -V
CC_
CC
EE_
OUT_ Rise Time (V
(Figure 1)
to GND)
V
V
= +100V, V
= -100V, 10% to 90%,
NN_
PP_
NN_
t
RNO
= +12V Q5%, V
= -V
CC_
CC
EE_
4
______________________________________________________________________________________
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= +3V, V
= +12V, V = -12V, V
= +100V, V
= -100V, T = T
to T
, unless otherwise noted. Typical values are
MAX
CC
EE
PP_
NN_
A
MIN
at T = +25NC.) (Note 2)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
OUT_ Fall Time (V
(Figure 1)
to GND)
V
V
= +100V, V
= +12V Q5%, V
= -100V, 10% to 90%,
PP_
PP_
NN_
t
17
35
ns
FPO
= -V
CC_
CC
EE_
Output Enable Time from EN
(Figure 2)
t
V
V
= +5V, V
= -5V
= -5V
100
150
ns
ns
EN
PP_
NN_
NN_
Output Disable Time from EN
(Figure 2)
t
= +5V, V
DI
PP_
f
V
= 5MHz, V
= +12V
= -V
= -V
= -V
= +5V,
OUT_
PP_
NN_
NN_
NN_
2nd Harmonic Distortion LV
2nd Harmonic Distortion HV
THD2_LV
THD2_HV
-40
-45
dB
dB
CC
f
= 5MHz, V
= +50V, V
OUT_
PP_
CC
= +12V, 10 periods
f
= 5MHz, V
PP_
= +50V,
OUT_
Pulse Cancellation
2HD
V
= +12V, 10 periods, 1st harmonic
-43
dB
CC
cancellation
RMS Output Jitter
Crosstalk
t
10
ps
J
CT
Adjacent channels, f = 5MHz
-60
dB
Note 2: Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at
= +70NC. Specifications at T = 0NC are guaranteed by design.
T
A
A
Typical Operating Characteristics
(V
DD
= +3.3V, V
= +12V, V = -12V, V
= +100V, V
= -100V, f
= 5MHz, R = 100I, C = 100pF, T = +25NC, unless
CC
EE
PP_
NN_
OUT
L
L
A
otherwise noted.)
I
vs. OUTPUT FREQUENCY
I
vs. TEMPERATURE
CC
I
vs. OUTPUT FREQUENCY
CC
CC
0.50
0.48
40
35
30
25
20
15
10
5
0.50
CONTINUOUS SWITCHING,
4 PULSES AT 10MHz, PRF = 10kHz
4 PULSES, PRF = 10kHz
= 100I
= 100pF
0.48
0.46
V
V
V
= V = +5V,
= V = -5V,
= +3.3V
R = 100I
PP_
NN_
DD
L
L
CC
EE
R
C
L
L
0.46
0.44
0.42
0.40
0.38
0.36
0.34
0.44
0.42
0.40
C = 100pF
0.38
0.36
0.34
0.32
0.30
0.32
0.30
0
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
60
70
1
3
5
7
9
11
13
15
FREQUENCY (MHz)
TEMPERATURE (NC)
FREQUENCY (MHz)
_______________________________________________________________________________________
5
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Typical Operating Characteristics (continued)
(V
DD
= +3.3V, V
= +12V, V = -12V, V
EE
= +100V, V
= -100V, f
= 5MHz, R = 100I, C = 100pF, T = +25NC, unless
CC
PP_
NN_
OUT
L
L
A
otherwise noted.)
I
vs. OUTPUT FREQUENCY
I
CC
vs. TEMPERATURE
I
vs. OUTPUT FREQUENCY
PP_
PP_
50
40
30
20
10
0
12
40
35
30
25
20
15
10
5
CONTINUOUS SWITCHING,
= 2.5MHz,
4 PULSES, PRF = 10kHz
CONTINUOUS SWITCHING,
f
V
V
V
= V = +5V,
= V = -5V,
EE
= +3.3V
OUT
PP_
NN_
DD
CC
11
10
9
V
V
V
= V = +5V,
= V = -5V,
EE
= +3.3V,
PP_
NN_
DD
CC
R = 0, C = 0
L
L
8
R
C
= 100I
= 100pF
R
C
= 100I
= 100pF
L
L
L
L
7
6
NO LOAD
NO LOAD
3
5
0
1
2
3
4
5
6
7
8
9
10
0
10
20
30
40
50
60
70
1
5
7
9
11
13
15
FREQUENCY (MHz)
TEMPERATURE (NC)
FREQUENCY (MHz)
I
vs. TEMPERATURE
I
vs. OUTPUT FREQUENCY
I
vs. TEMPERATURE
PP_
NN_
PP_
10
9
40
35
30
25
20
15
10
5
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
CONTINUOUS SWITCHING,
= 2.5MHz,
4 PULSES, PRF = 10kHz
4 PULSES AT 10MHz, PRF = 10kHz
f
OUT
PP_
NN_
DD
8
V
V
V
= V = +5V,
CC
= V = -5V,
= +3.3V,
EE
7
6
R = 0, C = 0
L
L
5
4
R
C
= 100I
= 100pF
L
L
3
2
NO LOAD
3
1
0
0
0
10
20
30
40
50
60
70
1
5
7
9
11
13
15
0
10
20
30
40
50
60
70
TEMPERATURE (NC)
FREQUENCY (MHz)
TEMPERATURE (NC)
I
vs. TEMPERATURE
NN_
I
vs. TEMPERATURE
NN_
I
vs. OUTPUT FREQUENCY
NN_
10
9
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
50
40
30
20
10
0
CONTINUOUS SWITCHING,
= 2.5MHz,
4 PULSES AT 10MHz, PRF = 10kHz
CONTINUOUS SWITCHING,
PP_
NN_
f
OUT
PP_
NN_
DD
L
V
V
V
= V = +5V,
CC
= V = -5V,
EE
8
V
V
V
= V = +5V,
CC
= V = -5V,
EE
= 3.3V
7
DD
= +3.3V,
6
R = 0, C = 0
L
5
4
R = 100I
L
C = 100pF
L
3
2
1
0
NO LOAD
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
1
2
3
4
5
6
7
8
9
10
TEMPERATURE (NC)
TEMPERATURE (NC)
FREQUENCY (MHz)
6
______________________________________________________________________________________
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Typical Operating Characteristics (continued)
(V
DD
= +3.3V, V
= +12V, V = -12V, V
= +100V, V
= -100V, f
= 5MHz, R = 100I, C = 100pF, T = +25NC, unless
CC
EE
PP_
NN_
OUT
L
L
A
otherwise noted.)
OUT_ RISE TIME (GND TO V
)
OUT_ FALL TIME (GND TO V
)
INP_ TO OUT_ RISE PROPAGATION DELAY
PP_
NN_
vs. V /V SUPPLY VOLTAGE
vs. V /V SUPPLY VOLTAGE
vs. V /V SUPPLY VOLTAGE
CC EE
CC EE
CC EE
22
20
18
16
14
12
10
8
22
20
18
16
14
12
10
8
25
20
15
10
5
R = 100I, C = 100pF
R = 100I, C = 100pF
L
L
L
L
R = 100I, C = 100pF
L
L
6
6
4
4
2
2
0
0
0
Q4.75 Q5 Q7.5 Q10 Q12 Q12.6
/V SUPPLY VOLTAGE (V)
Q4.75 Q5 Q7.5 Q10 Q12 Q12.6
/V SUPPLY VOLTAGE (V)
Q4.75 Q5 Q7.5 Q10 Q12 Q12.6
/V SUPPLY VOLTAGE (V)
V
V
CC EE
V
CC EE
CC EE
INP_ TO OUT_ FALL PROPAGATION DELAY
vs. TEMPERATURE
INP_ TO OUT_ RISE PROPAGATION DELAY
vs. TEMPERATURE
INP_ TO OUT_ FALL PROPAGATION DELAY
vs. V /V SUPPLY VOLTAGE
CC EE
20
15
10
5
20
15
10
5
25
20
15
10
5
R = 100I, C = 100pF
L
L
R = 100I, C = 100pF
R = 100I, C = 100pF
L
L
L
L
0
0
0
0
10
20
30
40
50
60
70
0
10
20
30
40
50
60
70
Q4.75 Q5 Q7.5 Q10 Q12 Q12.6
/V SUPPLY VOLTAGE (V)
TEMPERATURE (NC)
TEMPERATURE (NC)
V
CC EE
JITTER
SPECTRUM
= +50V, V
5MHz, V
= +5V, V
= -5V
NN_
MAX4940 toc19
5MHz, V
= -50V
NN_
PP_
PP_
MAX4940 toc20
_______________________________________________________________________________________
7
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Pin Description
PIN
NAME
FUNCTION
1
INP1A
Channel 1A High-Side Logic Input. See the Truth Tables section.
Channel 1A Clamp Logic Input. Clamp is turned on when CLP1A is high and when INP1A and
INN1A are low. See the Truth Table section.
2
CLP1A
3
4
INN1A
INP2A
Channel 1A Low-Side Logic Input. See the Truth Tables section.
Channel 2A High-Side Logic Input. See the Truth Tables section.
Channel 2A Clamp Logic Input. Clamp is turned on when CLP2A is high and when INP2A and
INN2A are low. See the Truth Tables section.
5
CLP2A
6
7
8
9
INN2A
AGND
EN
Channel 2A Low-Side Logic Input. See the Truth Tables section.
Analog Ground. Must be connected to common GND.
Enable Logic Input. Drive EN high to enable OUT1A, OUT1B, OUT2A, and OUT2B.
Channel 2B High-Side Logic Input. See the Truth Tables section.
INP2B
Channel 2B Clamp Logic Input. Clamp is turned on when CLP2B is high and when INP2B and
INN2B are low. See the Truth Tables section.
10
CLP2B
11
12
INN2B
INP1B
Channel 2B Low-Side Logic Input. See the Truth Tables section.
Channel 1B High-Side Logic Input. See the Truth Tables section.
Channel 1B Clamp Logic Input. Clamp is turned on when CLP1B is high and when INP1B and
INN1B are low. See the Truth Tables section.
13
14
15
CLP1B
INN1B
Channel 1B Low-Side Logic Input. See the Truth Tables section.
Negative Supply Input. Gate-drive supply voltage for the clamp. Bypass V to GND with a 0.1FF
EE
V
EE
capacitor as close as possible to the device.
16, 27, 29,
34, 37, 42,
44, 55
GND
Ground
Gate-Drive Supply Voltage Input. Bypass V
to the device.
to GND with a 0.1FF capacitor as close as possible
CC
17, 54
18
V
CC
Channel 1B High-Side Driver Output. Connect a 3.3nF capacitor between C
and C
as
as
as
as
DP1B
DN1B
DN2B
GP1B
GN1B
GN2B
C
DP1B
DN1B
DN2B
close as possible to the device
.
Channel 1B Low-Side Driver Output. Connect a 3.3nF capacitor between C
close as possible to the device
and C
and C
19
C
C
.
Channel 2B Low-Side Driver Output. Connect a 3.3nF capacitor between C
close as possible to the device
20
.
Channel 2B High-Side Driver Output. Connect a 3.3nF capacitor between C
and C
GP2B
DP2B
21
C
C
DP2B
GP2B
GN2B
GN1B
close as possible to the device
.
Channel 2B High-Side Gate Input. Connect a 3.3nF capacitor between C
and C
as close
as close
as close
as close
DP2B
DN2B
DN1B
GP2B
GN2B
GN1B
22
as possible to the device
.
Channel 2B Low-Side Gate Input. Connect a 3.3nF capacitor between C
as possible to the device
and C
and C
23
C
C
.
Channel 1B Low-Side Gate Input. Connect a 3.3nF capacitor between C
as possible to the device
24
.
Channel 1B High-Side Gate Input. Connect a 3.3nF capacitor between C
and C
GP1B
DP1B
25
C
GP1B
as possible to the device
.
8
______________________________________________________________________________________
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Pin Description (continued)
PIN
26, 45
28
NAME
FUNCTION
Channel 1A, 1B High-Side Positive Supply Voltage Input. Bypass V
capacitor as close as possible to the device.
to GND with a 0.1FF
PP1
V
PP1
OUT1B
Channel 1B Output
Channel 1A, 1B Low-Side Negative Supply Voltage Input. Bypass V
capacitor as close as possible to the device.
to GND with a 0.1FF
to GND with a 0.1FF
NN1
30, 41
V
NN1
NN2
Channel 2A, 2B Low-Side Negative Supply Voltage Input. Bypass V
capacitor as close as possible to the device.
NN2
31, 40
V
32, 39
33
N.C.
No Connection. Not connected internally.
Channel 2B Output
OUT2B
Channel 2A, 2B High-Side Positive Supply Voltage Input. Bypass V
capacitor as close as possible to the device.
to GND with a 0.1FF
PP2
35, 36
V
PP2
38
43
OUT2A
OUT1A
Channel 2A Output
Channel 1A Output
Channel 1A High-Side Gate Input. Connect a 3.3nF capacitor between C
and C
as close
as close
as close
as close
DP1A
DN1A
DN2A
GP1A
GN1A
GN2A
46
47
48
49
50
51
52
53
C
GP1A
GN1A
GN2A
as possible to the device
.
Channel 1A Low-Side Gate Input. Connect a 3.3nF capacitor between C
as possible to the device
and C
and C
C
C
.
Channel 2A Low-Side Gate Input. Connect a 3.3nF capacitor between C
as possible to the device
.
Channel 2A High-Side Gate Input. Connect a 3.3nF capacitor between C
and C
GP2A
DP2A
C
C
GP2A
DP2A
DN2A
DN1A
as possible to the device
.
Channel 2A High-Side Driver Output. Connect a 3.3nF capacitor between C
and C
as
as
as
as
DP2A
DN2A
DN1A
GP2A
GN2A
GN1A
close as possible to the device
.
Channel 2A Low-Side Driver Output. Connect a 3.3nF capacitor between C
close as possible to the device
and C
and C
C
C
.
Channel 1A Low-Side Driver Output. Connect a 3.3nF capacitor between C
close as possible to the device
.
Channel 1A High-Side Driver Output. Connect a 3.3nF capacitor between C
and C
GP1A
DP1A
C
DP1A
close as possible to the device
.
Logic-Supply Voltage Input. Bypass V
device.
to GND with a 0.1FF capacitor as close as possible to the
DD
56
—
V
DD
EP
Exposed Pad. EP must be connected to V
.
NN1
_______________________________________________________________________________________
9
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Logic Inputs (INP_, INN_, CLP_, EN)
Detailed Description
INP_ controls the on and off states of the high-side FET,
INN_ controls the on and off states of the low-side FET,
and CLP_ controls the active clamp. A global enable
input (EN) can be used to enable/disable all channels.
These signals give complete control of the output stage
of each driver (see the Truth Tables section for all logic
combinations). The MAX4940/MAX4940A logic inputs
are CMOS logic compatible and the logic levels are ref-
The MAX4940/MAX4940A are quad high-voltage, high-
speed pulsers that can be independently configured
for either unipolar/bipolar/multilevel pulse outputs (see
Figures 5 and 6.). These devices have independent
logic inputs for full pulse control and independent active
clamps. The clamp input, CLP_, can be set high to
activate the clamp automatically when the device is not
pulsing to the positive or negative high-voltage supplies.
erenced to V
for maximum flexibility. The low 5pF (typ)
DD
input capacitance of the logic inputs reduce loading and
increase switching speed.
Truth Tables
MAX4940
INPUTS
OUTPUTS
OUT_
STATE
EN
0
INP_
INN_
CLP_
X
0
0
0
1
1
X
0
0
1
0
1
X
0
1
X
X
X
High impedance
High impedance
GND
Powered up, INP_/INN_ disabled.
Powered up, all inputs enabled.
Powered up, all inputs enabled.
Powered up, all inputs enabled.
Powered up, all inputs enabled.
Not allowed.
1
1
1
V
NN_
1
V
PP_
1
Not allowed
MAX4940A
INPUTS
OUTPUTS
STATE
INP1A INN1A CLP1A
INP1B INN1B CLP1B
OUT1A
OUT1B
EN
0
1
1
1
1
1
X
0
0
0
1
1
X
0
0
1
0
1
X
0
1
0
0
1
High impedance
High impedance
GND
Powered up, INP_/INN_ disabled.
Powered up, all inputs enabled.
Powered up, all inputs enabled.
Powered up, all inputs enabled.
Powered up, all inputs enabled.
Not allowed.
V
NN_
V
PP_
Not allowed
INPUTS
OUTPUTS
STATE
INP2A INN2A CLP2A
INP2B INN2B CLP2B
OUT2A
OUT2B
EN
0
1
1
1
1
1
X
0
0
0
1
1
X
0
0
1
0
1
X
0
1
X
X
X
High impedance
High impedance
GND
Powered up, INP_/INN_ disabled.
Powered up, all inputs enabled.
Powered up, all inputs enabled.
Powered up, all inputs enabled.
Powered up, all inputs enabled.
Not allowed.
V
NN_
V
PP_
Not allowed
X = Don’t care.
0 = Logic-low.
1 = Logic-high.
10 _____________________________________________________________________________________
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Active Clamps
Power Dissipation
The power dissipation of the MAX4940/MAX4940A con-
sists of three major components caused by the current
The MAX4940/MAX4940A feature an integrated active
clamp circuit to improve pulse quality and reduce 2nd
harmonic distortion. The clamp circuit consists of an
n-channel (DC-coupled) and a p-channel (DC-coupled)
high-voltage FETs that are switched on or off by the logic
clamp input (CLP_).
consumption from V , V
, and V
PP_
. The sum of
NN_
CC
these components (P
, P
, and P ) must be
VNN_
VCC VPP_
kept below the maximum power-dissipation limit. See
the Typical Operating Characteristics section for more
information on typical supply currents versus switching
frequencies.
The MAX4940/MAX4940A feature protected clamp devic-
es, allowing the clamp circuit to be used in bipolar pulsing
circuits (see Figures 3 and 4). A diode in series with the
OUT_ output prevents the body diode of the low-side FET
from turning on when a voltage lower than GND is pres-
ent. Another diode in series with the OUT_ output prevents
the body diode of the high-side FET from turning on when
a voltage higher than ground is present. The MAX4940/
MAX4940A have an active clamp on all outputs.
The device consumes most of the supply current from
V
CC
supply to charge and discharge internal nodes
such as the gate capacitance of the high-side FET (C )
P
and the low-side FET (C ). Neglecting the small quies-
N
cent supply current and a small amount of current used
to charge and discharge the capacitances at the internal
gate clamp FETs, the power consumption can be esti-
mated as follows:
For the MAX4940 only, the user can connect the active
clamp input (CLP_) to a logic-high voltage and drive
only the INP_ and INN_ inputs to minimize the number of
signals used to drive the device. In this case, whenever
both the INP_ and INN_ inputs are low and the CLP_
input is high, the active clamp circuit pulls the output to
GND (see the Truth Tables section for more information).
2
2
P
=
C
× V
× f + C × V
× f
IN
× BRF ×BTD
(
)
VCC
(
N
CC
IN
)
(
P
CC
)
f
= f
+ f
IN INN_ INP_
where f
and f
are the switching frequency of
INN_
INP_
the inputs INN_, INP_, respectively, and where BRF is
the burst response frequency, and BTD is the burst time
duration. The typical values of the gate capacitances are
Integrated Blocking Diodes
(MAX4940A Only)
C
N
= 1.2FF, C = 0.4FF.
P
The high-voltage OUT2A/OUT2B outputs of the
MAX4940A feature integrated blocking diodes that allow
the user to implement multilevel pulsing by connect-
ing the outputs of multiple pulser channels in parallel.
Internal diodes in series with the OUT2A and OUT2B
outputs prevent the body diode of the high-side and low-
side FETs from switching on when a voltage greater than
See the Typical Operating Characteristics for V
and
PP_
V
NN_
power consumption.
Power Supplies and Bypassing
The MAX4940/MAX4940A operate from independent
supply voltage sets (only V , V , and V are com-
DD CC
EE
mon to all channels). V
/V
supply two channels
PP1 NN1
V
NN2
or V
is present on the output (see Figure 4).
PP2
and V
/V
supply the other two channels. The logic
PP2 NN2
input circuit operates from a +2.37V to +6V single sup-
Thermal Protection
ply (V ). The level-shift driver dual supplies, V /V
DD
CC EE
A thermal shutdown circuit with a typical threshold of
operate from Q4.75V to Q12.6V.
+155NC prevents damage due to excessive power dis-
sipation. When the junction temperature exceeds T =
The V
/V
high-side and low-side supplies are
J
PP_ NN_
+155NC, all outputs are disabled. Normal operation typi-
cally resumes after the IC’s junction temperature drops
below +130NC.
driven from a single positive supply up to +220V, from a
single negative supply up to -220V, or from Q110V dual
supplies. Either V
or V
can be set at 0. Bypass
PP_
NN_
each supply input to ground with a 0.1FF capacitor as
close as possible to the device.
Applications Information
Depending on the applications, additional bypassing may
AC-Coupling Capacitor Selection
be needed to maintain the input of both V
and V
NN_
PP_
The value of all AC-coupling capacitors (between C
DP_
stable during output transitions. For example, with C
OUT
and C
, and between C
and C ) should be
GN_
GP_
DN_
= 100pF and R
= 100Iload, the use of an additional
OUT
between 1nF to 10nF. The voltage rating of the capacitor
should be greater than V and V . The capacitors
10FF (typ) electrolytic capacitor is recommended.
PP_
NN_
should be placed as close as possible to the device.
______________________________________________________________________________________ 11
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
particular attention to minimize trace lengths and use suf-
ficient trace width to reduce inductance. Use of surface-
mount components is recommended.
Exposed Pad and Layout Concerns
The MAX4940/MAX4940A provide an exposed pad
(EP) underneath the TQFN package for improved ther-
mal performance. EP is internally connected to V
.
NN1
Supply Sequencing
Connect EP to V
externally. To aid heat dissipation,
NN1
In a typical trilevel application when V
and V
NN1
NN2
connect EP to a similarly sized pad on the component
side of the PCB. This pad should be connected through
the solder-side copper by several plated holes to a large
heat spreading copper area to conduct heat away from
the device.
are externally shorted (V
= V ), the MAX4940/
NN2
NN1
MAX4940A do not require any power sequencing. In
general, and in particular for the multilevel applica-
tion, V
must be less than or equal to V
(V
P
NN1
NN2 NN1
V
NN2
) at all times. No other power-supply sequencing is
required for the MAX4940/MAX4940A.
The MAX4940/MAX4940A high-speed pulsers require low-
inductance bypass capacitors to their supply inputs. High-
speed PCB trace design practices are recommended. Pay
Timing Diagrams
t
FPN
V
PP_
90%
10%
90%
10%
t
t
RNO
FON
OUT_
90%
10%
10%
GND
90%
t
t
ROP
FPO
90%
10%
10%
V
NN_
t
t
t
RNP
POH
PHO
50%
50%
50%
50%
50%
INP_
INN_
t
t
PHL
PLH
t
t
PLO
POL
V
DD
50%
50%
50%
GND
CLP_ = HIGH
Figure 1. Detail Timing (R = 100I, C = 100pF)
L
L
12 _____________________________________________________________________________________
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Timing Diagrams (continued)
OUT_ (INP_ = HIGH)
GND
10%
OUT_ (INN_ = HIGH)
10%
t
DI
t
EN
EN
50%
50%
CLP_ = HIGH
Figure 2. Enable Timing (R = 100I, C = 100pF)
L
L
______________________________________________________________________________________ 13
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Functional Diagrams
V
DD
V
C
C
GP_
CC_
DP_
V
PP_
V
V
DD
CC_
LEVEL
SHIFTER
C
DP_
INP_
C
GP_A
GND
V
DD
LEVEL
SHIFTER
CLP_
C
GP_A
V
V
EE_
EN
OUT_
MAX4940
V
DD
CC_
LEVEL
SHIFTER
GND
V
V
DD
CC_
C
GN_
LEVEL
SHIFTER
C
DN_
INN_
V
NN_
GND
V
C
C
GN_
EE_
DN_
Figure 3. MAX4940 Simplified Functional Diagram for One Channel
14 _____________________________________________________________________________________
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Functional Diagrams (continued)
V
V
CC_
C
C
GP_
DD
DP_
V
PP_
V
V
DD
CC_
LEVEL
SHIFTER
C
DP_
INP_
C
GP_A
*
GND
V
DD
LEVEL
SHIFTER
CLP_
C
GP_A
V
V
EE_
EN
OUT_
MAX4940A
V
DD
CC_
LEVEL
SHIFTER
GND
*
V
V
DD
CC_
C
GN_
LEVEL
SHIFTER
C
DN_
INN_
V
NN_
GND
V
C
C
GN_
EE_
DN_
*OUT2A/OUT2B ONLY.
Figure 4. MAX4940A Simplified Functional Diagram for One Channel
______________________________________________________________________________________ 15
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Typical Application Circuits
3.3nF
3.3nF
3.3nF
3.3nF
+3.3V
+12V
V
PP
56 55 54 53 52 51 50 49 48 47 46 45 44 43
+
42
41
40
39
38
37
36
35
34
33
INP1A
CLP1A
INN1A
INP2A
CLP2A
INN2A
AGND
EN
GND
1
2
3
4
5
6
7
8
9
V
NN
V
NN1
NN2
V
N.C.
OUT2A
GND
V
PP
V
PP2
V
PP2
MAX4940
INP2B
GND
10 CLP2B
11 INN2B
12 INP1B
13 CLP1B
14 INN1B
OUT2B
N.C. 32
V
NN
V
NN2
V
NN1
31
30
GND 29
15 16 17 18 19 20 21 22 23 24 25 26 27 28
-12V
3.3nF
3.3nF
3.3nF
+12V
V
PP
3.3nF
+3.3V
V
V
PP
+12V
-12V
NN
100nF
100nF
100nF
100nF
100nF
Figure 5. MAX4940 Quad Pulsing with Always-On Active Return-to-Zero
16 _____________________________________________________________________________________
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Typical Application Circuits (continued)
3.3nF
3.3nF
3.3nF
3.3nF
+3.3V
+12V
V
PP_H
56 55 54 53 52 51 50 49 48 47 46 45 44 43
+
42
41
40
39
38
37
36
35
34
33
INP1A
CLP1A
INN1A
INP2A
CLP2A
INN2A
AGND
EN
GND
1
2
3
4
5
6
7
8
9
V
NN_H
V
V
NN1
NN2
NN_L
V
N.C.
OUT2A
GND
V
PP_L
V
PP2
V
PP2
MAX4940A
INP2B
GND
10 CLP2B
11 INN2B
12 INP1B
13 CLP1B
14 INN1B
OUT2B
N.C. 32
V
NN_L
V
31
30
V
NN2
NN1
NN_H
V
GND 29
15 16 17 18 19 20 21 22 23 24 25 26 27 28
-12V
3.3nF
+12V
V
PP_H
3.3nF
3.3nF
3.3nF
V
V
V
V
PP_L
+3.3V
+12V
-12V
NN_H
PP_H
NN_L
100nF
100nF
100nF
100nF
100nF
100nF
100nF
Figure 6. MAX4940A Dual Five-Level Pulsing
______________________________________________________________________________________ 17
Dual/Quad, Unipolar/Bipolar,
High-Voltage Digital Pulsers
Chip Information
Package Information
For the latest package outline information and land pat-
PROCESS: BiCMOS
terns, go to www.maxim-ic.com/packages.
PACKAGE TYPE
PACKAGE CODE
DOCUMENT NO.
21-0135
56 TQFN
T5688-3
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
18
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
相关型号：
MAX4943ELA+T
Buffer/Inverter Based Peripheral Driver, BICMOS, PDSO8, 2 X 2 MM, ROHS COMPLIANT, UDFN-8
MAXIM
MAX4944ELA+
Buffer/Inverter Based Peripheral Driver, BICMOS, PDSO8, 2 X 2 MM, ROHS COMPLIANT, UDFN-8
MAXIM
MAX4944ELA+T
Buffer/Inverter Based Peripheral Driver, BICMOS, PDSO8, 2 X 2 MM, ROHS COMPLIANT, UDFN-8
MAXIM
MAX4944LELA+
Buffer/Inverter Based Peripheral Driver, BICMOS, PDSO8, 2 X 2 MM, ROHS COMPLIANT, UDFN-8
MAXIM
©2020 ICPDF网 联系我们和版权申明