MAX4885AEETI+ [MAXIM]
High-Bandwidth, VGA 2:1 Switch with ±15kV ESD Protection; 高带宽， VGA 2 ： 1开关，具有± 15kV ESD保护
| 型号： | MAX4885AEETI+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Bandwidth, VGA 2:1 Switch with ±15kV ESD Protection |
| 文件： | 总10页 (文件大小：995K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX4885AEETI+
-40NC to +85NC
28 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Typical Operating Circuit
+3.3V
+5V
1µF
1µF
V
L
V
CC
MAX4885AE
3
2
2
3
2
2
R1, G1, B1
H1, V1
R0, G0, B0
H0, V0
MXM
MODULE
VGA
PORT
SDA0, SCL0
SDA1, SCL1
3
2
2
R2, G2, B2
H2, V2
INTERNAL
GRAPHICS
SDA2, SCL2
SEL1
SEL2
CPU
GND
High-Bandwidth, VGA 2:1 Switch
with 1ꢀ5V ESD Protection
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to GND unless otherwise noted.)
Continuous Power Dissipation (T = +70NC)
A
V
CC
..........................................................................-0.3V to +6V
28-Pin TQFN (derate 28.6mW/NC above +70NC)....2285.7mW
V .............................................................. -0.3V to (V
R_, G_, B_, H0, V0, SDA0, SCL0 ............. -0.3V to (V
H1, H2, V1, V2, SDA1, SDA2, SCL1,
+ 0.3V)
+ 0.3V)
Junction-to-Ambient Thermal Resistance (B ) (Note 1)
28-Pin TQFN.................................................................35NC/W
L
CC
CC
JA
Junction-to-Ambient Thermal Resistance (B ) (Note 1)
JC
SCL2, SEL1, SEL2 ................................... -0.3V to (V + 0.3V)
28-Pin TQFN...................................................................3NC/W
Operating Temperature Range.......................... -40NC to +85NC
Storage Temperature Range............................ -65NC to +150NC
Junction Temperature ................................................... +150NC
Lead Temperature (soldering, 10s) ................................+300NC
L
Continuous Current through R_, G_, B_ Switches.......... Q50mA
Continuous Current through SDA_, SCL_ Switches ...... Q50mA
Continuous Current into SEL1, SEL2, H1, H2, V1, V2 .... Q20mA
Peak Current through all Switches
(pulsed at 1ms, 10% duty cycle)............................... Q100mA
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to http://www.maxim-ic.com/thermal-
tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
CC
= +4.5V to +5.5V, V = +2.2V to V , T = T
to T , unless otherwise noted. Typical values are at T = +25NC.)
MAX A
L
CC
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
+4.5
+2.2
TYP
MAX
UNITS
Supply Voltage
V
+5.5
V
V
CC
Logic Supply Voltage
V
L
V P V
V
CC
L
CC
V
= +5.5V, V = +3.6V,
L
CC
V
Supply Current
I
2
5
FA
FA
CC
CC
SEL_ = H1 = H2 = V1 = V2 = GND
V
= +5.5V, V = +3.6V,
CC
L
V Supply Current
L
I
L
1
SEL_ = H1 = H2 = V1 = V2 = GND
ANALOG SWITCHES
On-Resistance (R_, G_, B_)
R-HF-
V
= +0.7V, I = Q10mA
5
8
1
I
I
ON
IN
IN
On-Resistance Match (R_, G_,
B_)
DR
0 P V P+0.7V, I = -10mA
IN IN
ON
On-Resistance Flatness
(R_, G_, B_)
R
0 P V P+0.7V, I = -10mA
0.5
15
1
I
FLAT(ON)
IN
IN
Off Leakage Current (R_, G_, B_)
On-Resistance (SDA_, SCL_)
I
V
V
, V , V = 0V or V
CC
-1
-1
+1
FA
OFF
R_ G_ B_
R-DDC
= +0.7V, I = Q10mA
I
ON
IN
IN
Off-Leakage Current
(SDA_, SCL_)
V
V
, V
= 0V or V ,
SDA_ SCL_ L
I
+1
FA
OFF
= V = +5V
CC
L
2
High-Bandwidth, VGA 2:1 Switch
with 1ꢀ5V ESD Protection
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +4.5V to +5.5V, V = +2.2V to V , T = T
to T , unless otherwise noted. Typical values are at T = +25NC.)
MAX A
L
CC
A
MIN
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (SEL_, H1, H2, V1, V2)
Input Threshold Low
Input Threshold High
V
0.25 x V
V
V
IL
L
0.55 x
V
IH
V
L
Input Hysteresis
V
100
300
mV
FA
ns
HYST
Input Leakage Current
SEL_ Enable/Disable Time
DIGITAL OUTPUTS (H0, V0)
Output-Voltage Low
Output-Voltage High
Rise/Fall Time
I
L
-1
+1
t
, t
R = 2.2kI, C = 10pF, Figure 1
ON OFF
L
L
V
I
I
= 8mA, V
= +4.5V
= +4.5V
CC
0.8
8
V
V
OL
OUT
CC
V
= -8mA, V
2.4
OH
OUT
t
t
R = 2.2kI, C = 10pF, Figure 2
ns
R, F
L
L
RGB AC PERFORMANCE
Bandwidth
f
R = R = 50I
900
0.4
-40
2.5
MHz
dB
MAX
S
L
f = 10MHz, R = R = 50I, 0 PV P+0.7V,
S
L
On-Loss
I
LOSS
Figure 3
Crosstalk R_, G_, B_
Off-Capacitance
V
f = 50MHz, R = R = 50I, Figure 3
dB
CT
S
L
f = 1MHz, R0 to R1/R2, G0 to G1/G2, B0
to B1/B2 (Note 2)
C
pF
OFF
f = 1MHz, R0 to R1/R2, G0 to G1/G2, B0
to B1/B2 (Note 2)
On-Capacitance
C
ON
5.5
8
pF
ESD PROTECTION
R0, G0, B0, SDA0, SCL0, H0, V0
R0, G0, B0, SDA0, SCL0, H0, V0
All Other Terminals
V
V
V
HBM (Notes 2, 3)
Q15
Q8
kV
kV
kV
ESD
ESD
ESD
IEC 61000-4-2 Contact (Notes 2, 3)
HBM (Note 2)
Q2
Note 2: Guaranteed by design. Not production tested.
Note 3: Tested terminal to GND, 1µF bypass capacitors on V
and V .
L
CC
3
High-Bandwidth, VGA 2:1 Switch
with 1ꢀ5V ESD Protection
Typical Operating Characteristics
(V
CC
= +5.0V, V = +3.3V, T = 25°C, unless otherwise noted.)
L
A
R
vs. V
*
R
vs. V
*
HV BUFFER OUTPUT-VOLTAGE HIGH
vs. TEMPERATURE
ON
RO
ON
SDA0
(RGB SWITCHES)
(DDC SWITCHES)
5.2
5.0
4.8
4.6
4.4
4.2
4.0
10
50
40
30
20
10
0
*R0, G0, B0 ARE INTERCHANGEABLE
*SDA0, SCL0 ARE INTERCHANGEABLE
I
= 8mA
OUT
9
8
7
6
5
4
3
2
1
0
T = +85°C
A
T = +25°C
A
V = +3.3V
L
V = +5V
L
T = +85°C
A
T = +85°C
A
T = +25°C
A
T = +25°C
A
T = -40°C
A
T = -40°C
A
T = -40°C
A
-40
-15
10
35
60
85
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
(V)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
(V)
TEMPERATURE (°C)
V
V
SDA0
RO
HV BUFFER OUTPUT-VOLTAGE LOW
vs. TEMPERATURE
SUPPLY CURRENT
vs. TEMPERATURE
ON-RESPONSE vs. FREQUENCY
1.0
0.8
0.6
0.4
0.2
0
5
4
3
2
1
0
0
-1
I
= 8mA
OUT
-2
I
CC
-3
-4
-5
-6
-7
I
-8
L
-9
-10
-40
-15
10
35
60
85
-40
-15
10
35
60
85
1
10
100
1000
TEMPERATURE (°C)
TEMPERATURE (°C)
FREQUENCY (MHz)
CROSSTALK vs. FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
1
10
100
1000
FREQUENCY (MHz)
4
High-Bandwidth, VGA 2:1 Switch
with 1ꢀ5V ESD Protection
Test Circuits/Timing Diagrams
V
R
C
= 2.2kΩ
L
L
= 10pF
L
R
C
= 2.2kΩ
= 10pF
L
L
50%
50%
V
CC
80%
80%
SEL1,
SEL2
0V
CC
t
t
ON
OFF
V
20%
20%
H0, V0
0V
t
R
t
R
50%
50%
H0, V0
0V
Figure 1. Enable/Disable Time
Figure 2. Rise/Fall Time
+3.3V +5V
1µF
1µF
NETWORK
ANALYZER
V
V
CC
L
V
OUT
50Ω
50Ω
INSERTION-LOSS = 20log
CROSSTALK = 20log
V
IN
( V )
IN
GND OR V
SEL1, SEL2
R0, G0, B0
L
V
OUT
( V )
IN
MAX4885AE
MEAS
REF
V
OUT
R1, G1, B1 R2, G2, B2
GND
50Ω
50Ω
50Ω
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
INSERTION LOSS IS MEASURED BETWEEN R0 AND R1 OR R2 ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 3. Insertion Loss and Crosstalk
5
High-Bandwidth, VGA 2:1 Switch
with 1ꢀ5V ESD Protection
Pin Configuration
TOP VIEW
21 20 19 18 17 16 15
14
13
G1 22
R1 23
G2
R2
12 SCL2
24
25
26
27
28
SCL1
SDA1
GND
MAX4885AE
SDA2
11
10
9
V
V
CC
L
V
CC
*EP
6
+
8
SEL2
SEL1
1
2
3
4
5
7
TQFN
(4mm × 4mm)
*EXPOSED PAD. CONNECT TO GROUND OR LEAVE UNCONNECTED.
Pin Description
PIN
1
NAME
R0
FUNCTION
RGB Red Output (Note 4)
2
G0
RGB Green Output (Note 4)
RGB Blue Output (Note 4)
Horizontal Sync Output (Note 4)
3
B0
4
H0
5
V0
Vertical Sync Output (Note 4)
2
6
SDA0 I C Data Output (Note 4)
2
7
SCL0 I C Clock Output (Note 4)
8
SEL2 Select Input 2. Switches SDA_ and SCL_ signals.
9
V
L
Supply Voltage. +2.2V P V P V . Bypass V to GND with a 1FF or larger ceramic capacitor.
L CC L
10
11
12
13
14
15
16
17
18
19
20
21
V
Supply Voltage. V
2
= +5.0V Q10%. Bypass V
to GND with a 1FF or larger ceramic capacitor.
CC
CC
CC
SDA2 I C Input Data 2 (Note 5)
2
SCL2 I C Input Clock 2 (Note 5)
R2
G2
B2
H2
V2
RGB Red Input 2 (Note 6)
RGB Green Input 2 (Note 6)
RGB-Blue Input 2 (Note 6)
Horizontal Sync Input 2 (Note 7)
Vertical Sync Input 2 (Note 7)
I.C.
V1
Internal Connection. Connect to ground or leave unconnected.
Vertical Sync Input 1 (Note 7)
H1
B1
Horizontal Sync Input 1 (Note 7)
RGB Blue Input 1 (Note 6)
6
High-Bandwidth, VGA 2:1 Switch
with 1ꢀ5V ESD Protection
Pin Description (continued)
PIN
22
23
24
25
26
27
28
—
NAME
G1
FUNCTION
RGB Green Input 1 (Note 6)
R1
RGB Red Input 1 (Note 6)
2
SCL1 I C Clock Input 1 (Note 5)
2
SDA1 I C Data Input 1 (Note 5)
GND Ground
V
CC
+5V Supply Pin
SEL1 Select Input 1. Switches R_, G_, B_, H_, and V_ signals.
EP Exposed Pad. Connect exposed pad to ground or leave unconnected.
Note 4: Terminal with Q15kV HBM protection.
Note 5: SCL1, SCL2, SDA1, and SDA2 are identical and can be used interchangeably.
Note 6: R1, R2, G1, G2, B1, and B2 are identical and can be used interchangeably.
Note 7: H1, H2, V1, and V2 are identical and can be used interchangeably.
Typical Applications Circuit
+3.3V
+5.0V
10, 27
0.1µF
0.1µF
3.3kΩ
3.3kΩ
9
SCL
SDA
H
24
25
20
19
MXM
GRAPHICS
V
7
6
4
5
1
2
3
SCL
SDA
R
G
B
23
22
21
MAX4885AE
H
+3.3V
VGA
COMMON
OUTPUT
V
R
G
B
3.3kΩ
3.3kΩ
SCL
SDA
H
12
11
16
17
INTERNAL
GRAPHICS
V
R
G
B
13
14
15
26, EP
28
8
SEL1
SEL2
NOTE: TWO VIDEO INPUT SOURCES BEING SWITCHED INTO ONE OUTPUT/SINK USING MAX4885AE.
7
High-Bandwidth, VGA 2:1 Switch
with 1ꢀ5V ESD Protection
Functional Diagram
R1
R2
R0
G0
B0
G1
G2
B1
B2
SCL1
SCL0
V
V
V
V
L
L
L
L
SCL2
SDA1
SDA2
SDA0
MAX4885AE
H1
H2
H0
V0
V1
V2
SEL1
SEL2
CONTROL
8
High-Bandwidth, VGA 2:1 Switch
with 1ꢀ5V ESD Protection
RGB Switches
Detailed Description
The MAX4885AE provides three SPDT high-bandwidth
switches to route standard VGA R_, G_, and B_ signals
(see Table 1). The R_, G_, and B_ analog switches are
identical and any of the three switches can be used to
route red, green, or blue video signals. The R0, G0, and
B0 outputs are ESD protected to Q15kV (HBM).
The MAX4885AE integrates high-bandwidth analog
switches and level-translating buffers to implement a
complete 2:1 multiplexer for VGA signals. The device
provides switching for RGB, HSYNC, VSYNC, SDA, and
SCL signals. These signals are required in notebook
VGA switching applications.
Horizontal/Vertical Sync Level Shifter
H1, H2, V1, and V2 inputs are buffered to provide level-
shifting and drive capability for horizontal/vertical sync
signals that meet the VESA specification. The H_ and V_
level-shifters are identical, and each level-shifter can be
used for either horizontal or vertical signals. The SDA0
and SCL0 outputs are ESD protected to Q15kV (HBM).
The HSYNC and VSYNC inputs feature level-shifting
buffers to support 5V-TTL output logic levels from low-
voltage graphics controllers. These buffered switches
can be driven from +2.0V up to +5.5V. RGB signals are
routed with high-performance analog switches. SDA_
and SCL_ are I C signals with pullups to their respective
voltages. The MAX4885AE protects the low-voltage side
while effectively translating up to the high-voltage level.
2
Display-Data Channel Multiplexer
The MAX4885AE provides two logic-level translating
Two select inputs are provided to individually select
groups of switches.
switches to route DDC signals (see Table 2). V is nor-
L
mally set to +3.3V to provide logic-shifting for VESA
I C-compatible signals. The MAX4885AE protects the
low-voltage graphics controller from +5V that could be
present in VESA-compatible monitors. In some appli-
cations, such as KVM, where logic-level shifting is not
RGB, HSYNC, and VSYNC signals are controlled by
SEL1; and both SDA_ and SCL_ signals are controlled
by SEL2.
2
Table 1. RGB/HV Truth Table
required, then V can be connected to V . The SDA_
L
CC
SEL1
FUNCTION
and SCL_ switches are identical, and each switch can
be used to route either SDA_ or SCL_ signals. The SDA0
and SCL0 outputs are ESD protected to Q15kV (HBM).
R1 to R0
G1 to G0
B1 to B0
H1 to H0
V1 to V0
0
ESD Protection
As with all Maxim devices, ESD-protection structures are
incorporated on all pins to protect against electrostatic
discharges encountered during handling and assembly.
Additionally, the R0, G0, B0, H0, V0, SDA0, and SCL0
terminals of the MAX4885AE are designed for protection
to the following limit: 15kV using the HBM.
R2 to R0
G2 to G0
B2 to B0
H2 to H0
V2 to V0
1
Table 2. DDC Truth Table
SEL2
FUNCTION
For optimum ESD performance, bypass V
and V pins
L
CC
SDA1 to SDA0
SCL1 to SCL0
0
to ground with 1FF or larger ceramic capacitors as close
as possible to these supply pins.
SDA2 to SDA0
SCL2 to SCL0
1
9
High-Bandwidth, VGA 2:1 Switch
with 1ꢀ5V ESD Protection
R
R
D
C
1.5kΩ
1MΩ
I 100%
P
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
90%
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
STORAGE
CAPACITOR
S
100pF
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 4. Human Body ESD Test Model
Figure 5. Human Body Model Current Waveform
Human Body Model
Figure 4 shows the HBM, and Figure 5 shows the cur-
rent waveform it generates when discharged into a low-
impedance state. This model consists of a 100pF capac-
itor charged to the ESD voltage of interest, which is then
discharged into the device through a 1.5kI resistor.
Power-Supply Decoupling
pin and V pin to ground with a 1FF
or larger ceramic capacitor as close as possible to the
device.
Bypass each V
CC
L
PCB Layout
High-speed switches such as the MAX4885AE requires
proper PCB layout for optimum performance. Ensure that
impedance-controlled PCB traces for high-speed signals
are matched in length and as short as possible. Connect
the exposed pad to ground or leave unconnected.
ESD Test Conditions
ESD performance depends on a variety of conditions.
Contact Maxim for a reliability report, test setup, meth-
odology, and results.
Applications Information
Chip Information
The MAX4885AE provides the switching and level-
shifting necessary to drive a standard VGA port from
either an internal graphics controller or an add-in module
(MXM or GPU—see Typical Applications Circuit). The
R_, G_, and B_ signals are switched through the three
low-capacitance SPDT switches. Internal buffers drive
the HSYNC and VSYNC signals to VGA standard 5V-TTL
levels. The DDC multiplexer provides level-shifting.
PROCESS: BiCMOS
Pac5age Information
For the latest package outline information and land pat-
terns, go to www.maxim-ic.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS
status only. Package drawings may show a different suf-
fix character, but the drawing pertains to the package
regardless of RoHS status.
Connect V to +3.3V for normal operation, or to V
to
L
CC
disable level-shifting for DDC signals as for KVM appli-
cation.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 TQFN-EP
T2844+1
21-0139
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
10
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
相关型号：
MAX4885ETJ-T
Video Multiplexer, 1 Func, 2 Channel, BICMOS, 5 X 5 MM, 0.80 MM HEIGHT, MO-220WHHD-2, TQFN-32
MAXIM
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