MAX4885EETG+T [MAXIM]
Multiplexers/Switches, 2 Func, 2 Channel, BICMOS, PQCC24,;
| 型号： | MAX4885EETG+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Multiplexers/Switches, 2 Func, 2 Channel, BICMOS, PQCC24, 复用器 |
| 文件： | 总13页 (文件大小：367K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0554; Rev 0; 5/06
Complete VGA 1:2 or 2:1 Multiplexer
General Description
Features
The MAX4885 integrates high-bandwidth analog
switches and level-translating buffers to implement a
complete 1:2 or 2:1 multiplexer for VGA signals. The
device provides switching for RGB, display data chan-
nel (DDC), and horizontal and vertical synchronization
(HSYNC, VSYNC) signals. A low-noise charge pump
with internal capacitors provides a boosted gate-drive
voltage to improve performance of the RGB switches.
♦ +5V Single-Supply Operation
♦ Programmable Voltage Clamp for Open-Drain
DDC Signals
♦ Low 5 (typ) On-Resistance (R, G, B Signals)
♦ Low 13pF (typ) On-Capacitance (R, G, B Signals)
♦ Break-Before-Make Switching Protects Against
In the 1:2 multiplexer mode, HSYNC/VSYNC inputs fea-
ture level-shifting buffers to support low-voltage CMOS
or standard TTL-compatible graphics controllers. In the
2:1 multiplexer mode, the output buffers for the
HSYNC/VSYNC inputs are disabled, allowing bidirec-
tional signaling. In both modes, DDC signals are volt-
age-clamped to an external voltage to provide level
translation and protection. The MAX4885 features a
5µA shutdown mode and is ESD protected to ±8ꢀV
Human Body Model (HBM) on externally routed pins.
Circuit Shorts
♦ ±±kV ꢀBM ꢁSD Protection on ꢁEternally Routeꢂ
Pins
♦ Low 300µA Supply Current (Lower than 1µA with
Charge Pump Disableꢂ)
♦ Space-Saving, Leaꢂ-Free, 32-Pin (5mm E 5mm)
TQFN Package
The MAX4885 is specified over the extended (-40°C to
+85°C) temperature range, and is available in the 32-
pin, 5mm x 5mm TQFN pacꢀage.
Ordering Information
Applications
PKG
CODꢁ
PART
TꢁMP RANGꢁ PIN-PACKAGꢁ
Notebooꢀ Computers
Digital Projectors
Computer Monitors
Servers
MAX4885ETJ+ -40°C to +85°C 32 TQFN-EP*
T3255-4
*EP = Exposed pad.
+Denotes lead-free package.
KVM Switches
Pin Configuration
Typical Operating Circuit
TOP VIEW
24 23 22 21 20 19 18 17
+3.3V
16
15
G1 25
R1 26
G2
R2
+5V
0.1 F
0.1 F
V
V+
MAX4885
CL
14 DDCB2
27
28
29
30
31
32
DDCB1
DDCA1
GND
V+
DDCA2
GND
13
12
3
2
3
2
R0, B0, G0
H0, V0
R1, G1, B1
H1, V1
MAX4885
GRAPHICS
CONTROLLER
2
2
VGA
PORT 1
11 V+
DDCA1, DDCB1
DDCA0, DDCB0
*EP
3
10
9
V
M
CL
R2, G2, B2
H2, V2
DDCA2, DDCB2
GND
DOCKING
STATION
SEL
M
EN
VGA
2
EN
SEL
PORT 2
2
1
2
3
4
5
6
7
8
TQFN
*EXPOSED PADDLE CONNECTED TO GND
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
Complete VGA 1:2 or 2:1 Multiplexer
ABSOLUTꢁ MAXIMUM RATINGS
(All voltages referenced to GND.)
Continuous Power Dissipation (T = +±0°C)
A
V , V .....................................................................-0.3V to +6V
R_, G_, B_, DDCA_, DDCB_, SEL, M,
EN, QP (Note 1) ...........................................-0.3V to V+ + 0.3V
H_, V_ .......................................................................-0.3V to +6V
Continuous Current Through RGB Switches ....................±±0mA
Continuous Current Through HV, DDC Switches…..........±50mA
Peaꢀ Current Through RGB Switches
32-Pin TQFN (derate 21.3mW/°C above +±0°C) ........1±02mW
+
CL
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
(pulsed at 1ms, 10% duty cycle).................................±140mA
Peaꢀ Current Through HV, DDC Switches (pulsed at 1ms,
10% duty cycle)..............................................................±100mA
Note 1: Signals exceeding V+ or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ꢁLꢁCTRICAL CꢀARACTꢁRISTICS
(V+ = +5.0V ±10%, V = +3.3V ±10%, T = T
to T
, QP = GND, unless otherwise noted. Typical values are at V+ = +5.0V,
MAX
CL
A
MIN
V
= +3.3V and T = +25°C.)
CL
A
PARAMꢁTꢁR
SYMBOL
CONDITIONS
MIN
4.5
TYP
MAX
5.5
V+
0.5
1
UNITS
V
Supply Voltage Range
Clamp Voltage Range
V+
V
2.±
V
CL
QP = GND
QP = V+
0.3
mA
µA
µA
µA
V
Quiescent Supply Current
I
V+ = +5.5V
= V+ = +5.5V
+
+
V
V
Quiescent Supply Current
I
V
CL
1
CL
CL
Shutdown Current
I
V+ = +5.5V, all digital inputs to V+ or GND
5
+
+SHDN
V
GND
= V+ = +5.5V, all digital inputs to V+ or
CL
V
Shutdown Current
I
1
µA
CL
CLSHDN
RGB ANALOG SWITCꢀꢁS
QP = GND
QP = V+
5
6
±.5
10
0V < V < +2.5V,
IN
On-Resistance
R
ON
I
IN
= -40mA
On-Resistance Matching
On-Resistance Flatness
Off-Leaꢀage Current
On-Leaꢀage Current
R
0V < V < +2.5V, I = -40mA
0.5
0.02
1.5
0.±5
+1
ON
IN
IN
R
0V < V < +2.5V, I = -40mA
IN IN
FLAT(ON)
I
R_, G_, B_ = 0V or +5.5V, EN = GND
R_, G_, B_ = 0V or +5.5V, EN = V+
-1
-1
µA
µA
L(OFF)
I
+1
L(ON)
Q
QP = GND
QP = V+
10
8
R_, G_, B_ = 0V,
C = 1000pF
L
Charge Injection
pC
ꢀV MULTIPLꢁXꢁR
Input-Voltage Low
Input-Voltage High
High-Output Drive Current
Low-Output Drive Current
On-Resistance
V
M = GND
M = GND
0.8
V
ILHV
V
2.0
-16
V
IHHV
I
V
V
= V - 0.5V, M = GND
mA
mA
OHHV
OUT
OUT
+
I
= +0.5V, M = GND
+16
15
OLHV
R
ONHV
H_ = V_ = +2.5V, I = -40mA, M = V+
IN
Charge Injection
Q
H_, V_ = 0V, M = V+, C = 1000pF
21
pC
L
2
_______________________________________________________________________________________
Complete VGA 1:2 or 2:1 Multiplexer
ꢁLꢁCTRICAL CꢀARACTꢁRISTICS (continueꢂ)
(V+ = +5.0V ±10%, V = +3.3V ±10%, T = T
to T
, QP = GND, unless otherwise noted. Typical values are at V+ = +5.0V,
MAX
CL
A
MIN
V
= +3.3V and T = +25°C.)
CL
A
PARAMꢁTꢁR
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DDC MULTIPLꢁXꢁR
On-Resistance
R
V
V
< +0.4V, V = +3.0V, I = -20mA
20
+1
ON(DDC)
IN
CL
IN
DDC Leaꢀage
I
- 0.4V < V
< V , V = V+
-1
µA
pC
L(DDC)
Q
CL
OUT
CL IN
Charge Injection
DDCA_, DDCB_ = 0V, C = 1000pF
L
10
SWITCꢀ LOGIC (SꢁL, M, EN, QP)
Input-Low Voltage
V
V+ = +5.5V
V+ = +4.5V
0.8
+1
V
V
IL
Input-High Voltage
Input Leaꢀage Current
ꢁSD PROTꢁCTION
V
2.0
-1
IH
I
V
= V+
IN
µA
LEAK
Human Body Model, all pins
±2
±8
ꢀV
ꢀV
ESD Protection
Human Body Model, R_, G_, B_, H_, V_,
DDCA_, DDCB_
AC ꢁLꢁCTRICAL CꢀARACTꢁRISTICS
(V+ = +5.0V ±10%, V = +3.3V ±10%, T = T
to T
, QP = GND. Typical values are at V+ = +5.0V, V = +3.3V and T =
MAX CL A
CL
A
MIN
+25°C, unless otherwise noted.) (Note 2)
PARAMꢁTꢁR
Bandwidth
SYMBOL
CONDITIONS
MIN
TYP
350
350
0.85
1
MAX
UNITS
QP = GND
QP = V+
f
R = R = 50
MHz
MAX
S
L
QP = GND
QP = V+
1.2
1.6
1MHz < f < 50MHz,
R = R = 50
Insertion Loss
Crosstalꢀ
I
dB
dB
pF
LOS
S
L
1MHz < f < 50MHz, V = 0.±V
,
IN
P-P
V
-40
5
CT
R = R = 50
S
L
f = 1MHz,
QP = GND or V+
Off-Capacitance
C
OFF
QP = GND
QP = V+
13
1±
50
On-Capacitance
C
f = 1 MHz
pF
µV
ON
Charge-Pump Noise
V
V
= +1.0V, R = R = 50
200
NQP
IN
S
L
_______________________________________________________________________________________
3
Complete VGA 1:2 or 2:1 Multiplexer
TIMING CꢀARACTꢁRISTICS
(V+ = +5.0V ±10%, V = +3.3V ±10%, T = T
to T
, QP = GND. Typical values are at V+ = +5.0V, V = +3.3V and T =
MAX CL A
CL
A
MIN
+25°C, unless otherwise noted.) (Note 2)
PARAMꢁTꢁR
Charge-Pump Startup Time
RGB ANALOG SWITCꢀꢁS
Turn-On Time
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
t
150
µs
QPON
t
V
V
= +1.0V, R = 100 , Figure 1
±
µs
µs
ns
ON
IN
IN
L
Turn-Off Time
t
= +1.0V, R = 100 , Figure 1
0.1
0.1
OFF
L
Propagation Delay
t
C = 10pF, Figure 2, R = R = 50
L L S
PD
C = 10pF, Sꢀew between any two ports: R,
L
Output Sꢀew Between Ports
t
30
ps
SKEW
G, B. Figure 2, R = R = 50
S
L
ꢀV MULTIPLꢁXꢁR
Turn-On Time
t
M = 0, Figure 1
M = 0, Figure 1
5
µs
µs
ON
Turn-Off Time
t
0.1
6
OFF
M = GND
M = V+
16
Propagation Delay
t
C = 10pF
L
ns
PD
0.1
DDC MULTIPLꢁXꢁR
Turn-On Time
t
V
V
= +1.0V, R = 100 , Figure 1
5
µs
µs
ns
ON
IN
IN
L
Turn-Off Time
t
= +1.0V, R = 100 , Figure 1
0.1
OFF
L
Propagation Delay
t
C = 10pF, Figure 2
0.25
PD
L
Note 2: Timing parameters are guaranteed by design and correlation over the full operating temperature range.
Typical Operating Characteristics
(V+ = +5.0V, V = +3.3V and T = +25°C, unless otherwise noted.)
CL
A
R
vs. V *
R0
R
vs. V *
R0
ON
R
vs. V *
R0
ON
ON
(HV SWITCHES)
(RGB SWITCHES)
(RGB SWITCHES)
35
30
25
20
15
10
5
12
10
8
10
9
8
7
6
5
4
3
2
1
0
QP = 1
QP = 0 OR 1
T
= +85 C
A
T
= +25 C
= -40 C
A
T
= +85 C
A
T
= +25 C
A
T
A
6
T
= +25 C
A
4
T
= +85 C
A
T
= -40 C
A
2
T
= -40 C
A
0
0
0
1
2
3
4
0
1
2
3
4
5
0
1
2
3
4
5
V
(V)
V
(V)
R0
R0
V (V)
R0
*R0, G0, B0 ARE INTERCHANGEABLE.
*R0, G0, B0 ARE INTERCHANGEABLE.
*R0, G0, B0 ARE INTERCHANGEABLE.
4
_______________________________________________________________________________________
Complete VGA 1:2 or 2:1 Multiplexer
Typical Operating Characteristics (continued)
(V+ = +5.0V, V = +3.3V and T = +25°C, unless otherwise noted.)
CL
A
R
vs. V
*
HV BUFFER OUTPUT VOLTAGE
HIGH vs. TEMPERATURE
HV BUFFER OUTPUT VOLTAGE
LOW vs. TEMPERATURE
ON
DDAC0
(DDC SWITCHES)
75
60
45
30
15
0
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
3.2
3.0
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
I = 16mA
I = 16mA
V
A
= +3.3V
V
= +5.0V
CL
CL
T
= +85 C
= +25 C
T
= +85 C
= +25 C
A
T
T
A
A
T
= -40 C
T
= -40 C
A
A
0
0.5
1.0
1.5
2.0
2.5
3.0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
(V)
DDAC0
TEMPERATURE ( C)
TEMPERATURE ( C)
*DDAC0 AND DDCB0 ARE INTERCHANGEABLE.
HV LEAKAGE CURRENT
vs TEMPERATURE
DDC LEAKAGE CURRENT
vs. TEMPERATURE
RGB LEAKAGE CURRENT
vs. TEMPERATURE
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
QP = 0
ON LEAKAGE
OFF LEAKAGE
ON LEAKAGE
OFF LEAKAGE
ON LEAKAGE
OFF LEAKAGE
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
RGB CHARGE INJECTION
vs. COM VOLTAGE
t
ON
vs. TEMPERATURE
(RGB SWITCHES)
SUPPLY CURRENT
vs. TEMPERATURE
15
12
9
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
6.0
5.0
4.0
3.0
2.0
1.0
0
QP = 0
QP = 0
6
QP = 1
QP = 1
3
QP = 0
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
(V)
-40
-15
10
35
60
85
-40
-15
10
35
60
85
V
TEMPERATURE ( C)
TEMPERATURE ( C)
COM
_______________________________________________________________________________________
5
Complete VGA 1:2 or 2:1 Multiplexer
Typical Operating Characteristics (continued)
(V+ = +5.0V, V = +3.3V and T = +25°C, unless otherwise noted.)
CL
A
t
ON
vs. TEMPERATURE
(HV, DDC SWITCHES)
t
vs. TEMPERATURE
(RGB SWITCHES)
t
vs. TEMPERATURE
(HV, DDC SWITCHES)
OFF
OFF
3.0
2.5
2.0
1.5
1.0
0.5
0
150
125
100
75
30
25
20
15
10
5
HV
QP = 1
DDC
50
QP = 0
25
0
0
-40
-15
10
35
60
85
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE ( C)
TEMPERATURE ( C)
TEMPERATURE ( C)
RGB PROPAGATION DELAY
vs. TEMPERATURE
CROSSTALK vs. FREQUENCY
ON-RESPONSE vs. FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
1000
800
600
400
200
0
0
QP = 0 OR 1
-1
-2
-3
-4
-5
-6
QP = 1
QP = 0
t
PHL
t
PLH
0
50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
-40
-15
10
35
60
85
0
100
200
300
400
TEMPERATURE ( C)
FREQUENCY (MHz)
OFF-ISOLATION vs. FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
QP = 0 OR 1
0
50 100 150 200 250 300 350 400 450 500
FREQUENCY (MHz)
6
_______________________________________________________________________________________
Complete VGA 1:2 or 2:1 Multiplexer
Timing Circuits/Timing Diagrams
V+
MAX4885
t
< 5ns
r
f
V+
0V
t < 5ns
LOGIC
INPUT
V+
50%
50%
R0, G0, B0
R1, G1, B1
R2, G2, B2
V
N_
V
OUT
t
OFF
R
C
L
L
SEL
V
OUT
0.9 x V
0.9 x V
OUT
0UT
GND
LOGIC
INPUT
SWITCH
OUTPUT
0V
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
R
L
V
= V
N_
OUT
(
)
ON
R + R
L
Figure 1. Switching Time
1V
R
= R = 50
L
S
C = 10pF
L
50%
50%
INPUT
0V
V
OH
t
t
PHL
PLH
0.9V
50%
50%
OUTPUT
= | t - t
0V
t
t
|
PLH PHL
SKEW
= MAX (t , t
)
PD
PLH PHL
Figure 2. Propagation Delay and Skew Waveforms
V+
MAX4885
V
OUT
V+
V
OUT
R
GEN
R0, G0, B0
R1, G1, B1
R2, G2, B2
V
OUT
IN
OFF
OFF
OFF
OFF
C
L
ON
ON
V
GEN
GND
SEL
V
TO V
IH
IL
IN
Q = (
V
)(C )
OUT L
LOGIC INPUT WAVEFORMS INVERTED FOR SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
Figure 3. Charge Injection
_______________________________________________________________________________________
7
Complete VGA 1:2 or 2:1 Multiplexer
Timing Circuits/Timing Diagrams (continued)
+5V
10nF
V
V
OUT
OFF-ISOLATION = 20log ✕
ON-LOSS = 20log ✕
IN
NETWORK
ANALYZER
V
50
50
OUT
V+
V
V
0V OR V+
IN
SEL
V
IN
R0, G0, B0
V
V
OUT
CROSSTALK = 20log ✕
MAX4885
IN
MEAS
50
REF
R1, G1, B1
OUT
R2, G2, B2
GND
50
50
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
OFF-ISOLATION IS MEASURED BETWEEN R0 AND R1 OR R2 ON EACH SWITCH.
ON-LOSS IS MEASURED BETWEEN R0 AND R1 OR R2 ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 4. On-Loss, Off-Isolation, and Crosstalk
Pin Description
PIN
NAMꢁ
FUNCTION
Charge-Pump Enable, Active Low. Drive QP low for normal operation. Drive QP high to disable the
internal charge pump.
1
QP
2
3
4
5
6
±
8
R0
G0
RGB Analog I/O
RGB Analog I/O
RGB Analog I/O
Horizontal Sync I/O
Vertical Sync I/O
DDC I/O
B0
H0
V0
DDCA0
DDCB0
DDC I/O
Enable Input, Active Low. Drive EN low for normal operation. Drive EN high to disable the device. All
I/Os are high-impedance and charge pump is off when the device is disabled.
9
EN
DDC Clamp Voltage. Open-drain DDCA_ and DDCB_ outputs are clamped to one diode-drop below
10
V
V
. +2.±V < V < V+. Connect V to +3.3V for voltage clamping, or connect to V+ to disable
CL CL CL
CL
clamping. Bypass V to GND with a 0.1µF or larger ceramic capacitor.
CL
11, 21, 30
V+
GND
DDCA2
DDCB2
R2
Supply Voltage. V+ = +5.0V ± 10%. Bypass each to GND with a 0.1µF or larger ceramic capacitor.
12, 20, 29
Ground
13
14
15
16
1±
DDC I/O
DDC I/O
RGB Analog I/O
RGB Analog I/O
RGB Analog I/O
G2
B2
±
_______________________________________________________________________________________
Complete VGA 1:2 or 2:1 Multiplexer
Pin Description (continued)
PIN
18
19
22
23
24
25
26
2±
28
NAMꢁ
H2
FUNCTION
Horizontal Sync I/O
Vertical Sync I/O
Vertical Sync I/O
Horizontal Sync I/O
RGB Analog I/O
RGB Analog I/O
RGB Analog I/O
DDC I/O
V2
V1
H1
B1
G1
R1
DDCB1
DDCA1
DDC I/O
Mode Select. Drive M low for 1:2 multiplexer mode. Drive M high for 2:1 multiplexer mode. See Tables
1, 2, and 3.
31
M
32
EP
SEL
EP
Select. Logic input for switching RGB, HV, and DDC switches. See Tables 1, 2, and 3.
Exposed Pad. Connect exposed pad to ground.
Detailed Description
Table 1. RGB Truth Table
The MAX4885 integrates high-bandwidth analog
switches and level-translating buffers to implement a
complete 1:2 or 2:1 multiplexer for VGA signals. The
device provides switching for RGB, HSYNC, VSYNC,
and DDC signals. A low-noise charge pump with inter-
nal capacitors provides a boosted gate-drive voltage to
improve performance of the RGB switches.
EN
SꢁL
FUNCTION
R0 to R1
G0 to G1
B0 to B1
0
0
R0 to R2
G0 to G2
B0 to B2
0
1
X
The device provides two modes of operation: 1:2 and
2:1. In 1:2 mode (M = 0), the HSYNC and VSYNC
inputs feature level-shifting buffers to support TTL out-
put logic levels from low-voltage graphics controllers.
These buffered switches may be driven from as little as
+2.0V up to +5.5V. In 2:1 mode (M=1), the output
buffers for the HSYNC and VSYNC signals are dis-
abled. In both modes, RGB signals are routed with the
same high-performance analog switches, and DDC sig-
nals are voltage clamped to a diode drop less than
1
R_, B_, and G_, High Impedance
X = Don’t Care
RGB Switches
The MAX4885 provides three SPDT high-bandwidth
switches to route standard VGA R, G, and B signals
(see Table 1). A boosted gate-drive voltage is generat-
ed by an internal charge pump to improve performance
of the RGB switches. The R, G, and B analog switches
are identical, and any of the three switches can be
used to route red, green, or blue video signals. The
RGB switches function with reduced performance with
the charge pump disabled.
V
. Voltage clamping provides protection and com-
CL
patibility with DDC signals and low-voltage ASICs. In
ꢀeyboard/video/mouse (KVM) applications, V is nor-
CL
mally set to +5V because low-voltage clamping is not
required, as specified by the VESA standard.
Drive EN logic high to shut down the MAX4885. In shut-
down mode, supply current is reduced to 5µA and all
switches are high impedance, providing high-signal
rejection. The RGB, HSYNC, VSYNC, and DDC switches
are ESD protected to ±8ꢀV by the Human Body Model.
Charge Pump
A low-noise charge pump with internal capacitors pro-
vides a doubled voltage for driving the RGB analog
switches. Noise voltage from the charge pump is less
than 50µV
The noise level is more than 80dB below
P-P.
the signal level, maꢀing the charge pump suitable for
_______________________________________________________________________________________
9
Complete VGA 1:2 or 2:1 Multiplexer
standard VGA signals. The charge pump can be dis-
Table 2. ꢀV Truth Table
abled to eliminate charge-pump noise; however, RGB
switch performance is slightly degraded. Connect QP
to ground for normal operation.
EN
M
SꢁL
FUNCTION
1:2 Mode
Buffers Enabled
H0 to H1
V0 to V1
Horizontal/Vertical Sync Multiplexer
0
0
0
1:2 Multiplexer Mode
The MAX4885 provides two modes of operation for the
HSYNC and VSYNC signals. In 1:2 mode (M = 0), the
HSYNC/VSYNC inputs are buffered to provide level shift-
ing and drive capability to meet the VESA specification.
1:2 Mode
Buffers Enabled
H0 to H2
0
0
0
1
1
0
V0 to V2
2:1 Multiplexer Mode
In 2:1 mode (M = 1), the HSYNC/VSYNC output buffers
are disabled, and switches pass signals directly. The
HSYNC and VSYNC switches/buffers are identical, and
either input can be used to route HSYNC and
VSYNC signals.
2:1 Mode
Buffers Disabled
H0 to H1
V0 to V1
2:1 Mode
Buffers Disabled
H0 to H2
Display Data Channel Multiplexer
The MAX4885 provides two voltage-clamped switches
to route DDC signals (see Table 3). Each switch
clamps signals to a diode drop less than the voltage
0
1
1
X
1
X
V0 to V2
applied on V . Supply +3.3V on V
to provide volt-
CL
CL
H_, V_
High Impedance
age clamping for VESA I2C-compatible signals. If volt-
age clamping is not required, connect V to V+. The
CL
X = Don’t Care
DDCA and DDCB switches are identical, and each
switch can be used to route either DDC signal.
Table 3. DDC Truth Table
ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. Additionally, the MAX4885 is protected to
±8ꢀV on RGB, HSYNC, VSYNC, and DDC switches by
the Human Body Model (HBM). For optimum ESD per-
formance, bypass each V+ pin to ground with a 0.1µF
or larger ceramic capacitor.
EN
SꢁL
FUNCTION
DDCA0 to DDCA1
DDCB0 to DDCB1
0
0
DDCA0 to DDCA2
DDCB0 to DDCB2
0
1
X
DDCA_, DDCB_
High Impedance
1
X = Don’t Care
Human Body Model (HBM)
Several ESD testing standards exist for measuring the
robustness of ESD structures. The ESD protection of
the MAX4885 is characterized with the Human Body
Model. Figure 5 shows the model used to simulate an
ESD event resulting from contact with the human body.
The model consists of a 100pF storage capacitor that is
charged to a high voltage, then discharged through a
1.5ꢀ resistor. Figure 6 shows the current waveform
when the storage capacitor is discharged into a low
impedance.
Applications Information
1:2 Multiplexer for Low-Voltage Graphics
Controllers
The MAX4885 provides the level shifting necessary to
drive two standard VGA ports from a graphics con-
troller as low as +2.2V. In 1:2 mode, internal buffers
drive the HSYNC and VSYNC signals to VGA standard
TTL levels. The DDC multiplexer provides level shifting
by clamping signals to a diode drop less than V (see
the Typical Operating Circuit). Connect V
for normal operation, or to V+ to disable voltage clamp-
ing for DDC signals.
CL
ESD Test Conditions
ESD performance depends on a variety of conditions.
Please contact Maxim for a reliability report document-
ing test setup, methodology, and results.
to +3.3V
CL
10 ______________________________________________________________________________________
Complete VGA 1:2 or 2:1 Multiplexer
R
C
R
D
1M
1500
I 100%
P
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
100pF
STORAGE
CAPACITOR
s
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 5. Human Body ESD Test Model
Figure 6. HBM Discharge Current Waveform
2:1 Multiplexer
PC Board Layout
In 2:1 mode, HSYNC and VSYNC buffers are disabled,
allowing bidirectional signaling. The DDC multiplexer
provides level shifting by clamping signals to a diode
High-speed switches such as the MAX4885 require
proper PC board layout for optimum performance.
Ensure that impedance-controlled PC board traces for
high-speed signals are matched in length and as short
as possible. Connect the exposed pad to a solid
ground plane.
drop less than V (see the Typical Operating Circuit).
CL
Connect V
to V+ to disable voltage clamping for
CL
DDC signals.
Chip Information
PROCESS: BiCMOS
Power-Supply Decoupling
Bypass each V+ pin and V to ground with a 0.1µF or
CL
larger ceramic capacitor as close to the device as pos-
sible.
CONNECT EXPOSED PAD TO GND
______________________________________________________________________________________ 11
Complete VGA 1:2 or 2:1 Multiplexer
Functional Diagram
MAX4885
M
H1
V1
*
*
H0
H2
V2
V0
SEL
R1
G1
B1
R2
G2
B2
R0
G0
B0
RGB
CHARGE
PUMP
QP
EN
DDCA1
DDCB1
DDCA0
DDCB0
DDCA2
DDCB2
VOLTAGE
CLAMP
V
CL
12 ______________________________________________________________________________________
Complete VGA 1:2 or 2:1 Multiplexer
Package Information
(The pacꢀage drawing(s) in this data sheet may not reflect the most current specifications. For the latest pacꢀage outline information,
go to www.maEim-ic.com/packages.)
D2
D
b
0.10 M
C A B
C
L
D2/2
D/2
k
L
MARKING
AAAAA
E/2
E2/2
C
(NE-1) X
e
L
E2
E
PIN # 1 I.D.
0.35x45°
DETAIL A
e/2
PIN # 1
I.D.
e
(ND-1) X
e
DETAIL B
e
L
C
L
C
L
L1
L
L
e
e
0.10
C
A
0.08
C
C
A3
A1
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
1
-DRAWING NOT TO SCALE-
I
21-0140
2
COMMON DIMENSIONS
20L 5x5 28L 5x5
EXPOSED PAD VARIATIONS
D2 E2
MIN. NOM. MAX. MIN. NOM. MAX.
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
PKG.
SYMBOL MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX. MIN. NOM. MAX.
16L 5x5
32L 5x5
40L 5x5
L
DOWN
BONDS
ALLOWED
YES
NO
exceptions
PKG.
CODES
±0.15
A
0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80 0.70 0.75 0.80
0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05 0.02 0.05
0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF. 0.20 REF.
T1655-2
T1655-3
**
**
**
**
A1
0
0
0
0
0
A3
b
T1655N-1 3.00 3.10 3.20 3.00 3.10 3.20
NO
0.25 0.30 0.35 0.25 0.30 0.35 0.20 0.25 0.30 0.20 0.25 0.30 0.15 0.20 0.25
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10 4.90 5.00 5.10
T2055-3
T2055-4
T2055-5
T2855-3
3.00 3.10 3.20 3.00 3.10 3.20
3.00 3.10 3.20 3.00 3.10 3.20
YES
D
E
NO
**
YES
3.15 3.25 3.35 3.15 3.25 3.35 0.40
e
0.80 BSC.
0.25
0.65 BSC.
0.25
0.50 BSC.
0.25
0.50 BSC.
0.25
0.40 BSC.
3.15 3.25 3.35 3.15 3.25 3.35
YES
YES
NO
**
**
**
k
-
-
-
-
-
-
-
-
0.25 0.35 0.45
T2855-4
T2855-5
2.60 2.70 2.80 2.60 2.70 2.80
2.60 2.70 2.80 2.60 2.70 2.80
3.15 3.25 3.35 3.15 3.25 3.35
L
0.30 0.40 0.50 0.45 0.55 0.65 0.45 0.55 0.65 0.30 0.40 0.50 0.40 0.50 0.60
L1
-
-
-
-
-
-
-
-
-
-
-
-
0.30 0.40 0.50
NO
YES
YES
T2855-6
T2855-7
**
**
N
ND
NE
16
4
4
20
5
28
7
32
8
8
40
10
10
2.80
2.60 2.70
2.60 2.70 2.80
5
7
T2855-8
3.15 3.25 3.35 3.15 3.25 3.35 0.40
WHHB
WHHC
WHHD-1
WHHD-2
-----
JEDEC
T2855N-1 3.15 3.25 3.35 3.15 3.25 3.35
NO
YES
NO
YES
NO
**
**
**
**
**
**
3.20
3.00 3.10 3.20
T3255-3
T3255-4
T3255-5
3.00 3.10
3.00 3.10 3.20 3.00 3.10 3.20
3.20
NOTES:
3.00 3.10
3.00 3.10 3.20
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
T3255N-1 3.00 3.10 3.20 3.00 3.10 3.20
T4055-1 3.20 3.30 3.40 3.20 3.30 3.40
YES
**SEE COMMON DIMENSIONS TABLE
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR
T2855-3 AND T2855-6.
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
2
-DRAWING NOT TO SCALE-
21-0140
I
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13
© 2006 Maxim Integrated Products
Boblet
Printed USA
is a registered trademarꢀ of Maxim Integrated Products, Inc.
相关型号：
MAX4885ETJ-T
Video Multiplexer, 1 Func, 2 Channel, BICMOS, 5 X 5 MM, 0.80 MM HEIGHT, MO-220WHHD-2, TQFN-32
MAXIM
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