MAX4885EETG+ [MAXIM]
Ultra-Low Capacitance 1:2 VGA Switch with ±15kV ESD; 超低电容1 ： 2 VGA开关，具有± 15kV ESD保护
| 型号： | MAX4885EETG+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Ultra-Low Capacitance 1:2 VGA Switch with ±15kV ESD |
| 文件： | 总10页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4269; Rev ꢁ; 1ꢁ/ꢁ8
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
MAX485E
General Description
Features
The MAX4885E integrates high-bandwidth analog
switches and level-translating buffers to implement a
complete 1:2 multiplexer for VGA signals. The device
provides switching for RGB, display data channel (DDC).
♦ ±±15kV HBVꢀESVꢁProteoꢂrꢃVrꢃVꢀꢄotPꢃnaalVꢅrꢆotꢇ
TtPmꢂꢃnas
♦ ±G zVHnꢃꢇwꢂꢇoh
♦ LrwV1Ω (olp)VOꢃ-ꢅtsꢂsonꢃetV(ꢅ,VG,VHVEꢂgꢃnas)
♦ LrwV6pFV(olp)VOꢃ-CnpneꢂonꢃetV(ꢅ,VG,VHVEꢂgꢃnas)
♦ LrwVꢅ,VG,VHVE5twV-10psV(olp)
Horizontal and vertical synchronization (HSYNC/VSYNC)
inputs feature level-shifting buffers to support low-volt-
age CMOS or standard TTL-compatible graphics con-
trollers, meeting the VESA requirement of 8mA. DDC,
consisting of SDA_ and SCL_, is a bidirectional active-
level translating switch that reduces capacitive load. The
MAX4885E features high ESD protection to 15ꢀV
Human Body Model (HBM) on all twelve externally rout-
ed terminals. See the Pin Description section. All other
pins are protected to 1ꢁꢀV Human Body Model (HBM).
♦ NtnPVZtPrVꢁrwtPVCrꢃsꢆmpoꢂrꢃV(<V2µA)
♦ UaoPn-Emnaa,V24-ꢁꢂꢃV(4mmVꢄV4mm)VTQFNVꢁne5ngt
The MAX4885E is specified over the extended -4ꢁ°C to
+85°C temperature range, and is available in the
24-pin, 4mm x 4mm TQFN pacꢀage.
Ordering Information
ꢁAꢅT
TꢀBꢁVꢅANGꢀ
ꢁIN-ꢁACKAGꢀ
Applications
MAX4885EETG+
-4ꢁ°C to +85°C
24 TQFN-EP*
Notebooꢀ Computers/Docꢀing Stations
*EP = Exposed pad.
Digital Projectors
+Denotes lead-free pacꢀage/RoHS-compliant pacꢀage.
Computer Monitors
Servers/Storage
KVM Switches
Pin Configuration
Typical Operating Circuit
TOP VIEW
+3.3V
+5.0V
18 17 16 15 14 13
0.1µF
0.1µF
19
12
SCL2
V1
V
L
V
CC
SCL1 20
11 H1
MAX4885E
21
22
23
24
10
9
3
2
2
3
2
2
SDA2
SDA1
GND
R0, B0, G0
H0, V0
R1, G1, B1
SDA1, SCL1
H1, V1
GRAPHICS
CONTROLLER
VGA
PORT
MAX4885E
V
L
SDA0, SCL0
EN
V
8
CC
2
3
2
*EP
SEL
V0
7
DOCKING
STATION
+3.3V
EN
R2, G2, B2
+
1
2
3
4
5
6
DOCKING
STATION
SDA2, SCL2
SEL
GND
TQFN-ꢀꢁ
*EXPOSED PAD. CONNECTED TO GROUND OR LEAVE UNCONNECTED.
________________________________________________________________ BnꢄꢂmVIꢃotgPnotꢇVꢁPrꢇꢆeos
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rPVvꢂsꢂoVBnꢄꢂm'sVwtbsꢂotVnoVwww.mnꢄꢂm-ꢂe.erm.
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
AHEOLUTꢀVBAXIBUBVꢅATINGE
(All voltages referenced to GND.)
Continuous Power Dissipation (T = +7ꢁ°C)
A
V
, V .....................................................................-ꢁ.3V to +6V
24-Pin TQFN (derate 27.8mW/°C above +7ꢁ°C) ........2222mW
CC
L
R_, G_, B_, SDA1, SCL1, SDA2, SCL2,
Junction to Ambient Thermal Resistance (θ ) (Note 2)
JA
H1, V1, (Note 1) ........................................-ꢁ.3V to V
Hꢁ, Vꢁ, SDAꢁ, SCLꢁ, EN, SEL.........................-ꢁ.3V to V + ꢁ.3V
+ ꢁ.3V
24-Pin TQFN..................................................................36°C/W
CC
L
Junction to Ambient Thermal Resistance (θ ) (Note 2)
JC
Continuous Current through RGB Switches ..................... 3ꢁmA
Continuous Current through DDC Switches..................... 3ꢁmA
Peaꢀ Current through RGB Switches
(pulsed at 1ms, 1ꢁ% duty cycle)................................... 9ꢁmA
Peaꢀ Current through DDC Switches (pulsed at 1ms,
1ꢁ% duty cycle)............................................................ 9ꢁmA
24-Pin TQFN....................................................................3°C/W
Operating Temperature Range ...........................-4ꢁ°C to +85°C
Storage Temperature Range.............................-65°C to +15ꢁ°C
Junction Temperature......................................................+15ꢁ°C
Lead Temperature (soldering, 1ꢁs) .................................+3ꢁꢁ°C
MAX485E
NrotV±: Signals exceeding V
or GND are clamped by internal diodes. Limit forward-diode current to maximum current rating.
CC
NrotV2: Pacꢀage thermal resistances were obtained using the method described in JEDEC specifications. For detailed information
on pacꢀage thermal considerations, refer to www.mnꢄꢂm-ꢂe.erm/ohtPmna-oꢆorPꢂna.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ꢀLꢀCTꢅICALVC AꢅACTꢀꢅIETICE
(V = +5.ꢁV 1ꢁ%, V = +2V to +5.5V, T = T
to T
, unless otherwise noted. Typical values are at V = +5.ꢁV, V = +3.3V and
CC
L
A
MIN
MAX
CC
L
T
A
= +25°C.) (Note 3)
ꢁAꢅABꢀTꢀꢅ
EYBHOL
CONSITIONE
BIN
TYꢁ
BAX
UNITE
EN = V
L
V
Quiescent Supply Current
I
V = +5.ꢁV
CC
1
µA
CC
CC
EN = GND
EN = V
L
V Quiescent Supply Current
L
I
V = +3.3V
L
1
µA
VL
EN = GND
ꢅGHVANALOGVEWITC ꢀE
V
= +5.ꢁV, I = -1ꢁmA, V = +ꢁ.7V
IN IN
CC
On-Resistance
R
ON
6
Ω
(Note 4)
On-Resistance Matching
On-Resistance Flatness
ΔR
ꢁ ≤ V ≤ ꢁ.7V, I = -1ꢁmA
ꢁ.5
ꢁ.5
Ω
Ω
ON
IN
IN
R
ꢁ ≤ V ≤ ꢁ.7V, I = -1ꢁmA
IN IN
FLAT(ON)
V
V
= +5.5V, V = +ꢁ.3V or +5.5V,
IN
CC
EN
Off-Leaꢀage Current
I
-1
-1
+1
+1
µA
µA
L(OFF)
= ꢁ or V
L
V
V
= +5.5V, V = +ꢁ.3V or +5.5V,
IN
CC
EN
On-Leaꢀage Current
kVHUFFꢀꢅ
I
L(ON)
= V
L
ꢁ.33 x
Input Voltage Low
V
V
V
ILHV
V
L
ꢁ.66 x
Input Voltage High
V
IHHV
V
L
Input Logic Hysteresis
Input Leaꢀage Current
High-Output Drive Current
Low-Output Drive Current
V
75
mV
µA
HYST
I
V
V
V
= +5.5V, V = +5.5V, V = ꢁ or V
L
-1
+1
INHV
CC
L
IN
I
≥ 3.ꢁV
≤ ꢁ.6V
8.ꢁ
8.ꢁ
mA
mA
OHHV
OHHV
OLHV
I
OLHV
2
_______________________________________________________________________________________
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
MAX485E
ꢀLꢀCTꢅICALVC AꢅACTꢀꢅIETICEV(erꢃoꢂꢃꢆtꢇ)
(V = +5.ꢁV 1ꢁ%, V = +2V to +5.5V, T = T
to T
, unless otherwise noted. Typical values are at V = +5.ꢁV, V = +3.3V and
CC
L
A
MIN
MAX
CC
L
T
A
= +25°C.) (Note 3)
ꢁAꢅABꢀTꢀꢅ
EYBHOL
CONSITIONE
BIN
TYꢁ
BAX
UNITE
ESA_,VECL_
Supply Voltage
On-Resistance
On-Capacitance
V
2.ꢁ
5.5
V
Ω
L
R
ON
C
ON
V
= +ꢁ.4V, I
=
2mA, V = +2.ꢁV
1ꢁ
15
IN
IN
L
f = 1ꢁꢁꢀHz
pF
EN = GND, V = +5.5V, V = +3.6V,
CC
L
High-Impedance Input Leaꢀage
Current
SCLꢁ, SDAꢁ, SCL1, SCL2, SDA1, SDA2
= GND or V (Note 5)
I
-1
-1
+1
+1
µA
µA
INHIZ
VL
Off-Input Leaꢀage Current
I
EN = V , V = +3.6V, V = V - ꢁ.2V
L L IN L
INOFF
CONTꢅOLVLOGICV(EꢀL,VꢀN)
ꢁ.33 x
Input Voltage Low
Input Voltage High
V
V
V
ILLOG
V
L
ꢁ.66 x
V
I
IHLOG
V
L
Input Logic Hysteresis
Input Leaꢀage Current
ꢀESVꢁꢅOTꢀCTION
V
75
mV
µA
HYST
V
= +5.5V, V = +3.6V, V = ꢁ or V
L
-1
+1
INLEK
CC
L
IN
Human Body Model; R1, G1, B1, R2, G2,
B2, SDA1, SCL1, SDA2, SCL2, H1, V1
15
1ꢁ
ESD Protection
ꢀV
Human Body Model; all other pins
ACVꢀLꢀCTꢅICALVC AꢅACTꢀꢅIETICE
(V = +5.ꢁV 1ꢁ%, V = +2V to +5.5V, T = T
to T
, unless otherwise noted. Typical values are at V = +5.ꢁV, V = +3.3V and
CC
L
A
MIN
MAX
CC
L
T
A
= +25°C.) (Note 3)
ꢁAꢅABꢀTꢀꢅ
EYBHOL
CONSITIONE
BIN
TYꢁ
BAX
UNITE
GHz
dB
Bandwidth
f
R = R = 5ꢁΩ
1
MAX
S
L
Insertion Loss
Crosstalꢀ
I
f = 1MHz, R = R = 5ꢁΩ, Figure 1
ꢁ.6
-4ꢁ
4.5
6.4
LOS
S
L
V
f = 5ꢁMHz, R = R = 5ꢁΩ, Figure 1
dB
CT
S
L
Off-Capacitance
On-Capacitance
C
f = 25ꢁMHz
f = 25ꢁMHz
pF
OFF
C
pF
ON
_______________________________________________________________________________________
3
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
TIBINGVC AꢅACTꢀꢅIETICE
(V = +5.ꢁV 1ꢁ%, V = +2V to +5.5V, T = T
to T
, unless otherwise noted. Typical values are at V = +5.ꢁV, V = +3.3V and
CC
L
A
MIN
MAX
CC
L
T
A
= +25°C.) (Note 3)
ꢁAꢅABꢀTꢀꢅ
EYBHOL
CONSITIONE
BIN
TYꢁ
BAX
UNITE
ps
ꢅGHVANALOGVEWITC ꢀE
Sꢀew between any two ports: R_, G_, B_,
Figure 2
Output Sꢀew Between Ports
t
5ꢁ
15
SKEW
kVHUFFꢀꢅ
MAX485E
Propagation Delay
t
R = 1ꢀΩ, C = 1ꢁpF, Figure 2
ns
PD
L
L
NrotV3: All devices are 1ꢁꢁ% production tested at T = +25°C. Specifications over the full temperature range are guaranteed by design.
A
NrotV4: On-resistance guarantees the low-static logic level.
NrotV1: SDA_, SCL_ off-input leaꢀage current guarantees the high-static logic level.
Typical Operating Characteristics
(V
= +5.ꢁV, V = +3.3V and T = +25°C, unless otherwise noted.)
L A
CC
HV BUFFER OUTPUT VOLTAGE
HIGH vs. TEMPERATURE
R
vs. V
*
R
vs. V
*
ON
R0
ON
SDA0
(RGB SWITCHES)
(DDC SWITCHES)
8
7
6
5
4
3
10
60
45
30
15
0
SDA0, SCL0 ARE
INTERCHANGEABLE
I
= 8mA
*R0, G0, B0 ARE INTERCHANGEABLE
OUT
9
8
7
6
5
4
3
2
1
0
T
A
= +85°C
T
A
= +25°C
V = +3.3V
L
V = +5.0V
L
T
A
= +85°C
T
= +85°C
= +25°C
= -40°C
A
T
A
= +25°C
T
A
T
A
= -40°C
T
A
T
A
= -40°C
-40
-15
10
35
60
85
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
(V)
1
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
(V)
TEMPERATURE (°C)
V
R0
V
SDA0
4
_______________________________________________________________________________________
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
MAX485E
Typical Operating Characteristics (continued)
(V
= +5.ꢁV, V = +3.3V and T = +25°C, unless otherwise noted.)
L A
CC
HV BUFFER OUTPUT VOLTAGE
LOW vs. TEMPERATURE
SUPPLY CURRENT vs. TEMPERATURE
1.0
0.5
0.4
0.3
0.2
0.1
0.0
I
= 8mA
OUT
0.8
0.6
0.4
0.2
0.0
I
CC
I
VL
-40
-15
10
35
60
85
-40
-15
10
35
60
85
TEMPERATURE (°C)
TEMPERATURE (°C)
ON-RESPONSE vs. FREQUENCY
CROSSTALK vs. FREQUENCY
0
-1
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-2
-3
-4
-5
-6
-7
-8
-9
-10
1
10
100
1000
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
_______________________________________________________________________________________
1
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
Timing Circuits/Timing Diagrams
+5V
10nF
NETWORK
ANALYZER
V
OUT
50Ω
50Ω
V
CC
INSERTION-LOSS = 20log ✕
CROSSTALK = 20log ✕
V
V
0 OR V
IN
CC
SEL
V
IN
R0, G0, B0
V
OUT
MAX4885E
V
IN
MEAS
REF
R1, G1, B1
8
OUT
R2, G2, B2
GND
50Ω
50Ω
50Ω
MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS.
INSERTION-LOSS IS MEASURED BETWEEN R0 AND R1 OR R2 ON EACH SWITCH.
CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL.
SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
Figure 1. Insertion-Loss and Crosstalꢀ
1V
R = 1kΩ
L
C = 10pF
L
50%
50%
INPUT
0
V
OH
t
t
PHL
PLH
0.9V
0
50%
50%
OUTPUT
t
t
= |t - t
|
SKEW
PLH PHL
= MAX (t , t
)
PD
PLH PHL
Figure 2. Propagation Delay and Sꢀew Waveforms
6
_______________________________________________________________________________________
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
MAX485E
Pin Description
ꢁIN
1
NABꢀ
SDAꢁ
SCLꢁ
Rꢁ
FUNCTION
SDA I/O
2
SCL I/O
3
RGB Analog I/O
RGB Analog I/O
RGB Analog I/O
4
Gꢁ
5
Bꢁ
6
Hꢁ
Horizontal Sync Input
Vertical Sync Input
7
Vꢁ
8
V
Supply Voltage. V
= +5.ꢁV 1ꢁ%. Bypass V
to GND with a ꢁ.1µF or larger ceramic capacitor.
CC
CC
CC
9
V
Supply Voltage. +2V ≤ V ≤ +5.5V. Bypass V to GND with a ꢁ.1µF or larger ceramic capacitor.
L L
L
1ꢁ
11
12
13
14
15
16
17
18
19
2ꢁ
21
22
23
24
—
GND
H1
Ground
Horizontal Sync Output*
Vertical Sync Output*
RGB Analog I/O*
RGB Analog I/O*
RGB Analog I/O*
RGB Analog I/O*
RGB Analog I/O*
RGB Analog I/O*
SCL I/O*
V1
B2
B1
G2
G1
R2
R1
SCL2
SCL1
SDA2
SDA1
EN
SCL I/O*
SDA I/O*
SDA I/O*
Enable Input. Drive EN high for normal operation. Drive EN low to disable the device.
Select Input. Logic input for switching RGB and DDC swiches.
SEL
EP
Exposed Pad. Connect exposed pad to ground or leave unconnected.
*Terminal as 15ꢀV ESD protection—Human Body Model.
mouse (KVM) applications, V is normally set to +5V
L
because low-voltage clamping is not required, as spec-
ified by the VESA standard.
Detailed Description
The MAX4885E integrates high-bandwidth analog
switches and level-translating buffers to implement a
complete 1:2 multiplexer for VGA signals. The device
provides switching for RGB, HSYNC, VSYNC, SDA_
and SCL_ signals.
Drive EN logic-low to shut down the MAX4885E. In shut-
down mode, all switches are high impedance, providing
high-signal rejection. The RGB, HSYNC, VSYNC, SDA_,
and SCL_ outputs are ESD protected to 15ꢀV by the
Human Body Model.
The HSYNC and VSYNC inputs feature level-shifting
buffers to support TTL output logic levels from low-volt-
age graphics controllers. These buffered switches may
be driven from as little as +2.ꢁV up to +5.5V. RGB sig-
nals are routed with the same high-performance analog
switches, and SDA_, SCL_ signals are voltage clamped
to a diode drop less than V . Voltage clamping pro-
L
vides protection and compatibility with SDA_ and SCL_
signals and low-voltage ASICs. In ꢀeyboard/video/
RGB Switches
The MAX4885E provides three SPDT high-bandwidth
switches to route standard VGA R, G, and B signals
(see Table 1). The R, G, and B analog switches are
identical, and any of the three switches can be used to
route red, green, or blue video signals.
_______________________________________________________________________________________
7
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
outputs by the Human Body Model (HBM). See the Pin
TnbatV±.VꢅGHVTPꢆohVTnbat
Description section. For optimum ESD performance,
ꢀN
EꢀL
FUNCTION
bypass each V
pin to ground with a ꢁ.1µF or larger
CC
ceramic capacitor.
Rꢁ to R1
Gꢁ to G1
Bꢁ to B1
1
ꢁ
ꢆmnꢃVHrꢇlVBrꢇtaV( HB)
Several ESD testing standards exist for measuring the
robustness of ESD structures. The ESD protection of
the MAX4885E is characterized with the Human Body
Model. Figure 3 shows the model used to simulate an
ESD event resulting from contact with the human body.
The model consists of a 1ꢁꢁpF storage capacitor that is
charged to a high voltage, then discharged through a
1.5ꢀΩ resistor. Figure 4 shows the current waveform
when the storage capacitor is discharged into a low
impedance.
Rꢁ to R2
Gꢁ to G2
Bꢁ to B2
1
ꢁ
1
X
R_, B_, and G_, high impedance
MAX485E
X = Don’t care.
TnbatV2.V kVTPꢆohVTnbat
ꢀN
FUNCTION
ESD Test Conditions
ESD performance depends on a variety of conditions.
Please contact Maxim for a reliability report document-
ing test setup, methodology, and results.
ꢁ
H_, V_ = ꢁ
X = Don’t care.
TnbatV3.VSSCVTPꢆohVTnbat
Applications Information
ꢀN
EꢀL
FUNCTION
The MAX4885E provides the level shifting necessary to
drive two standard VGA ports from a graphics con-
troller as low as +2.2V. Internal buffers drive the
HSYNC and VSYNC signals to VGA standard TTL lev-
els. The DDC multiplexer provides level shifting by
SDAꢁ to SDA1
SCLꢁ to SCL1
1
ꢁ
SDAꢁ to SDA2
SCLꢁ to SCL2
1
ꢁ
1
X
clamping signals to a diode drop less than V (see the
L
SDA_, SCL_, high impedance
Typical Operating Circuit). Connect V to +3.3V for nor-
L
mal operation, or to V
DDC signals.
to disable voltage clamping for
CC
X = Don’t care.
Power-Supply Decoupling
pin and V to ground with a ꢁ.1µF
or larger ceramic capacitor as close as possible to the
device.
Horizontal/Vertical Sync Level Shifter
HSYNC/VSYNC are buffered to provide level shifting
and drive capability to meet the VESA specification.
Bypass each V
CC
L
Display-Data Channel Multiplexer
The MAX4885E provides two voltage-clamped switches
to route DDC signals (see Table 3). Each switch clamps
signals to a diode drop less than the voltage applied on
PCB Layout
High-speed switches such as the MAX4885E require
proper PCB layout for optimum performance. Ensure
that impedance-controlled PCB traces for high-speed
signals are matched in length and as short as possible.
Connect the exposed pad to a solid ground plane.
V . Supply +3.3V on V to provide voltage clamping for
L
L
VESA I2C-compatible signals. If voltage clamping is not
required, connect V to V . The SDA_ and SCL_
L
CC
switches are identical, and each switch can be used to
route either SDA_ and SCL_ signals.
Chip Information
ESD Protection
As with all Maxim devices, ESD-protection structures
are incorporated on all pins to protect against electro-
static discharges encountered during handling and
assembly. Additionally, the MAX4885E is protected to
15ꢀV on RGB, HSYNC, VSYNC, SDA_ and SCL_
PROCESS: BiCMOS
8
_______________________________________________________________________________________
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
MAX485E
R
C
R
D
1MΩ
1500Ω
I
P
100%
90%
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
R
DISCHARGE
RESISTANCE
CHARGE-CURRENT-
LIMIT RESISTOR
AMPERES
HIGH-
VOLTAGE
DC
DEVICE
UNDER
TEST
36.8%
C
100pF
STORAGE
CAPACITOR
s
10%
0
SOURCE
TIME
0
t
RL
t
DL
CURRENT WAVEFORM
Figure 3. Human Body ESD Test Model
Figure 4. HBM Discharge Current Waveform
Functional Diagram
MAX4885E
R1
G1
B1
R0
G0
B0
R2
G2
B2
EN
SEL
SDA1
SCL1
SDA0
SCL0
BIDIRECTIONAL
LEVEL SHIFTER
SDA2
SCL2
H1
V1
H0
V0
_______________________________________________________________________________________
9
Ultra-Low Capacitance 1:2 VGA
Switch with 15ꢀV ESD
Pacꢀage Information
For the latest pacꢀage outline information and land patterns, go to www.mnꢄꢂm-ꢂe.erm/pne5ngts.
ꢁACKAGꢀVTYꢁꢀ
ꢁACKAGꢀVCOSꢀ
SOCUBꢀNTVNO.
2±-0±39
24 TQFN-EP
T2444-4
MAX485E
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
±0 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2ꢁꢁ8 Maxim Integrated Products
is a registered trademarꢀ of Maxim Integrated Products, Inc.
相关型号：
MAX4885ETJ-T
Video Multiplexer, 1 Func, 2 Channel, BICMOS, 5 X 5 MM, 0.80 MM HEIGHT, MO-220WHHD-2, TQFN-32
MAXIM
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