MAX24101ELU+ [MAXIM]
Interface Circuit, BICMOS, FCLGA-60;
| 型号： | MAX24101ELU+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Interface Circuit, BICMOS, FCLGA-60 信息通信管理 接口集成电路 |
| 文件： | 总27页 (文件大小：2068K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MAX24101
15Gbps Octal Linear Equalizer
General Description
Benefits and Features
●ꢀ 1Gbpsꢀtoꢀ15GbpsꢀLinearꢀEQ
The MAX24101 restores high-frequency signal level at
the decision-feedback equalizer (DFE) receiver for high-
loss backplane and cable channels. This permits the DFE
receiver to meet BER goals. At 15Gbps, the MAX24101
can operate in channels with FR4 and cable HF loss more
of than 30dB at 7.5GHz. The linear transfer function is
transparent to Adaptive DFE equalizers, permitting DFE
adaptation to track temperature and changing channel
conditions.
●ꢀ IncreasesꢀHigh-FrequencyꢀSignalꢀLevelꢀToꢀHelpꢀRxꢀ
DFE Achieve BER Goals
●ꢀ LowerꢀPower,ꢀLowerꢀCost,ꢀAndꢀSmallerꢀBoardꢀ
Footprint Than CDR Solutions
●ꢀ Transparent-to-LinkꢀTraining,ꢀOOBꢀAndꢀIdle
●ꢀ PlugꢀandꢀPlay—SetꢀControlꢀPinsꢀ(AllꢀChannelsꢀSetꢀ
theꢀSame)ꢀorꢀIndependentꢀControlꢀofꢀEachꢀChannelꢀ
2
throughꢀI C Bus
Together with the DFE, integrated into Serializer/
Deserializer (SERDES), the device adds increased mar-
gin rather than full signal regeneration. Unlike conven-
tional equalizers with limiting output stages, the device
preserves the linear channel characteristics, allowing
the DFE to linearly operate over the entire channel. This
permits extending total channel reach and/or improving
signal-to-noise ratio (SNR). The device typically compen-
sates for up to 19dB of the total loss in a long channel,
effectively reducing the channel length seen by the DFE
receiver.
2
●ꢀ I CꢀDaisyꢀChainꢀForꢀAddressingꢀUpꢀtoꢀ63ꢀICs
●ꢀ SelectableꢀEQꢀPeakingꢀSpanningꢀ+6dBꢀtoꢀ+19dBꢀatꢀ
7.5GHz
●ꢀ SelectableꢀFlatꢀGainꢀSpanningꢀ-2.9dBꢀtoꢀ+1.7dB
●ꢀ SelectableꢀOutputꢀLinearꢀSwingꢀSpanningꢀ700mV
P-P
toꢀ1000mV
P-P
●ꢀ LowꢀInput-ReferredꢀNoiseꢀ<ꢀ1mV
●ꢀ Data-RateꢀandꢀCodingꢀAgnostic
RMS
●ꢀ InputꢀReturnꢀLossꢀBetterꢀThanꢀ16dBꢀTypicalꢀUpꢀtoꢀ
The device has 8 channels and is packaged in a space-
saving, 4mm x 13mm, FCLGA package.
7.5GHz
●ꢀ Power-DownꢀModeꢀSavesꢀPowerꢀWhenꢀNotꢀInꢀUse
●ꢀ 4mmꢀxꢀ13mmꢀFCLGAꢀPackage
Applications
●ꢀ 1Gbpsꢀtoꢀ15GbpsꢀHigh-SpeedꢀBackplanesꢀandꢀCables
●ꢀ 12.5GbpsꢀQuadꢀXAUIꢀInterconnect
●ꢀ 14Gbpsꢀ16GꢀFiberꢀChannelꢀ
●ꢀ Singleꢀ2.5VꢀSupply
●ꢀ 131mWꢀPerꢀChannelꢀPowerꢀDissipationꢀwithꢀaꢀ
700mV ꢀOutput
●ꢀ 12GbpsꢀSASꢀIII
P-P
Typical Application Circuit
MAX24101
MAX24101
MAX LOSS CHANNEL = 48dB AT 7.5GHz
TX
RX
CMOS
+6dB
Pre-Em
CMOS
DFE AND
SLICER
BOARD
4dB TO 12dB LOSS
AT 7.5GHz
BACKPLANE
6dB TO 24dB LOSS
AT 7.5GHz
BOARD
4dB TO 12dB LOSS
AT 7.5GHz
(INCLUDING CONNECTORS)
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX24101.related.
19-6804; Rev 0; 11/13
MAX24101
15Gbps Octal Linear Equalizer
Absolute Maximum Ratings
Power-SupplyꢀVoltage..........................................-0.5Vꢀtoꢀ+4.0V
DCꢀInputꢀVoltageꢀAppliedꢀ(all control pins except SDA
and SCL) .............................................. -0.5Vꢀtoꢀ(V ꢀ+ꢀ0.3V)
OutputꢀCurrent.................................................. -90mAꢀtoꢀ+90mA
OperatingꢀJunctionꢀTemperature.....................................+125ºC
Storage Temperature Range.............................-40ºCꢀtoꢀ+150°C
CC
DCꢀInputꢀVoltageꢀAppliedꢀ(SDA,ꢀSCL) .................-0.5Vꢀtoꢀ+4.0V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
(Note 1)
Package Thermal Characteristics
FCLGA
Junction-to-CaseꢀThermalꢀResistanceꢀ(q )...............10°C/W
JC
Junction-to-AmbientꢀThermalꢀResistance
(q )ꢀ(EIA/JESD51-2ꢀstandard)...................................29°C/W
JA
Note 1:ꢀ PackageꢀthermalꢀresistancesꢀwereꢀobtainedꢀusingꢀtheꢀmethodꢀdescribedꢀinꢀJEDECꢀspecificationꢀJESD51-7,ꢀusingꢀaꢀfour-layerꢀ
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Operating Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
,
,
CCR
SupplyꢀVoltage
2.312
2.5
2.75
V
CCT
V
CCP
OperatingꢀAmbientꢀ
Temperature
T
-40
1
+25
+85
15
°C
A
Data Rate
Gbps
CID
Source Data Coding and
CID
DC balanced NRZ, 8B10B or
Scrambled;ꢀPRBS31
66
LFꢀBaselineꢀ(withoutꢀꢀPE)ꢀ
measured at source; source HF
pre-emphasis swing can be higher
Differential Source Diff Low-
FrequencyꢀVoltage
V
1200
150
mV
P-P
LAUNCH
Source Rise/Fall Time
Test source 10% to 90%
DC - 200MHz
26
ps
Source Common-Mode
Noise
mV
mV
P-P
Supply Noise
DC - 1MHz
50
P-P
Electrical Characteristics
(TypicalꢀvaluesꢀareꢀatꢀV
ꢀ=ꢀV
ꢀ=ꢀV
ꢀ=ꢀ2.5V,ꢀT ꢀ=ꢀ+25°C.ꢀSeeꢀFigure 1 for typical supply filtering.) (Note 2)
CCR
CCT
CCP A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
I
I
ꢀ+ꢀ
ꢀ+ꢀ
Total supply
current with all 8
channels enabled
TXAx[1:0] = 00
TXAx[1:0] = 11
420
550
CCR
Supply Current
mA
CCT
I
511
4.8
610
CCP
Supply Current During
Power-Down
mA
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MAX24101
15Gbps Octal Linear Equalizer
Electrical Characteristics (continued)
(TypicalꢀvaluesꢀareꢀatꢀV
ꢀ=ꢀV
ꢀ=ꢀV
ꢀ=ꢀ2.5V,ꢀT ꢀ=ꢀ+25°C.ꢀSeeꢀFigure 1 for typical supply filtering.) (Note 2)
CCR
CCT
CCP A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Beyond steady-state supply current
with supply ramp-up time less than
200µs
InrushꢀCurrent
<ꢀ10
%
Over-bitꢀrateꢀwithꢀEQꢀpeakingꢀ
optimized for loss channel, in linear
range
ResidualꢀDeterministicꢀJitterꢀ
(Notes 3, 4)
DJ
9
ps
P-P
RX
EQx[3:0]ꢀ=ꢀ1110
EQx[3:0]ꢀ=ꢀ1001
EQx[3:0]ꢀ=ꢀ0101
18.5
15.7
13.2
PeakingꢀGain
(Compensation at 7.5GHz,
relative to 100MHz,
GN
dB
P
T ꢀ=ꢀ+85°C
-3.67
-1.61
-1.62
+0.82
+1.96
+3.60
A
100mV ꢀSineꢀWaveꢀInput)ꢀ
P-P
Variationꢀaroundꢀ
typical
T ꢀ=ꢀ+25°C
A
T ꢀ=ꢀ-40°C
A
FGx[1:0] = 11
FGx[1:0] = 10
FGx[1:0] = 01
FGx[1:0] = 00
1.68
0.14
-1.36
-2.87
FlatꢀGainꢀ(100MHz,ꢀEQx[3:0]ꢀ
= 1000, TXAx[1:0] = 10)
GN
dB
F
T ꢀ=ꢀ+85°C
-4.05
-3.32
-3.40
1000
+0.95
+1.83
+2.86
A
Variationꢀaroundꢀ
typical
T ꢀ=ꢀ+25°C
A
T ꢀ=ꢀ-40°C
A
TXAx[1:0] = 11
TXAx[1:0] = 10
TXAx[1:0] = 01
TXAx[1:0] = 00
TXAx[1:0] = 11
TXAx[1:0] = 10
TXAx[1:0] = 01
TXAx[1:0] = 00
1370
1280
1040
920
-1dBꢀCompressionꢀPointꢀ
OutputꢀSwingꢀ(atꢀ100MHz)
V
V
mV
1dB_OUT
P-P
1000
940
-1dBꢀCompressionꢀPointꢀ
OutputꢀSwingꢀ(Noteꢀ5)ꢀ(atꢀ
7.5GHz)
mV
1dB_OUT
P-P
700
600
100MHz to 7.5GHz, FGx[1:0] = 11,
EQx[3:0]ꢀ=ꢀ0000,ꢀFigureꢀ3
0.6
0.5
0.8
1.0
Input-ReferredꢀNoise
V
V
mV
mV
NOISE
RMS
100MHz to 7.5GHz, FGx[1:0] = 11,
EQx[3:0]ꢀ=ꢀ1010,ꢀFigureꢀ3
100MHz to 7.5GHz, FGx[1:0] = 11,
EQx[3:0]ꢀ=ꢀ0000,ꢀFigureꢀ3
Output-ReferredꢀNoiseꢀ
(Note 3)
NOISE
RMS
100MHz to 7.5GHz, FGx[1:0] = 11,
EQx[3:0]ꢀ=ꢀ1010,ꢀFigureꢀ3
1.97
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MAX24101
15Gbps Octal Linear Equalizer
Electrical Characteristics (continued)
(TypicalꢀvaluesꢀareꢀatꢀV
ꢀ=ꢀV
ꢀ=ꢀV
ꢀ=ꢀ2.5V,ꢀT ꢀ=ꢀ+25°C.ꢀSeeꢀFigure 1 for typical supply filtering.) (Note 2)
CCR
CCT
CCP A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
HIGH SPEED I/O
InputꢀCommon-ModeꢀVoltage
InputꢀResistance
V
2.05
V
ICM
DC differential resistance
100
50
R
Ω
AC common-mode (single-ended)
resistance
IN
10MHz to 7.5GHz
1GHz to 7.5GHz
Differential
>ꢀ16
> 10
100
InputꢀReturnꢀLoss
OutputꢀResistance
S
dB
11
Common mode
DC differential resistance
R
Ω
AC common mode (single-ended)
resistance
OUT
50
PulseꢀResponseꢀRinging
Intra-PairꢀSkew
3
2
%
ps
ps
Inter-PairꢀSkew
4
10MHz to 7.5GHz
1GHz to 7.5GHz
Differential
> 13
> 8
OutputꢀReturnꢀLoss
S
dB
dB
22
Common Mode
100MHz to 7.5GHz, Figure 4
(Noteꢀ6)
ChannelꢀIsolation
LVCMOS I/O
V
Coup
40
0.7 x
V
ꢀ+ꢀ
CC
0.3
InputꢀLogic-HighꢀVoltage
V
V
V
IH
V
CC
0.3 x
V
InputꢀLogic-LowꢀVoltageꢀ
V
-0.3
IL
CC
V
ꢀ+ꢀ
CC
0.2
OutputꢀLogic-HighꢀVoltage
OutputꢀLogic-LowꢀVoltage
V
AtꢀI
= -200µA
V
V
OH
OH
V
AtꢀI = -200µA
0.2
OL
OL
OpenꢀStateꢀCurrentꢀTolerance
InputꢀLogic-HighꢀCurrent
H
±5
mA
mA
IZ
V
ꢀ<ꢀV ꢀ<ꢀV
, all other
IH(MIN)
IN
IH(MAX)
±450
CMOSꢀpins
I
IH
V
ꢀ<ꢀV ꢀ<ꢀV
, PGM_IN
+120
IH(MIN)
IL(MIN)
IN
IH(MAX)
V
ꢀ<ꢀV ꢀ<ꢀV
, all other
IN
IL(MAX)
-450
-18
CMOSꢀpins
ꢀ<ꢀV ꢀ<ꢀV , PGM_IN
IL(MAX)
InputꢀLogic-LowꢀCurrent
I
mA
IL
V
IL(MIN)
IN
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MAX24101
15Gbps Octal Linear Equalizer
Electrical Characteristics (continued)
(TypicalꢀvaluesꢀareꢀatꢀV
ꢀ=ꢀV
ꢀ=ꢀV
ꢀ=ꢀ2.5V,ꢀT ꢀ=ꢀ+25°C.ꢀSeeꢀFigure 1 for typical supply filtering.) (Note 2)
CCR
CCT
CCP A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
2
I C CHARACTERISTICS (SDA, SCL) (Note 7)
0.3 x
Low-LevelꢀInputꢀVoltage
High-LevelꢀInputꢀVoltage
V
V
V
IL
V
CC
0.7 x
V
IH
V
CC
InputꢀHysteresis
V
200
10
mV
pF
HYS
InputꢀCapacitance
InputꢀLeakageꢀCurrent
C
IN
I
±1
0.4
0.6
400
mA
IN
I
I
= 3mA
SINK
OutputꢀLowꢀVoltageꢀSDA
SCLKꢀClockꢀFrequency
V
V
OL
ꢀ=ꢀ6mA
SINK
f
kHz
SCLK
Note 2: The MAX24101 is 100% production tested at T ꢀ=ꢀ+25°CꢀandꢀT ꢀ=ꢀ+85°C. SpecificationꢀatꢀT = -40°C is guaranteed by
A
A
A
design or characterization, unless otherwise noted.
Note 3: Guaranteed by design and characterization.
Note 4:ꢀ MeasuredꢀwithꢀcircuitꢀboardꢀlossꢀoptimizedꢀforꢀbestꢀDJ.ꢀResidualꢀjitterꢀisꢀtheꢀdifferenceꢀinꢀdeterministicꢀjitterꢀbetweenꢀtheꢀ
referenceꢀdataꢀsourceꢀandꢀdeviceꢀoutput.ꢀDJRESIDUALꢀ=ꢀDJOUTPUTꢀ–ꢀDJSOURCE.ꢀTheꢀdeterministicꢀjitterꢀatꢀtheꢀoutputꢀ
of the transmission line must be from media induced loss. Measured at point D in Figure 2.ꢀTestꢀPatter:ꢀ66ꢀZeroes,ꢀ1010,ꢀ
PRBS7,ꢀ66ꢀones,ꢀ0101ꢀInvertedꢀPRBS7.
Note 5: The output voltage range in which a linear relationship between the input and output maintains less than or equal to 1dB
compression.
Note 6:ꢀ Measuredꢀusingꢀaꢀvector-networkꢀanalyzerꢀ(VNA)ꢀwithꢀ-15dBmꢀpowerꢀlevelꢀappliedꢀtoꢀtheꢀadjacentꢀinput.ꢀTheꢀVNAꢀdetectsꢀ
theꢀsignalꢀatꢀtheꢀoutputꢀofꢀtheꢀvictimꢀchannel.ꢀAllꢀotherꢀinputsꢀandꢀoutputsꢀareꢀterminatedꢀwithꢀ50Ω.
Note 7:ꢀ ReferꢀtoꢀUM10204:ꢀI2C-busꢀspecificationꢀandꢀuserꢀmanual,ꢀRev.ꢀ03ꢀ–ꢀ19ꢀJuneꢀ2007.
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MAX24101
15Gbps Octal Linear Equalizer
1µH
2.5V
V
CC
SUPPLY
100µF
0.1µF
100µF
0.1µF
Figure 1. Recommended Supply Filtering
RECEIVE TEST SETUP
PCB (FRA)
SIGNAL
SOURCE
OSCILLOSCOPE OR
BIT ERROR DETECTOR
A
B
D
MAX24101
6 MIL
RX
TX
6 MIL
SMA
CONNECTORS
SMA
CONNECTORS
2in < L < 30in
L = 2in
FR4
4.0 < ε < 4.4
R
tanδ = 0.022
Figure 2. Receiver Test Setup (Points Labeled A, B, and D are Referenced for AC Parameter Test Conditions)
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MAX24101
15Gbps Octal Linear Equalizer
LOWPASS
FILTER
MAX24101
50Ω
50Ω
RX_+
TX_+
POWER METER
GIGATRONICS 8652A
WITH 80301A HEAD
(10MHz to 18GHz)
BALUN
PSPL 5315A
(200kHz TO 17GHz)
RX_-
TX_-
4TH OBT
Figure 3. Noise Test Configuration
4-PORT VECTOR
NETWORK ANALYZER
N52454
AGGRESSOR
SIGNAL
MAX24101
(0dBm)
50Ω
TX1+
TX1-
TX2+
TX2-
RX1+
RX1-
RX2+
RX2-
50Ω
50Ω
50Ω
VICTIM
OUTPUT
VICTIM
INPUT
Figure 4. Channel-Isolation Test Configuration
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MAX24101
15Gbps Octal Linear Equalizer
Typical Operating Characteristics
(TypicalꢀvaluesꢀareꢀatꢀV
ꢀ=ꢀV
ꢀ=ꢀV
ꢀ=ꢀ2.5V,ꢀT ꢀ=ꢀ+25°C,ꢀunlessꢀotherwiseꢀnoted.)
CCR
CCT
CC_DG A
DETERMINISTIC JITTER
vs. EQUALIZATION SETTING
DETERMINISTIC JITTER
vs. EQUALIZATION SETTING
1dB Compression
(7.5GHz Nyquist)
toc01
toc02
toc03
0.25
0.20
0.15
0.10
0.05
0.00
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0.00
5
0
TXAx[1:0] = 11
TXAx[1:0] = 00
3dB Loss, Linear
Range Operation
16.7dB Loss, Linear
Range Operation
-5
16.7dB Loss, Linear
Range Operation
3dB Loss, Linear
Range Operation
-10
-15
-20
Data Rate = 15Gbps, TXAx[1:0] = 10, FGx[2:0] = 10
EQx[3:0] = 0111, FGx[1:0] = 10
Data Rate = 10.3Gbps, TXAx[1:0] = 10, FGx[1:0] = 10
0000 0010 0100 0110 1000 1010 1100 1110
0000 0010 0100 0110 1000 1010 1100 1110
-30
-25
-20
-15
-10
-5
INPUT AMPLITUDE (dBV)
EQUALIZATION SETTING (EQxx[3:0])
EQUALIZATION SETTING (EQxx[3:0])
1dB COMPRESSION
(100MHz Nyquist)
FREQUENCY RESPONSE
toc04
toc05
10.0
5.0
30
TXAx[1:0] = 11
FGx[1:0] = 111
25
20
15
10
5
FGx[1:0] = 10
FGx[1:0] = 01
0.0
TXAx[1:0] = 00
-5.0
-10.0
-15.0
-20.0
-25.0
FGx[1:0] = 00
0
EQx[3:0] = 0111, FGx[1:0] = 10
TXAx[1:0] = 11, EQx[3:0] = 0000
10
-5
-25
-20
-15
-10
-5
0
5
10
0
2
4
6
8
INPUT AMPLITUDE (dBV)
FREQUENCY (GHz)
FREQUENCY RESPONSE
WITH 18in of FR4
FREQUENCY RESPONSE
toc06
toc07
25
20
15
10
5
5
0
EQxx[3:0] = 1111
EQxx[3:0] = 0111
FR4 with EQx[3:0] = 1110
EQxx[3:0] = 0100
-5
FR4 ONLY
-10
-15
-20
-25
EQxx[3:0] = 0010
0
EQxx[3:0] = 0000
TXAx[1:0] = 11, FGxx[1:0] = 10
10
TXAx[1:0] = 11, FGx[1:0] = 10
-5
0
2
4
6
8
0
2
4
6
8
10
FREQUENCY (GHz)
FREQUENCY (GHz)
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MAX24101
15Gbps Octal Linear Equalizer
Typical Operating Characteristics (continued)
(TypicalꢀvaluesꢀareꢀatꢀV
ꢀ=ꢀV
ꢀ=ꢀV
ꢀ=ꢀ2.5V,ꢀT ꢀ=ꢀ+25°C,ꢀunlessꢀotherwiseꢀnoted.)
CCR
CCT
CC_DG A
MAX24101 SINGLE-ENDED OUTPUT AFTER 18in OF INPUT FR4
(EQx[3:0] = 1110, FGx[1:0] = 01, TXAx[1:0] = 11, 13.5Gbps)
MAX24101 SINGLE-ENDED OUTPUT AFTER 18in FR4 AT INPUT
(EQx[3:0] = 1110, FGx[1:0] = 01, TXAx[1:0] = 11, 10.3Gbps)
toc9
toc8
50mV/div
50mV/div
100mV/div
50mV/div
20ps/div
20ps/div
SINGLE-ENDED OUTPUT FROM BERT SOURCE AFTER 18in FR4
(12Gbps)
SINGLE-ENDED OUTPUT FROM BERT SOURCE
(12Gbps)
toc10
toc11
100mV/div
20ps/div
20ps/div
MAX24101 SINGLE-ENDED OUTPUT AFTER 18in FR4 AT INPUT
(EQx[3:0] = 1110, FGx[1:0] = 01, TXAx[1:0] = 11, 12Gbps)
MAX24101 SINGLE-ENDED TIME DOMAIN OUTPUT VS. EQUALIZATION LEVEL
(FGx[1:0] = 01, TXAx[1:0] = 11, WITH 18in FR4 AT 1Gbps)
toc12
toc13
EQxx[3:0] = 1111
EQxx[3:0] = 0000
62mV/div
20ps/div
100ps/div
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MAX24101
15Gbps Octal Linear Equalizer
Pin Configuration
RX1P
RX1N
VCCR
RX2P
RX2N
VCCR
RX3P
RX3N
VCCR
1
2
3
4
5
6
7
8
9
54 TX1P
53 TX1N
52 VCCT
51 TX2P
50 TX2N
49 VCCT
48 TX3P
47 TX3N
46 VCCT
45 TX4P
44 TX4N
43 VCCT
42 TX5P
41 TX5N
40 VCCT
39 TX6P
38 TX6N
37 VCCT
36 TX7P
35 TX7N
34 VCCT
33 TX8P
32 TX8N
31 VCCT
+
RX4P 10
RX4N 11
VCCR 12
RX5P 13
RX5N 14
VCCR 15
RX6P 16
RX6N 17
VCCR 18
RX7P 19
RX7N 20
VCCR 21
RX8P 22
RX8N 23
VCCR 24
MAX24101
FCLGA
4mm x 13mm
Pin Description
PIN
NAME
FUNCTION
1, 2
RX1P,ꢀRX1N
DifferentialꢀChannelꢀ1ꢀInput,ꢀCML
3,ꢀ6,ꢀ9,ꢀ12,ꢀ15,ꢀ
18, 21, 24
VCCR
PositiveꢀReceiveꢀPowerꢀSupply,ꢀ2.5V.ꢀFilterꢀeachꢀpinꢀwithꢀaꢀ0.1µFꢀcapacitorꢀtoꢀGND.
DifferentialꢀChannelꢀ2ꢀInput,ꢀCML
4, 5
RX2P,ꢀRX2N
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MAX24101
15Gbps Octal Linear Equalizer
Pin Description (continued)
PIN
NAME
FUNCTION
7, 8
RX3P,ꢀRX3N
RX4P,ꢀRX4N
RX5P,ꢀRX5N
RX6P,ꢀRX6N
RX7P,ꢀRX7N
RX8P,ꢀRX8N
DifferentialꢀChannelꢀ3ꢀInput,ꢀCML
DifferentialꢀChannelꢀ4ꢀInput,ꢀCML
DifferentialꢀChannelꢀ5ꢀInput,ꢀCML
DifferentialꢀChannelꢀ6ꢀInput,ꢀCML
DifferentialꢀChannelꢀ7ꢀInput,ꢀCML
DifferentialꢀChannelꢀ8ꢀInput,ꢀCML
10, 11
13, 14
16,ꢀ17
19, 20
22, 23
I2CꢀEnableꢀInput,ꢀLVCMOS.ꢀHardwireꢀlowꢀforꢀpinꢀcontrol.ꢀHardwireꢀhighꢀforꢀI2C control.
User must select mode of operation before power-on reset.
25
I2C_EN
VCCP
26
PositiveꢀPowerꢀSupply,ꢀ2.5V.ꢀFilterꢀeachꢀpinꢀwithꢀaꢀ0.1µFꢀcapacitorꢀtoꢀGND.ꢀ
27
LDO_DIG
CompensationꢀcapacitorꢀpinꢀforꢀinternalꢀLDO.ꢀBypassꢀpinꢀwithꢀaꢀ0.22µFꢀcapacitorꢀtoꢀGND.
2
28
29
30
SCL
SDA
AnalogꢀI CꢀSerial-InterfaceꢀClockꢀInput.ꢀUseꢀexternalꢀ4.7kΩꢀpullupꢀtoꢀV
.
CC
2
AnalogꢀI CꢀSerial-InterfaceꢀDataꢀInputꢀandꢀOutput.ꢀUseꢀexternalꢀ4.7kΩꢀpullupꢀtoꢀV
.
CC
2
PGM_OUT
CascadableꢀI CꢀOutput.ꢀLVCMOS.ꢀSeeꢀtheꢀSlave Address Configuration section.
31, 34, 37, 40,
43,ꢀ46,ꢀ49,ꢀ52
VCCT
PositiveꢀTransmitꢀPowerꢀSupply,ꢀ2.5V.ꢀFilterꢀeachꢀpinꢀwithꢀaꢀ0.1µFꢀcapacitorꢀtoꢀGND.
32, 33
35,ꢀ36
38, 39
41, 42
44, 45
47, 48
50, 51
53, 54
55
TX8N,ꢀTX8P
TX7N,ꢀTX7P
TX6N,ꢀTX6P
TX5N,ꢀTX5P
TX4N,ꢀTX4P
TX3N,ꢀTX3P
TX2N,ꢀTX2P
TX1N,ꢀTX1P
PGM_IN
DifferentialꢀChannelꢀ8ꢀOutput,ꢀCML
DifferentialꢀChannelꢀ7ꢀOutput,ꢀCML
DifferentialꢀChannelꢀ6ꢀOutput,ꢀCML
DifferentialꢀChannelꢀ5ꢀOutput,ꢀCML
DifferentialꢀChannelꢀ4ꢀOutput,ꢀCML
DifferentialꢀChannelꢀ3ꢀOutput,ꢀCML
DifferentialꢀChannelꢀ2ꢀOutput,ꢀCML
DifferentialꢀChannelꢀ1ꢀOutput,ꢀCML
2
2
CascadableꢀI CꢀInput.ꢀHasꢀ30kΩꢀpulldown,ꢀseeꢀthe I C Address Configuration section.
Power-DownꢀEnableꢀPin,ꢀLVCMOS.ꢀThree-stateꢀpinꢀtoꢀprogramꢀtheꢀpowerꢀmodeꢀofꢀtheꢀ
part at startup. For high and open, see Table 5 for settings. Set low for reset. Reset,
disables all communication to the chip along with resetting the registers to their default
states.
56
ENABLE
ApplicationꢀSelectꢀInput,ꢀLVCMOS.ꢀSelectꢀbetweenꢀchannelꢀcases:ꢀShortꢀandꢀLong.ꢀSetꢀ
low or open for long. Set high for short.
57
58
59
60
APPLICATION
OUTPUT_LEVEL
EQ_PEAKING
FLAT_GAIN
OutputꢀLevelꢀControl,ꢀLVCMOS.ꢀThree-stateꢀpinꢀtoꢀprogramꢀtheꢀoutputꢀlevelꢀofꢀallꢀ
channels. See Table 4 for settings.
EqualizationꢀControlꢀPin,ꢀLVCMOS.ꢀThree-stateꢀpinꢀtoꢀprogramꢀtheꢀequalizationꢀlevelꢀofꢀ
all channels. See Table 2 for settings.
GainꢀAdjustꢀControlꢀPin,ꢀLVCMOS.ꢀThree-stateꢀpinꢀtoꢀprogramꢀtheꢀflatꢀgainꢀlevelꢀofꢀallꢀ
channels. See Table 3 for settings.
ExposedꢀPad.ꢀInternallyꢀconnectedꢀtoꢀGND.ꢀGroundꢀreferenceꢀforꢀpowerꢀsupplies,ꢀthree-
state,ꢀandꢀotherꢀlow-speedꢀpins.ꢀConnectꢀEPꢀtoꢀaꢀlargeꢀgroundꢀplaneꢀtoꢀmaximizeꢀthermalꢀ
performance.
—
EP
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MAX24101
15Gbps Octal Linear Equalizer
Functional Diagram
8 CHANNELS
EQUALIZER
FLAT GAIN
OUTPUT BUFFER
TX1P
50Ω
50Ω
RX1P
RX1N
TX1N
LANE 1 OF 8
EQ_PEAKING
FLAT GAIN
OUTPUT LEVEL
CONTROL
Input Termination
Detailed Description
Theꢀinputꢀterminationꢀconsistsꢀofꢀtwoꢀ50Ωꢀresistorsꢀform-
ing a differential termination between the input pins. The
excellent return loss minimizes reflections in a channel.
Theꢀ MAX24101ꢀ isꢀ anꢀ 8-channelꢀ linearꢀ equalizerꢀ (EQ)ꢀ
functioning up to 15Gbps. Each channel has a program-
mable equalization network and programmable flat gain
adjust.ꢀAllꢀcontrolsꢀforꢀequalization,ꢀgain,ꢀoutputꢀenable/
disable, etc., are individually programmed through the on-
chip programming block. The programming block can be
Table 1. APPLICATION Pin Control
2
controlledꢀeitherꢀthroughꢀpinꢀcontrolsꢀorꢀtheꢀI C serial bus.
INPUT LEVEL
CHANNEL LENGTH
APPLICATION Pin Control
Short Channel. 0dB to 18dB channel loss
before MAX24101.
High
The placement range of a linear equalizer is limited by
its dynamic range and noise performance. To allow the
widest placement range, the MAX24101 has two optimi-
zations. The two cases are Short and Long Channels.
By selecting the case based on channel loss as shown
in Table 1, the best dynamic range and noise operating
points are selected for the application.
Long Channel. 18dB to 33dB channel loss
before MAX24101.
Low,ꢀOpen
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MAX24101
15Gbps Octal Linear Equalizer
2
I Cꢀcontrol,ꢀtheꢀflatꢀgainꢀcanꢀbeꢀadjustedꢀindependentlyꢀ
Receive Equalizer
for each channel.
For the MAX24101, the input data goes into a selectable
equalization stage. The receive equalizer is designed to
compensate losses up to 19dB (at 7.5GHz) of channel
loss. The selectable equalization can be controlled using
commandsꢀ sentꢀ overꢀ theꢀ I C serial bus or pin control.
Withꢀpinꢀcontrolꢀtheꢀequalizationꢀsettingꢀhasꢀthreeꢀavail-
Output Stage
The MAX24101 data path transitions from the gain stages
into a linear output buffer with selectable output level.
Withꢀpinꢀcontrolꢀtheꢀoutputꢀlevelsꢀcanꢀbeꢀadjustedꢀgloballyꢀ
as shown in Table 4.ꢀWithꢀI C control, the output levels
canꢀbeꢀadjustedꢀindependentlyꢀforꢀeachꢀchannel.ꢀ
2
2
able compensation levels and all the channels are con-
2
trolled globally. See Table 2ꢀforꢀdetails.ꢀWithꢀtheꢀI C serial
bus,ꢀtheꢀequalizationꢀhasꢀ16ꢀsettingsꢀandꢀeachꢀchannelꢀ
canꢀbeꢀadjustedꢀindependently.
Power Saving
The MAX24101 features a power-down enable input
(ENABLE) pin to shut down the device and reduce sup-
ply current at startup. Set high to power down the output
stage of all channels. Set open to power up all channels.
Set low for reset. Reset disables all communication to
the chip along with resetting the registers to their default
states.
Gain Stage
The MAX24101 data path goes through a wideband flat
gainꢀstage.ꢀWithꢀpinꢀcontrolꢀtheꢀflatꢀgainꢀcanꢀbeꢀadjustedꢀ
globallyꢀfromꢀ-2.9dBꢀtoꢀ+1.7dBꢀasꢀshownꢀinꢀTable 3.ꢀWithꢀ
Table 2. EQ_PEAKING Pin Control
LONG CHANNEL
INPUT LEVEL
MEDIUM CHANNEL
(APPLICATION = OPEN)
SHORT CHANNEL
UNITS
(APPLICATION = LOW, OPEN)
+15ꢀ(EQx[3:0]ꢀ=ꢀ1110)
(APPLICATION = HIGH)
High
Open
Low
+15ꢀ(EQx[3:0]ꢀ=ꢀ1110)
+12ꢀ(EQx[3:0]ꢀ=ꢀ1001)
+9ꢀ(EQx[3:0]ꢀ=ꢀ0101)
+12ꢀ(EQx[3:0]ꢀ=ꢀ1001)
+9ꢀ(EQx[3:0]ꢀ=ꢀ0101)
+6ꢀ(EQx[3:0]ꢀ=ꢀ0011)
+12ꢀ(EQx[3:0]ꢀ=ꢀ1001)
+9ꢀ(EQx[3:0]ꢀ=ꢀ0101)
dB
Table 3. FLAT_GAIN Pin Control
LONG CHANNEL
INPUT LEVEL
MEDIUM CHANNEL
SHORT CHANNEL
UNITS
(APPLICATION = LOW, OPEN)
(APPLICATION = OPEN)
(APPLICATION = HIGH)
High
Open
Low
1.7 (FGx[1:0] = 11)
0.1 (FGx[1:0] = 10)
-1.4 (FGx[1:0] = 01)
1.7 (FGx[1:0] = 11)
0.1 (FGx[1:0] = 10)
-1.4 (FGx[1:0] = 01)
0.1 (FGx[1:0] = 10)
-1.4 (FGx[1:0] = 01)
-2.9 (FGx[1:0] = 00)
dB
Table 4. OUTPUT_LEVEL Pin Control
INPUT LEVEL
OUTPUT AMPLITUDE
UNITS
High
Open
Low
1000 (TXAx[1:0] = 11]
940 (TXAx[1:0] = 10]
700 (TXAx[1:0] = 01]
mV
P-P
Table 5. ENABLE and Reset Pin Control
INPUT LEVEL
(ENABLE)
I2C CONTROL MODE
(I2C_EN = high)
PIN CONTROL MODE
(I2C_EN = low)
Powerꢀdownꢀallꢀchannels
Powerꢀonꢀallꢀchannels
Resetꢀ(POR)
High
Open
Low
UponꢀPORꢀorꢀreset,ꢀpowerꢀdownꢀallꢀchannels
UponꢀPORꢀorꢀreset,ꢀpowerꢀonꢀallꢀchannels
Resetꢀ(POR)
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MAX24101
15Gbps Octal Linear Equalizer
Definitions
dBVꢀ isꢀ definedꢀ asꢀ dBꢀ relativeꢀ toꢀ 1V
Applications Information
(differential).
P-P
Linear Equalizer (EQ) Placement and Use, in 3
Steps
Placementꢀ ofꢀ linearꢀ equalizersꢀ inꢀ lossyꢀ channelsꢀ isꢀ
boundedꢀ byꢀ outputꢀ linearityꢀ andꢀ inputꢀ noiseꢀ (I ). See
Figure 5. Although placement is quite flexible, it is
important to maintain linear operation with sufficient SNR,
hence the boundary conditions stated in the following two
sections.
Hence,ꢀtheꢀTxꢀlevelꢀofꢀ1V ꢀisꢀ0dBV,ꢀandꢀaꢀTxꢀlevelꢀofꢀ
P-P
0.5V ꢀisꢀ-6dBV.
P-P
Source Tx Level [dBV]ꢀisꢀtheꢀtotalꢀmeasuredꢀTxꢀV
including pre-emphasis.
,
P-P
RN
Desired Margin is a user decision regarding margin
needed to account for all system min/max variations,
includingꢀsourceꢀTx,ꢀMAX24101,ꢀandꢀASICꢀreceiver.ꢀ
Tx1V
P-P
W/6dB PE
POSITION 1
POSITION 2
2.0V
dBV
0
1.0V
0.5V
LINEAR EQ OUTPUT REFERRED -1dB COMPRESSION LEVEL [V
]
P-P
H
F
-5
-10
-15
-20
-25
-30
-35
-40
-45
-50
L
O
S
LF
(LONG CID)
S
S
L
O
P
E (
N
Y
Q
U
I
S
T
7.5
G
H
z
S
q
0.2V
DESIGN
MARGIN
W
A
V
E)
TOTAL GAIN
AT NYQUIST
100mV
50mV
DFE IRN
AT BER
1E-15
ASIC DFE IR-NOISE AT BER 1E-15 [V
]
P-P
-24dB
20mV
10mV
5mV
LINEAR EQ OR-NOISE AT BER 1E-15 [V
]
P-P
LINEAR EQ IR-NOISE AT BER 1E-15 [V
]
P-P
2mV
0
4
8
12
16
20
24
28
32
36
CHANNEL LOSS [dB]
PLACEMENT RANGE
IN LOSSY CHANNEL
TX
RX
CMOS
1V
6dbPE
CMOS
DFE AND
SLICER
PPD
1
2
Figure 5. Linear Equalizer Placement
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MAX24101
15Gbps Octal Linear Equalizer
Minimum Distance (Nyquist Loss) from Source Tx [dB] =
Step 1—Maintain EQ Linearity at Low Frequency
(LF)
ꢀ
ꢀ
ꢀ
ꢀ
SourceꢀTxꢀLevelꢀ[dBV]ꢀ+
The source Tx low frequency (LF) amplitude needs to be
consideredꢀtoꢀkeepꢀlinearꢀEQꢀwithinꢀitsꢀlinearꢀrange.ꢀTheꢀ
source Tx low-frequency (LF) amplitude is the differential
peak-peak amplitude after any pre-emphasis has fully set-
tled,ꢀe.g.,ꢀtheꢀlevelꢀofꢀlongꢀCIDꢀ(continuousꢀidenticalꢀdigits)ꢀ
sequences. The primary controls over LF levels in Linear
EQꢀareꢀtheꢀꢀUsedꢀASICꢀSourceꢀTxꢀpre-emphasisꢀ(orꢀde-
emphasis)ꢀandꢀtheꢀLinearꢀEQꢀFlatꢀGainꢀ(MAX24101).
LinearꢀEQꢀPeakingꢀGainꢀ[dB]ꢀ+
LinearꢀEQꢀFlatꢀGainꢀ[dB]ꢀ–
Linearꢀ EQꢀ Outputꢀ Levelꢀ settingꢀ (-1dBꢀ Compressionꢀ
level)ꢀ[dBV]ꢀ+
User System Margin [dB]
For example:
ꢀ
ꢀ
ꢀ
ꢀ
SourceꢀTxꢀLevelꢀ=ꢀ0dBV
Figure 5ꢀshowsꢀaꢀtypicalꢀexampleꢀwithꢀASICꢀSourceꢀTxꢀ
LinearꢀEQꢀPeakingꢀGainꢀ=ꢀ14dB
LinearꢀEQꢀFlatꢀGainꢀ=ꢀ0dB
havingꢀ 6dBꢀ pre-emphasis,ꢀ withꢀ 1V
peak swing and
P-P
0.5V
swingꢀ afterꢀ pre-emphasisꢀ (e.g.,ꢀ longꢀ CIDꢀ LFꢀ
P-Pꢀ
content).ꢀ Noteꢀ thatꢀ 0.5V
fits easily under the -1dB
P-P
Linearꢀ EQꢀ Outputꢀ Levelꢀ settingꢀ (-1dBꢀ Compressionꢀ
Point)ꢀ=ꢀ-3dBVꢀ
Compressionꢀline.ꢀIfꢀtheꢀSourceꢀTxꢀwereꢀtoꢀhaveꢀhigherꢀ
LFꢀ swing,ꢀ drivingꢀ linearꢀ EQꢀ intoꢀ nonlinearity,ꢀ theꢀ linearꢀ
EQꢀflat-gainꢀcontrolꢀcanꢀbeꢀusedꢀtoꢀattenuateꢀinputꢀsignalꢀ
level, as needed, to maintain linearity.
User System Margin = 2dB
Then:
Minimum Distance (Nyquist Loss) from Source Tx = 0
For example:
+ꢀ14ꢀ+ꢀ0ꢀ-ꢀ(-3)ꢀ+ꢀ2ꢀ=ꢀ19dB
MaximumꢀLinearꢀEQꢀFlatꢀGainꢀsettingꢀ=ꢀ
ꢀ
Linearꢀ EQꢀ Outputꢀ Levelꢀ settingꢀ (-1dBꢀ compression)ꢀ
[dBV]ꢀ-
Step 3—Keep Nyquist Level Sufficiently Above
Noise Floor
The amplitude of the Nyquist sequence (10101010…)
must be maintained sufficiently above noise floor to
achieve BER goals. Hence, Nyquist level at input to
theꢀLinearꢀEQꢀneedsꢀtoꢀbeꢀsufficientlyꢀaboveꢀtheꢀLinearꢀ
EQꢀ self-noise,ꢀ IRNꢀ (inputꢀ referredꢀ noise).ꢀ Thisꢀ setsꢀ theꢀ
maximumꢀNyquistꢀchannelꢀlossꢀprecedingꢀtheꢀLinearꢀEQ,ꢀ
e.g, farthest placement from Source Tx (see Position 2
in Figure 5).
ꢀ
ꢀ
SourceꢀTxꢀLevelꢀ[dBV]ꢀ+
SourceꢀTxꢀPre-Emphasisꢀ(De-emphasis)ꢀ[dB]ꢀ-
User System Margin [dB]
For example:
ꢀ
Linearꢀ EQꢀ Outputꢀ Levelꢀ settingꢀ (-1dBꢀ compression)ꢀ
[dBV]ꢀ=ꢀ-3dBV
ꢀ
ꢀ
SourceꢀTxꢀLevelꢀ[dBV]ꢀ=ꢀ0dB
Maximum Distance (Nyquist Loss) from Source Tx [dB] =
SourceꢀTxꢀPre-Emphasisꢀ(De-emphasis)ꢀ[dB]ꢀ=ꢀ6dB
User System Margin = 2dB
ꢀ
ꢀ
ꢀ
SourceꢀTxꢀLevelꢀ(whichꢀisꢀNyquistꢀlevel)ꢀ[dBV]ꢀ–
LinearꢀEQꢀIRNppꢀatꢀBERꢀgoalꢀ[dBV]ꢀ–ꢀ
MarginꢀrequiredꢀtoꢀreduceꢀRJꢀcreationꢀ–
User System Margin [dB]
Then:
MaximumꢀLinearꢀEQꢀFlatꢀGainꢀsettingꢀ=ꢀ(-3)ꢀ-ꢀ0ꢀ+ꢀ6ꢀ-ꢀ2ꢀ
= 1dB
ꢀ
For example:
(There are three Flat Gain settings available lower than
ꢀ
ꢀ
SourceꢀTxꢀLevelꢀ=ꢀ0dBV
+1dB:ꢀꢀTheyꢀareꢀ-3dB,ꢀ-1.5dB,ꢀ0dB)
Linearꢀ EQꢀ IRNppꢀ atꢀ BERꢀ goalꢀ (0.5mVrmsꢀ xꢀ 15.9ꢀ atꢀ
BERꢀ1E-15)ꢀ[dBV]ꢀ=ꢀ-43dB
Step 2—Maintain EQ Linearity at High Frequency
(Nyquist)
ꢀ
MarginꢀrequiredꢀtoꢀreduceꢀRJꢀcreationꢀ(toꢀ0.2UIppꢀatꢀ
BER) = 10dB
A linear equalizer when placed too close to a Source Tx
is vulnerable to nonlinear compression at high frequency
(Nyquist),ꢀ especiallyꢀ ifꢀ theꢀ EQꢀ peakingꢀ gainꢀ isꢀ higherꢀ
than the preceding channel loss. The -1dB compression
specification gives maximum output level that guarantees
linearꢀoperation.ꢀAsꢀaꢀfunctionꢀofꢀtheꢀEQꢀsettings,ꢀtheꢀmini-
mum placement distance from the Source Tx is calculated
as follows: (see Position 1 in Figure 5).
User System Margin = 3dB
Then:
Maximum Distance (Nyquist Loss) from Source Tx =
0 - (-43) - 10 - 3 = 30dB
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MAX24101
15Gbps Octal Linear Equalizer
of SCL. Data is arranged in packets of 9 bits. The first 8
bits represent data to be transferred (most significant bit
(MSB) first). The last bit is an acknowledge bit from the
slave. The recipient of the data holds SDA low during the
ninthꢀclockꢀcycleꢀofꢀaꢀdataꢀpacketꢀtoꢀacknowledgeꢀ(ACK)ꢀ
the byte. Leaving SDA left open on the ninth bit signals
aꢀnot-acknowledgedꢀ(NACK)ꢀcondition.ꢀTheꢀinterpretationꢀ
of the acknowledge bit by the sender depends on the type
of transaction and the nature of the byte being received.
SDA is bidirectional so that the master may send data
bytes during write transactions and the slave may send
data bytes during reads.
Tools—Frequency Response Plotting and EQ
Placement in Channel Calculator
Several simple Microsoft Excel spreadsheet tools are
available to assist in the application of the MAX24101
LinearꢀEQs.ꢀPleaseꢀvisitꢀwww.maximintegrated.com to
access the latest version of these spreadsheets:
®
2
I C Interface
2
TheꢀSDAꢀandꢀSCLꢀpinsꢀareꢀreferredꢀtoꢀasꢀtheꢀslaveꢀI C.
2
TheꢀslaveꢀI C provides external access to the register set
within the MAX24101. Typically, an MCU is connected to
2
theꢀslaveꢀI C.
Framing and Data Transfer
Device Addressing
An individual transaction is framed by a START condition
andꢀaꢀSTOPꢀcondition.ꢀAꢀSTARTꢀconditionꢀoccursꢀwhenꢀ
aꢀbusꢀmasterꢀpullsꢀSDAꢀlowꢀwhileꢀSCLꢀisꢀhigh.ꢀAꢀSTOPꢀ
condition occurs when the bus master allows SDA to tran-
sitionꢀlow-to-highꢀwhenꢀSCLꢀisꢀhigh.ꢀWithinꢀtheꢀframeꢀtheꢀ
master has exclusive control of the bus. The MAX24101
supports Repeated START conditions whereby the mas-
ter may simultaneously end one frame and start another
withoutꢀreleasingꢀtheꢀbusꢀbyꢀreplacingꢀtheꢀSTOPꢀconditionꢀ
with a START condition.
The first byte to be sent after a START condition is a slave
address byte. The first seven bits of the byte contain the
target slave address (MSB first). The eighth bit indicates
theꢀtransactionꢀtypeꢀ–ꢀ‘0’ꢀ=ꢀwrite,ꢀ‘1’ꢀ=ꢀread.ꢀEachꢀslaveꢀ
interfaceꢀonꢀtheꢀbusꢀisꢀassignedꢀaꢀ7-bitꢀslaveꢀaddress.ꢀIfꢀ
no slave matches the address broadcast by the master
then SDA will be left open during the acknowledge bit
andꢀtheꢀmasterꢀreceivesꢀaꢀNACK.ꢀTheꢀmasterꢀmustꢀthenꢀ
assertꢀaꢀSTOPꢀcondition.ꢀIfꢀaꢀslaveꢀidentifiesꢀtheꢀaddressꢀ
then it acknowledges it by pulling SDA low. The master
then proceeds with the transaction identified by the type
bit. The two-wire interface of the MAX24101 decodes
slave addresses ranging from 00h to 3Fh.
WithinꢀaꢀframeꢀtheꢀstateꢀofꢀSDAꢀonlyꢀchangesꢀwhenꢀSCLꢀ
is low. A data bit is transferred on a low-to-high transition
Flatgain (vgc)
VOUT (txa)
Peak Gain (eq)
MAX24101FREQUENCY RESPONSE
UPDATE
20
15
10
5
MAX24101
TXA2 VGC3 EQ15
TXA2 VGC2 EQ7
TXA1 VGC1 EQ3
TXA0 VGC0 EQ0
0
-5
-10
0
2E+09
4E+09
6E+09
8E+09
1E+10
Frequency (Hz)
Figure 6. Frequency Response Plotting
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MAX24101
15Gbps Octal Linear Equalizer
MAX24101 10.3Gbps Linear EQ: Calculate Placement Range in Channel
ASIC TX
LINEAR EQ
ASIC RX
Entry Box in Yellow: Entry Box
Pull Down Box in Pink: Pull Down
Entry Box in Yellow: Entry Box
ASIC TX SETTINGS
LINEAR EQ SETTINGS
ASIC RX SETTINGS
T = Tx HF Level [mVpp]
[dBVpp]
1000
0.00
P = Peaking Gain (HF reLF) [dB]
F = Flat Gain (LF) [dB]
15
0
N = Input Ref Noise [dBVrms]
[Vpp]
[dBVpp]
0.5
7.9
-42.0
D = Tx De-Emphasis [dB]
3.0
Input Ref
0.50 n = Refer'd Noise [mVrms]
Mult Output Ref
2
1.00
15.8
-36.0
800
M = Margin [dB]:
12.0
STEP 1: Make sure that L (Tx LF Level)
7.9 [mVpp]
-42.0 [dBVpp]
800 CL = LF -1dB Compress [mVpp]
Nyquist (010101) [Vpp] above N [Vpp@BER]
(recommend > 16dB for RJ < 0.10UIpp)
(recommend > 12dB for RJ < 0.16UIpp)
is less than EQ LF compression level:
L = Tx LF Level [mVpp]
[dBVpp]
708
-3.00
<
-1.94 [dBVpp]
142 CH = HF -1dB Compress [mVpp]
-1.94
800
-1.94
BER Target = 1E-xx, where xx=
Vpp/Vrms Multiplier =
(for BER in 1E-12 to 1E-17 range)
15
15.85
-16.9
[dBVpp]
12.0 m = Margin [dB]: Nyquist above n [dBVpp@BER]
(recommend > 16dB for RJ < 0.10UIpp)
(recommend > 12dB for RJ < 0.16UIpp)
RESULTS:
EQ PLACEMENT [Loss@Nyquist]
A = Nearest to Tx [dB] >
Over PVT >
T - CH (Input Ref)
B = Farthest from Tx [dB] <
C = Longest Channel [dB] <
16.94
18.94
30.02 dB
28.02 dB
45.02 dB
43.02 dB
Over PVT <
Over PVT <
=
=
T
-
n (Input Ref)
-
m
=
=
T + F + P - N - M
= Keeps Nyquist(010101)
level below EQ HF
compression level.
= Keeps Nyquist (010101) level above
above EQ IRN (input referred noise)
to meet BER and constrain RJ gen.
Keeps Nyquist (010101) level sufficiently
above DFE IRN (input referred noise)
to meet BER and constrain RJ generation
A = Farthest from Rx [dB] <
B = Nearest to Rx [dB] >
28.08
26.08
6.02 dB
8.02 dB
Over PVT <
Over PVT >
=
=
CH (Output Ref) - N - M
Keeps Nyquist above
DFE IRN to meet BER
and constrain RJ gen.
= n (output)
=
- N
Keeps EQ ORN (output ref noise)
below DFE IRN (input ref noise),
including channel loss on noise.
If using "Typical" specs, add
Margin for PVT Variation +/-
2 dB
Figure 7. EQ Placement Calculator
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MAX24101
15Gbps Octal Linear Equalizer
Write Transaction
Read Transaction
Inꢀ aꢀ writeꢀ transaction,ꢀ theꢀ addressꢀ byteꢀ isꢀ successfullyꢀ
acknowledged by the slave, and the type bit is set low.
After the first acknowledge, the master sends a single
data byte. All signaling is controlled by the master except
for the SDA line during the acknowledge bits. During
the acknowledge cycle the direction of the SDA line is
reversedꢀandꢀtheꢀslaveꢀpullsꢀSDAꢀlowꢀtoꢀreturnꢀaꢀ‘0’ꢀ(ACK)ꢀ
to the master.
Inꢀaꢀreadꢀtransaction,ꢀtheꢀslaveꢀaddressꢀbyteꢀisꢀsuccess-
fully acknowledged by the slave, and the type bit is set
high.ꢀAfterꢀtheꢀACKꢀtheꢀslaveꢀreturnsꢀaꢀbyteꢀfromꢀtheꢀloca-
tion identified by the internal memory pointer. This pointer
is then auto-incremented. The slave then releases SDA
soꢀthatꢀtheꢀmasterꢀcanꢀACKꢀtheꢀbyte.ꢀIfꢀtheꢀslaveꢀreceivesꢀ
anꢀACKꢀthenꢀitꢀwillꢀsendꢀanotherꢀbyte.ꢀTheꢀmasterꢀidenti-
fiesꢀtheꢀlastꢀbyteꢀbyꢀsendingꢀaꢀNACKꢀtoꢀtheꢀslave.ꢀTheꢀ
masterꢀthenꢀissuesꢀaꢀSTOPꢀtoꢀterminateꢀtheꢀtransaction.
The MAX24101 interprets the first data byte as a register
address. This is used to set an internal memory pointer.
Subsequent data bytes within the same transaction will
then be written to the memory location addressed by the
pointer. The pointer is auto-incremented after each byte.
There is no limit to the number of bytes which may be
written in a single burst to the internal registers of the
MAX24101.
Thus, to implement a random access read transaction,
a write must first be issued by the master containing a
slave address byte and a single data byte (the register
address). This sets up the memory pointer. A read is then
sent to retrieve data from this address.
STOP
START
ADDRESS
R/W ACK
MSB
7
LSB
0
SDA
6
5
4
3
2
1
SCL
Figure 8. Device Addressing
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MAX24101
15Gbps Octal Linear Equalizer
2
2
ThereꢀisꢀlittleꢀdifferenceꢀbetweenꢀaꢀnormalꢀI C serial bus
I C Access Destination
and the MAX24101 solution except that there is a new
signal which controls the programming of the device
addresses. This signal is daisy-chained through all of the
The MAX24101 does not provide any security level on the
I C serial bus. Accesses to unimplemented registers in
the device are discarded in the case of a write, and return
an unpredictable value in the case of a read. During burst
mode accesses, destination addresses are tested on a
byte-by-byte basis.
2
2
devicesꢀonꢀtheꢀI C bus via the PGM_IN and the PGM_
OUT pins. The programming of device addresses is done
as a single parallel write to all devices 1 to N.
2
TheꢀI C bus is the usual “SCL” and bidirectional “SDA”
Slave Address Configuration
with the pullup. The “program_reset” signal is a single bit
passed through each device as a flying enable. The input
pin for this signal is PGM_IN and the corresponding output
pin is PGM_OUT. The PGM_IN pin on the first MAX24101
in the chain can be tied low or left unconnected because
the PGM_IN pin has an internal pulldown resistor.
2
Theꢀ slaveꢀ addressꢀ ofꢀ theꢀ MAX24101ꢀ I C can be set
using an initialization procedure involving PGM_IN and
2
PGM_OUT,ꢀinꢀconjunctionꢀwithꢀtheꢀstandardꢀI C signals.
This procedure facilitates the assignment of a large num-
ber of slave addresses, enabling several MAX24101s to
2
beꢀcontrolledꢀbyꢀaꢀsingleꢀI C serial bus and commands.
2
AllꢀtransactionsꢀonꢀtheꢀI C bus follow standard protocol,
allowing simple firmware development.
ACK
ACK
STOP
START
MSB
7
LSB
0
SDA
7
6
5
4
3
2
1
1
W
SCL
SDA
DIRECTION
TO SLAVE
FROM SLAVE
Figure 9. Write Transaction
ACK
START
ACK
NACK
STOP
SDA
7
1
R
7
0
7
0
SCL
SDA
DIRECTION
TO SLAVE
TO SLAVE
FROM SLAVE
TO SLAVE
FROM SLAVE
Figure 10. Read Transaction
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MAX24101
15Gbps Octal Linear Equalizer
2
address”+’0’)ꢀisꢀthenꢀassignedꢀbyꢀwritingꢀtoꢀpgm_registerꢀ
(3Ch)ꢀ atꢀ I C address A2h. All devices accept the new
address value (for example: 10h). Each device then starts
to increment it on SCL edges while PGM_IN is high. The
“program_reset” signal ripples down the chain, fixing the
I C Address Configuration
2
The new features of this interface compared to a conven-
tionalꢀI C interface are:
2
●ꢀ TheꢀdaisyꢀchainꢀPGM_IN and PGM_OUT pins
2
2
●ꢀ Aꢀdevice_addressꢀ registerꢀ(7ꢀbits[7:1]ꢀ).ꢀBit[0]ꢀinꢀthisꢀ
I Cꢀ addressꢀ suchꢀ thatꢀ deviceꢀ Nꢀ hasꢀ anꢀ I C address of
(“address”+’0’)+2*N-1ꢀ(forꢀexample:ꢀdeviceꢀ1ꢀatꢀ(10hꢀandꢀ
12h),ꢀdeviceꢀ2ꢀatꢀ(14hꢀandꢀ16h)ꢀandꢀdeviceꢀ3ꢀatꢀ(18hꢀandꢀ
2
registerꢀisꢀusedꢀasꢀaꢀI C read/write bit
●ꢀ Anꢀinternalꢀ“write_once”ꢀbit
2
1Ah)).ꢀNoteꢀthatꢀeachꢀMAX24101ꢀtakesꢀtwoꢀI C address-
Atꢀ power-up,ꢀ theꢀ “write_once”ꢀ bitꢀ willꢀ beꢀ setꢀ toꢀ ‘1’ꢀ andꢀ
theꢀ deviceꢀ I C address will be set to its default value
(A2h). All MAX24101 devices will respond to read and
writes to this slave address until a write to register 3Ch is
performed.ꢀTheꢀrequiredꢀI C address of device 1 (“7 bit
es with channels 1 to 4 being controlled by the lower
address and channels 5 to 8 from the upper address.
2
2
SDA
HOST MCU
SCL
MAX24101
#1
MAX24101
#2
MAX24101
#(N-1)
MAX24101
#N
PGM_IN
PGM_OUT
PGM_IN
PGM_OUT
PGM_IN
PGM_OUT
PGM_IN
PGM_OUT
Figure 11. Slave Address Configuration
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MAX24101
15Gbps Octal Linear Equalizer
Startup Sequence
Programming Tables
Inꢀthisꢀexample,ꢀaꢀchainꢀofꢀMAX24101sꢀareꢀloadedꢀwithꢀ
theꢀrequiredꢀI C slave address.
Table 6. EQ_PEAKING Bit Control
2
1)ꢀ Powerꢀupꢀtheꢀdevices.
EQx[3:0]
1111
EQ PEAKING GAIN
UNITS
2
19.0
18.5
18.0
17.5
17.0
16.4
15.8
15.1
14.4
13.6
12.7
11.7
10.6
9.3
2)ꢀ WriteꢀI Cꢀsequenceꢀ<ꢀ“A2h”ꢀackꢀ“3Ch”ꢀackꢀ“address”ꢀ
1110
1101
1100
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
andꢀ‘0’ꢀack>.ꢀ
3) The first device is now accessible at its given
addressꢀ(“address”ꢀandꢀ‘0’ꢀforꢀtheꢀlowerꢀchannelsꢀandꢀ
“address+1”ꢀandꢀ‘0’ꢀforꢀtheꢀupperꢀchannels).
4) By accessing the first device, the SCL pin is tog-
gled and hence the “program_reset” signal is propa-
gated through the devices using the PGM_IN and
PGM_OUT pins. For long chains, a number of access-
es may be needed before all devices have an assigned
address since each access results in 27 SCL transi-
tions and hence 13 devices are allocated an address
dB
To reset the slave address requires a power cycle or
setting the ENABLE pin low.
7.8
6.0
Table 7. FLAT_GAIN Bit Control
FGx[1:0]
FLAT GAIN
1.68
UNITS
11
10
01
00
0.14
dB
-1.36
-2.87
Table 8. OUTPUT_LEVEL Bit Control
TXAx[1:0]
OUTPUT LEVEL
UNITS
11
10
01
00
1000
940
700
600
mV
P-P
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MAX24101
15Gbps Octal Linear Equalizer
Register Map
Table 9. Register Configuration
2
2
ADDRESS
00h
LOWER I C ADDRESS
Reserved (read only)
Channel 1
UPPER I C ADDRESS
Reserved (read only)
Channel 5
01h
02h
Channel 2
Channelꢀ6
03h
Channel 3
Channel 7
04h
Channel 4
Channel 8
05h
Channelꢀ1–4ꢀControls
Reserved
Channelꢀ5–8ꢀControls
Reserved
06h
07h
Reserved
Reserved
08h
Reserved
Reserved
2
2
3Ch
I C address
I C address
2
The register map is split into two sections depending on the I C address used. In general the lower address
2
controls the lower four channels and the upper I C address controls the upper four channels.
2
Register 01h (Lower I C Address): Channel 1
BIT
NAME
7
6
5
4
3
2
1
0
EQ1[3]
EQ1[2]
EQ1[1]
EQ1[0]
FG1[1]
FG1[0]
TXA1[1]
TXA1[0]
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
EQ1[3:0]:ꢀSetsꢀtheꢀequalizerꢀpeakingꢀforꢀchannelꢀ1.ꢀSeeꢀTableꢀ6ꢀforꢀvalues.
FG1[1:0]:ꢀSetsꢀtheꢀflatꢀgainꢀforꢀchannelꢀ1.ꢀSeeꢀTableꢀ7ꢀforꢀvalues.
TXA1[1:0]: Sets the output amplitude for channel 1. See Table 8 for values.
2
Register 02h (Lower I C Address): Channel 2
BIT
NAME
7
6
5
4
3
2
1
0
EQ2[3]
EQ2[2]
EQ2[1]
EQ2[0]
FG2[1]
FG2[0]
TXA2[1]
TXA2[0]
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
EQ2[3:0]:ꢀSetsꢀtheꢀequalizerꢀpeakingꢀforꢀchannelꢀ2.ꢀSeeꢀTableꢀ6ꢀforꢀvalues.
FG2[1:0]:ꢀSetsꢀtheꢀflatꢀgainꢀforꢀchannelꢀ2.ꢀSeeꢀTableꢀ7ꢀforꢀvalues.
TXA2[1:0]: Sets the output amplitude for channel 2. See Table 8 for values.
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MAX24101
15Gbps Octal Linear Equalizer
2
Register 03h (Lower I C Address): Channel 3
BIT
NAME
7
6
5
4
3
2
1
0
EQ3[3]
EQ3[2]
EQ3[1]
EQ3[0]
FG3[1]
FG3[0]
TXA3[1]
TXA3[0]
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
EQ3[3:0]:ꢀSetsꢀtheꢀequalizerꢀpeakingꢀforꢀchannelꢀ3.ꢀSeeꢀTableꢀ6ꢀforꢀvalues.
FG3[1:0]:ꢀSetsꢀtheꢀflatꢀgainꢀforꢀchannelꢀ3.ꢀSeeꢀTableꢀ7ꢀforꢀvalues.
TXA3[1:0]: Sets the output amplitude for channel 3. See Table 8 for values.
2
Register 04h (Lower I C Address): Channel 4
BIT
NAME
7
6
5
4
3
2
1
0
EQ4[3]
EQ4[2]
EQ4[1]
EQ4[0]
FG4[1]
FG4[0]
TXA4[1]
TXA4[0]
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
EQ4[3:0]:ꢀSetsꢀtheꢀequalizerꢀpeakingꢀforꢀchannelꢀ3.ꢀSeeꢀTableꢀ6ꢀforꢀvalues.
FG4[1:0]:ꢀSetsꢀtheꢀflatꢀgainꢀforꢀchannelꢀ3.ꢀSeeꢀTableꢀ7ꢀforꢀvalues.
TXA4[1:0]: Sets the output amplitude for channel 3. See Table 8 for values.
2
Register 05h (Lower I C Address): Channel 1–4 Controls
BIT
NAME
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
REGCONT14
CH1OFF
CH2OFF
CH3OFF
CH4OFF
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
REGCONT14:ꢀSelectsꢀchannelꢀsettings,ꢀforꢀchannelsꢀ1–4,ꢀfromꢀpinꢀcontrolꢀorꢀI2C accessible registers. 0 = pin control (equalizer
2
peaking,ꢀflatꢀgainꢀandꢀoutputꢀamplitude),ꢀ1ꢀ=ꢀI C accessible registers.
CH1OFF:ꢀDisablesꢀchannelꢀ1.ꢀ0ꢀ=ꢀenabled,ꢀ1ꢀ=ꢀdisabled.
CH2OFF:ꢀDisablesꢀchannelꢀ2.ꢀ0ꢀ=ꢀenabled,ꢀ1ꢀ=ꢀdisabled.
CH3OFF:ꢀDisablesꢀchannelꢀ3.ꢀ0ꢀ=ꢀenabled,ꢀ1ꢀ=ꢀdisabled.
CH4OFF:ꢀDisablesꢀchannelꢀ4.ꢀ0ꢀ=ꢀenabled,ꢀ1ꢀ=ꢀdisabled.
2
Register 01h (Upper I C Address): Channel 5
BIT
NAME
7
6
5
4
3
2
1
0
EQ5[3]
EQ5[2]
EQ5[1]
EQ5[0]
FG5[1]
FG5[0]
TXA5[1]
TXA5[0]
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
EQ5[3:0]:ꢀSetsꢀtheꢀequalizerꢀpeakingꢀforꢀchannelꢀ5.ꢀSeeꢀTableꢀ6ꢀforꢀvalues.
FG5[1:0]:ꢀSetsꢀtheꢀflatꢀgainꢀforꢀchannelꢀ5.ꢀSeeꢀTableꢀ7ꢀforꢀvalues.
TXA5[1:0]: Sets the output amplitude for channel 5. See Table 8 for values.
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MAX24101
15Gbps Octal Linear Equalizer
2
Register 02h (Upper I C Address): Channel 6
BIT
NAME
7
6
5
4
3
2
1
0
EQ6[3]
EQ6[2]
EQ6[1]
EQ6[0]
FG6[1]
FG6[0]
TXA6[1]
TXA6[0]
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
EQ6[3:0]:ꢀSetsꢀtheꢀequalizerꢀpeakingꢀforꢀchannelꢀ6.ꢀSeeꢀTableꢀ6ꢀforꢀvalues.
FG6[1:0]:ꢀSetsꢀtheꢀflatꢀgainꢀforꢀchannelꢀ6.ꢀSeeꢀTableꢀ7ꢀforꢀvalues.
TXA6[1:0]:ꢀSetsꢀtheꢀoutputꢀamplitudeꢀforꢀchannelꢀ6.ꢀSeeꢀTableꢀ8ꢀforꢀvalues.
2
Register 03h (Upper I C Address): Channel 7
BIT
NAME
7
6
5
4
3
2
1
0
EQ7[3]
EQ7[2]
EQ7[1]
EQ7[0]
FG7[1]
FG7[0]
TXA7[1]
TXA7[0]
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
EQ7[3:0]:ꢀSetsꢀtheꢀequalizerꢀpeakingꢀforꢀchannelꢀ7.ꢀSeeꢀTableꢀ6ꢀforꢀvalues.
FG7[1:0]:ꢀSetsꢀtheꢀflatꢀgainꢀforꢀchannelꢀ7.ꢀSeeꢀTableꢀ7ꢀforꢀvalues.
TXA7[1:0]: Sets the output amplitude for channel 7. See Table 8 for values.
2
Register 04h (Upper I C Address): Channel 8
BIT
NAME
7
6
5
4
3
2
1
0
EQ8[3]
EQ8[2]
EQ8[1]
EQ8[0]
FG8[1]
FG8[0]
TXA8[1]
TXA8[0]
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
EQ8[3:0]:ꢀSetsꢀtheꢀequalizerꢀpeakingꢀforꢀchannelꢀ8.ꢀSeeꢀTableꢀ6ꢀforꢀvalues.
FG8[1:0]:ꢀSetsꢀtheꢀflatꢀgainꢀforꢀchannelꢀ8.ꢀSeeꢀTableꢀ7ꢀforꢀvalues.
TXA8[1:0]: Sets the output amplitude for channel 8. See Table 8 for values.
2
Register 05h (Upper I C Address): Channel 5-8 Controls
BIT
NAME
7
6
5
4
3
2
1
0
Reserved
Reserved
Reserved
REGCONT58
CH5OFF
CH6OFF
CH7OFF
CH8OFF
DEFAULT
VALUE
0
0
0
0
0
0
0
0
ACCESS
RW
RW
RW
RW
RW
RW
RW
RW
REGCONT58:ꢀSelectsꢀchannelꢀsettings,ꢀforꢀchannelsꢀ5-8,ꢀfromꢀpinꢀcontrolꢀorꢀI2C accessible registers. 0 = pin control (equalizer
2
peaking,ꢀflatꢀgainꢀandꢀoutputꢀamplitude),ꢀ1ꢀ=ꢀI C accessible registers.
CH5OFF:ꢀDisablesꢀchannelꢀ5.ꢀ0ꢀ=ꢀenabled,ꢀ1ꢀ=ꢀdisabled.
CH6OFF:ꢀDisablesꢀchannelꢀ6.ꢀ0ꢀ=ꢀenabled,ꢀ1ꢀ=ꢀdisabled.
CH7OFF:ꢀDisablesꢀchannelꢀ7.ꢀ0ꢀ=ꢀenabled,ꢀ1ꢀ=ꢀdisabled.
CH8OFF:ꢀDisablesꢀchannelꢀ8.ꢀ0ꢀ=ꢀenabled,ꢀ1ꢀ=ꢀdisabled.
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MAX24101
15Gbps Octal Linear Equalizer
Exposed Pad Package
Layout Considerations
The exposed pad of the MAX24101 package incorpo-
rates features that provide a very low thermal resistance
pathꢀforꢀheatꢀremovalꢀfromꢀtheꢀIC.ꢀTheꢀexposedꢀpadꢀonꢀ
the MAX24101 must be soldered to the circuit board
for proper thermal performance and correct electrical
grounding. For more information on exposed-pad pack-
ages, refer to Maxim Applicationꢀ Noteꢀ862:ꢀHFAN-08.1:ꢀ
Thermal Considerations of QFN and Other Exposed-
Paddle Packages.
Circuit board layout and design can significantly affect the
performance of the MAX24101. Use good high-frequency
design techniques, including minimizing ground induc-
tance and using controlled-impedance transmission lines
onꢀtheꢀdataꢀsignals.ꢀPower-supplyꢀdecouplingꢀshouldꢀalsoꢀ
beꢀ placedꢀ asꢀ closeꢀ toꢀ theꢀ V
pins as possible. There
CC
should be sufficient supply filtering. Always connect all
V
s to a power plane. Take care to isolate the input from
CC
the output signals to reduce feed through.
Interface Schematics
MAX24101
MAX24101
V
CC
V
CC
50Ω
50Ω
V
- 0.8V
CC
TXxP
TXxN
50Ω
50Ω
RXxP
RXxN
Figure 12. CML Equivalent Input Structure
Figure 13. CML Equivalent Output Structure
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MAX24101
15Gbps Octal Linear Equalizer
Ordering Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
thatꢀaꢀ“+”,ꢀ“#”,ꢀorꢀ“-”ꢀinꢀtheꢀpackageꢀcodeꢀindicatesꢀRoHSꢀstatusꢀ
only.ꢀPackageꢀdrawingsꢀmayꢀshowꢀaꢀdifferentꢀsuffixꢀcharacter,ꢀbutꢀ
the drawing pertains to the package regardless of RoHS status.
PART
TEMP RANGE
-40°Cꢀtoꢀ+85°C
PIN-PACKAGE
MAX24101ELU+
60ꢀFCLGA-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
Chip Information
PROCESS:ꢀSiGeꢀBiCMOS
60ꢀFCLGA-EP
L6043FM+1
21-0650
90-0407
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MAX24101
15Gbps Octal Linear Equalizer
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
11/13
Initialꢀrelease
—
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2013 MaximꢀIntegratedꢀProducts,ꢀInc.ꢀꢀ
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