MAX2120CTI+T [MAXIM]
Video Tuner, 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WHHD-1, TQFN-28;
| 型号： | MAX2120CTI+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Video Tuner, 5 X 5 MM, 0.80 MM HEIGHT, LEAD FREE, MO-220WHHD-1, TQFN-28 放大器 信息通信管理 射频 商用集成电路 |
| 文件： | 总21页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0832; Rev 2; 5/10
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
General Description
Features
o 925MHz to 2175MHz Frequency Range
The MAX2120 low-cost, direct-conversion tuner IC is
designed for satellite set-top and VSAT applications.
The IC is intended for QPSK, Digital Video Broadcast
(DVB-S), DSS, and free-to-air applications.
o Monolithic VCO: No Calibration Required
o -75dBm to 0dBm High Dynamic Range
o 4MHz to 40MHz Integrated Variable BW LP Filters
o Single +3.3V 5% Supply
The MAX2120 directly converts the satellite signals
from the LNB to baseband using a broadband I/Q
downconverter. The operating frequency range extends
from 925MHz to 2175MHz.
o Low-Power Standby Mode
o Address Pin for Multituner Applications
o Differential I/Q Interface
The device includes an LNA and an RF variable-gain
amplifier, I and Q downconverting mixers, and baseband
lowpass filters with programmable cutoff frequency
control and digitally controlled baseband variable-gain
amplifiers. Together, the RF and baseband variable-gain
amplifiers provide more than 80dB of gain-control range.
The IC is compatible with virtually all QPSK demodulators.
o I2C 2-Wire Serial Interface
o Very Small 28-Pin Thin QFN Package
Ordering Information
The MAX2120 includes fully monolithic VCOs, as well as
a complete frequency synthesizer. Additionally, an on-
chip crystal oscillator is provided along with a buffered
output for driving additional tuners and demodulators.
Synthesizer programming and device configuration are
accomplished with a 2-wire serial interface. The IC fea-
tures a VCO autoselect (VAS) function that automatically
selects the proper VCO. For multituner applications, the
device can be configured to have one of two 2-wire
interface addresses. A low-power standby mode is
available whereupon the signal path is shut down while
leaving the reference oscillator, digital interface, and
buffer circuits active, providing a method to reduce
power in single and multituner applications.
PART
TEMP RANGE
PIN-PACKAGE
MAX2120CTI+
0°C to +70°C
28 Thin QFN-EP*
*EP = Exposed paddle.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration/
Functional Diagram
28
27
26
25
24
23
22
+
21
IDC+
The MAX2120 is the most advanced DBS tuner available
today. The low noise figure eliminates the need for an
external LNA. A small number of passive components are
needed to form a complete DVB, DBS, or VSAT RF front-
end solution. The tuner is available in a very small 28-pin
thin QFN package.
VCC_RF2
VCC_RF1
1
2
3
DC OFFSET
CORRECTION
MAX2120
INTERFACE LOGIC
AND CONTROL
LPF BW
CONTROL
IOUT-
IOUT+
20
19
18
17
GND
RFIN
GC1
QOUT-
QOUT+
4
5
Applications
DirecTV and Dish Network DBS
FREQUENCY
SYNTHESIZER
÷
DIV2/DIV4
DVB-S
VCC_LO
6
7
16 VCC_DIG
EP
Two-Way Satellite Systems
VSATs
VCC_VCO
15
REFOUT
8
9
10
11
12
13
14
Free-to-Air
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
ABSOLUTE MAXIMUM RATINGS
V
to GND...........................................................-0.3V to +3.9V
Continuous Power Dissipation (T = +70°C)
A
CC
All Other Pins to GND.................................-0.3V to (V
+ 0.3V)
28-Pin Thin QFN (derated 34.5mW/°C above +70°C)........2.75W
Operating Temperature Range...............................0°C to +70°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
CC
RF Input Power: RFIN.....................................................+10dBm
VCOBYP, CPOUT, REFOUT, XTAL, IOUT_, QOUT_, IDC_, and
QDC_ Short-Circuit Protection.............................................10s
CAUTION! ESD SENSITIVE DEVICE
MAX120
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
= +0.5V (max gain), T = 0°C to +70°C. No input signals at RF, baseband
GC1
A
(MAX2120 Evaluation Kit: V
= +3.13V to +3.47V, V
CC
I/Os are open circuited, and LO frequency = 2150MHz. Default register settings except BBG[3:0] = 1011. Typical values measured
at V = +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY
Supply Voltage
3.13
3.3
100
3
3.47
160
V
Receive mode, bit STBY = 0
Standby mode, bit STBY = 1
Supply Current
mA
ADDRESS SELECT INPUT (ADDR)
Digital Input-Voltage High, V
2.4
-50
V
V
IH
Digital Input-Voltage Low, V
0.5
50
IL
Digital Input-Current High, I
µA
µA
IH
Digital Input-Current Low, I
IL
ANALOG GAIN-CONTROL INPUT (GC1)
Input Voltage Range
Maximum gain = 0.5V
0.5
-50
2.7
V
Input Bias Current
+50
µA
VCO TUNING VOLTAGE INPUT (VTUNE)
Input Voltage Range
0.4
2.3
V
2-WIRE SERIAL INPUTS (SCL, SDA)
Clock Frequency
400
kHz
V
0.7 x
Input Logic-Level High
Input Logic-Level Low
V
CC
0.3 x
V
V
CC
Input Leakage Current
Digital inputs = GND or V
0.1
1
µA
CC
2-WIRE SERIAL OUTPUT (SDA)
Output Logic-Level Low
I
= 1mA
0.4
V
SINK
2
_______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
AC ELECTRICAL CHARACTERISTICS
= +0.5V (max gain), T = 0°C to +70°C. Default register settings except
GC1
A
(MAX2120 Evaluation Kit: V
BBG[3:0] = 1011. Typical values measured at V
= +3.13V to +3.47V, V
CC
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MAIN SIGNAL PATH PERFORMANCE
Input Frequency Range
RF Gain-Control Range (GC1)
Baseband Gain-Control Range
In-Band Input IP3
(Note 2)
0.5V < V
925
65
2175
MHz
dB
< 2.7V
73
15
GC1
Bits GC2 = 1111 to 0000
(Note 3)
13
dB
+2
dBm
dBm
dBm
dB
Out-of-Band Input IP3
Input IP2
(Note 4)
+15
+40
25
(Note 5)
Adjacent Channel Protection
(Note 6)
V
is set to 0.5V (maximum RF gain) and BBG[3:0] is
GC1
adjusted to give a 1V
baseband output level for a
8
P-P
-75dBm CW input tone at 1500MHz
Noise Figure
dB
dB
Starting with the same BBG[3:0] setting as above, V
is adjusted to back off RF gain by 10dB (Note 7)
GC1
9
12
Minimum RF Input Return Loss
925MHz < f < 2175MHz, in 75Ω system
12
RF
BASEBAND OUTPUT CHARACTERISTICS
Nominal Output Voltage Swing
I/Q Amplitude Imbalance
R
= 2kΩ//10pF
0.5
1
V
P-P
LOAD
Measured at 500kHz; filter set to 22.27MHz
1
dB
I/Q Quadrature Phase Imbalance Measured at 500kHz; filter set to 22.27MHz
Single-Ended I/Q Output
3.5
Degrees
Real Z , from 1MHz to 40MHz
30
3
Ω
O
Impedance
Output 1dB Compression Voltage Differential
Baseband Highpass -3dB
V
P-P
47nF capacitors at IDC_, QDC_
400
Hz
Frequency Corner
BASEBAND LOWPASS FILTERS
Filter Bandwidth Range
Rejection Ratio
4
40
MHz
dB
At 2 x f
39
37
-3dB
Group Delay
Up to 1dB bandwidth
ns
Ratio of In-Filter-Band to Out-of-
Filter-Band Noise
f
= 100Hz to 22.5MHz, f
= 87.5MHz to
OUTBAND
INBAND
25
dB
112.5MHz
FREQUENCY SYNTHESIZER
RF-Divider Frequency Range
RF-Divider Range (N)
925
16
2175
2175
MHz
MHz
Reference-Divider Frequency
Range
4
1
1
30
31
2
Reference-Divider Range (R)
Phase-Detector Comparison
Frequency
MHz
_______________________________________________________________________________________
3
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
AC ELECTRICAL CHARACTERISTICS (continued)
= +0.5V (max gain), T = 0°C to +70°C. Default register settings except
GC1
A
(MAX2120 Evaluation Kit: V
BBG[3:0] = 1011. Typical values measured at V
= +3.13V to +3.47V, V
CC
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION
Guaranteed LO Frequency
T
A
= 0°C to +70°C
925
2175
Range
MAX120
f
f
f
= 10kHz
= 100kHz
= 1MHz
-82
OFFSET
OFFSET
OFFSET
LO Phase Noise
dBc/Hz
-102
-122
XTAL/REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER
XTAL Oscillator Frequency
Parallel-resonance-mode crystal (Note 8)
Range
4
0.5
1
8
2.0
8
MHz
Input Overdrive Level
AC-coupled sine wave input
1
V
P-P
XTAL Output-Buffer Divider
Range
XTAL Output Voltage Swing
XTAL Output Duty Cycle
4MHz to 30MHz, C
= 10pF
1
1.5
50
2
V
LOAD
P-P
%
Note 1: Min/max values are production tested at T = +70°C. Min/max limits at T = 0°C and T = +25°C are guaranteed by design
A
A
A
and characterization.
Note 2: Gain-control range specifications met over this band.
Note 3: In-band IIP3 test conditions: GC1 set to provide the nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
LO
-26dBm each are applied at 2174MHz and 2175MHz. The IM3 tone at 3MHz is measured at baseband, but is referred to the
RF input.
Note 4: Out-of-band IIP3 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
LO
-20dBm each are applied at 2070MHz and 1975MHz. The IM3 tone at 5MHz is measured at baseband, but is referred to the
RF input.
Note 5: Input IP2 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz
to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm
LO
each are applied at 925MHz and 1250MHz. The IM2 tone at 5MHz is measured at baseband, but is referred to the RF input.
Note 6: Adjacent channel protection test conditions: GC1 is set to provide the nominal baseband output drive with a 2110MHz
27.5Mbaud signal at -55dBm. GC2 set for mid-scale. The test signal will be set for PR = 7/8 and SNR of -8.5dB. An adjacent
channel at 40MHz is added at -25dBm. DVB-S BER performance of 2E-4 will be maintained for the desired signal. GC2
may be adjusted for best performance.
Note 7: Guaranteed by design and characterization at T = +25°C.
A
Note 8: See Table 14 for crystal ESR requirements.
4
_______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
Typical Operating Characteristics
(MAX2120 Evaluation Kit: V
except BBG[3:0] = 1011.)
= +3.3V, baseband output frequency = 5MHz; V
= 1.2V; T = +25°C. Default register settings
CC
GC1 A
STANDBY MODE SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT
vs. BASEBAND FILTER CUTOFF FREQUENCY
SUPPLY CURRENT vs. SUPPLY VOLTAGE
98
97
96
95
94
93
92
91
90
89
88
2.900
2.800
2.700
2.600
2.500
104
T
= +70°C
102
100
98
96
94
92
90
88
86
84
A
T
= +25°C
A
T
= +70°C
A
T
= 0°C
T
= 0°C, +25°C
A
A
2.400
2.300
3.0
3.1
3.2
3.3
3.4
3.5
3.6
3.0
3.1
3.2
3.3
3.4
3.5
3.6
4
8
12 16 20 24 28 32 36 40
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
BASEBAND FILTER CUTOFF FREQUENCY (MHz)
QUADRATURE MAGNITUDE MATCHING
vs. LO FREQUENCY
HD3 vs. OUTPUT VOLTAGE
QUADRATURE PHASE vs. LO FREQUENCY
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
1.0
0.8
0.6
93.5
92.5
91.5
f
= 10MHz
f
= 10MHz
BASEBAND
BASEBAND
T
= +25°C
A
T
= +25°C
A
0.4
0.2
0
T
= +70°C
A
90.5
89.5
88.5
87.5
86.5
-0.2
-0.4
-0.6
-0.8
-1.0
T
= 0°C
A
T
= 0°C
A
T
= +70°C
A
1.0
1.5
2.0
V
2.5
)
3.0
3.5
900
1200
1500
1800
2100
2400
900
1200
1500
1800
2100
2400
(V
LO FREQUENCY (MHz)
OUT P-P
LO FREQUENCY (MHz)
QUADRATURE PHASE
vs. BASEBAND FREQUENCY
QUADRATURE MAGNITUDE MATCHING
vs. BASEBAND FREQUENCY
93.5
92.5
91.5
1.0
0.8
0.6
f
= 925MHz
LO
f
= 925MHz
LO
T
= +70°C
A
0.4
0.2
0
T
= +70°C
A
90.5
89.5
88.5
87.5
86.5
T
= +25°C
A
T
= 0°C
A
-0.2
-0.4
-0.6
-0.8
-1.0
T
= +25°C
A
T
= 0°C
A
0
4
8
12
16
20
0
4
8
12
16
20
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
_______________________________________________________________________________________
5
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Typical Operating Characteristics (continued)
(MAX2120 Evaluation Kit: V
except BBG[3:0] = 1011.)
= +3.3V, baseband output frequency = 5MHz; V
= 1.2V; T = +25°C. Default register settings
CC
GC1 A
BASEBAND FILTER
FREQUENCY RESPONSE
BASEBAND FILTER HIGHPASS
FREQUENCY RESPONSE
0
-10
-20
2
0
MAX120
-2
-30
-40
-50
-4
-6
-8
-60
-70
-80
-10
-12
-14
0
20
40
60
80
100
1000
10,000
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
BASEBAND FILTER 3dB FREQUENCY
vs. TEMPERATURE
PROGRAMMED f
vs. MEASURED f
FREQUENCY
FREQUENCY
-3dB
-3dB
1.0
45
40
NORMALIZED TO T = +25°C
LPF[7:0] = 12 + (f
- 4MHz) / 290kHz
A
-3dB
0.8
0.6
0.4
35
30
0.2
0
25
20
-0.2
-0.4
-0.6
-0.8
-1.0
15
10
5
0
0
10
20
30
40
50
60
70
0
5
10 15 20 25 30 35 40 45
TEMPERATURE (°C)
PROGRAMMED f FREQUENCY (MHz)
-3dB
NOISE FIGURE vs. FREQUENCY
INPUT POWER vs. V
GC1
10.0
10
0
ADJUST BBG[3:0] FOR 1V
ADJUST BBG[3:0] FOR 1V
P-P
P-P
BASEBAND OUTPUT WITH
= -75dBm AND V = 0.5V
BASEBAND OUTPUT WITH
P
P
= -75dBm AND V
= 0.5V
IN
GC1
IN
GC1
9.5
9.0
8.5
-10
-20
-30
T
= +70°C
A
T
= +70°C
A
T
= +25°C
A
-40
-50
-60
-70
-80
8.0
7.5
T
= +25°C
A
900 1100 1300 1500 1700 1900 2100 2300
FREQUENCY (MHz)
0.5
1.0
1.5
2.0
(V)
2.5
3.0
V
GC1
6
_______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
Typical Operating Characteristics (continued)
(MAX2120 Evaluation Kit: V
except BBG[3:0] = 1011.)
= +3.3V, baseband output frequency = 5MHz; V
= 1.2V; T = +25°C. Default register settings
CC
GC1 A
NOISE FIGURE vs. INPUT POWER
OUT-OF-BAND IIP3 vs. INPUT POWER
70
30
20
ADJUST BBG[3:0] FOR 1V
P-P
BASEBAND OUTPUT WITH
SEE NOTE 4 ON PAGE 4 FOR CONDITIONS
60
50
40
30
20
10
0
P
f
= -75dBm AND V
= 0.5V
IN
GC1
= 1500MHz
LO
10
0
-10
-20
-30
-80 -70 -60 -50 -40 -30 -20 -10
INPUT POWER (dBm)
0
-80 -70 -60 -50 -40 -30 -20 -10
INPUT POWER (dBm)
0
IN-BAND IIP3 vs. INPUT POWER
IIP2 vs. INPUT POWER
30
20
10
60
50
40
SEE NOTE 3 ON PAGE 4 FOR CONDITIONS
SEE NOTE 5 ON PAGE 4 FOR CONDITIONS
0
-10
30
20
-20
-30
-40
-50
-60
10
0
-10
-80 -70 -60 -50 -40 -30 -20 -10
INPUT POWER (dBm)
0
-80 -70 -60 -50 -40 -30 -20 -10
INPUT POWER (dBm)
0
PHASE NOISE AT 10kHz OFFSET
vs. CHANNEL FREQUENCY
INPUT RETURN LOSS vs. FREQUENCY
-70
-72
0
-74
-76
-5
V
= 0.5V
GC1
-78
-80
-10
-15
-82
-84
-86
-88
-90
-20
-25
V
= 2.7V
GC1
925 1115 1305 1495 1685 1875 2065 2255
CHANNEL FREQUENCY (MHz)
900 1125 1350 1575 1800 2025 2250
FREQUENCY (MHz)
_______________________________________________________________________________________
7
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Typical Operating Characteristics (continued)
(MAX2120 Evaluation Kit: V
except BBG[3:0] = 1011.)
= +3.3V, baseband output frequency = 5MHz; V
= 1.2V; T = +25°C. Default register settings
A
CC
GC1
LO LEAKAGE vs. LO FREQUENCY
PHASE NOISE vs. OFFSET FREQUENCY
-70
-75
-60
-70
-80
MEASURED AT RF INPUT
f
= 1800MHz
LO
MAX120
-90
-80
-85
-90
-100
-110
-120
-130
925
1175
1425
1675
1925
2175
0.1
1
10
100
1000
LO FREQUENCY (MHz)
OFFSET FREQUENCY (kHz)
Pin Description
PIN
NAME
FUNCTION
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground
connections.
1
VCC_RF2
VCC_RF1
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground
connections.
2
3
4
GND
RFIN
Ground. Connect to the board’s ground plane for proper operation.
Wideband 75Ω RF Input. Connect to an RF source through a DC-blocking capacitor.
RF Gain-Control Input. High-impedance analog input, with a 0.5V to 2.7V operating range. V
0.5V corresponds to the maximum gain setting.
=
GC1
5
GC1
DC Power Supply for LO Generation Circuits. Connect to a +3.3V low-noise supply. Bypass to GND
with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias
with other ground connections.
6
VCC_LO
DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF
capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
7
VCC_VCO
Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to
the pin. Do not share capacitor ground vias with other ground connections.
8
9
VCOBYP
VTUNE
High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this pin with as short
of a connection as possible.
10
11
GNDTUNE Ground for VTUNE. Connect to the PCB ground plane.
GNDSYN
Ground for Synthesizer. Connect to the PCB ground plane.
Charge-Pump Output. Connect this output to the PLL loop filter input with the shortest connection
possible.
12
CPOUT
8
_______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
Pin Description (continued)
PIN
NAME
FUNCTION
DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
13
VCC_SYN
Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal by a series 1nF
capacitor. See the Typical Operating Circuit.
14
15
XTAL
Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external
circuitry.
REFOUT
DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND
with a 1nF capacitor connected as close to the pin as possible. Do not share capacitor ground vias
with other ground connections.
16
VCC_DIG
17
18
19
20
21
22
23
24
QOUT+
QOUT-
IOUT+
IOUT-
IDC+
Quadrature Baseband Differential Output. AC-couple with a 47nF capacitor to the demodulator input.
In-Phase Baseband Differential Output. AC-couple with a 47nF capacitor to the demodulator input.
I-Channel baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to
IDC+.
IDC-
QDC+
QDC-
Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to
QDC+.
DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a
1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
25
VCC_BB
26
27
28
—
SDA
SCL
ADDR
EP
2-Wire Serial Data Interface. Requires a > 1kΩ pullup resistor to V
.
CC
2-Wire Serial Clock Interface. Requires a > 1kΩ pullup resistor to V
.
CC
Address. ADDR is at logic-high if unconnected.
Exposed Paddle. Solder evenly to the board’s ground plane for proper operation.
_______________________________________________________________________________________
9
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
figurations. The register configuration of Table 1 shows
each bit name and the bit usage information for all regis-
Detailed Description
Register Description
The MAX2120 includes 12 user-programmable registers
and 2 read-only registers. See Table 1 for register con-
ters. Note that all registers must be written after and no
earlier than 100µs after the device is powered up.
Table 1. Register Configuration
MSB
LSB
REG REGISTER READ/
REG
DATA BYTE
MAX120
NO
NAME
WRITE ADDRESS
D[7]
X
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
N[9]
D[0]
N[8]
N-Divider
MSB
1
2
3
Write
Write
Write
0x00
0x01
0x02
N[14]
N[13]
N[12]
N[11]
N[10]
N-Divider
LSB
N[7]
N[6]
N[5]
N[4]
N[3]
X
N[2]
X
N[1]
X
N[0]
X
Charge
Pump
CPMP[1]
0
CPMP[0]
0
CPLIN[1]
0
CPLIN[0]
0
4
5
Not Used
Not Used
Write
Write
0x03
0x04
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
XTAL
6
Divider/
R-Divider
Write
0x05
XD[2]
XD[1]
XD[0]
R[4]
R[3]
R[2]
R[1]
R[0]
7
8
9
PLL
VCO
LPF
Write
Write
Write
0x06
0x07
0x08
D24
CPS
ICP
X
X
X
X
X
VCO[4]
LPF[7]
VCO[3]
LPF[6]
VCO[2]
LPF[5]
VCO[1]
LPF[4]
VCO[0]
LPF[3]
VAS
ADL
ADE
LPF[2] LPF[1] LPF[0]
PWDN
0
10
11
Control
Write
Write
0x09
0x0A
STBY
X
X
X
BBG[3] BBG[2] BBG[1] BBG[0]
PLL
0
DIV
0
VCO
0
BB
0
RFMIX RFVGA
FE
0
Shutdown
0
0
LD
LD
LD
CPTST[2] CPTST[1] CPTST[0]
TURBO
1
MUX[2] MUX[1] MUX[0]
12
Test
Write
0x0B
X
0
0
0
0
0
0
Status
Byte-1
13
14
Read
Read
0x0C
0x0D
POR
VASA
VASE
LD
X
X
X
X
Status
Byte-2
VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
0 = Set to “0” for factory-tested operation.
1 = Set to “1” for factory-tested operation.
X = Don’t care.
Table 2. N-Divider MSB Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
X
7
X
Don’t care.
Sets the most significant bits of the PLL integer-divide number (N).
Default value is N = 950 decimal. N can range from 16 to 2175.
N[14:8]
6–0
0000011
Table 3. N-Divider LSB Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Sets the least significant bits of the PLL integer-divide number (N).
Default value is N = 950 decimal. N can range from 16 to 2175.
N[7:0]
7–0
10110110
10 ______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
Table 4. Charge-Pump Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Charge-pump minimum pulse width. Users must program to 00
upon powering up the device.
CPMP[1:0]
7, 6
00
Controls charge-pump linearity.
CPLIN[1:0]
X
5, 4
3–0
00
X
00 = Typically balanced charge and sink currents.
Other values are not tested.
Don’t care.
Table 5. XTAL Buffer and Reference Divider Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Sets the crystal-divider setting.
000 = Divide by 1 (default)
001 = Divide by 2
XD[2:0]
7, 6, 5
000
011 = Divide by 3
100 = Divide by 4
101 through 110 = All divide values from 5 (101) to 7 (110)
111 = Divide by 8
Sets the PLL reference-divider (R) number.
00001 = Divide by 1
00010 = Divide by 2
00011 = Divide by 3
R[4:0]
4–0
00100
00100 = Divide by 4 (default)
00101 through 11110 = All divide values from 3 (00101) to 29
(11110)
11111 = Divide by 31
Table 6. PLL Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
VCO divider setting.
D24
7
6
1
0 = Divide by 2. Use for LO frequencies ≥ 1125MHz.
1 = Divide by 4. Use for LO frequencies < 1125MHz.
Charge-pump current mode.
0 = Charge-pump current controlled by ICP bit
1 = Charge-pump current controlled by VCO autoselect (VAS)
CPS
1
Charge-pump current.
0 = 600µA typical
1 = 1200µA typical
ICP
X
5
0
X
4–0
Don’t care.
______________________________________________________________________________________ 11
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Table 7. VCO Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Controls which VCO is activated when using manual VCO
programming mode. This also serves as the starting point for
the VCO autoselect mode.
VCO[4:0]
7–3
11001
VCO Autoselection (VAS) Circuit
VAS
ADL
2
1
1
0
0 = Disable VCO selection must be program through I2C
1 = Enable VCO selection controlled by autoselection circuit
MAX120
Enables or disables the VCO tuning voltage ADC latch when
the VCO autoselect mode (VAS) is disabled.
0 = Disables the ADC latch
1 = Latches the ADC value
Enables or disables VCO tuning voltage ADC read when the
VCO autoselect mode (VAS) is disabled.
0 = Disables ADC read
ADE
0
0
1 = Enables ADC read
Table 8. Lowpass Filter Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Sets the baseband lowpass filter 3dB corner frequency. 3dB
corner frequency = 4MHz + (LPF[7:0] - 12) x 290kHz.
LPF[7:0]
7–0
01001011
Table 9. Control Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Software standby control.
0 = Normal operation
STBY
7
0
1 = Disables the signal path and frequency synthesizer, leaving
only the 2-wire bus, crystal oscillator, XTALOUT buffer, and
XTALOUT buffer divider active
X
PWDN
X
6
5
4
X
0
X
Don’t care.
Factory use only.
0 = Normal operation; other value is not tested.
Don’t care.
Baseband gain setting (1dB typical per step).
0000 = Minimum gain (0dB)
…
BBG[3:0]
3–0
0000
1111 = Maximum gain (15dB typical)
12 ______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
Table 10. Shutdown Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
X
7
X
Don’t care.
PLL enable.
PLL
DIV
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0 = Normal operation
1 = Shuts down the PLL. Value not tested.
Divider enable.
0 = Normal operation
1 = Shuts down the divider. Value not tested.
VCO enable.
0 = Normal operation
1 = Shuts down the VCO. Value not tested.
VCO
BB
Baseband enable.
0 = Normal operation
1 = Shuts down the baseband. Value not tested.
RF mixer enable.
0 = Normal operation
1 = Shuts down the RF mixer. Value not tested.
RFMIX
RFVGA
FE
RF VGA enable.
0 = Normal operation
1 = Shuts down the RF VGA. Value not tested.
RF front-end enable.
0 = Normal operation
1 = Shuts down the RF front-end. Value not tested.
Table 11. Test Register
BIT NAME
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Charge-pump test modes.
000 = Normal operation (default)
001 = Crystal translator ECL to CMOS path
100 = Both source and sink currents enabled
101 = Source current enabled
CPTST[2:0]
7, 6, 5
000
110 = Sink current enabled
111 = High impedance (both source and sink current disabled)
X
4
3
X
0
Don’t care.
Charge-pump fast lock. Users must program to 1 upon powering
up the device.
TURBO
REFOUT output.
000 = Normal operation; other values are not tested
LDMUX[2:0]
2, 1, 0
000
______________________________________________________________________________________ 13
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Table 12. Status Byte-1 Register
BIT NAME
BIT LOCATION (0 = LSB)
FUNCTION
Power-on reset status.
0 = Chip status register has been read with a stop condition since last power-on
1 = Power-on reset (power cycle) has occurred, default values have been loaded
in registers
POR
7
Indicates whether VCO autoselection was successful.
0 = Indicates the autoselect function is disabled or unsuccessful VCO selection
1 = Indicates successful VCO autoselection
MAX120
VASA
VASE
6
5
Status indicator for the autoselect function.
0 = Indicates the autoselect function is active
1 = Indicates the autoselect process is inactive
PLL lock detector. TURBO bit must be programmed to 1 for valid LD reading.
LD
X
4
0 = Unlocked
1 = Locked
3–0
Don’t care.
Table 13. Status Byte-2 Register
BIT NAME
BIT LOCATION (0 = LSB)
FUNCTION
VCOSBR[4:0]
7–3
VCO band readback.
VAS ADC output readback.
000 = Out of lock
001 = Locked
ADC[2:0]
2, 1, 0
010 = VAS locked
101 = VAS locked
110 = Locked
111 = Out of lock
14 ______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
Slave Address
The MAX2120 has a 7-bit slave address that must be
sent to the device following a START condition to initi-
ate communication. The slave address is internally pro-
grammed to 1100000. The eighth bit (R/W) following
the 7-bit address determines whether a read or write
operation will occur.
2-Wire Serial Interface
2
The MAX2120 uses a 2-wire I C-compatible serial
interface consisting of a serial data line (SDA) and a
serial clock line (SCL). SDA and SCL facilitate bidirec-
tional communication between the MAX2120 and the
master at clock frequencies up to 400kHz. The master
initiates a data transfer on the bus and generates the
SCL signal to permit data transfer. The MAX2120
behaves as a slave device that transfers and receives
data to and from the master. SDA and SCL must be
pulled high with external pullup resistors (1kΩ or
greater) for proper bus operation.
The MAX2120 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 1).
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2120 (8 bits and an
ACK/NACK). The data on SDA must remain stable
during the high period of the SCL clock pulse. Changes
in SDA while SCL is high and stable are considered
control signals (see the START and STOP Conditions
section). Both SDA and SCL remain high when the bus
is not busy. Pullup resistors should be referenced to the
The write/read address is C0/C1 if the ADDR pin is con-
nected to ground. The write/read address is C2/C3 if
the ADDR pin is connected to V
.
CC
SLAVE ADDRESS
1
1
0
0
0
0
0
7
S
ACK
9
R/W
8
SDA
SCL
MAX2120’s V
.
CC
1
2
3
4
5
6
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
Figure 1. MAX2120 Slave Address Byte with ADDR Pin
Connected to Ground
Write Cycle
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX2120 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
When addressed with a write command, the MAX2120
allows the master to write to a single register or to multi-
ple successive registers.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX2120 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the
address of the first register it wishes to write to (see
Table 1 for register addresses). If the slave acknowl-
edges the address, the master can then write one byte
to the register at the specified address. Data is written
beginning with the most significant bit. The MAX2120
again issues an ACK if the data is successfully written
to the register. The master can continue to write data to
the successive internal registers with the MAX2120
acknowledging each successful transfer, or it can ter-
minate transmission by issuing a STOP condition. The
write cycle will not terminate until the master issues a
STOP condition.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master must reattempt
communication at a later time.
______________________________________________________________________________________ 15
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Figure 2 illustrates an example in which registers 0
through 2 are written with 0x0E, 0xD8, and 0xE1,
respectively.
wishes to read (see Table 1 for register addresses). The
slave acknowledges the address. Then, a START condi-
tion is issued by the master, followed by the 7 slave
address bits and a read bit (R/W = 1). The MAX2120
issues an ACK if the slave address byte is successfully
received. The MAX2120 starts sending data MSB first
with each SCL clock cycle. At the 9th clock cycle, the
master can issue an ACK and continue to read succes-
sive registers, or the master can terminate the transmis-
sion by issuing a NACK. The read cycle does not
terminate until the master issues a STOP condition.
Read Cycle
When addressed with a read command, the MAX2120
allows the master to read back a single register, or mul-
tiple successive registers.
A read cycle begins with the bus master issuing a
START condition followed by the 7 slave address bits
and a write bit (R/W = 0). The MAX2120 issues an ACK if
the slave address byte is successfully received. The bus
master must then send the address of the first register it
MAX120
Figure 3 illustrates an example in which registers 0
through 2 are read back.
WRITE
DEVICE
ADDRESS
WRITE
REGISTER ACK
ADDRESS
WRITE DATA
WRITE DATA
WRITE DATA
R/W
ACK
TO REGISTER ACK TO REGISTER ACK TO REGISTER ACK
START
STOP
0x00
0x01
0x02
1100000
0
—
0x00
—
0x0E
—
0xD8
—
0x0E1
—
Figure 2. Example: Write Registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.
S
T
A
R
T
S
T
A
R
T
DEVICE
ADDRESS
REGISTER
ADDRESS
DEVICE
ADDRESS
REG 00
DATA
REG 01
DATA
REG 02
DATA
N
A
C
K
S
T
O
P
R/ W
0
R/ W
1
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
1100000
00000000
1100000
xxxxxxxx
xxxxxxxx
xxxxxxxx
Figure 3. Example: Receive data from read registers.
16 ______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
XTAL Oscillator
Applications Information
The MAX2120 contains an internal reference oscillator,
The MAX2120 downconverts RF signals in the 925MHz to
reference output divider, and output buffer. All that is
2175MHz range directly to the baseband I/Q signals. The
devices are targeted for digital DBS tuner applications.
required is to connect a crystal through a series, 1nF
capacitor. To minimize parasitics, place the crystal and
series capacitor as close as possible to pin 14 (XTAL
RF Input
pin). See Table 14 for crystal (XTAL) ESR (equivalent
series resistance) requirements. The typical input
capacitance is 40pF.
The RF input of the MAX2120 is internally matched to
75Ω. Only a DC-blocking capacitor is needed. See the
Typical Operating Circuit.
VCO Autoselect (VAS)
The MAX2120 includes 24 VCOs. The local oscillator fre-
quency can be manually selected by programming the
VCO[4:0] bits in the VCO register. The selected VCO is
reported in the Status Byte-2 register (see Table 13).
RF Gain Control
The MAX2120 features a variable-gain low-noise amplifi-
er providing 73dB of RF gain range. The voltage-control
(VGC) range is 0.5V (minimum attenuation) to 2.7V
(maximum attenuation).
Alternatively, the MAX2120 can be set to autonomously
choose a VCO by setting the VAS bit in the VCO regis-
ter to logic-high. The VAS routine is initiated once the
N-divider LSB register word (REG 2) is loaded.
Baseband Variable-Gain Amplifier
The receiver baseband variable-gain amplifiers provide
15dB of gain-control range programmable in 1dB
steps. The VGA gain can be serially programmed
through the SPI™ interface by setting bits BBG[3:0] in
the Control register.
In the event that only the R-divider register or N-
divider MSB register word is changed, the N-divider
LSB word must also be loaded last to initiate the
VCO autoselect function. The VCO value pro-
grammed in the VCO[4:0] register serves as the start-
ing point for the automatic VCO selection process.
Baseband Lowpass Filter
The MAX2120 includes a programmable on-chip 7th-
order Butterworth filter. The -3dB corner frequency of
the baseband filter is programmable by setting the bits
LPF[7:0] in the Lowpass register. The value of the
LPF[7:0] is determined by the following equation:
During the selection process, the VASE bit in the Status
Byte-1 register is cleared to indicate the autoselection
function is active. Upon successful completion, bits
VASE and VASA are set and the VCO selected is
reported in the Status Byte-2 register (see Table 13). If
the search is unsuccessful, VASA is cleared and VASE
is set. This indicates that searching has ended but no
good VCO has been found, and occurs when trying to
tune to a frequency outside the VCO’s specified
frequency range.
(f
− 4MHz)
0.29MHz
−3dB
LPF[7:0]dec =
+12,
where f
is in units of MHz.
-3dB
The filter can be adjusted from approximately 4MHz to
40MHz. Total device supply current depends on the fil-
ter BW setting, with increasing current commensurate
with increasing -3dB BW.
Refer to the MAX2112/MAX2120 VAS application note
for more information.
DC Offset Cancellation
The DC offset cancellation is required to maintain the I/Q
output dynamic range. Connecting an external capacitor
between IDC+ and IDC- forms a highpass filter for the I
channel, and an external capacitor between QDC+ and
QDC- forms a highpass filter for the Q channel. Keep the
value of the external capacitor less than 47nF to form a
typical highpass corner of 400Hz.
Table 14. Maximum Cystal ESR
Requirements
ESR
(ꢀ)
XTAL FREQUENCY (MHz)
MAX
150
100
40
4 < f
6 < f
ꢀ 6
ꢀ 8
XTAL
XTAL
8 < f
ꢀ 13.5
XTAL
SPI is a trademark of Motorola, Inc.
______________________________________________________________________________________ 17
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
3-Bit ADC
The MAX2120 has an internal 3-bit ADC connected to
the VCO tune pin (VTUNE). This ADC can be used for
checking the lock status of the VCOs.
Standby Mode
The MAX2120 features normal operating mode and
2
standby mode using the I C interface. Setting a logic-
high to the PWDN bit in the Control register enables
power-down. In this mode, all circuitries except for the 2-
wire-compatible bus are disabled, allowing for program-
ming of the MAX2120 registers while in power-down.
Table 15 summarizes the ADC trip points, and the VCO
lock indication. The VCO autoselect routine will only
select a VCO in the “VAS locked” range. This allows
room for a VCO to drift over temperature and remain in
a valid “locked” range.
In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active
mode. Default register values are provided for the
user’s convenience only. It’s the user’s responsibility to
load all the registers no sooner than 100µs after the
device is powered up.
MAX120
The ADC must first be enabled by setting the ADE bit in
the VCO register. The ADC reading is latched by a sub-
sequent programming of the ADC latch bit (ADL = 1).
The ADC value is reported in the Status Byte-2 register
(see Table 13).
Layout Considerations
The MAX2120 EV kit serves as a guide for PCB
layout. Keep RF signal lines as short as possible to mini-
mize losses and radiation. Use controlled impedance on
all high-frequency traces. For proper operation, the
exposed paddle must be soldered evenly to the board’s
ground plane. Use abundant vias beneath the exposed
paddle for maximum heat dissipation. Use abundant
ground vias between RF traces to minimize undesired
Table 15. ADC Trip Points and Lock Status
ADC[2:0]
000
LOCK STATUS
Out of Lock
Locked
001
010
VAS Locked
VAS Locked
Locked
101
coupling. Bypass each V
pin to ground with a 1nF
capacitor placed as close as possible to the pin.
CC
110
111
Out of Lock
18 ______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
Typical Operating Circuit
SERIAL DATA
INPUT/OUTPUT
SERIAL CLOCK
INPUT
V
CC
V
CC
28
27
26
25
24
23
22
+
IDC+
VCC_RF2
VCC_RF1
21
1
2
3
DC OFFSET
CORRECTION
V
CC
MAX2120
INTERFACE LOGIC
AND CONTROL
IOUT-
IOUT+
QOUT-
QOUT+
LPF BW
CONTROL
20
19
18
17
16
15
GND
BASEBAND
OUTPUTS
RF INPUT
RFIN
GC1
4
5
V
V
CC
CC
FREQUENCY
SYNTHESIZER
VCC_DIG
REFOUT
÷
DIV2/DIV4
VCC_LO
6
7
V
CC
EP
VCC_VCO
8
9
10
11
12
13
14
VCC
______________________________________________________________________________________ 19
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
Package Information
Chip Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-” in
the package code indicates RoHS status only. Package draw-
ings may show a different suffix character, but the drawing per-
tains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
28 TQFN
PACKAGE
CODE
T2855+3
OUTLINE
NO.
21-0140
LAND
PATTERN NO.
MAX120
90-0023
20 ______________________________________________________________________________________
Complete, Direct-Conversion Tuner for DVB-S
and Free-to-Air Applications
MAX120
Revision History
REVISION
NUMBER
REVISION
DATE
PAGES
CHANGED
DESCRIPTION
0
1
2
6/07
3/08
5/10
Initial release
—
1–18
11
Corrected errors in data sheet, replaced Read Cycle section and Figure 3,
added Table 14
Corrected D24 bit Function in Table 6
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
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