MAX2121BETI+ [MAXIM]
Telecom Circuit, 1-Func, BICMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-28;
| 型号： | MAX2121BETI+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Telecom Circuit, 1-Func, BICMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-28 电信 信息通信管理 电信集成电路 |
| 文件： | 总20页 (文件大小：729K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
EVALUATION KIT AVAILABLE
MAX2121B
L-Band Tuner with Programmable
Baseband Filter
General Description
The MAX2121B low-cost, direct-conversion tuner IC is
designed for satellite set-top and VSAT applications.
Benefits and Features
● Monolithic Receiver Saves Cost and Space
•ꢀ Integrated VCO with Low Phase Noise: -97dBc/Hz
at 10kHz
The device directly converts the satellite signals from the
LNB to baseband using a broadband I/Q downconverter.
The operating frequency range extends from 925MHz to
2250MHz.
•ꢀ Integrated 14-Bit Fractional-N Synthesizer
•ꢀ Address Pin Allows for Multi-Tuner Applications
● Low Power Reduces Cost
•ꢀ 495mW Power Dissipation
•ꢀ 10mW Standby Mode
The device includes an LNA and an RF variable-gain ampli-
fier, I and Q downconverting mixers, and digitally controlled
baseband filters (40MHz to 124MHz) and variable-gain
amplifiers. Together, the RF and baseband variable-gain
amplifiers provide more than 80dB of gain control range.
● High Dynamic Range Eliminates Need for External
LNA and/or Attenuators
•ꢀ -75dBm to 0dBm Input Power
•ꢀ 8dB Noise Figure
The device includes fully monolithic VCOs, as well as a
complete fractional-N frequency synthesizer. Additionally,
an on-chip crystal oscillator is provided along with a buff-
ered output for driving additional tuners and demodula-
tors. Synthesizer programming and device configuration
are accomplished with a 2-wire serial interface. The IC
features a VCO autoselect (VAS) function that automati-
cally selects the proper VCO. For multituner applications,
the device can be configured to have one of two 2-wire
interface addresses. A low-power standby mode is avail-
able whereupon the signal path is shut down while leaving
the reference oscillator, digital interface, and buffer cir-
cuits active, providing a method to reduce power in single
and multituner applications.
● Integrated LP Filters Simplify Design
•ꢀ Programmable Bandwidth from 40MHz to 124MHz
● Differential I/Q Interface Minimizes EMI
•ꢀ 1V
Full-Scale Outputs
P-P
● Serial Interface and Small Package Reduce Size
•ꢀ 5mm x 5mm, 28-Pin TQFN Package
2
•ꢀ I C 2-Wire Serial Interface
Functional Diagram
28
27
26
25
24
23
22
+
The device is the most advanced broadband/VSAT DBS
tuner available. The low noise figure eliminates the need
for an external LNA. A small number of passive compo-
nents are needed to form a complete broadband satellite
tuner DVB-S2 RF front-end solution. The tuner is avail-
able in a very small, 5mm x 5mm, 28-pin TQFN package.
21
IDC+
V
V
1
2
3
CC_RF2
DC OFFSET
CORRECTION
INTERFACE LOGIC
AND CONTROL
MAX2121B
IOUT-
IOUT+
20
19
18
17
16
15
CC_RF1
GND
QOUT-
QOUT+
RFIN
GC1
4
5
Applications
● VSATs
● Navigation Systems
● Satellite Set-Top Box
● DBS Tuner
FREQUENCY
SYNTHESIZER
DIV2/DIV4
EP
V
6
7
V
CC_LO
CC_DIG
V
REFOUT
CC_VCO
Ordering Information appears at end of data sheet.
8
9
10
11
12
13
14
19-7601; Rev 1; 9/16
MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Absolute Maximum Ratings
V
to GND.........................................................-0.3V to +3.9V
Operating Temperature Range..............................-40°C to +85°C
Junction Temperature.......................................................+150°C
Storage Temperature Range...............................-65°C to +160°C
Lead Temperature (soldering, 10s)...................................+300°C
Soldering Temperature (reflow)........................................+260°C
CC_
All Other Pins to GND.................................-0.3V to (V
+ 0.3V)
CC
RF Input Power: RFIN.....................................................+10dBm
BYPVCO, CPOUT, XTAL, REFOUT, IOUT_, QOUT_, IDC_,
QDC_ to GND Short-Circuit Protection...............................10s
Continuous Power Dissipation (T = +70°C)
A
TQFN (derate 34.5mW/°C above +70°C)......................2.75W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC Electrical Characteristics
(MAX2121 Evaluation Kit: V
= +3.13V to +3.47V, f
= 27MHz, T = -40°C to +85°C, V
= +0.5V (max gain), default register
CC_
XTAL
A
GC1
settings except BBG[3:0] = 1011, LPF[7:0] =97h. No input signals at RF, baseband I/Os are open circuited. Typical values measured
at V = +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SUPPLY
Supply Voltage (V
)
3.13
3.3
148
3
3.47
200
V
CC_
Receive mode, bit STBY = 0
Standby mode, bit STBY = 1
Supply Current
mA
ADDRESS SELECT INPUT (ADDR)
Digital Input-Voltage High, V
2.4
-50
V
IH
Digital Input-Voltage Low, V
0.5
50
V
IL
Digital Input-Current High, I
µA
µA
IH
Digital Input-Current Low, I
IL
ANALOG GAIN-CONTROL INPUT (GC1)
Input Voltage Range
Maximum gain = 0.5V
0.5
-50
2.7
V
Input Bias Current
+50
µA
VCO TUNING VOLTAGE INPUT (TUNEVCO)
Input Voltage Range
0.4
2.3
V
2-WIRE SERIAL INPUTS (SCL, SDA)
Clock Frequency
400
kHz
V
0.7 x
Input Logic-Level High
Input Logic-Level Low
V
CC
0.3 x
V
V
CC
Input Leakage Current
Digital inputs = GND or V
±0.1
±1
µA
CC
2-WIRE SERIAL OUTPUT (SDA)
Output Logic-Level Low
I
= 1mA (Note 2)
0.4
V
SINK
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
AC Electrical Characteristics
(MAX2121 Evaluation Kit: V
= +3.13V to +3.47V, f = 27MHz, T = -40°C to +85°C, default register settings except BBG[3:0] = 1111,
CC_
XTAL A
LPF[7:0] = 97h. Typical values measured at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
A
CC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MAIN SIGNAL PATH PERFORMANCE
Minimum Gain
f
= 2175MHz
72
78
4
dB
dB
IN
Gain Flatness
925MHz to 2250MHz (Note 2)
(Note 3)
6
Input Frequency Range
RF Gain-Control Range (GC1)
Baseband Gain-Control Range
In-Band Input IP3
925
65
2250
MHz
dB
0.5V < V
< 2.7V
73
13.5
+2
GC1
Bits BBG[3:0] = 1111 to 0000
11.5
dB
(Note 4)
(Note 5)
(Note 6)
dBm
dBm
dBm
Out-of-Band Input IP3
Input IP2
+15
+40
V
is set to 0.5V (maximum RF gain) and BBG[3:0] is
GC1
adjusted to give a 1V
baseband output level for a
8
P-P
-75dBm CW input tone at 1500MHz
Noise Figure
dB
dB
Starting with the same BBG[3:0] setting as above, V
is adjusted to back off RF gain by 10dB (Note 2)
GC1
9
12
Minimum RF Input Return Loss
925MHz < f <ꢀ2175MHz,ꢀinꢀ75Ωꢀsystem
12
RF
BASEBAND OUTPUT CHARACTERISTICS
Nominal Output Voltage Swing
I/Q Amplitude Imbalance
R
ꢀ=ꢀ200Ω//5pF
0.5
1
V
P-P
LOAD
Measured at 500kHz
Measured at 500kHz
±1
dB
I/Q Quadrature Phase Imbalance
3.5
Degrees
Single-Ended I/Q Output
Impedance
Real Z , from 1MHz to 140MHz
O
24
3
Ω
Output 1dB Compression Voltage
Differential
V
P-P
Baseband Highpass -3dB
Frequency Corner
47nF capacitors at IDC_, QDC_
400
Hz
BASEBAND LOWPASS FILTERS (5th-Order Butterworth with 1st-Order Group Delay Compensation)
Typical Filter Bandwidth Range
(-3dB)
LPF[7:0] = 2Eh to 97h
40
124
±10
MHz
Rejection Ratio
At 247.5MHz, LPF[7:0] = 97h
Up to 0.5dB bandwidth
31
dB
ns
%
Group Delay
1.0
3dB Bandwidth Tolerance
FREQUENCY SYNTHESIZER
RF-Divider Frequency Range
RF-Divider Range (N)
925
19
12
1
2175
251
30
MHz
MHz
Reference-Divider Frequency Range
Reference-Divider Range (R)
1
Phase-Detector Comparison
Frequency
12
30
MHz
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
AC Electrical Characteristics (continued)
(MAX2121 Evaluation Kit: V
= +3.13V to +3.47V, f = 27MHz, T = -40°C to +85°C, default register settings except BBG[3:0] = 1111,
CC_
XTAL A
LPF[7:0] = 97h. Typical values measured at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
A
CC
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION
Guaranteed LO Frequency Range
925
2250
f
f
f
= 10kHz
= 100kHz
= 1MHz
-97
OFFSET
OFFSET
OFFSET
LO Phase Noise
-100
-122
dBc/Hz
XTAL/REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER
XTAL Oscillator Frequency
Parallel-resonance-mode crystal (Note 7)
AC-coupled sine-wave input
12
30
MHz
Range f
XTAL
Input Overdrive Level
0.5
1
1
2.0
8
V
P-P
XTAL Output-Buffer Divider Range
XTAL Output Voltage Swing
XTAL Output Duty Cycle
—
12MHz to 30MHz, C
= 10pF
1
1.5
50
2
V
LOAD
P-P
%
Note 1: Min/max values are production tested at T = +25°C. Min/max limits at T = -40°C and T = +85°C are guaranteed by
A
A
A
design and characterization.
Note 2: Guaranteed by design and characterization at T = +25°C.
A
Note 3: Input gain range specifications met over this band.
Note 4: In-band IIP3 test conditions: GC1 set to provide the nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
LO
-26dBm each are applied at 2174MHz and 2175MHz. The IM3 tone at 3MHz is measured at baseband, but is referred to
the RF input.
Note 5: Out-of-band IIP3 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
LO
-20dBm each are applied at 1919MHz and 1663MHz. The IM3 tone at 5MHz is measured at baseband, but is referred to
the RF input.
Note 6: Input IP2 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz
to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm
LO
each are applied at 925MHz and 1250MHz. The IM2 tone at 5MHz is measured at baseband, but is referred to the RF input.
Note 7: See Table 16 for crystal ESR requirements.
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Typical Operating Characteristics
(MAX2121 Evaluation Kit: V
= +3.3V, T = +25°C, baseband output frequency = 5MHz, V = +1.2V, default register settings except
CC
A
GC1
BBG[3:0] = 1011, LPF[7:0] = 97h, unless otherwise noted.)
STANDBY SUPPLY CURRENT
SUPPLY CURRENT vs. SUPPLY VOLTAGE
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. LPF[7:0]
toc01a
150
145
140
135
130
125
120
175
170
165
160
155
150
145
140
135
130
125
3.0
T
= +85°C
= +25°C
= -40°C
A
2.5
T
= +85°C
= -40°C
A
T
A
2.0
1.5
1.0
T
A
T
A
46
62
78
94
110 126 142 158
3.1
3.2
3.3
3.4
3.5
3.1
3.2
3.3
3.4
3.5
LPF[7:0] (DECIMAL)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
QUADRATURE PHASE ERROR
vs. LO FREQUENCY
QUADRATURE MAGNITUDE MATCHING
vs. LO FREQUENCY
HD3 vs. V
OUT
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
f
= 50MHz
f
= 50MHz
BASEBAND
BASEBAND
T
A
= +25°C
T
A
= -40°C
T
= -40°C
A
T
A
= +85°C
1150
T
= +85°C
1900
A
T
A
= +25°C
1.0
1.5
2.0
(V
2.5
3.0
900
1150
1400
1650
2150
900
1400
1650
1900
2150
V
)
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
OUT P-P
QUADRATURE PHASE ERROR
vs. BASEBAND FREQUENCY
QUADRATURE MAGNITUDE MATCHING
vs. BASEBAND FREQUENCY
BASEBAND FILTER FREQUENCY
RESPONSE
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
0
-5
f
= 1425MHz
f
= 1425MHz
LO
LO
T
= -40°C
A
-10
-15
-20
-25
-30
-35
-40
T
A
= +85°C
A
T
= +25°C
A
T
= +25°C
LPF=151d
T
= +85°C
= -40°C
A
T
A
LPF=84d
100 150
LPF=46d
50
LPF=121d
200
0
250
300
0.1
1
10
100
0.1
1
10
100
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Typical Operating Characteristics (continued)
(MAX2121 Evaluation Kit: V
= +3.3V, T = +25°C, baseband output frequency = 5MHz, V = +1.2V, default register settings except
CC
A
GC1
BBG[3:0] = 1011, LPF[7:0] = 97h, unless otherwise noted.)
BASEBAND FILTER 3dB FREQUENCY
vs. TEMPERATURE
LOWPASS FILTER 3dB FREQUENCY
BASEBAND FILTER FREQUENCY RESPONSE
1
vs. LPF[7:0]
toc10a
130
1.00
0.75
0.50
0.25
0
NORMALIZED AT T = +25°C
A
0
120
110
100
90
-1
-2
-3
-4
-5
T
A
= +25°C
80
-0.25
-0.50
-0.75
-1.00
-6
70
-7
60
-8
50
-9
40
-10
46
62
78
94
110 126 142 158
0
25
50
75
100
125
150
-40
-20
0
20
40
60
80
LPF[7:0] (DECIMAL)
BASEBAND FREQUENCY (MHz)
TEMPERATURE (°C)
NOISE FIGURE vs. LO FREQUENCY
BASEBAND FILTER HIGHPASS
FREQUENCY RESPONSE
VOLTAGE GAIN vs. V
(T = +25°C)
A
GC1
80
70
60
50
40
30
20
10
0
11.0
0
-1
10.5
10.0
9.5
ADJUST BBG[3:0] FOR 1V
P-P
BBG[3:0] = 1111
BASEBAND OUTPUT WITH
PIN = -75dBm AND V = 0.5V
-2
GC1
-3
-4
9.0 10dB BACKED OFF GAIN
-5
-6
8.5
8.0
7.5
7.0
-7
-8
-9
-10
100
1000
10,000
0
0.5
1.0
1.5
(V)
2.0
2.5
3.0
900
1150
LO FREQUENCY (MHz)
1400
1650
1900
2150
BASEBAND FREQUENCY (Hz)
V
GC1
IN-BAND IIP3 vs. INPUT POWER
NOISE FIGURE vs. INPUT POWER
OUT-OF-BAND IIP3 vs. INPUT POWER
20
10
35
30
25
20
15
10
5
30
20
10
0
ADJUST BBG[3:0] for 1V
SEE NOTE 5 ON PAGE 4 FOR
CONDITIONS
P-P
SEE NOTE 4 ON PAGE 4 FOR
CONDITIONS
BASEBAND OUTPUT WITH PIN = -75dBm
AND V = -0.5V, f = 1500MHz
GC1
LO
0
-10
-20
-30
-40
-50
-60
-10
-20
-30
-75 -65 -55 -45 -35 -25 -15 -5
INPUT POWER (dBm)
-75
-65
-55
-45
-35
-75 -65 -55 -45 -35 -25 -15 -5
INPUT POWER (dBm)
INPUT POWER (dBm)
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Typical Operating Characteristics (continued)
(MAX2121 Evaluation Kit: V
= +3.3V, T = +25°C, baseband output frequency = 5MHz, V
= +1.2V, default register settings except
GC1
CC
A
BBG[3:0] = 1011, LPF[7:0] = 97h, unless otherwise noted.)
INPUT RETURN LOSS vs. FREQUENCY
IIP2 vs. INPUT POWER
0
40
SEE NOTE 6 ON PAGE 4
FOR CONDITIONS
35
-5
30
25
20
15
10
5
V
GC1
= 0.5V
-10
-15
-20
-25
0
-5
V
GC1
= 2.7V
-10
900 1125 1350 1575 1800 2025 2052
FREQUENCY (MHz)
-75 -65 -55 -45 -35 -25 -15 -5
INPUT POWER (dBm)
PHASE NOISE AT 10kHz OFFSET vs.
CHANNEL FREQUENCY
PHASE NOISE vs. OFFSET FREQUENCY
-90
-90
-100
-110
-120
-130
-95
-100
f
= 1800MHz
LO
-105
925 1115 1305 1495 1685 1875 2065 2255
1.0E+03
1.0E+04
1.0E+05
1.0E+06
CHANNEL FREQUENCY (MHz)
OFFSET FREQUENCY (Hz)
VCO: KV vs. VTUNE
LO LEAKAGE vs. LO FREQUENCY
450
400
350
300
250
200
150
100
50
-70
MEASURED AT RF INPUT
SUB-BAND 23
SUB-BAND 12
-75
-80
-85
-90
SUB-BAND 0
0.5
0
0
1.0
1.5
2.0
2.5
3.0
925
1175
1425
1675
1925
2175
VTUNE (V)
LO FREQUENCY (MHz)
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Pin Configuration
TOP VIEW
V
28
27
26
25
24
23
22
21
IDC+
1
2
3
CC_RF2
+
IOUT-
IOUT+
V
20
19
18
17
16
15
CC_RF1
GND
MAX2121B
QOUT-
QOUT+
RFIN
GC1
4
5
V
6
7
V
CC_LO
CC_DIG
EP
V
REFOUT
CC_VCO
8
9
10
11
12
13
14
TQFN
(5mm x 5mm)
Pin Description
PIN
NAME
FUNCTION
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
1
V
CC_RF2
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
2
V
CC_RF1
3
4
GND
RFIN
Ground. Connect to board’s ground plane for proper operation.
Widebandꢀ75ΩꢀRFꢀInput.ꢀConnectꢀtoꢀanꢀRFꢀsourceꢀthroughꢀaꢀDC-blockingꢀcapacitor.
RF Gain-Control Input. High-impedance analog input with a 0.5V to 2.7V operating range.
5
GC1
V
= 0.5V corresponds to the maximum gain setting.
GC1
DC Power Supply for LO Generation Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
6
V
CC_LO
DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF
capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground
connections.
7
V
CC_VCO
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Pin Description (continued)
PIN
NAME
FUNCTION
Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to the pin.
Do not share capacitor ground vias with other ground connections.
8
BYPVCO
High-ImpedanceꢀVCOꢀTuneꢀInput.ꢀConnectꢀtheꢀPLLꢀloopꢀfilterꢀoutputꢀdirectlyꢀtoꢀthisꢀpinꢀwithꢀasꢀshortꢀofꢀaꢀ
connection as possible.
9
TUNEVCO
10
11
GNDTUNE Ground for TUNEVCO. Connect to the PCB ground plane.
GNDSYN Ground for Synthesizer. Connect to the PCB ground plane.
Charge-Pump Output. Connect this output to the PLL loop filter input with the shortest connection
possible.
12
CPOUT
DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF
13
V
capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground
connections.
CC_SYN
XTAL
Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal through a series 1nF
capacitor. See the Typical Application Circuit.
14
15
REFOUT Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external circuitry.
DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF
16
V
capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other ground
connections.
CC_DIG
17
18
19
20
21
22
23
24
QOUT+
QOUT-
IOUT+
IOUT-
IDC+
Quadrature Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
In-Phase Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
I-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to IDC+.
Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to QDC+.
IDC-
QDC+
QDC-
DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
25
V
CC_BB
26
27
28
—
SDA
SCL
2-WireꢀSerial-DataꢀInterface.ꢀRequiresꢀ≥ꢀ1kΩꢀpullupꢀresistorꢀtoꢀV
.
CC
2-WireꢀSerial-ClockꢀInterface.ꢀRequiresꢀ≥ꢀ1kΩꢀpullupꢀresistorꢀtoꢀV
.
CC
ADDR
EP
Address. Must be connected to either ground (logic 0) or supply (logic 1).
Exposed Pad. Solder evenly to the board’s ground plane for proper operation.
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
each bit name and the bit usage information for all regis-
ters. Note that all registers must be written after and no
earlierꢀ thanꢀ 100μsꢀ afterꢀ theꢀ deviceꢀ isꢀ poweredꢀ up.ꢀTheꢀ
VCO autoselection circuit is triggered by writing to register
5. Thus register 5 should be the last register to be written
in order to ensure proper PLL lock.
Detailed Description
Register Description
The MAX2121B includes 12 user-programmable registers
and two read-only registers. See Table 1 for register con-
figurations. The register configuration of Table 1 shows
Table 1. Register Configuration
MSB
LSB
REG
NUMBER
REGISTER READ/
REG
DATA BYTE
NAME
WRITE ADDRESS
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
N-Divider
MSB
FRAC
1
1
2
3
4
5
Write
Write
Write
Write
Write
0x00
0x01
0x02
0x03
0x04
N[14]
N[13]
N[12]
N[11]
N[10]
N[9]
N[8]
N-Divider
LSB
N[7]
N[6]
N[5]
N[4]
N[3]
F[19]
F[11]
F[3]
N[2]
N[1]
N[0]
Charge
Pump
CPMP[1]
0
CPMP[0] CPLIN[1] CPLIN[0]
F[18] F[17] F[16]
0
0
1
F-Divider
MSB
F[15]
F[7]
F[14]
F[13]
F[12]
F[10]
F[2]
F[9]
F[1]
F[8]
F[0]
F-Divider
LSB
F[6]
F[5]
F[4]
R[4]
XTAL
Buffer and
Reference
Divider
6
Write
0x05
XD[2]
XD[1]
XD[0]
R[3]
R[2]
R[1]
R[0]
7
8
PLL
Write
Write
0x06
0x07
D24
CPS
ICP
X
X
X
X
X
VCO
VCO[4]
VCO[3]
VCO[2]
VCO[1]
VCO[0]
VAS
ADL
ADE
Lowpass
Filter
9
Write
Write
0x08
0x09
0x0A
LPF[7]
STBY
X
LPF[6]
X
LPF[5]
LPF[4]
X
LPF[3]
BBG[3]
LPF[2] LPF[1] LPF[0]
PWDN
0
10
11
Control
BBG[2] BBG[1] BBG[0]
RFMIX RFVGA FE
PLL
0
DIV
0
VCO
0
BB
0
Shutdown Write
0
0
0
LD
LD
LD
CPTST[2] CPTST[1] CPTST[0]
TURBO
1
12
13
Test
Write
0x0B
X
MUX[2] MUX[1] MUX[0]
0
0
0
0
0
0
Status
Byte-1
Read
Read
0x0C
0x0D
POR
VASA
VASE
LD
X
X
X
X
Status
Byte-2
14
VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
1 = Set to 1 for factory-tested operation.
X = Don’t care.
0 = Set to 0 for factory-tested operation.
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Table 2. N-Divider MSB Register (Address: 0x00)
BIT NAME BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
FRAC
7
1
Users must program to 1 upon powering up the device.
SetsꢀtheꢀmostꢀsignificantꢀbitsꢀofꢀtheꢀPLLꢀinteger-divideꢀnumberꢀ(N).ꢀNꢀcanꢀ
range from 19 to 251.
N[14:8]
6–0
0000000
Table 3. N-Divider LSB Register (Address: 0x01)
BIT NAME BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
SetsꢀtheꢀleastꢀsignificantꢀbitsꢀofꢀtheꢀPLLꢀinteger-divideꢀnumber.ꢀNꢀcanꢀ
range from 19 to 251.
N[7:0] 7–0
00100011
Table 4. Charge-Pump Register (Address: 0x02)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Charge-pump minimum pulse width. Users must program to 00 upon
powering up the device.
CPMP[1:0]
CPLIN[1:0]
F[19:16]
00
00
7–6
Controls charge-pump linearity. Users must program to 01 upon powering
up the device.
5–4
Setsꢀtheꢀ4ꢀmostꢀsignificantꢀbitsꢀofꢀtheꢀPLLꢀfractionalꢀdivideꢀnumber.ꢀ
Default value is F = 194,180 decimal.
3–0
0010
Table 5. F-Divider MSB Register (Address: 0x03)
BIT NAME BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
SetsꢀtheꢀmostꢀsignificantꢀbitsꢀofꢀtheꢀPLLꢀfractional-divideꢀnumberꢀ(F).ꢀ
Default value is F = 194,180 decimal.
F[15:8] 7–0
11110110
Table 6. F-Divider LSB Register (Address: 0x04)
BIT NAME BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
SetsꢀtheꢀleastꢀsignificantꢀbitsꢀofꢀtheꢀPLLꢀfractional-divideꢀnumberꢀ(F).ꢀ
Default value is F = 194,180 decimal.
F[7:0] 7–0
10000100
Table 7. XTAL Buffer and Reference Divider Register (Address: 0x05)
BIT NAME BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Sets the crystal-divider setting.
000 = Divide by 1.
001 = Divide by 2.
XD[2:0]
R[4:0]
7–5
4–0
000
011 = Divide by 3.
100 = Divide by 4.
101 through 110 = All divide values from 5 (101) to 7 (110).
111 = Divide by 8.
Sets the PLL reference-divider (R) number. Users must program to 00001
upon powering up the device.
00001
00001 = Divide by 1; other values are not tested.
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Table 8. PLL Register (Address: 0x06)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
VCO divider setting.
D24
7
6
1
1
0ꢀ=ꢀDivideꢀbyꢀ2.ꢀUseꢀforꢀLOꢀfrequenciesꢀ≥ꢀ1125MHz.
1 = Divide by 4. Use for LO frequencies < 1125MHz.
Charge-pump current mode.
0 = Charge-pump current controlled by ICP bit.
1 = Charge-pump current controlled by VCO autoselect (VAS).
CPS
Charge-pump current.
0 = 600µA typical.
1 = 1200µA typical.
ICP
X
5
0
4–0
X
Don’t care.
Table 9. VCO Register (Address: 0x07)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Controls which VCO is activated when using manual VCO programming mode.
This also serves as the starting point for the VCO autoselection (VAS) mode.
VCO[4:0]
VAS
7–3
2
11001
1
VCO autoselection (VAS) circuit.
2
0 = Disable VCO selection must be programmed through I C.
1 = Enable VCO selection controlled by autoselection circuit.
Enables or disables the VCO tuning voltage ADC latch when the VCO
autoselect mode (VAS) is disabled.
0 = Disables the ADC latch.
ADL
ADE
1
0
0
0
1 = Latches the ADC value.
Enables or disables VCO tuning voltage ADC read when the VCO autoselect
mode (VAS) is disabled.
0 = Disables ADC read.
1 = Enables ADC read.
Table 10. Lowpass Filter Register (Address: 0x08)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Setsꢀtheꢀbasebandꢀlowpassꢀfilterꢀcornerꢀfrequency.ꢀ
f
f
f
= 0.8 x LPF[7:0]d +3.2
-3dB
LPF[7:0]
7–0
01001011
= 40MHz (LPF[7:0] = 46d = 2Eh)
= 124MHz (LPF[7:0] = 151d = 97h)
-3dBmin
-3dBmax
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Table 11. Control Register (Address: 0x09)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Software standby control.
0 = Normal operation.
STBY
7
0
1 = Disables the signal path and frequency synthesizer leaving only the
2-wire bus, crystal oscillator, XTALOUT buffer, and XTALOUT buffer divider
active.
X
PWDN
X
6
5
4
X
0
Don’t care.
Factory use only.
0 = Normal operation; other value is not tested.
X
Don’t care.
Baseband gain setting (1dB typical per step).
0000 = Minimum gain (0dB, default).
…
BBG[3:0]
3–0
0000
1111 = Maximum gain (15dB typical).
Table 12. Shutdown Register (Address: 0x0A)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
X
7
X
Don’t care.
PLL enable.
PLL
6
0
0 = Normal operation.
1 = Shuts down the PLL. Value not tested.
Divider enable.
DIV
VCO
BB
5
4
3
2
1
0
0
0
0
0
0
0
0 = Normal operation.
1 = Shuts down the divider. Value not tested.
VCO enable.
0 = Normal operation.
1 = Shuts down the VCO. Value not tested.
Baseband enable.
0 = Normal operation.
1 = Shuts down the baseband. Value not tested.
RF mixer enable.
0 = Normal operation.
1 = Shuts down the RF mixer. Value not tested.
RFMIX
RFVGA
FE
RF VGA enable.
0 = Normal operation.
1 = Shuts down the RF VGA. Value not tested.
Front-end enable.
0 = Normal operation.
1 = Shuts down the front-end. Value not tested.
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Table 13. Test Register (Address: 0x0B)
BIT NAME
CPTST[2:0]
X
BIT LOCATION (0 = LSB)
DEFAULT
FUNCTION
Charge-pump test modes.
7–5
4
000
X
000 = Normal operation (default).
Don’t care.
Charge-pump fast lock.
Users must program to 1 after powering up the device.
TURBO
3
1
REFOUT output.
000 = Normal operation; other values are not tested.
LDMUX[2:0]
2–0
000
Table 14. Status Byte-1 Register (Address: 0x0C)
BIT NAME
BIT LOCATION (0 = LSB)
FUNCTION
Power-on reset status.
0 = Chip status register has been read with a stop condition since last power-on.
1 = Power-on reset (power cycle) has occurred. Default values have been loaded in
registers.
POR
7
Indicates whether VCO autoselection was successful.
VASA
VASE
6
5
0 = Indicates the autoselect function is disabled or unsuccessful VCO selection.
1 = Indicates successful VCO autoselection.
Status indicator for the autoselect function.
0 = Indicates the autoselect function is active.
1 = Indicates the autoselect process is inactive.
PLL lock detector. TURBO bit must be programmed to 1 for valid LD reading.
LD
X
4
0 = Unlocked.
1 = Locked.
3–0
Don’t care.
Table 15. Status Byte-2 Register (Address: 0x0D)
BIT NAME
BIT LOCATION (0 = LSB)
FUNCTION
VCOSBR[4:0]
7–3
VCO band readback.
VAS ADC output readback.
000 = Out of lock.
001 = Locked.
010 = VAS locked.
101 = VAS locked.
110 = Locked.
ADC[2:0]
2–0
111 = Out of lock.
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Slave Address
2-Wire Serial Interface
2
The MAX2121B has a 7-bit slave address that must be sent
to the device following a START condition to initiate com-
munication. The slave address is internally programmed to
1100000. The eighth bit (R/W) following the 7-bit address
determines whether a read or write operation occurs.
The MAX2121B uses a 2-wire I C-compatible serial inter-
face consisting of a serial-data line (SDA) and a serial clock
line (SCL). SDA and SCL facilitate bidirectional communi-
cation between the MAX2121B and the master at clock fre-
quencies up to 400kHz. The master initiates a data transfer
on the bus and generates the SCL signal to permit data
transfer. The MAX2121B behaves as a slave device that
transfers and receives data to and from the master. SDA
and SCL must be pulled high with external pullup resistors
(1kΩꢀorꢀgreater)ꢀforꢀproperꢀbusꢀoperation.ꢀPullupꢀresistorsꢀ
The MAX2121B continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept or
send data depending on the R/W bit (Figure 1).
should be referenced to the MAX2121B’s V
.
CC
The write/read address is C0/C1 if ADDR pin is connected
to ground. The write/read address is C2/C3 if the ADDR
pin is connected to V
One bit is transferred during each SCL clock cycle. A mini-
mum of nine clock cycles is required to transfer a byte in
or out of the MAX2121B (8 bits and an ACK/NACK). The
data on SDA must remain stable during the high period of
the SCL clock pulse. Changes in SDA while SCL is high
and stable are considered control signals (see the START
and STOP Conditions). Both SDA and SCL remain high
when the bus is not busy.
.
CC
Write Cycle
When addressed with a write command, the MAX2121B
allows the master to write to a single register or to multiple
successive registers.
A write cycle begins with the bus master issuing a START
condition followed by the seven slave address bits and
a write bit (R/W = 0). The MAX2121B issues an ACK if
the slave address byte is successfully received. The bus
master must then send to the slave the address of the
first register it wishes to write to (see Table 1 for regis-
ter addresses). If the slave acknowledges the address,
the master can then write one byte to the register at the
specified address. Data is written beginning with the most
significant bit. The MAX2121B again issues an ACK if the
data is successfully written to the register. The master
can continue to write data to the successive internal reg-
isters with the MAX2121B acknowledging each success-
ful transfer, or it can terminate transmission by issuing a
STOP condition. The write cycle does not terminate until
the master issues a STOP condition.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition on
SDA while SCL is high.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit (ACK)
or a not-acknowledge bit (NACK). Both the master and
the MAX2121B (slave) generate acknowledge bits. To
generate an acknowledge, the receiving device must
pull SDA low before the rising edge of the acknowledge-
related clock pulse (ninth pulse) and keep it low during the
high period of the clock pulse.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse. Monitoring
the acknowledge bits allows for detection of unsuccessful
data transfers. An unsuccessful data transfer happens if a
receiving device is busy or if a system fault has occurred.
In the event of an unsuccessful data transfer, the bus
master must reattempt communication at a later time.
SLAVE ADDRESS
1
1
0
0
0
0
0
S
ACK
9
R/W
SDA
SCL
1
2
3
4
5
6
7
8
Figure 1. MAX2121B Slave Address Byte with ADDR Pin
Connected to Ground
WRITE DEVICE
ADDRESS
WRITE REGISTER
ADDRESS
WRITE DATA TO
REGISTER 0x00
WRITE DATA TO
REGISTER 0x01
WRITE DATA TO
REGISTER 0x02
R/W
ACK
—
AC
—
ACK
—
ACK
—
ACK
—
START
STOP
1100000
0
0x00
0x0E
0xD8
0xE1
Figure 2. Example: Write Registers 0, 1, and 2 with 0x0E, 0xD8, and 0xE1, respectively.
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
ACK/
NACK
R/W
WRITE DEVICE ADDRESS
1100000
ACK READ FROM STATUS BYTE-1 REGISTER ACK
READ FROM STATUS BYTE-2 REGISTER
—
START
STOP
1
—
—
—
—
Figure 3. Example: Receive Data from Read Registers
Read Cycle
Table 16. Maximum Crystal ESR
Requirement
When addressed with a read command, the MAX2121B
allows the master to read back a single register, or mul-
tiple successive registers.
ESR
(Ω)
XTAL FREQUENCY (MHz)
12 < f ꢀ≤ꢀ14
MAX
80
XTAL
A read cycle begins with the bus master issuing a START
condition followed by the seven slave address bits and
a write bit (R/W = 0). The MAX2121B issues an ACK if
the slave address byte is successfully received. The bus
master must then send the address of the first register it
wishes to read (see Table 1 for register addresses). The
slave acknowledges the address. Then, a START condi-
tion is issued by the master, followed by the seven slave
address bits and a read bit (R/W = 1). The MAX2121B
issues an ACK if the slave address byte is successfully
received. The MAX2121B starts sending data MSB first
with each SCL clock cycle. At the 9th clock cycle, the
master can issue an ACK and continue to read succes-
sive registers, or the master can terminate the transmis-
sion by issuing a NACK. The read cycle does not termi-
nate until the master issues a STOP condition.
60
14 < f
ꢀ≤ꢀ30
XTAL
Baseband Lowpass Filter
The MAX2121B includes a programmable on-chip 5th-
order Butterworth filter with 1st-order group delay com-
pensation. The filter -3dB corner frequency can be adjust-
ed to approximately 40MHz to 124MHz by programming
the LPF[7:0] register using the following equation:
LPF[7:0]dec = 1.25(f
is in units of MHz.
- 3.2)
-3dB
where f
-3dB
The supply current is dependant on the filter bandwidth
setting. See the Supply Current vs. LPF[7:0] graph in the
Typical Operating Characteristics.
DC Offset Cancellation
The DC offset cancellation is required to maintain the I/Q
output dynamic range. Connecting an external capacitor
between IDC+ and IDC- forms a highpass filter for the I
channel and an external capacitor between QDC+ and
QDC- forms a highpass filter for the Q channel. Keep the
value of the external capacitor less than 47nF to form a
typical highpass corner of 250Hz.
Figure 3 illustrates an example in which registers 0, 1, and
2 are read back.
Applications Information
The MAX2121B downconverts RF signals in the 925MHz
to 2175MHz range directly to the baseband I/Q signals.
RF Input
XTAL Oscillator
The RF input of the MAX2121B is internally matched to
75Ω.ꢀ Onlyꢀ aꢀ DC-blockingꢀ capacitorꢀ isꢀ needed.ꢀ Seeꢀ theꢀ
Typical Application Circuit.
The MAX2121B contains an internal reference oscilla-
tor, reference output divider, and output buffer. All that
is required is to connect a crystal through a series 1nF
capacitor. To minimize parasitics, place the crystal and
series capacitor as close as possible to pin 14 (XTAL).
See Table 16 for crystal (XTAL) ESR (equivalent series
resistance) requirements.
RF Gain Control
The MAX2121B features a variable-gain low-noise ampli-
fier providing 73dB of RF gain range. The voltage con-
trol (VGC) range is 0.5V (minimum attenuation) to 2.7V
(maximum attenuation).
Programming the Fractional
N- Synthesizer
Baseband Variable-Gain Amplifier
The receiver baseband variable-gain amplifiers provide
15dB of gain control range programmable in 1dB steps.
The VGA gain can be serially programmed through the I C
The MAX2121B utilizes a fractional-N type synthesizer
for LO frequency programming. To program the frequency
synthesizer, the N and F values are encoded as straight
binary numbers. Determination of these values is illus-
trated by the following example:
2
interface by setting bits BBG[3:0] in the Control register.
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
f
f
is 2170MHz
LO
Table 17. ADC Trip Points and Lock Status
is 27 MHz
XTAL
ADC[2:0]
LOCK STATUS
Out of lock
Locked
Phase-detector comparison frequency is from 12MHz and
30MHz
000
001
010
VAS locked
VAS locked
Locked
R divider = R[4:0] = 1
101
f
= 27MHz/1 = 27MHz
COMP
110
D = f /f
= 2170/27 = 80.37037
LO COMP
111
Out of lock
Integer portion:
N = 80
the Status Byte-2 register (see Table 15). If the search
is unsuccessful, VASA is cleared and VASE is set. This
indicates that searching has ended but no good VCO has
been found, and occurs when trying to tune to a frequency
outside the VCO’s specified frequency range.
N[14:8] = 0
N[7:0] = 0101 0000
Fractional portion:
20
Refer to Application Note 4256: Extended
Characterization for the MAX2112/MAX2120 Satellite
Tuners.
F = 0.370370 x 2 = 388,361 (round up the decimal portion)
F = 0101 1110 1101 0000 1001
Note: When changing LO frequencies, all the divider
registers (integer and fractional) must be programmed to
activate the VAS function regardless of whether individual
registers are changed.
3-Bit ADC
The MAX2121B has an internal 3-bit ADC connected to
the VCO tune pin (TUNEVCO). This ADC can be used for
checking the lock status of the VCOs.
VCO Autoselect (VAS)
Table 17 summarizes the ADC output bits and the VCO
lock indication. The VCO autoselect routine only selects
a VCO in the “VAS locked” range. This allows room for
a VCO to drift over temperature and remain in a valid
“locked” range.
The MAX2121B includes 24 VCOs. The local oscillator
frequency can be manually selected by programming the
VCO[4:0] bits in the VCO register. The selected VCO is
reported in the Status Byte-2 register (see Table 15).
Alternatively, the MAX2121B can be set to autonomously
choose a VCO by setting the VAS bit in the VCO reg-
ister to logic-high. The VAS routine is initiated once the
F-Divider LSB register word (register 5) is loaded.
The ADC must first be enabled by setting the ADE bit in
the VCO register. The ADC reading is latched by a sub-
sequent programming of the ADC latch bit (ADL = 1). The
ADC value is reported in the Status Byte-2 register (see
Table 15).
Thus it is important to write register 5 after any of the fol-
lowing PLL related bits have been changed:
Standby Mode
N-Divider bits (registers 1 and/or 2)
F-Divider bits (registers 3 and/or 4)
Reference Divider bits (register 6)
D24, CPS, or ICP bits (register 7)
The MAX2121B features normal operating mode and
2
standby mode using the I C interface. Setting a logic-high
to the STBY bit in the Control register puts the device into
standby mode, during which only the 2-wire-compatible
bus, the crystal oscillator, the XTAL buffer, and the XTAL
buffer divider are active.
This will ensure all intended bits have been programmed
before the VAS is initiated and the PLL is locked. The VCO
value programmed in the VCO[4:0] register serves as the
starting point for the automatic VCO selection process.
In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active mode.
Default register values are provided for the user’s con-
venience only. It is the user’s responsibility to load all
theꢀ registersꢀ noꢀ soonerꢀ thanꢀ 100μsꢀ afterꢀ theꢀ deviceꢀ isꢀ
powered up.
During the selection process, the VASE bit in the Status
Byte-1 register is cleared to indicate the autoselection
function is active. Upon successful completion, bits VASE
and VASA are set and the VCO selected is reported in
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Typical Application Circuit
SERIAL-DATA
INPUT/OUTPUT
SERIAL-CLOCK
INPUT
V
CC
V
CC
28
27
26
25
24
23
22
+
IDC+
V
V
CC_RF2
CC_RF1
21
1
DC OFFSET
CORRECTION
V
CC
INTERFACE LOGIC
AND CONTROL
IOUT-
MAX2121B
20
19
18
17
16
15
2
3
IOUT+
QOUT-
QOUT+
GND
BASEBAND
OUTPUTS
RF INPUT
RFIN
GC1
4
5
V
GC
V
V
CC
CC
FREQUENCY
SYNTHESIZER
DIV2
/DIV4
V
V
CC_LO
CC_DIG
6
7
V
CC
EP
REFOUT
V
CC_VCO
8
9
10
11
12
13
14
V
CC
Layout Considerations
Ordering Information
The MAX2121 EV kit serves as a guide for PCB layout.
Keep RF signal lines as short as possible to minimize
losses and radiation. Use controlled impedance on all
high-frequency traces. For proper operation, the exposed
paddle must be soldered evenly to the board’s ground
plane. Use abundant vias beneath the exposed paddle
for maximum heat dissipation. Use abundant ground
vias between RF traces to minimize undesired coupling.
PART
TEMP RANGE
PIN-PACKAGE
MAX2121BETI+
-40°C to +85°C
28 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
Chip Information
PROCESS: BiCMOS
Bypass each V
pin to ground with a 1nF capacitor
CC
placed as close as possible to the pin.
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 TQFN-EP
T2855+3
21-0140
90-0023
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MAX2121B
L-Band Tuner with Programmable
Baseband Filter
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1
6/15
Initial release
—
9/16
Updated Programming the Fractional N-Synthesizer equation
17
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
©
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
2016 Maxim Integrated Products, Inc.
│ 20
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