MAX2121ETI+ [MAXIM]
Complete Direct-Conversion L-Band Tuner; 完整的直接变频L波段调谐器
| 型号： | MAX2121ETI+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Complete Direct-Conversion L-Band Tuner |
| 文件： | 总19页 (文件大小：330K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5959; Rev 1; 7/12
Complete Direct-Conversion L-Band Tuner
MAX21
General Description
Features
o 925MHz to 2175MHz Frequency Range
o Monolithic VCO
The MAX2121 low-cost, direct-conversion tuner IC is
designed for satellite set-top and VSAT applications.
Low Phase Noise: -97dBc/Hz at 10kHz
The device directly converts the satellite signals from
the LNB to baseband using a broadband I/Q downcon-
verter. The operating frequency range extends from
925MHz to 2175MHz.
No Calibration Required
o High Dynamic Range: -75dBm to 0dBm
o Integrated LP Filters: 123.75MHz
o Single +3.3V 5ꢀ Suꢁꢁly
The device includes an LNA and an RF variable-gain
amplifier, I and Q downconverting mixers, and base-
band lowpass filters and digitally controlled baseband
variable-gain amplifiers. Together, the RF and base-
band variable-gain amplifiers provide more than 80dB
of gain control range.
o Low-Power Standby Mode
o Address Pin for Multituner Aꢁꢁlications
o Differential I/Q Interface
2
o I C 2-Wire Serial Interface
The device includes fully monolithic VCOs, as well as a
complete fractional-N frequency synthesizer.
Additionally, an on-chip crystal oscillator is provided
along with a buffered output for driving additional tuners
and demodulators. Synthesizer programming and device
configuration are accomplished with a 2-wire serial inter-
face. The IC features a VCO autoselect (VAS) function
that automatically selects the proper VCO. For multituner
applications, the device can be configured to have one
of two 2-wire interface addresses. A low-power standby
mode is available whereupon the signal path is shut
down while leaving the reference oscillator, digital inter-
face, and buffer circuits active, providing a method to
reduce power in single and multituner applications.
o Very Small, 5mm x 5mm, 28-Pin TQFN Package
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX2121ETI+
-40°C to +85°C
28 TQFN-EP*
*EP = Exposed pad.
+Denotes a lead(Pb)-free/RoHS-compliant package.
Functional Diagram
28
27
26
25
24
23
22
The device is the most advanced broadband/VSAT
DBS tuner available. The low noise figure eliminates the
need for an external LNA. A small number of passive
components are needed to form a complete broadband
satellite tuner DVB-S2 RF front-end solution. The tuner
is available in a very small, 5mm x 5mm, 28-pin thin
QFN package.
+
21
IDC+
V
V
1
2
3
CC_RF2
DC OFFSET
CORRECTION
INTERFACE LOGIC
AND CONTROL
MAX2121
IOUT-
IOUT+
20
19
18
17
16
15
CC_RF1
GND
QOUT-
QOUT+
RFIN
GC1
4
5
Applications
VSATs
FREQUENCY
SYNTHESIZER
DIV2/DIV4
V
6
7
V
CC_LO
CC_DIG
EP
V
REFOUT
CC_VCO
8
9
10
11
12
13
14
For ꢁricing, delivery, and ordering information, ꢁlease contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1
Complete Direct-Conversion L-Band Tuner
ABSOLUTE MAXIMUM RATINGS
CC_
All Other Pins to GND.................................-0.3V to (V
RF Input Power: RFIN.....................................................+10dBm
BYPVCO, CPOUT, XTAL, REFOUT, IOUT_, QOUT_ , IDC_,
QDC_ to GND Short-Circuit Protection...............................10s
V
to GND .........................................................-0.3V to +3.9V
Operating Temperature Range .............................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
+ 0.3V)
CC
Continuous Power Dissipation (T = +70°C)
A
TQFN (derate 34.5mW/°C above +70°C) ......................2.75W
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
MAX21
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX2121 Evaluation Kit: V
= +3.13V to +3.47V, f
= 27MHz, T = -40°C to +85°C, V
= +0.5V (max gain), default register
CC_
XTAL
A
GC1
settings except BBG[3:0] = 1011. No input signals at RF, baseband I/Os are open circuited. Typical values measured at V
=
CC
+3.3V, T = +25°C, unless otherwise noted.) (Note 1)
A
PARAMETER
SUPPLY
CONDITIONS
MIN
TYP
MAX
UNITS
Supply Voltage (V
)
3.13
3.3
148
3
3.47
200
V
CC_
Receive mode, bit STBY = 0
Standby mode, bit STBY = 1
Supply Current
mA
ADDRESS SELECT INPUT (ADDR)
Digital Input-Voltage High, V
2.4
-50
V
V
IH
Digital Input-Voltage Low, V
0.5
50
IL
Digital Input-Current High, I
µA
µA
IH
Digital Input-Current Low, I
IL
ANALOG GAIN-CONTROL INPUT (GC1)
Input Voltage Range
Maximum gain = 0.5V
0.5
-50
2.7
V
Input Bias Current
+50
µA
VCO TUNING VOLTAGE INPUT (TUNEVCO)
Input Voltage Range
0.4
2.3
V
2-WIRE SERIAL INPUTS (SCL, SDA)
Clock Frequency
400
kHz
V
0.7 x
Input Logic-Level High
Input Logic-Level Low
V
CC
0.3 x
V
V
CC
Input Leakage Current
Digital inputs = GND or V
0.1
1
µA
CC
2-WIRE SERIAL OUTPUT (SDA)
Output Logic-Level Low
I
= 1mA (Note 2)
0.4
V
SINK
2
Complete Direct-Conversion L-Band Tuner
MAX21
AC ELECTRICAL CHARACTERISTICS
(MAX2121 Evaluation Kit: V
= +3.13V to +3.47V, T = -40°C to +85°C, default register settings except BBG[3:0] = 1111. Typical
CC
A
values measured at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
MAIN SIGNAL PATH PERFORMANCE
CONDITIONS
MIN
TYP
MAX
UNITS
Minimum Gain
f
= 2175MHz
72
78
4
dB
dB
IN
Gain Flatness
925MHz to 2175MHz (Note 2)
(Note 3)
6
Input Frequency Range
RF Gain-Control Range (GC1)
Baseband Gain-Control Range
In-Band Input IP3
925
65
2175
MHz
dB
0.5V < V
< 2.7V
73
13.5
+2
GC1
Bits BBG[3:0] = 1111 to 0000
11.5
dB
(Note 4)
(Note 5)
(Note 6)
dBm
dBm
dBm
Out-of-Band Input IP3
Input IP2
+15
+40
V
is set to 0.5V (maximum RF gain) and BBG[3:0]
GC1
is adjusted to give a 1V
baseband output level for a
8
P-P
-75dBm CW input tone at 1500MHz
Noise Figure
dB
dB
Starting with the same BBG[3:0] setting as above,
9
12
V
is adjusted to back off RF gain by 10dB (Note 2)
GC1
Minimum RF Input Return Loss
925MHz < f < 2175MHz, in 75ꢀ system
12
RF
BASEBAND OUTPUT CHARACTERISTICS
Nominal Output Voltage Swing
I/Q Amplitude Imbalance
R
= 200ꢀ//5pF
0.5
1
V
P-P
LOAD
Measured at 500kHz
Measured at 500kHz
1
dB
I/Q Quadrature Phase Imbalance
3.5
Degrees
Single-Ended I/Q Output
Impedance
Real Z , from 1MHz to 140MHz
24
3
ꢀ
O
Output 1dB Compression Voltage Differential
V
P-P
Baseband Highpass -3dB
Frequency Corner
47nF capacitors at IDC_, QDC_
400
Hz
BASEBAND LOWPASS FILTERS (5th-Order Butterworth with 1st-Order Group Delay Compensation)
Filter Bandwidth (-3dB)
123.75
31
MHz
dB
ns
Rejection Ratio
At 247.5MHz
Group Delay
Up to 0.5dB bandwidth
1.0
3dB Bandwidth Tolerance
FREQUENCY SYNTHESIZER
RF-Divider Frequency Range
RF-Divider Range (N)
10
%
925
19
2175
251
MHz
MHz
Reference-Divider Frequency
Range
12
1
30
1
Reference-Divider Range (R)
Phase-Detector Comparison
Frequency
12
30
MHz
3
Complete Direct-Conversion L-Band Tuner
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX2121 Evaluation Kit: V
= +3.13V to +3.47V, T = -40°C to +85°C, default register settings except BBG[3:0] = 1111. Typical
CC
A
values measured at V
= +3.3V, T = +25°C, unless otherwise noted.) (Note 1)
CC
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
MHz
VOLTAGE-CONTROLLED OSCILLATOR AND LO GENERATION
Guaranteed LO Frequency Range
925
2175
f
f
f
= 10kHz
= 100kHz
= 1MHz
-97
OFFSET
OFFSET
OFFSET
MAX21
LO Phase Noise
dBc/Hz
-100
-122
XTAL/REFERENCE OSCILLATOR INPUT AND OUTPUT BUFFER
XTAL Oscillator Frequency
Parallel-resonance-mode crystal (Note 7)
AC-coupled sine-wave input
12
0.5
1
30
2.0
8
MHz
Range f
XTAL
Input Overdrive Level
1
V
P-P
XTAL Output-Buffer Divider
Range
XTAL Output Voltage Swing
XTAL Output Duty Cycle
12MHz to 30MHz, C
= 10pF
1
1.5
50
2
V
LOAD
P-P
%
Note 1: Min/max values are production tested at T = +25°C. Min/max limits at T = -40°C and T = +85°C are guaranteed by
A
A
A
design and characterization.
Note 2: Guaranteed by design and characterization at T = +25°C.
A
Note 3: Input gain range specifications met over this band.
Note 4: In-band IIP3 test conditions: GC1 set to provide the nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
LO
-26dBm each are applied at 2174MHz and 2175MHz. The IM3 tone at 3MHz is measured at baseband, but is referred to the
RF input.
Note 5: Out-of-band IIP3 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at
2175MHz to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at
LO
-20dBm each are applied at 1919MHz and 1663MHz. The IM3 tone at 5MHz is measured at baseband, but is referred to the
RF input.
Note 6: Input IP2 test conditions: GC1 set to provide nominal baseband output drive when mixing down a -23dBm tone at 2175MHz
to 5MHz baseband (f = 2170MHz). Baseband gain is set to its default value (BBG[3:0] = 1011). Two tones at -20dBm
LO
each are applied at 925MHz and 1250MHz. The IM2 tone at 5MHz is measured at baseband, but is referred to the RF input.
Note 7: See Table 16 for crystal ESR requirements.
4
Complete Direct-Conversion L-Band Tuner
MAX21
Typical Operating Characteristics
(MAX2121 Evaluation Kit: V
= +3.3V, T = +25°C, baseband output frequency = 5MHz, V
= +1.2V, default register settings
CC
A
GC1
except BBG[3:0] = 1011, unless otherwise noted.)
STANDBY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
HD3 vs. V
OUT
3.0
175
170
165
160
155
150
145
140
135
130
125
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
T
= +85°C
= +25°C
= -40°C
A
A
2.5
2.0
1.5
1.0
T
= +85°C
= -40°C
A
T
T
A
T
A
3.1
3.2
3.3
3.4
3.5
3.1
3.2
3.3
3.4
3.5
1.0
1.5
2.0
2.5
3.0
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
V
(V
)
OUT P-P
QUADRATURE PHASE ERROR
vs. LO FREQUENCY
QUADRATURE MAGNITUDE MATCHING
vs. LO FREQUENCY
QUADRATURE PHASE ERROR
vs. BASEBAND FREQUENCY
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
1.0
0.8
0.6
0.4
0.2
0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
f
= 50MHz
f
= 50MHz
f = 1425MHz
LO
BASEBAND
BASEBAND
T
= -40°C
A
T
= +85°C
A
T
A
= +25°C
T
= -40°C
A
T
= +25°C
A
T
= -40°C
A
T
= +85°C
A
T
= +85°C
A
T
= +25°C
A
900
1150
1400
1650
1900
2150
900
1150
1400
1650
1900
2150
0.1
1
10
100
LO FREQUENCY (MHz)
LO FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
QUADRATURE MAGNITUDE MATCHING
vs. BASEBAND FREQUENCY
BASEBAND FILTER FREQUENCY RESPONSE
BASEBAND FILTER FREQUENCY RESPONSE
1.0
0.8
0.6
0.4
0.2
0
0
-5
1
0
f
= 1425MHz
LO
-10
-15
-20
-25
-30
-35
-40
-45
-50
-55
-60
-65
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
T
= +25°C
A
T
= +25°C
A
T
= +85°C
= -40°C
A
T
A
0.1
1
10
100
0
100
200
300
400
500
0
25
50
75
100
125
150
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
BASEBAND FREQUENCY (MHz)
5
Complete Direct-Conversion L-Band Tuner
Typical Operating Characteristics (continued)
(MAX2121 Evaluation Kit: V
= +3.3V, T = +25°C, baseband output frequency = 5MHz, V
= +1.2V, default register settings
CC
A
GC1
except BBG[3:0] = 1011, unless otherwise noted.)
BASEBAND FILTER 3dB FREQUENCY
BASEBAND FILTER HIGHPASS
FREQUENCY RESPONSE
VOLTAGE GAIN vs. V
GC1
vs. TEMPERATURE
80
70
60
50
40
30
20
10
1.00
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
NORMALIZED AT T = +25°C
A
0.75
0.50
0.25
0
BBG[3:0] = 1111
MAX21
-0.25
-0.50
-0.75
0
0
-1.00
-10
0.5
1.0
1.5
(V)
2.0
2.5
3.0
-40
-20
0
20
40
60
80
100
1000
10,000
V
TEMPERATURE (°C)
BASEBAND FREQUENCY (Hz)
GC1
NOISE FIGURE vs. LO FREQUENCY
(T = +25°C)
NOISE FIGURE vs. INPUT POWER
OUT-OF-BAND IIP3 vs. INPUT POWER
A
11.0
10.5
10.0
9.5
35
30
25
20
15
10
5
30
20
ADJUST BBG[3:0] for 1V
P-P
SEE NOTE 5 ON PAGE 4 FOR CONDITIONS
BASEBAND OUTPUT WITH PIN = -75dBm
AND V = -0.5V, f = 1500MHz
ADJUST BBG[3:0] FOR 1V BASEBAND
P-P
GC1
LO
OUTPUT WITH PIN = -75dBm AND V
= 0.5V
GC1
10
9.0
10dB BACKED OFF GAIN
0
8.5
-10
-20
-30
8.0
7.5
7.0
900
1150
1400
1650
1900
2150
-75
-65
-55
-45
-35
-75 -65 -55 -45 -35 -25 -15 -5
INPUT POWER (dBm)
LO FREQUENCY (MHz)
INPUT POWER (dBm)
IN-BAND IIP3 vs. INPUT POWER
IIP2 vs. INPUT POWER
INPUT RETURN LOSS vs. FREQUENCY
20
10
40
35
30
25
20
15
10
5
0
SEE NOTE 4 ON PAGE 4 FOR CONDITIONS
SEE NOTE 6 ON PAGE 4
FOR CONDITIONS
-5
0
-10
-20
-30
-40
-50
-60
V
= 0.5V
GC1
-10
-15
0
-20
-25
-5
V
= 2.7V
GC1
-10
-75 -65 -55 -45 -35 -25 -15 -5
INPUT POWER (dBm)
-75 -65 -55 -45 -35 -25 -15 -5
INPUT POWER (dBm)
900 1125 1350 1575 1800 2025 2250
FREQUENCY (MHz)
6
Complete Direct-Conversion L-Band Tuner
MAX21
Typical Operating Characteristics (continued)
(MAX2121 Evaluation Kit: V
= +3.3V, T = +25°C, baseband output frequency = 5MHz, V
= +1.2V, default register settings
CC
A
GC1
except BBG[3:0] = 1011, unless otherwise noted.)
PHASE NOISE AT 10kHz OFFSET vs.
CHANNEL FREQUENCY
PHASE NOISE vs. OFFSET FREQUENCY
-90
-90
-100
-110
-120
-130
-95
-100
f
= 1800MHz
LO
-105
925 1115 1305 1495 1685 1875 2065 2255
1.0E+03
1.0E+04
1.0E+05
1.0E+06
CHANNEL FREQUENCY (MHz)
OFFSET FREQUENCY (Hz)
LO LEAKAGE vs. LO FREQUENCY
VCO: KV vs. VTUNE
-70
450
400
350
300
250
200
150
100
50
MEASURED AT RF INPUT
SUB-BAND 23
SUB-BAND 12
-75
-80
-85
-90
SUB-BAND 0
0.5
0
925
1175
1425
1675
1925
2175
0
1.0
1.5
2.0
2.5
3.0
LO FREQUENCY (MHz)
VTUNE (V)
7
Complete Direct-Conversion L-Band Tuner
Pin Configuration
TOP VIEW
V
28
27
26
25
24
23
22
21
IDC+
1
2
3
CC_RF2
+
MAX21
IOUT-
IOUT+
V
20
19
18
17
16
15
CC_RF1
GND
MAX2121
QOUT-
QOUT+
RFIN
GC1
4
5
V
6
7
V
CC_LO
CC_DIG
EP
V
REFOUT
CC_VCO
8
9
10
11
12
13
14
TQFN
(5mm x 5mm)
Pin Description
PIN
NAME
FUNCTION
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
1
V
CC_RF2
DC Power Supply for LNA. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF capacitor
connected as close as possible to the pin. Do not share capacitor ground vias with other ground connections.
2
V
CC_RF1
3
4
GND
RFIN
Ground. Connect to board’s ground plane for proper operation.
Wideband 75 RF Input. Connect to an RF source through a DC-blocking capacitor.
RF Gain-Control Input. High-impedance analog input with a 0.5V to 2.7V operating range.
5
GC1
V
= 0.5V corresponds to the maximum gain setting.
GC1
DC Power Supply for LO Generation Circuits. Connect to a +3.3V low-noise supply. Bypass to GND
with a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias
with other ground connections.
6
V
CC_LO
DC Power Supply for VCO Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with a 1nF
capacitor connected as close as possible to the pin. Do not share capacitor ground vias with other
ground connections.
7
V
CC_VCO
8
Complete Direct-Conversion L-Band Tuner
MAX21
Pin Description (continued)
PIN
NAME
FUNCTION
Internal VCO Bias Bypass. Bypass to GND with a 100nF capacitor connected as close as possible to
the pin. Do not share capacitor ground vias with other ground connections.
8
BYPVCO
High-Impedance VCO Tune Input. Connect the PLL loop filter output directly to this pin with as short of
a connection as possible.
9
TUNEVCO
10
11
GNDTUNE Ground for TUNEVCO. Connect to the PCB ground plane.
GNDSYN Ground for Synthesizer. Connect to the PCB ground plane.
Charge-Pump Output. Connect this output to the PLL loop filter input with the shortest
connection possible.
12
CPOUT
DC Power Supply for Synthesizer Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
13
V
CC_SYN
Crystal-Oscillator Interface. Use with an external parallel-resonance-mode crystal through a series
1nF capacitor. See the Typical Application Circuit.
14
15
XTAL
REFOUT Crystal-Oscillator Buffer Output. A DC-blocking capacitor must be used when driving external circuitry.
DC Power Supply for Digital Logic Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
16
V
a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
CC_DIG
17
18
19
20
21
22
23
24
QOUT+
QOUT-
IOUT+
IOUT-
IDC+
Quadrature Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
In-Phase Baseband Differential Output. AC-couple with 47nF capacitors to the demodulator input.
I-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from IDC- to IDC+.
Q-Channel Baseband DC Offset Correction. Connect a 47nF ceramic chip capacitor from QDC- to QDC+.
IDC-
QDC+
QDC-
DC Power Supply for Baseband Circuits. Connect to a +3.3V low-noise supply. Bypass to GND with
a 1nF capacitor connected as close as possible to the pin. Do not share capacitor ground vias with
other ground connections.
25
V
CC_BB
26
27
28
—
SDA
SCL
2-Wire Serial-Data Interface. Requires ꢀ 1k pullup resistor to V
.
CC
2-Wire Serial-Clock Interface. Requires ꢀ 1k pullup resistor to V
.
CC
ADDR
EP
Address. Must be connected to either ground (logic 0) or supply (logic 1).
Exposed Pad. Solder evenly to the board’s ground plane for proper operation.
9
Complete Direct-Conversion L-Band Tuner
shows each bit name and the bit usage information for all
Detailed Description
registers. Note that all registers must be written after and
no earlier than 100µs after the device is powered up. The
VCO autoselection circuit is triggered by writing to regis-
ter 5. Thus register 5 should be the last register to be
written in order to ensure proper PLL lock.
Register Description
The MAX2121 includes 12 user-programmable registers
and two read-only registers. See Table 1 for register
configurations. The register configuration of Table 1
Table 1. Register Configuration
MAX21
MSB
LSB
REG
NUMBER
REGISTER READ/
REG
DATA BYTE
NAME
WRITE ADDRESS
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
N-Divider
MSB
FRAC
1
1
2
3
4
5
Write
Write
Write
Write
Write
0x00
0x01
0x02
0x03
0x04
N[14]
N[13]
N[12]
N[11]
N[10]
N[9]
N[8]
N-Divider
LSB
N[7]
N[6]
N[5]
N[4]
N[3]
F[19]
F[11]
F[3]
N[2]
N[1]
N[0]
Charge
Pump
CPMP[1]
0
CPMP[0]
0
CPLIN[1]
0
CPLIN[0]
1
F[18] F[17] F[16]
F-Divider
MSB
F[15]
F[7]
F[14]
F[6]
F[13]
F[5]
F[12]
F[4]
F[10]
F[2]
F[9]
F[1]
F[8]
F[0]
F-Divider
LSB
XTAL
Buffer and
Reference
Divider
6
Write
0x05
XD[2]
XD[1]
XD[0]
R[4]
R[3]
R[2]
R[1]
R[0]
7
8
PLL
Write
Write
0x06
0x07
D24
CPS
ICP
X
X
X
X
X
VCO
VCO[4]
VCO[3]
VCO[2]
VCO[1]
VCO[0]
VAS
ADL
ADE
Lowpass
Filter
9
Write
Write
0x08
0x09
0x0A
10010111
X
PWDN
0
10
11
Control
STBY
X
X
BBG[3]
BBG[2] BBG[1] BBG[0]
PLL
0
DIV
0
VCO
0
BB
0
RFMIX RFVGA
FE
0
Shutdown Write
0
0
LD
LD
LD
CPTST[2] CPTST[1] CPTST[0]
TURBO
1
12
13
Test
Write
0x0B
X
MUX[2] MUX[1] MUX[0]
0
0
0
0
0
0
Status
Byte-1
Read
Read
0x0C
0x0D
POR
VASA
VASE
LD
X
X
X
X
Status
Byte-2
14
VCOSBR[4] VCOSBR[3] VCOSBR[2] VCOSBR[1] VCOSBR[0] ADC[2] ADC[1] ADC[0]
1 = Set to 1 for factory-tested operation.
X = Don’t care.
0 = Set to 0 for factory-tested operation.
10
Complete Direct-Conversion L-Band Tuner
MAX21
Table 2. N-Divider MSB Register (Address: 0x00)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
FRAC
7
1
Users must program to 1 upon powering up the device.
Sets the most significant bits of the PLL integer-divide number (N). N can
range from 19 to 251.
N[14:8]
6–0
0000000
Table 3. N-Divider LSB Register (Address: 0x01)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Sets the least significant bits of the PLL integer-divide number. N can range
from 19 to 251.
N[7:0]
7–0
00100011
Table 4. Charge-Pumꢁ Register (Address: 0x02)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Charge-pump minimum pulse width. Users must program to 00 upon
powering up the device.
CPMP[1:0]
CPLIN[1:0]
F[19:16]
7–6
5–4
3–0
00
00
Controls charge-pump linearity. Users must program to 01 upon powering
up the device.
Sets the 4 most significant bits of the PLL fractional divide number.
Default value is F = 194,180 decimal.
0010
Table 5. F-Divider MSB Register (Address: 0x03)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Sets the most significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
F[15:8]
7–0
11110110
Table 6. F-Divider LSB Register (Address: 0x04)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Sets the least significant bits of the PLL fractional-divide number (F).
Default value is F = 194,180 decimal.
F[7:0]
7–0
10000100
Table 7. XTAL Buffer and Reference Divider Register (Address: 0x05)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Sets the crystal-divider setting.
000 = Divide by 1.
001 = Divide by 2.
XD[2:0]
R[4:0]
7–5
4–0
000
011 = Divide by 3.
100 = Divide by 4.
101 through 110 = All divide values from 5 (101) to 7 (110).
111 = Divide by 8.
Sets the PLL reference-divider (R) number. Users must program to 00001
upon powering up the device.
00001
00001 = Divide by 1; other values are not tested.
11
Complete Direct-Conversion L-Band Tuner
Table 8. PLL Register (Address: 0x06)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
VCO divider setting.
0 = Divide by 2. Use for LO frequencies ꢀ 1125MHz.
1 = Divide by 4. Use for LO frequencies < 1125MHz.
D24
CPS
7
6
1
1
Charge-pump current mode.
0 = Charge-pump current controlled by ICP bit.
1 = Charge-pump current controlled by VCO autoselect (VAS).
MAX21
Charge-pump current.
0 = 600µA typical.
1 = 1200µA typical.
ICP
X
5
0
X
4–0
Don’t care.
Table 9. VCO Register (Address: 0x07)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Controls which VCO is activated when using manual VCO programming mode.
This also serves as the starting point for the VCO autoselection (VAS) mode.
VCO[4:0]
VAS
7–3
2
11001
1
VCO autoselection (VAS) circuit.
2
0 = Disable VCO selection must be programmed through I C.
1 = Enable VCO selection controlled by autoselection circuit.
Enables or disables the VCO tuning voltage ADC latch when the VCO
autoselect mode (VAS) is disabled.
0 = Disables the ADC latch.
ADL
ADE
1
0
0
0
1 = Latches the ADC value.
Enables or disables VCO tuning voltage ADC read when the VCO
autoselect mode (VAS) is disabled.
0 = Disables ADC read.
1 = Enables ADC read.
Table 10. Lowꢁass Filter Register (Address: 0x08)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Reserved
7–0
01001011 User must program to 10010111 (97h) upon powering up the device.
12
Complete Direct-Conversion L-Band Tuner
MAX21
Table 11. Control Register (Address: 0x09)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Software standby control.
0 = Normal operation.
STBY
7
0
1 = Disables the signal path and frequency synthesizer leaving only the
2-wire bus, crystal oscillator, XTALOUT buffer, and XTALOUT buffer divider
active.
X
PWDN
X
6
5
4
X
0
X
Don’t care.
Factory use only.
0 = Normal operation; other value is not tested.
Don’t care.
Baseband gain setting (1dB typical per step).
0000 = Minimum gain (0dB, default).
…
BBG[3:0]
3–0
0000
1111 = Maximum gain (15dB typical).
Table 12. Shutdown Register (Address: 0x0A)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
X
7
X
Don’t care.
PLL enable.
PLL
6
0
0 = Normal operation.
1 = Shuts down the PLL. Value not tested.
Divider enable.
DIV
VCO
BB
5
4
3
2
1
0
0
0
0
0
0
0
0 = Normal operation.
1 = Shuts down the divider. Value not tested.
VCO enable.
0 = Normal operation.
1 = Shuts down the VCO. Value not tested.
Baseband enable.
0 = Normal operation.
1 = Shuts down the baseband. Value not tested.
RF mixer enable.
0 = Normal operation.
1 = Shuts down the RF mixer. Value not tested.
RFMIX
RFVGA
FE
RF VGA enable.
0 = Normal operation.
1 = Shuts down the RF VGA. Value not tested.
Front-end enable.
0 = Normal operation.
1 = Shuts down the front-end. Value not tested.
13
Complete Direct-Conversion L-Band Tuner
Table 13. Test Register (Address: 0x0B)
BIT NAME BIT LOCATION (0 = LSB) DEFAULT
FUNCTION
Charge-pump test modes.
000 = Normal operation (default).
CPTST[2:0]
X
7–5
4
000
X
Don’t care.
Charge-pump fast lock.
Users must program to 1 after powering up the device.
TURBO
3
1
MAX21
REFOUT output.
000 = Normal operation; other values are not tested.
LDMUX[2:0]
2–0
000
Table 14. Status Byte-1 Register (Address: 0x0C)
BIT NAME BIT LOCATION (0 = LSB)
FUNCTION
Power-on reset status.
0 = Chip status register has been read with a stop condition since last power-on.
1 = Power-on reset (power cycle) has occurred. Default values have been loaded in
registers.
POR
7
Indicates whether VCO autoselection was successful.
VASA
VASE
6
5
0 = Indicates the autoselect function is disabled or unsuccessful VCO selection.
1 = Indicates successful VCO autoselection.
Status indicator for the autoselect function.
0 = Indicates the autoselect function is active.
1 = Indicates the autoselect process is inactive.
PLL lock detector. TURBO bit must be programmed to 1 for valid LD reading.
LD
X
4
0 = Unlocked.
1 = Locked.
3–0
Don’t care.
Table 15. Status Byte-2 Register (Address: 0x0D)
BIT NAME
BIT LOCATION (0 = LSB)
FUNCTION
VCOSBR[4:0]
7–3
VCO band readback.
VAS ADC output readback.
000 = Out of lock.
001 = Locked.
ADC[2:0]
2–0
010 = VAS locked.
101 = VAS locked.
110 = Locked.
111 = Out of lock.
14
Complete Direct-Conversion L-Band Tuner
MAX21
Slave Address
The MAX2121 has a 7-bit slave address that must be
sent to the device following a START condition to initi-
ate communication. The slave address is internally pro-
grammed to 1100000. The eighth bit (R/W) following
the 7-bit address determines whether a read or write
operation occurs.
2-Wire Serial Interface
2
The MAX2121 uses a 2-wire I C-compatible serial inter-
face consisting of a serial-data line (SDA) and a serial-
clock line (SCL). SDA and SCL facilitate bidirectional
communication between the MAX2121 and the master
at clock frequencies up to 400kHz. The master initiates
a data transfer on the bus and generates the SCL sig-
nal to permit data transfer. The MAX2121 behaves as a
slave device that transfers and receives data to and
from the master. SDA and SCL must be pulled high
with external pullup resistors (1kΩ or greater) for proper
bus operation. Pullup resistors should be referenced to
The MAX2121 continuously awaits a START condition
followed by its slave address. When the device recog-
nizes its slave address, it acknowledges by pulling the
SDA line low for one clock period; it is ready to accept
or send data depending on the R/W bit (Figure 1).
the MAX2121’s V
.
CC
The write/read address is C0/C1 if ADDR pin is con-
nected to ground. The write/read address is C2/C3 if
One bit is transferred during each SCL clock cycle. A
minimum of nine clock cycles is required to transfer a
byte in or out of the MAX2121 (8 bits and an ACK/NACK).
The data on SDA must remain stable during the high
period of the SCL clock pulse. Changes in SDA while
SCL is high and stable are considered control signals
(see the START and STOP Conditions section). Both SDA
and SCL remain high when the bus is not busy.
the ADDR pin is connected to V
.
CC
SLAVE ADDRESS
1
1
0
0
0
0
0
7
S
ACK
9
R/W
8
SDA
SCL
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high.
1
2
3
4
5
6
Figure 1. MAX2121 Slave Address Byte with ADDR Pin
Connected to Ground
Write Cycle
When addressed with a write command, the MAX2121
allows the master to write to a single register or to multi-
ple successive registers.
Acknowledge and Not-Acknowledge Conditions
Data transfers are framed with an acknowledge bit
(ACK) or a not-acknowledge bit (NACK). Both the mas-
ter and the MAX2121 (slave) generate acknowledge
bits. To generate an acknowledge, the receiving device
must pull SDA low before the rising edge of the
acknowledge-related clock pulse (ninth pulse) and
keep it low during the high period of the clock pulse.
A write cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX2121 issues an
ACK if the slave address byte is successfully received.
The bus master must then send to the slave the address
of the first register it wishes to write to (see Table 1 for
register addresses). If the slave acknowledges the
address, the master can then write one byte to the regis-
ter at the specified address. Data is written beginning
with the most significant bit. The MAX2121 again issues
an ACK if the data is successfully written to the register.
The master can continue to write data to the successive
internal registers with the MAX2121 acknowledging each
successful transfer, or it can terminate transmission by
issuing a STOP condition. The write cycle does not termi-
nate until the master issues a STOP condition.
To generate a not-acknowledge condition, the receiver
allows SDA to be pulled high before the rising edge of
the acknowledge-related clock pulse, and leaves SDA
high during the high period of the clock pulse.
Monitoring the acknowledge bits allows for detection of
unsuccessful data transfers. An unsuccessful data
transfer happens if a receiving device is busy or if a
system fault has occurred. In the event of an unsuc-
cessful data transfer, the bus master must reattempt
communication at a later time.
WRITE DEVICE
ADDRESS
WRITE REGISTER
ADDRESS
WRITE DATA TO
REGISTER 0x00
WRITE DATA TO
REGISTER 0x01
WRITE DATA TO
REGISTER 0x02
R/W
0
ACK
—
ACK
—
ACK
—
ACK
—
ACK
—
START
STOP
1100000
0x00
0x0E
0xD8
0xE1
Figure 2. Example: Write Registers 0, 1, and 2 with 0x0E, 0xD8, and 0xE1, respectively.
15
Complete Direct-Conversion L-Band Tuner
ACK/
R/W
1
WRITE DEVICE ADDRESS
1100000
ACK
—
READ FROM STATUS BYTE-1 REGISTER
ACK
—
READ FROM STATUS BYTE-2 REGISTER
NACK
START
STOP
—
—
—
Figure 3. Example: Receive Data from Read Registers
Read Cycle
Table 16. Maximum Crystal ESR
Requirement
When addressed with a read command, the MAX2121
allows the master to read back a single register, or mul-
tiple successive registers.
MAX21
ESR
(ꢀ)
XTAL FREQUENCY (MHz)
MAX
80
12 < f
ꢁ 14
ꢁ 30
XTAL
A read cycle begins with the bus master issuing a
START condition followed by the seven slave address
bits and a write bit (R/W = 0). The MAX2121 issues an
ACK if the slave address byte is successfully received.
The bus master must then send the address of the first
register it wishes to read (see Table 1 for register
addresses). The slave acknowledges the address.
Then, a START condition is issued by the master, fol-
lowed by the seven slave address bits and a read bit
(R/W = 1). The MAX2121 issues an ACK if the slave
address byte is successfully received. The MAX2121
starts sending data MSB first with each SCL clock
cycle. At the 9th clock cycle, the master can issue an
ACK and continue to read successive registers, or the
master can terminate the transmission by issuing a
NACK. The read cycle does not terminate until the mas-
ter issues a STOP condition.
60
14 < f
XTAL
Baseband Lowpass Filter
The MAX2121 includes an on-chip 5th-order Butterworth
filter with 1st-order group delay compensation.
DC Offset Cancellation
The DC offset cancellation is required to maintain the
I/Q output dynamic range. Connecting an external
capacitor between IDC+ and IDC- forms a highpass fil-
ter for the I channel and an external capacitor between
QDC+ and QDC- forms a highpass filter for the Q chan-
nel. Keep the value of the external capacitor less than
47nF to form a typical highpass corner of 250Hz.
XTAL Oscillator
The MAX2121 contains an internal reference oscillator,
reference output divider, and output buffer. All that is
required is to connect a crystal through a series 1nF
capacitor. To minimize parasitics, place the crystal and
series capacitor as close as possible to pin 14 (XTAL).
See Table 16 for crystal (XTAL) ESR (equivalent series
resistance) requirements.
Figure 3 illustrates an example in which registers 0, 1,
and 2 are read back.
Application Information
The MAX2121 downconverts RF signals in the 925MHz
to 2175MHz range directly to the baseband I/Q signals.
RF Input
Programming the Fractional
N- Synthesizer
The MAX2121 utilizes a fractional-N type synthesizer for
LO frequency programming. To program the frequency
synthesizer, the N and F values are encoded as
straight binary numbers. Determination of these values
is illustrated by the following example:
The RF input of the MAX2121 is internally matched to
75Ω. Only a DC-blocking capacitor is needed. See the
Typical Application Circuit.
RF Gain Control
The MAX2121 features a variable-gain low-noise ampli-
fier providing 73dB of RF gain range. The voltage con-
trol (VGC) range is 0.5V (minimum attenuation) to 2.7V
(maximum attenuation).
f
f
is 2170MHz
is 27 MHz
LO
XTAL
Phase-detector comparison frequency is from 12MHz
and 30MHz
Baseband Variable-Gain Amplifier
The receiver baseband variable-gain amplifiers provide
15dB of gain control range programmable in 1dB
steps. The VGA gain can be serially programmed
R divider = R[4:0] = 1
f
= 27MHz/1 = 27MHz
COMP
2
through the I C interface by setting bits BBG[3:0] in the
D = f /f
= 2170/27 = 80.37470
LO COMP
Control register.
16
Complete Direct-Conversion L-Band Tuner
MAX21
Integer portion:
N = 80
Table 17. ADC Triꢁ Points and Lock Status
ADC[2:0]
LOCK STATUS
Out of lock
Locked
N[14:8] = 0
N[7:0] = 0101 0000
Fractional portion:
000
001
010
VAS locked
VAS locked
Locked
20
F = 0.370370 x 2 = 388,361 (round up the decimal portion)
101
110
F = 0101 1110 1101 0000 1001
111
Out of lock
Note: When changing LO frequencies, all the divider
registers (integer and fractional) must be programmed
to activate the VAS function regardless of whether indi-
vidual registers are changed.
Table 17 summarizes the ADC output bits and the VCO
lock indication. The VCO autoselect routine only selects
a VCO in the “VAS locked” range. This allows room for
a VCO to drift over temperature and remain in a valid
“locked” range.
VCO Autoselect (VAS)
The MAX2121 includes 24 VCOs. The local oscillator
frequency can be manually selected by programming
the VCO[4:0] bits in the VCO register. The selected VCO
is reported in the Status Byte-2 register (see Table 15).
The ADC must first be enabled by setting the ADE bit in
the VCO register. The ADC reading is latched by a sub-
sequent programming of the ADC latch bit (ADL = 1).
The ADC value is reported in the Status Byte-2 register
(see Table 15).
Alternatively, the MAX2121 can be set to autonomously
choose a VCO by setting the VAS bit in the VCO regis-
ter to logic-high. The VAS routine is initiated once the
F-Divider LSB register word (register 5) is loaded.
Standby Mode
The MAX2121 features normal operating mode and
standby mode using the I C interface. Setting a logic-
high to the STBY bit in the Control register puts the
device into standby mode, during which only the 2-
wire-compatible bus, the crystal oscillator, the XTAL
buffer, and the XTAL buffer divider are active.
Thus it is important to write register 5 after any of the
following PLL related bits have been changed:
2
N-Divider bits (registers 1 and/or 2)
F-Divider bits (registers 3 and/or 4)
Reference Divider bits (register 6)
D24, CPS, or ICP bits (register 7)
In all cases, register settings loaded prior to entering
shutdown are saved upon transition back to active
mode. Default register values are provided for the
user’s convenience only. It is the user’s responsibility to
load all the registers no sooner than 100µs after the
device is powered up.
This will ensure all intended bits have been pro-
grammed before the VAS is initiated and the PLL is
locked. The VCO value programmed in the VCO[4:0]
register serves as the starting point for the automatic
VCO selection process.
Layout Considerations
The MAX2121 EV kit serves as a guide for PCB layout.
Keep RF signal lines as short as possible to minimize
losses and radiation. Use controlled impedance on all
high-frequency traces. For proper operation, the
exposed paddle must be soldered evenly to the board’s
ground plane. Use abundant vias beneath the exposed
paddle for maximum heat dissipation. Use abundant
ground vias between RF traces to minimize undesired
During the selection process, the VASE bit in the Status
Byte-1 register is cleared to indicate the autoselection
function is active. Upon successful completion, bits VASE
and VASA are set and the VCO selected is reported in the
Status Byte-2 register (see Table 15). If the search is
unsuccessful, VASA is cleared and VASE is set. This indi-
cates that searching has ended but no good VCO has
been found, and occurs when trying to tune to a frequen-
cy outside the VCO’s specified frequency range.
coupling. Bypass each V
pin to ground with a 1nF
CC
Refer to Application Note 4256: Extended Characterization
for the MAX2112/MAX2120 Satellite Tuners.
capacitor placed as close as possible to the pin.
3-Bit ADC
The MAX2121 has an internal 3-bit ADC connected to
the VCO tune pin (TUNEVCO). This ADC can be used
for checking the lock status of the VCOs.
17
Complete Direct-Conversion L-Band Tuner
Typical Application Circuit
SERIAL-DATA
INPUT/OUTPUT
SERIAL-CLOCK
INPUT
V
CC
MAX21
V
CC
28
27
26
25
24
23
22
+
IDC+
V
V
CC_RF2
21
1
DC OFFSET
CORRECTION
V
CC
INTERFACE LOGIC
AND CONTROL
IOUT-
MAX2121
CC_RF1
20
19
18
17
16
15
2
3
IOUT+
QOUT-
QOUT+
GND
BASEBAND
OUTPUTS
RF INPUT
RFIN
GC1
4
5
V
GC
V
V
CC
CC
FREQUENCY
SYNTHESIZER
DIV2
/DIV4
V
V
CC_LO
CC_DIG
6
7
V
CC
EP
REFOUT
V
CC_VCO
8
9
10
11
12
13
14
V
CC
Chip Information
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maxim-ic.com/ꢁackages. Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
PROCESS: BiCMOS
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 TQFN-EP
T2855+3
21-0140
90-0023
18
Complete Direct-Conversion L-Band Tuner
MAX21
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/11
Initial release
—
Corrected 2-tone frequencies, added new TOCs, added text to Register Description
section, corrected incorrect symbol in Table 8, corrected VCO Autoselect (VAS)
section
1
7/12
4, 6, 10, 17
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. The parametric values (min and max limits) shown in
the Electrical. Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated Products, 160 Rio Robles, San Jose, CA 95134 USA 1-408-601-1000 ____________________ 19
© 2012 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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