MAX19708ETM [MAXIM]
Telecom Circuit, 1-Func, 7 X 7 MM, 0.80 MM HEIGHT, MO-220, TQFN-48;
| 型号： | MAX19708ETM |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Telecom Circuit, 1-Func, 7 X 7 MM, 0.80 MM HEIGHT, MO-220, TQFN-48 电信 电信集成电路 |
| 文件： | 总37页 (文件大小：547K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-3764; Rev 0; 8/05
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
General Description
Features
♦ Dual 10-Bit, 11Msps Rx ADC and Dual 10-Bit,
The MAX19708 is an ultra-low-power, mixed-signal ana-
log front-end (AFE) designed for TD-SCDMA handsets
and data cards. Optimized for high dynamic perfor-
mance at ultra-low power, the device integrates a dual
10-bit, 11Msps receive (Rx) ADC; dual 10-bit, 11Msps
transmit (Tx) DAC with TD-SCDMA baseband filters;
three fast-settling 12-bit aux-DAC channels for ancillary
RF front-end control; and a 10-bit, 333ksps housekeep-
ing aux-ADC. The typical operating power in Tx-Rx
FAST mode is 36.9mW at a 5.12MHz clock frequency.
11Msps Tx DAC
♦ Ultra-Low Power
36.9mW at fCLK = 5.12MHz, Fast Mode
19.8mW at fCLK = 5.12MHz, Slow Mode
Low-Current Standby and Shutdown Modes
♦ Integrated TD-SCDMA Filters with > 55dB
Stopband Rejection
♦ Programmable Tx DAC Common-Mode DC Level
and I/Q Offset Trim
The Rx ADCs feature 55dB SNR and 77.4dBc SFDR at a
1.87MHz input frequency with an 11MHz clock frequen-
cy. The analog I/Q input amplifiers are fully differential
♦ Excellent Dynamic Performance
SNR = 55dB at fIN = 1.87MHz (Rx ADC)
SFDR = 73dBc at fOUT = 620kHz (Tx DAC)
and accept 1.024V
full-scale signals. Typical I/Q
P-P
♦ Three 12-Bit, 1µs Aux-DACs
channel matching is 0.08° phase and 0.02dB gain.
♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and
The Tx DACs with TD-SCDMA lowpass filters feature -3dB
cutoff frequency of 1.32MHz and > 55dB stopband rejec-
Data Averaging
♦ Excellent Gain/Phase Match
0.08ꢀ Phase, 0.02dB Gain (Rx ADC) at
fIN = 1.87MHz
tion at f
= 4.32MHz. The analog I-Q full-scale output
IMAGE
voltage range is selectable at 410mV or 500mV differ-
ential. The output DC common-mode voltage is selec-
table from 0.9V to 1.4V. The I/Q channel offset is
adjustable to optimize radio lineup sideband/carrier sup-
pression. Typical I-Q channel matching is 0.02dB gain
and 0.04° phase.
♦ Multiplexed Parallel Digital I/O
♦ Serial-Interface Control
♦ Versatile Power-Control Circuits
Shutdown, Standby, Idle, Tx/Rx Disable
The Rx ADC and Tx DAC share a single, 10-bit parallel,
high-speed digital bus allowing half-duplex operation
for time-division duplex (TDD) applications. A 3-wire
serial interface controls power-management modes, the
aux-DAC channels, and the aux-ADC channels.
♦ Miniature 48-Pin Thin QFN Package
(7mm x 7mm x 0.8mm)
Pin Configuration
The MAX19708 operates on a single +2.7V to +3.3V
analog supply and +1.8V to +3.3V digital I/O supply.
The MAX19708 is specified for the extended (-40°C to
+85°C) temperature range and is available in a 48-pin,
thin QFN package. The Selector Guide at the end of the
data sheet lists other pin-compatible versions in this
AFE family.
TOP VIEW
36 35 34 33
31 30 29 28 27 26 25
32
24
23
22
21
20
19
18
17
16
15
14
13
DAC2 37
DAC1 38
D9
D8
D7
D6
OV
V
DD
39
IDN 40
IDP 41
Applications
DD
GND
42
43
OGND
D5
TD-SCDMA Handsets
V
DD
MAX19708
D4
QDN 44
QDP 45
REFIN 46
TD-SCDMA Data Cards
D3
Portable Communication Equipment
EXPOSED PADDLE (GND)
D2
COM
47
D1
D0
Ordering Information
REFN 48
1
2
3
4
6
7
8
9
10 11 12
5
PART*
PIN-PACKAGE
48 Thin QFN-EP**
48 Thin QFN-EP**
PKG CODE
T4877-4
MAX19708ETM
MAX19708ETM+
T4877-4
THIN QFN
*All devices are specified over the -40°C to +85°C operating range.
**EP = Exposed paddle.
+Denotes lead-free package.
Functional Diagram and Selector Guide appear at end of
data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ABSOLUTE MAXIMUM RATINGS
V
to GND, OV to OGND ..............................-0.3V to +3.6V
DD
D0–D9, DOUT, T/R, SHDN, SCLK, DIN, CS,
CLK to OGND .....................................-0.3V to (OV
DD
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
+ 0.3V)
DD
Continuous Power Dissipation (T = +70°C)
A
QDN, DAC1, DAC2, DAC3 to GND.....................-0.3V to V
ADC1, ADC2 to GND.................................-0.3V to (V
REFP, REFN, REFIN, COM to GND ...........-0.3V to (V
48-Pin Thin QFN (derate 27.8mW/°C above +70°C) .....2.22W
DD
+ 0.3V)
+ 0.3V)
Thermal Resistance θ ..................................................36°C/W
DD
DD
JA
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFP
REFN
C
= 0.33µF, unless otherwise noted. C < 5pF on all aux-DAC outputs. Typical values are at T = +25°C.) (Note 1)
COM
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
V
2.7
1.8
3.0
3.3
V
V
DD
OV
V
DD
DD
Ext1-Tx, Ext3-Tx, and SPI2-Tx states;
transmit DAC operating mode (Tx):
f
= 5.12MHz, f
= 620kHz on both
10.3
12.6
12.3
6.6
CLK
OUT
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Tx, Ext4-Tx, and SPI4-Tx states;
transmit DAC operating mode (Tx):
f
= 5.12MHz, f
= 620kHz on both
CLK
OUT
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext1-Rx, Ext4-Rx, and SPI3-Rx states;
receive ADC operating mode (Rx):
f
= 5.12MHz, f = 1.87MHz on both
IN
V
Supply Current
mA
CLK
DD
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Rx, Ext3-Rx, and SPI1-Rx states;
receive ADC operating mode (Rx):
f
= 5.12MHz, f = 1.87MHz on both
IN
CLK
channels; aux-DACs ON and at midscale,
aux-ADC ON
Ext2-Tx, Ext4-Tx, and SPI4-Tx states;
transmit DAC operating mode (Tx):
f
= 11MHz, f
= 620kHz on both
14.1
16
CLK
OUT
channels, aux-DACs ON and at midscale,
aux-ADC ON
2
_______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, unless otherwise noted. C < 5pF on all aux-DAC outputs. Typical values are at T = +25°C.) (Note 1)
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Ext1-Tx, Ext3-Tx, and SPI2-Tx states;
transmit DAC operating mode (Tx):
f
= 11MHz, f
= 620kHz on both
11.7
CLK
OUT
channels, aux-DACs ON and at midscale,
aux-ADC ON
Ext1-Rx, Ext4-Rx, and SPI3-Rx states;
receive ADC operating mode (Rx):
f
= 11MHz, f = 1.87MHz on both
13.7
16
CLK
IN
channels, aux-DACs ON and at midscale,
aux-ADC ON
mA
V
Supply Current
Ext2-Rx, Ext3-Rx, and SPI1-Rx states;
receive ADC operating mode (Rx):
DD
f
= 11MHz, f = 1.87MHz on both
8
CLK
IN
channels, aux-DACs ON and at midscale,
aux-ADC ON
Standby mode: CLK = 0 or OV
;
DD
aux-DACs ON and at midscale,
aux-ADC ON
2.9
4
7
Idle mode: f
= 11MHz; aux-DACs ON
CLK
5.5
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OV
0.52
µA
DD
Ext1-Rx, Ext2-Rx, Ext3-Rx, Ext4-Rx,
SPI1-Rx, SPI3-Rx states; receive ADC
operating mode (Rx): f
= 11MHz,
CLK
1.5
mA
f
IN
= 1.87MHz on both channels;
aux-DACs ON and at midscale,
aux-ADC ON
Ext1-Tx, Ext2-Tx, Ext3-Tx, Ext4-Tx,
SPI2-Tx, SPI4-Tx states; transmit DAC
OV
Supply Current
DD
operating mode (Tx): f
= 11MHz, f
110
1
CLK
OUT
= 620kHz on both channels; aux-DACs
ON and at midscale, aux-ADC ON
µA
Standby mode: CLK = 0 or OV ; aux-
DD
DACs ON and at midscale, aux-ADC ON
Idle mode: f
and at midscale, aux-ADC ON
= 11MHz; aux-DACs ON
CLK
19
Shutdown mode: CLK = 0 or OV
0.1
DD
_______________________________________________________________________________________
3
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, unless otherwise noted. C < 5pF on all aux-DAC outputs. Typical values are at T = +25°C.) (Note 1)
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Rx ADC DC ACCURACY
Resolution
N
10
Bits
LSB
LSB
%FS
%FS
dB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
0.9
0.4
0.1
1.5
0.01
10
Guaranteed no missing code (Note 2)
Residual DC offset error
-1.0
-5
+1.2
+5
Gain Error
Include reference error
-7.0
-0.25
+10.5
+0.25
DC Gain Matching
Offset Matching
LSB
Gain Temperature Coefficient
18.4
2
ppm/°C
LSB
Offset error (V
5%)
5%)
DD
Power-Supply Rejection
PSRR
Gain error (V
0.07
%FS
DD
Rx ADC ANALOG INPUT
Input Differential Range
V
Differential or single-ended inputs
Switched capacitor load
0.512
V
V
ID
Input Common-Mode Voltage
Range
V
V
/ 2
DD
CM
R
491
5
kΩ
IN
Input Impedance
C
pF
IN
Rx ADC CONVERSION RATE
Maximum Clock Frequency
f
(Note 3)
11
MHz
CLK
Channel I
Channel Q
5
Clock
Cycles
Data Latency (Figure 3)
5.5
Rx ADC DYNAMIC CHARACTERISTICS (Note 4)
f
f
f
f
f
f
f
f
= 1.875MHz, f
= 11MHz
53.3
53.2
63.5
55
IN
IN
IN
IN
IN
IN
IN
IN
CLK
CLK
CLK
CLK
Signal-to-Noise Ratio
SNR
SINAD
SFDR
HD3
dB
dB
= 3.5MHz, f
= 11MHz
55
CLK
= 1.875MHz, f
= 3.5MHz, f
= 11MHz
54.9
54.9
77.4
78.3
Signal-to-Noise and Distortion
Spurious-Free Dynamic Range
Third-Harmonic Distortion
Intermodulation Distortion
= 11MHz
CLK
= 1.875MHz, f
= 3.5MHz, f
= 11MHz
dBc
dBc
dBc
dBc
dB
= 11MHz
CLK
= 1.875MHz, f
= 3.5MHz, f
= 11MHz
-84.3
-85
= 11MHz
CLK
f = 1.8MHz, -7dBFS;
1
IMD
-72.7
-74.4
f = 1MHz, -7dBFS
2
Third-Order Intermodulation
Distortion
f = 1.8MHz, -7dBFS;
1
f = 1MHz, -7dBFS
2
IM3
f
f
= 1.875MHz, f
= 11MHz
-75.6
-76.3
3.5
-63
IN
CLK
Total Harmonic Distortion
THD
= 3.5MHz, f
= 11MHz
IN
CLK
Aperture Delay
ns
ns
Overdrive Recovery Time
1.5x full-scale input
2
4
_______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, unless otherwise noted. C < 5pF on all aux-DAC outputs. Typical values are at T = +25°C.) (Note 1)
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Rx ADC INTERCHANNEL CHARACTERISTICS
f
= 1.875MHz at -0.5dBFS, f
=
INX,Y
INX,Y
Crosstalk Rejection
-90
dB
1MHz at -0.5dBFS (Note 5)
Amplitude Matching
Phase Matching
f
= 1.875MHz at -0.5dBFS (Note 6)
= 1.875MHz at -0.5dBFS (Note 6)
0.02
0.08
dB
IN
f
IN
Degrees
Tx DAC DC ACCURACY
Resolution
N
10
Bits
LSB
LSB
Integral Nonlinearity
Differential Nonlinearity
INL
DNL
0.45
0.4
Guaranteed monotonic (Note 2)
-1
-4
+1
+4
T
> +25°C
< +25°C
1
1
A
A
Residual DC Offset
Full-Scale Gain Error
V
mV
mV
OS
T
-5.5
-50
+5.5
+50
Include reference error (peak-to-peak error)
Tx PATH DYNAMIC PERFORMANCE
Corner Frequency
Passband Ripple
Group Delay Variation in Passband
Error-Vector Magnitude
3dB corner
DC to 640kHz (Note 2)
DC to 640kHz
1.05
1.32
0.15
50
1.65
0.5
MHz
dB
P-P
ns
%
EVM
DC to 700kHz
2
f
= 4.32MHz, f
= 800kHz, f
=
IMAGE
OUT
CLK
Stopband Rejection
55
62.5
dBc
5.12MHz
2MHz
21.5
49
4MHz
Spot relative to
100kHz
5MHz
58
Baseband Attenuation
dB
10MHz
20MHz
90
90
DAC Conversion Rate
In-Band Noise Density
f
(Note 3)
11
MHz
CLK
f
= 620kHz, f
= 5.12MHz,
OUT
CLK
N
-120.6
dBc/Hz
D
offset = 500kHz
Third-Order Intermodulation
Distortion
IM3
f = 620kHz, f = 640kHz
82
10
73
dBc
pV•s
dBc
1
2
Glitch Impulse
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
= 11MHz, f
= 620kHz
60
CLK
OUT
Total Harmonic Distortion to
Nyquist
THD
SNR
f
f
= 11MHz, f
= 11MHz, f
= 620kHz
= 620kHz
-71
-60
dB
dB
CLK
CLK
OUT
Signal-to-Noise Ratio to Nyquist
56.5
OUT
_______________________________________________________________________________________
5
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, unless otherwise noted. C < 5pF on all aux-DAC outputs. Typical values are at T = +25°C.) (Note 1)
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Tx PATH INTERCHANNEL CHARACTERISTICS
I-to-Q Output Isolation
f
= 500kHz, f
= 620kHz
OUTX,Y
90
dB
dB
OUTX,Y
Gain Mismatch Between DAC
Outputs
Measured at DC
-0.30
0.02
+0.31
Phase Mismatch Between DAC
Outputs
f
= 620kHz, f
= 11MHz
0.04
800
Degrees
OUT
CLK
Differential Output Impedance
Ω
Tx PATH ANALOG OUTPUT
Bit E7 = 0 (default)
Bit E7 = 1
410
500
1.4
Full-Scale Output Voltage (Table 8)
V
mV
V
FS
Bits CM1 = 0, CM0 = 0 (default)
Bits CM1 = 0, CM0 = 1
Bits CM1 = 1, CM0 = 0
Bits CM1 = 1, CM0 = 1
1.27
1.48
1.25
1.1
Output Common-Mode Voltage
(Table 11)
V
COM
0.9
Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICS
ADC f = f
= 1.875MHz, DAC f
= 11MHz
CLK
=
OUTI
INI
INQ
Receive Transmit Isolation
90
dB
f
= 620kHz, f
OUTQ
AUXILIARY ADC (ADC1, ADC2)
Resolution
N
10
Bits
V
AD1 = 0 (default)
AD1 = 1
2.048
Full-Scale Reference
V
REF
V
DD
0 to
Analog Input Range
V
V
REF
Analog Input Impedance
Input-Leakage Current
At DC
500
kΩ
µA
Measured at unselected input from 0 to
0.1
V
REF
Gain Error
GE
ZE
Includes reference error
-5
+5
%FS
mV
Zero-Code Error
Differential Nonlinearity
Integral Nonlinearity
Supply Current
2
DNL
INL
0.53
0.45
210
LSB
LSB
µA
6
_______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, unless otherwise noted. C < 5pF on all aux-DAC outputs. Typical values are at T = +25°C.) (Note 1)
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
AUXILIARY DACs (DAC1, DAC2, DAC3)
Resolution
N
12
Bits
Integral Nonlinearity
INL
1.25
LSB
Guaranteed monotonic over codes 100 to
4000 (Note 2)
Differential Nonlinearity
DNL
-1.0
0.65
+1.2
0.1
LSB
Gain Error
GE
ZE
R > 200kΩ
L
0.7
0.6
%FS
%FS
V
Zero-Code Error
Output-Voltage Low
Output-Voltage High
DC Output Impedance
Settling Time
R > 200kΩ
L
V
OL
V
R > 200kΩ
L
2.56
V
OH
DC output at midscale
4
1
Ω
From 1/4 FS to 3/4 FS, within 10 LSB
From 0 to FS transition
µs
Glitch Impulse
24
nV•s
Rx ADC-Tx DAC TIMING CHARACTERISTICS
CLK Rise to Channel-I Output Data
Valid
t
Figure 3 (Note 2)
Figure 3 (Note 2)
Figure 6 (Note 2)
5.3
6.8
10
7.0
9.1
8.5
ns
ns
ns
DOI
CLK Fall to Channel-Q Output
Data Valid
t
11.3
DOQ
I-DAC DATA to CLK Fall Setup
Time
t
DSI
Q-DAC DATA to CLK Rise Setup
Time
t
Figure 6 (Note 2)
Figure 6 (Note 2)
Figure 6 (Note 2)
10
0
ns
ns
ns
DSQ
CLK Fall to I-DAC Data Hold Time
t
DHI
CLK Rise to Q-DAC Data Hold
Time
t
0
DHQ
CLK Duty Cycle
50
15
%
%
ns
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
20% to 80%
2.5
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 7, Note 2)
Falling Edge of CS to Rising Edge
of First SCLK Time
t
10
ns
CSS
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Period
t
10
0
ns
ns
ns
ns
ns
ns
ns
ns
DS
DH
CH
t
t
25
25
50
10
80
t
CL
CP
CS
t
t
SCLK to CS Setup Time
CS High Pulse Width
t
CSW
CS High to DOUT Active High
t
Bit AD0 set
200
CSD
_______________________________________________________________________________________
7
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFP
REFN
C
= 0.33µF, unless otherwise noted. C < 5pF on all aux-DAC outputs. Typical values are at T = +25°C.) (Note 1)
COM
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
4.36
200
200
MAX
UNITS
Bit AD0 set, no averaging (see Table 15),
= 11MHz,
CLK divider = 4 (see Table 16)
CS High to DOUT Low (Aux-ADC
Conversion Time)
t
f
µs
CONV
CLK
DOUT Low to CS Setup Time
SCLK Low to DOUT Data Out
CS High to DOUT High Impedance
t
t
Bit AD0, AD10 set
Bit AD0, AD10 set
Bit AD0, AD10 set
ns
ns
ns
DCS
t
14.5
CD
CHZ
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 8)
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
82.2
29
Shutdown Wake-Up Time
Idle Wake-Up Time (With CLK)
Standby Wake-Up Time
t
µs
µs
µs
WAKE,SD
From shutdown to Tx mode, DAC settles to
within 10 LSB error
From idle to Rx mode with CLK present
during idle, ADC settles to within 1dB SINAD
9.6
7.6
17.5
24
t
t
WAKE,ST0
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error
From standby to Rx mode, ADC settles to
within 1dB SINAD
WAKE,ST1
From standby to Tx mode, DAC settles to
10 LSB error
Enable Time from Tx to Rx (Ext2-Tx
to Ext2-Rx, Ext4-Tx to Ext4-Rx, and
SPI4-Tx to SPI3-Rx States)
t
ADC settles to within 1dB SINAD
DAC settles to within 10 LSB error
ADC settles to within 1dB SINAD
DAC settles to within 10 LSB error
500
500
8.1
7.0
ns
ns
µs
µs
ENABLE, RX
Enable Time from Rx to Tx (Ext1-Rx
to Ext1-Tx, Ext4-Rx to Ext4-Tx, and
SPI3-Rx to SPI4-Tx States)
t
ENABLE, TX
Enable Time from Tx to Rx (Ext1-Tx
to Ext1-Rx, Ext3-Tx to Ext3-Rx, and
SPI1-Tx to SPI1-Rx States)
t
ENABLE, RX
Enable Time from Rx to Tx (Ext2-Rx
to Ext2-Tx, Ext3-Rx to Ext3-Tx, and
SPI1-Rx to SPI2-Tx States)
t
ENABLE,TX
INTERNAL REFERENCE (V
Positive Reference
= V ; V
, V
, V
levels are generated internally)
REFIN
DD REFP REFN COM
V
V
- V
0.256
V
V
REFP
REFN
COM
Negative Reference
- V
-0.256
COM
V
/ 2
V
/ 2
DD
DD
Common-Mode Output Voltage
V
V
/ 2
V
COM
DD
2
- 0.15
+ 0.15
Maximum REFP/REFN/COM
Source Current
I
mA
SOURCE
8
_______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFP
REFN
C
= 0.33µF, unless otherwise noted. C < 5pF on all aux-DAC outputs. Typical values are at T = +25°C.) (Note 1)
COM
L
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
mA
Maximum REFP/REFN/COM
Sink Current
I
2
SINK
Differential Reference Output
V
V
- V
REFN
+0.460 +0.512 +0.548
18
V
REF
REFP
Differential Reference Temperature
Coefficient
REFTC
ppm/°C
BUFFERED EXTERNAL REFERENCE (external V
= 1.024V applied; V
, V
, V
levels are generated internally)
REFIN
REFP REFN COM
Reference Input Voltage
V
1.024
0.512
V
V
V
REFIN
Differential Reference Output
Common-Mode Output Voltage
V
V
- V
REFP REFN
DIFF
V
V
/ 2
COM
DD
Maximum REFP/REFN/COM
Source Current
I
2
mA
mA
SOURCE
Maximum REFP/REFN/COM
Sink Current
I
2
SINK
REFIN Input Current
-0.7
500
µA
REFIN Input Resistance
kΩ
DIGITAL INPUTS (CLK, SCLK, DIN, CS, D0–D9, T/R, SHDN)
Input High Threshold
Input Low Threshold
V
0.7 x OV
V
V
INH
DD
V
0.3 x OV
DD
INL
D0–D9, CLK, SCLK, DIN, CS, T/R,
SHDN = OGND or OV
Input Leakage
DI
-1
+1
µA
pF
IN
DD
Input Capacitance
DC
5
5
IN
DIGITAL OUTPUTS (D0–D9, DOUT)
Output-Voltage Low
V
I
I
= 200µA
0.2 x OV
DD
V
V
OL
SINK
Output-Voltage High
V
= 200µA
0.8 x OV
-1
OH
SOURCE
DD
Tri-State Leakage Current
Tri-State Output Capacitance
I
+1
µA
pF
LEAK
C
OUT
Note 1: Specifications from T = +25°C to +85°C are guaranteed by production tests. Specifications from T = +25°C to -40°C are
A
A
guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.
Note 3: The minimum clock frequency (f
) for the MAX19708 is 1.5MHz (typ). The minimum aux-ADC sample rate clock frequen-
CLK
cy (ACLK) is determined by f
and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 1.5MHz /
CLK
128 = 11.7kHz. The aux-ADC conversion time does not include the time to clock the serial data out of the SPI. The maximum
conversion time (for no averaging, NAVG = 1) will be t (max) = (12 x 1 x 128) / 1.5MHz = 1024µs.
CONV
Note 4: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second
channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel
FFT test tone.
Note 6: Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output
signals using a sine-wave fit.
_______________________________________________________________________________________
9
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Typical Operating Characteristics
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFP
REFN
C
COM
= 0.33µF, T = +25°C, unless otherwise noted.)
A
Rx ADC CHANNEL-IA
TWO-TONE FFT PLOT
Rx ADC CHANNEL-IA FFT PLOT
Rx ADC CHANNEL-QA FFT PLOT
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
0
f = 1.885MHz
f
= 1.882886MHz
f
= 1.882886MHz
QA
1
IA
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f = 1.985MHz
2
A
= -7dBFS
IA
PER TONE
4096-POINT
DATA RECORD
f
f
2
1
HD3
HD2
HD2
HD3
0
1.1
2.2
3.3
4.4
5.5
0
1.1
2.2
3.3
4.4
5.5
0
1.1
2.2
3.3
4.4
5.5
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
Rx ADC CHANNEL-QA
TWO-TONE FFT PLOT
Rx ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT FREQUENCY
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
57
55
53
51
49
47
45
57
f = 1.885MHz
1
f = 1.985MHz
2
55
53
51
49
47
45
A
= -7dBFS
IA
QA
IA
QA
IA
PER TONE
4096-POINT
DATA RECORD
f
f
2
1
0
1.1
2.2
3.3
4.4
5.5
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
FREQUENCY (MHz)
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
Rx ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT AMPLITUDE
Rx ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
80
75
70
65
60
55
50
-64
60
55
50
45
40
35
30
25
20
f
= 1.875MHz
IN
IA
-66
-68
-70
-72
-74
-76
-78
-80
IA
QA
IA
QA
QA
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
-25
-20
-15
-10
-5
0
ANALOG INPUT AMPLITUDE (dBFS)
10 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Typical Operating Characteristics (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, T = +25°C, unless otherwise noted.)
A
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT AMPLITUDE
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
Rx ADC SIGNAL-TO-NOISE RATIO
vs. SAMPLING RATE
vs. ANALOG INPUT AMPLITUDE
60
55
50
45
40
35
30
25
20
80
75
70
65
60
55
50
45
40
56.0
55.5
55.0
54.5
54.0
53.5
53.0
f
= 1.875MHz
f
= 1.875MHz
IN
f
= 1.875MHz
IN
IN
QA
QA
IA
IA
IA
QA
-25
-20
-15
-10
-5
0
-25
-20
-15
-10
-5
0
2
3
4
5
6
7
8
9
10 11
ANALOG INPUT AMPLITUDE (dBFS)
ANALOG INPUT AMPLITUDE (dBFS)
SAMPLING RATE (MHz)
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. SAMPLING RATE
Rx ADC SPURIOUS-FREE DYNAMIC
RANGE vs. SAMPLING RATE
Rx ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
57.0
56.5
56.0
55.5
55.0
54.5
54.0
53.5
53.0
52.5
52.0
57.0
56.5
56.0
55.5
80
78
76
74
72
70
68
66
f
= 1.875MHz
f
= 1.875MHz
f
= 1.875MHz
IN
IN
IN
IA
QA
QA
55.0
54.5
54.0
53.5
53.0
52.5
52.0
QA
IA
IA
2
3
4
5
6
7
8
9
10 11
2
3
4
5
6
7
8
9
10 11
35
40
45
50
55
60
65
SAMPLING RATE (MHz)
SAMPLING RATE (MHz)
CLOCK DUTY CYCLE (%)
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLE
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
Rx ADC OFFSET ERROR
vs. TEMPERATURE
57.0
56.5
56.0
55.5
55.0
54.5
54.0
53.5
53.0
52.5
52.0
80
78
76
74
72
70
68
66
64
62
60
1.00
f
= 1.875MHz
f = 1.875MHz
IN
IN
0.75
0.50
0.25
0
IA
QA
IA
IA
QA
-0.25
-0.50
-0.75
-1.00
QA
35
40
45
50
55
60
65
35
40
45
50
55
60
65
-40
-15
10
35
60
85
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
TEMPERATURE (°C)
______________________________________________________________________________________ 11
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Typical Operating Characteristics (continued)
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFP
REFN
C
COM
= 0.33µF, T = +25°C, unless otherwise noted.)
A
Tx PATH SPURIOUS-FREE DYNAMIC
RANGE vs. SAMPLING RATE
Rx ADC GAIN ERROR
vs. TEMPERATURE
77
Tx PATH SPURIOUS-FREE DYNAMIC
RANGE vs. OUTPUT FREQUENCY
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
78.0
75.5
73.0
70.5
68.0
65.5
63.0
f
= 617kHz
OUT
76
ID
75
74
QA
ID
73
72
71
70
69
68
67
IA
QD
QD
8
-40
-15
10
35
60
85
2
3
4
5
6
7
9
10 11
100 200 300 400 500 600 700 800
OUTPUT FREQUENCY (MHz)
TEMPERATURE (°C)
SAMPLING RATE (MHz)
Tx PATH SPURIOUS-FREE DYNAMIC
RANGE vs. OUTPUT AMPLITUDE
Tx PATH CHANNEL-ID SPECTRAL PLOT
Tx PATH CHANNEL-QD SPECTRAL PLOT
80
75
70
65
60
55
50
45
40
35
30
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
= 617kHz
f
= 617kHz
QD
f
= 620kHz
ID
OUT
QA
IA
0.20 0.73 1.26 1.79 2.32 2.85 3.38 3.91 4.44 4.97 5.50
FREQUENCY (MHz)
0.20 0.73 1.26 1.79 2.32 2.85 3.38 3.91 4.44 4.97 5.50
FREQUENCY (MHz)
-30
-25
-20
-15
-10
-5
0
OUTPUT AMPLITUDE (dBFS)
Tx PATH CHANNEL-ID SPECTRAL PLOT
WITH IMAGE REJECTION
Tx PATH CHANNEL-ID TWO-TONE
SPECTRAL PLOT
Tx PATH CHANNEL-QD TWO-TONE
SPECTRAL PLOT
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
f
f
= 800kHz,
= 5.12MHz
f = 560kHz,
1
f = 660kHz
2
f = 560kHz,
1
f = 660kHz
2
ID
CLK
IMAGE REJECTION
0.200
1.184
2.168
3.152
4.136
5.120
0.20 0.73 1.26 1.79 2.32 2.85 3.38 3.91 4.44 4.97 5.50
FREQUENCY (MHz)
0.20 0.73 1.26 1.79 2.32 2.85 3.38 3.91 4.44 4.97 5.50
FREQUENCY (MHz)
0.692
1.676
2.660
3.644
4.628
FREQUENCY (MHz)
12 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Typical Operating Characteristics (continued)
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, T = +25°C, unless otherwise noted.)
A
TRANSMIT FILTER
FREQUENCY RESPONSE
SUPPLY CURRENT vs. SAMPLING RATE
Rx ADC INTEGRAL NONLINEARITY
1.00
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
Ext4 MODE
0
0.75
0.50
I
Tx MODE
Rx MODE
-20
VDD
0.25
0
-40
-0.25
-0.50
-0.75
-1.00
-60
-80
I
VDD
-100
0.1
1
10
2
3
4
5
6
7
8
9
10 11
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
FREQUENCY (MHz)
SAMPLING RATE (MHz)
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
Tx PATH INTEGRAL NONLINEARITY
Tx PATH DIFFERENTIAL NONLINEARITY
0.520
0.515
0.510
0.505
0.500
0.8
0.6
0.4
0.75
0.60
0.45
0.30
0.15
0
V
- V
REFN
REFP
0.2
0
-0.15
-0.30
-0.45
-0.60
-0.75
-0.2
-0.4
-0.6
-0.8
-40
-15
10
35
60
85
0
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
0
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
TEMPERATURE (°C)
TRANSMIT FILTER PASSBAND RIPPLE
AUX-DAC INTEGRAL NONLINEARITY
AUX-DAC DIFFERENTIAL NONLINEARITY
0.04
0.02
2.0
1.5
0.8
0.6
0.4
0.2
0
0
1.0
-0.02
-0.04
-0.06
-0.08
-0.10
-0.12
-0.14
0.5
0
-0.5
-1.0
-1.5
-2.0
-0.2
-0.4
-0.6
-0.8
0
0.3
0.6
0.9
1.2
0
1024
2048
3072
4096
0
1024
2048
3072
4096
FREQUENCY (MHz)
DIGITAL INPUT CODE
DIGITAL INPUT CODE
______________________________________________________________________________________ 13
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Typical Operating Characteristics (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 11MHz (50% duty cycle), Rx ADC input
DD
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
= C
=
REFN
REFP
C
COM
= 0.33µF, T = +25°C, unless otherwise noted.)
A
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
AUX-ADC INTEGRAL NONLINEARITY
AUX-ADC DIFFERENTIAL NONLINEARITY
3.0
2.5
2.0
1.5
1.0
0.5
0
2.0
1.5
1.0
0.5
0
0.8
0.4
0
-0.5
-1.0
-1.5
-2.0
-0.4
-0.8
0.001
0.01
0.1
1
10
100
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
OUTPUT SOURCE CURRENT (mA)
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
AUX-DAC SETTLING TIME
3.0
2.5
2.0
1.5
1.0
0.5
0
STEP FROM 1/4FS TO 3/4FS
500mV/div
0.001
0.01
0.1
1
10
100
500ns/div
OUTPUT SINK CURRENT (mA)
Pin Description
PIN
NAME
FUNCTION
Upper Reference Voltage. Bypass with a 0.33µF capacitor to GND as close to REFP as possible.
1
REFP
2, 8, 11, 31,
33, 39, 43
Analog Supply Voltage. Bypass V
a 0.1µF capacitor.
to GND with a combination of a 2.2µF capacitor in parallel with
DD
V
DD
3
4
IAP
IAN
Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP.
Channel-IA Negative Analog Input. For single-ended operation, connect IAN to COM.
Analog Ground. Connect all GND pins to ground plane.
5, 7, 12, 32, 42
GND
CLK
QAN
6
9
Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs.
Channel-QA Negative Analog Input. For single-ended operation, connect QAN to COM.
14 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Pin Description (continued)
PIN
NAME
FUNCTION
10
QAP
Channel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP.
Digital I/O. Outputs for receive ADC in Rx mode. Inputs for transmit DAC in Tx mode. D9 is the most
significant bit (MSB) and D0 is the least significant bit (LSB).
13–18, 21–24
D0–D9
OGND
19
20
Output-Driver Ground
Output-Driver Power Supply. Supply range from +1.8V to V . Bypass OV
DD
to OGND with a
DD
OV
DD
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
25
26
SHDN
Active-Low Shutdown Input. Apply logic-low to place the MAX19708 in shutdown.
Aux-ADC Digital Output
DOUT
Transmit- or Receive-Mode Select Input. T/R logic-low input sets the device in receive mode. A
logic-high input sets the device in transmit mode.
27
T/R
28
29
DIN
SCLK
CS
3-Wire Serial-Interface Data Input. Data is latched on the rising edge of the SCLK.
3-Wire Serial-Interface Clock Input
30
3-Wire Serial-Interface Chip-Select Input. Logic-low enables the serial interface.
Analog Input for Auxiliary ADC
34
ADC2
ADC1
DAC3
DAC2
DAC1
IDN, IDP
35
Analog Input for Auxiliary ADC
36
Analog Output for Auxiliary DAC3
37
Analog Output for Auxiliary DAC2
38
Analog Output for Auxiliary DAC1 (AFC DAC, V = 1.1V During Power-Up)
OUT
40, 41
44, 45
46
Tx Path Channel-ID Differential Voltage Output
QDN, QDP Tx Path Channel-QD Differential Voltage Output
REFIN
COM
Reference Input. Connect to V
for internal reference.
DD
47
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
Negative Reference I/O. Rx ADC conversion range is (V
0.1µF capacitor.
- V
). Bypass REFN to GND with a
REFP
REFN
48
—
REFN
EP
Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
and AFC level setting. The aux-ADC features data aver-
aging to reduce processor overhead and a selectable
clock-divider to program the conversion rate.
Detailed Description
The MAX19708 integrates a dual, 10-bit Rx ADC and a
dual, 10-bit Tx DAC with TD-SCDMA baseband filters
while providing ultra-low power and high dynamic per-
formance at 11Msps conversion rate. The Rx ADC ana-
log input amplifiers are fully differential and accept
The MAX19708 includes a 3-wire serial interface to
control operating modes and power management. The
serial interface is SPI™ and MICROWIRE™ compatible.
The MAX19708 serial interface selects shutdown, idle,
standby, transmit (Tx), and receive (Rx) modes, as well
as controlling aux-DAC and aux-ADC channels.
1.024V
full-scale signals. The Tx DAC analog out-
P-P
puts are fully differential with 410mV or 500mV full-
scale output, selectable common-mode DC level, and
adjustable I/Q offset trim.
The Rx ADC and Tx DAC share a common digital I/O to
reduce the digital interface to a single 10-bit parallel
multiplexed bus. The 10-bit digital bus operates on a
single +1.8V to +3.3V supply.
The MAX19708 integrates three 12-bit auxiliary DAC
(aux-DAC) channels and a 10-bit, 333ksps auxiliary
ADC (aux-ADC) with 4:1 input multiplexer. The aux-DAC
channels feature 1µs settling time for fast AGC, VGA,
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
______________________________________________________________________________________ 15
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
is the difference between V
and V
. See the
REFN
Dual 10-Bit Rx ADC
The ADC uses a seven-stage, fully differential, pipelined
architecture that allows for high-speed conversion while
minimizing power consumption. Samples taken at the
inputs move progressively through the pipeline stages
every half clock cycle. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for channel IA and 5.5 clock cycles for channel
REFP
Reference Configurations section for details.
Input Track-and-Hold (T/H) Circuits
Figure 1 displays a simplified diagram of the Rx ADC
input track-and-hold (T/H) circuitry. Both ADC inputs
(IAP, QAP, IAN, and QAN) can be driven either differen-
tially or single-ended. Match the impedance of IAP and
IAN, as well as QAP and QAN, and set the input signal
QA. The ADC full-scale analog input range is
V
REF
REF
common-mode voltage within the V /2 ( 200mV) Rx
DD
ADC range for optimum performance.
with a V / 2 ( 0.2V) common-mode input range. V
DD
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
S4a
S4b
IAP
IAN
OUT
OUT
C2a
C2b
S4c
S1
C1b
S3b
S5b
COM
S2b
CLK
HOLD
HOLD
INTERNAL
BIAS
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
TRACK
TRACK
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
S4a
S4b
QAP
QAN
OUT
C2a
C2b
S4c
S1
MAX19708
OUT
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
Figure 1. Rx ADC Internal T/H Circuits
16 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Table 1. Rx ADC Output Codes vs. Input Voltage
DIFFERENTIAL INPUT
VOLTAGE
DIFFERENTIAL INPUT (LSB)
OFFSET BINARY (D0–D9)
OUTPUT DECIMAL CODE
V
V
x 512/512
x 511/512
511 (+Full Scale - 1 LSB)
510 (+Full Scale - 2 LSB)
+1
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
1023
1022
513
512
511
1
REF
REF
V
V
x 1/512
x 0/512
x 1/512
REF
REF
0 (Bipolar Zero)
-1
-V
REF
-V
x 511/512
x 512/512
-511 (-Full Scale +1 LSB)
-512 (-Full Scale)
REF
REF
-V
0
multiplexed at the D0–D9 outputs. CHI data is updated
on the rising edge and CHQ data is updated on the
falling edge of the CLK. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for CHI and 5.5 clock cycles for CHQ.
2 x V
REF
V
= V
- V
1 LSB =
REF
REFP REFN
1024
V
V
REF
REF
11 1111 1111
11 1111 1110
11 1111 1101
Digital Input/Output Data (D0–D9)
D0–D9 are the Rx ADC digital logic outputs when the
MAX19708 is in receive mode. This bus is shared with
the Tx DAC digital logic inputs and operates in half-
duplex mode. D0–D9 are the Tx DAC digital logic inputs
when the MAX19708 is in transmit mode. The logic level
10 0000 0001
10 0000 0000
01 1111 1111
(COM)
is set by OV
from 1.8V to V . The digital output cod-
DD
DD
ing is offset binary (Table 1). Keep the capacitive load
on the digital outputs D0–D9 as low as possible
(< 15pF) to avoid large digital currents feeding back into
the analog portion of the MAX19708 and degrading its
dynamic performance. Buffers on the digital outputs iso-
late the outputs from heavy capacitive loads. Adding
100Ω resistors in series with the digital outputs close to
the MAX19708 will help improve ADC performance.
Refer to the MAX19708EVKIT schematic for an example
of the digital outputs driving a digital buffer through
100Ω series resistors.
00 0000 0011
00 0000 0010
00 0000 0001
00 0000 0000
-512 -511 -510 -509
-1 0+
(COM)
INPUT VOLTAGE (LSB)
1
+512
+509 +510 +511
Figure 2. Rx ADC Transfer Function
During SHDN, IDLE, and STBY states, D0–D9 are inter-
nally pulled up to prevent floating digital inputs. To
ensure no current flows through D0–D9 I/O, the external
Rx ADC System Timing Requirements
Figure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channel I
(CHI) and channel Q (CHQ) are sampled on the rising
edge of the clock signal (CLK) and the resulting data is
bus needs to be either tri-stated or pulled up to OV
and should not be pulled to ground.
DD
______________________________________________________________________________________ 17
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
5.5 CLOCK-CYCLE LATENCY (CHQ)
5 CLOCK-CYCLE LATENCY (CHI)
CHI
CHQ
t
CLK
t
t
CH
CL
CLK
t
DOQ
t
DOI
D0–D9
D0Q
D1I
D1Q
D2I
D2Q
D3I
D3Q
D4I
D4Q
D5I
D5Q
D6I
D6Q
Figure 3. Rx ADC System Timing Diagram
Table 2. Tx Path Output Voltage vs. Input Codes
(Internal Reference Mode V
= 1.024V, External Reference Mode V
Full Scale)
P-P
= V ; V = 410 for 820mV
REFIN FS P-P
REFDAC
REFDAC
Full Scale and V = 500 for 1V
FS
DIFFERENTIAL OUTPUT VOLTAGE (V)
OFFSET BINARY (D0–D9)
INPUT DECIMAL CODE
V
1023
1023
REFDAC
1024
V
×
×
11 1111 1111
1023
(
)
)
FS
V
1021
1023
REFDAC
1024
V
(
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
1022
513
512
511
1
FS
V
3
1023
REFDAC
1024
V
×
×
(
(
)
)
FS
V
1
1023
REFDAC
1024
V
FS
−V
1
1023
REFDAC
1024
V
×
(
)
FS
−V
1021
1023
1023
1023
REFDAC
1024
V
×
(
(
)
)
FS
−V
REFDAC
1024
V
×
0
FS
The TD-SCDMA filters are tuned for 1.32MHz cutoff fre-
quency and > 55dB image rejection at f
Dual 10-Bit Tx DAC and Transmit Path
The dual 10-bit digital-to-analog converters (Tx DAC)
operate with clock speeds up to 11MHz. The Tx DAC
digital inputs, D0–D9, are multiplexed on a single 10-bit
bus. The voltage reference determines the Tx path full-
scale voltage at IDP, IDN and QDP, QDN analog out-
puts. See the Reference Configurations section for
setting reference voltage. Each Tx path output channel
integrates a lowpass filter tuned to meet the TD-SCDMA
spectral mask requirements.
=
IMAGE
= 5.12MHz. See
4.32MHz, f
= 800kHz, and f
OUT
CLK
Figure 4 for an illustration of the filter frequency response.
Buffer amplifiers follow the TD-SCDMA filters. The amplifi-
er outputs (IDN, IDP, QDN, QDP) are biased at an
adjustable common-mode DC level and designed to
drive a differential input stage with ≥ 70kΩ input imped-
ance. This simplifies the analog interface between RF
18 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
DAC sin(x)/x
RESPONSE
OCCUPIED
CHANNEL
AMPLITUDE
TD-SCDMA
FILTER RESPONSE
0dB
-3dB
Tx PATH:
-15dB
SFDR = 73dBc
THD = -71dB
SNR = 56.5dB
-49.3dB
-55dB (min)
-57.1dB
FREQ (MHz)
4.32
IMAGE
5.12
0.8
CHANNEL EDGE
1.27
NOT TO SCALE
f
f
CLK
C
Figure 4. TD-SCDMA Filter Frequency Response
quadrature upconverters and the MAX19708. Many RF
upconverters require a 0.9V to 1.4V common-mode bias.
The MAX19708 common-mode DC bias eliminates dis-
crete level-setting resistors and code-generated level
shifting while preserving the full dynamic range of each
Tx DAC. The Tx DAC differential analog outputs cannot
be used in single-ended mode because of the internally
generated common-mode DC level. Table 2 shows the
Tx path output voltage vs. input codes. Table 11 shows
the selection of DC common-mode levels. See Figure 5
for an illustration of the Tx DAC analog output levels.
3-Wire Serial Interface and
Operation Modes
The 3-wire serial interface controls the MAX19708 oper-
ation modes as well as the three 12-bit aux-DACs and
the 10-bit aux-ADC. Upon power-up, program the
MAX19708 to operate in the desired mode. Use the 3-
wire serial interface to program the device for shutdown,
idle, standby, Rx, Tx, aux-DAC controls, or aux-ADC
conversion. A 16-bit data register sets the mode control
as shown in Table 3. The 16-bit word is composed of
A3–A0 control bits and D11–D0 data bits. Data is shifted
in MSB first (D11) and LSB last (A0). Tables 4, 5, and 6
show the MAX19708 operating modes and SPI com-
mands. The serial interface remains active in all modes.
The buffer amplifiers also feature a programmable full-
scale output level of 410mV or 500mV and indepen-
dent DC offset trim on each I/Q channel. Both features
are configured through the SPI interface. The DC offset
correction is used to optimize sideband and carrier sup-
pression in the Tx signal path (see Tables 8 and 10).
SPI Register Description
Program the control bits, A3–A0, in the register as shown
in Table 3 to select the operating mode. Modify A3–A0
bits to select from ENABLE-16, Aux-DAC1, Aux-DAC2,
Aux-DAC3, IOFFSET, QOFFSET, Aux-ADC, ENABLE-8,
and COMSEL modes. ENABLE-16 is the default operat-
ing mode. This mode allows for shutdown, idle, and
standby states as well as switching between FAST,
SLOW, Rx and Tx modes. Table 4 shows the MAX19708
power-management modes. Table 5 shows the T/R pin-
controlled external Tx-Rx switching modes. Table 6
shows the SPI-controlled Tx-Rx switching modes.
Tx DAC Timing
Figure 6 shows the relationship between the clock, input
data, and analog outputs. Data for the I channel (ID) is
latched on the falling edge of the clock signal, and Q-
channel (QD) data is latched on the rising edge of the
clock signal. Both I and Q outputs are simultaneously
updated on the next rising edge of the clock signal.
______________________________________________________________________________________ 19
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
MAX19708
EXAMPLE:
Tx DAC
FILTER
I-CH
Tx RFIC INPUT REQUIREMENTS
• DC COMMON-MODE BIAS =
1.0V (MIN), 1.2V (TYP)
0
90
• BASEBAND INPUT = 410mV
DC-COUPLED
Tx DAC
FILTER
Q-CH
FULL SCALE = 1.305V
COMMON-MODE LEVEL
SELECT CM1 = 1, CM0 = 0
V
= 1.10V
COM
V
V
= 1.10V
COM
DIFF
=
410mV
ZERO SCALE = 0.895V
0V
Figure 5. Tx DAC Common-Mode DC Level at IDN, IDP or QDN, QDP Differential Outputs
CLK
t
t
DHQ
DSQ
Q: N - 2
I: N - 1
Q: N - 1
Q: N
I: N + 1
D0–D9
I: N
t
t
DHI
DSI
N - 2
N - 2
ID
N - 1
N - 1
N
N
QD
Figure 6. Tx DAC System Timing Diagram
20 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Table 3. MAX19708 Mode Control
D11
D10
15
D9
14
D8
13
D7
12
D6
11
D5
10
D4
9
D3
8
D2
7
D1
6
D0 A3 A2 A1
A0
REGISTER
NAME
(MSB)
5
4
3
2
1 (LSB)
E11 = 0
Reserved Reserved
E10 = 0
ENABLE-16
E9
—
E7
E6
E5
E4
E3
E2
E1
E0
0
0
0
0
Aux-DAC1
Aux-DAC2
Aux-DAC3
IOFFSET
1D11
2D11
3D11
—
1D10
2D10
3D10
—
1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0
2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0
3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
IO5 IO4 IO3 IO2 IO1 IO0
QO5 QO4 QO3 QO2 QO1 QO0
QOFFSET
COMSEL
—
—
—
—
—
—
—
—
CM1 CM0
AD11 = 0
Reserved
Aux-ADC
AD10
—
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0
1
1
0
1
0
1
0
ENABLE-8
—
—
—
—
—
—
—
E3
E2
E1
E0
— = Not used.
Table 4. Power-Management Modes
ADDRESS
DATA BITS
T/R
FUNCTION
(POWER
MODE
DESCRIPTION
COMMENT
MANAGEMENT)
A3 A2 A1 A0 E9* E3 E2 E1 E0 PIN 27
Rx ADC = OFF
Tx DAC = OFF
Aux-DAC = OFF
Aux-ADC = OFF
CLK = OFF
Device is in complete
shutdown.
Overrides T/R pin.
1X000
XX001
1X010
X
X
X
SHDN
SHUTDOWN
REF = OFF
0000
(16-Bit Mode)
or
1000
(8-Bit Mode)
Rx ADC = OFF
Tx DAC = OFF
Aux-DAC = Last State Moderate idle power.
CLK = ON
REF = ON
Fast turn-on time.
IDLE
IDLE
Overrides T/R pin.
Rx ADC = OFF
Tx DAC = OFF
Aux-DAC = Last State
Aux-ADC = OFF
CLK = OFF
Slow turn-on time.
Low standby power.
Overrides T/R pin.
STBY
STANDBY
REF = ON
X = Don’t care.
*Bit E9 is not available in 8-bit mode.
______________________________________________________________________________________ 21
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Table 5. External Tx-Rx Control Using T/R Pin (T/R = 0 = Rx Mode, T/R = 1 = Tx Mode)
FUNCTION
STATE Rx TO Tx-Tx TO Rx
SWITCHING SPEED
ADDRESS
DATA BITS
T/R
DESCRIPTION
COMMENT
A3 A2 A1 A0 E3 E2 E1 E0 PIN 27
Rx Mode:
Moderate Power:
Fast Rx to Tx when T/R
transitions 0 to 1.
Rx ADC = ON
Tx DAC = ON
Rx Bus = Enable
0
Ext1-Rx
0011
FAST-SLOW
Ext1-Tx
Tx Mode:
Low Power:
Slow Tx to Rx when T/R
transitions 1 to 0.
Rx ADC = OFF
Tx DAC = ON
Tx Bus = Enable
1
Rx Mode:
Low Power:
Slow Rx to Tx when T/R
transitions 0 to 1.
Ext2-Rx
(Default)
Rx ADC = ON
Tx DAC = OFF
Rx Bus = Enable
0
0100
SLOW-FAST
Ext2-Tx
Tx Mode:
Moderate Power:
Rx ADC = ON
Tx DAC = ON
Tx Bus = Enable
Fast Tx to Rx when T/R
transitions 1 to 0.
1
0000
(16-Bit Mode)
or
1000
Rx Mode:
Low Power:
Slow Rx to Tx when T/R
transitions 0 to 1.
Rx ADC = ON
Tx DAC = OFF
Rx Bus = Enable
(8-Bit Mode)
0
Ext3-Rx
0101
SLOW-SLOW
Ext3-Tx
Tx Mode:
Low Power:
Slow Tx to Rx when T/R
transitions 1 to 0.
Rx ADC = OFF
Tx DAC = ON
Tx Bus = Enable
1
Rx Mode:
Moderate Power:
Fast Rx to Tx when T/R
transitions 0 to 1.
Rx ADC = ON
Tx DAC = ON
Rx Bus = Enable
0
Ext4-Rx
0110
FAST-FAST
Tx Mode:
Moderate Power:
Fast Tx to Rx when T/R
transitions 1 to 0.
Rx ADC = ON
Tx DAC = ON
Tx Bus = Enable
1
Ext4-Tx
In ENABLE-16 mode, the aux-DACs have independent
control bits E4, E5, and E6, bit E7 sets the Tx path full-
scale ouputs, and bit E9 enables the aux-ADC. Table 7
shows the auxiliary DAC enable codes. Table 8 shows
the full-scale output selection. Table 9 shows the auxil-
iary ADC enable code. Bits E11 and E10 are reserved.
Program bits E11 and E10 to logic-low.
Modes aux-DAC1, aux-DAC2, and aux-DAC3 select the
aux-DAC channels named DAC1, DAC2, and DAC3
and hold the data inputs for each DAC. Bits _D11–_D0
22 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Table 6. Tx-Rx Control Using SPI Commands
FUNCTION
(Tx-Rx SWITCHING
SPEED)
ADDRESS
DATA BITS
T/R
MODE
DESCRIPTION
COMMENTS
A3 A2 A1 A0 E3 E2 E1 E0 PIN 27
Rx Mode:
Low Power:
Slow Rx to Tx through
SPI command.
Rx ADC = ON
Tx DAC = OFF
Rx Bus = Enable
1011
1100
1101
1110
X
X
X
X
SPI1-Rx
SLOW
SLOW
FAST
FAST
Tx Mode:
Low Power:
Slow Tx to Rx through
SPI command.
Rx ADC = OFF
Tx DAC = ON
Tx Bus = Enable
SPI2-Tx
SPI3-Rx
SPI4-Tx
0000
(16-Bit Mode)
or
1000
(8-Bit Mode)
Rx Mode:
Moderate Power:
Fast Rx to Tx through
SPI command.
Rx ADC = ON
Tx DAC = ON
Rx Bus = Enabled
Tx Mode:
Moderate Power:
Fast Tx to Rx through
SPI command.
Rx ADC = ON
Tx DAC = ON
Tx Bus = Enabled
X = Don’t care.
Table 7. Aux-DAC Enable Table
(ENABLE-16 Mode)
Table 8. Tx Path Full-Scale Select
(ENABLE-16 Mode)
E6 E5
E4
Aux-DAC3
Aux-DAC2
Aux-DAC1
ON
E7
0 (Default)
1
Tx-PATH OUTPUT FULL SCALE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
ON
ON
410mV
500mV
1
ON
ON
OFF
ON
0
ON
OFF
OFF
ON
1
ON
OFF
ON
Table 9. Aux-ADC Enable Table
(ENABLE-16 Mode)
0
OFF
OFF
OFF
OFF
1
ON
OFF
ON
E9
0 (Default)
1
SELECTION
0
OFF
OFF
Aux-ADC is Powered ON
Aux-ADC is Powered OFF
1
OFF
are the data inputs for each aux-DAC and can be pro-
grammed through SPI. The MAX19708 also includes
two 6-bit registers that can be programmed to adjust
the offsets for the Tx path I and Q channels indepen-
dently (see Table 10). Use the COMSEL mode to select
the output common-mode voltage with bits CM1 and
CM0 (see Table 11). Use aux-ADC mode to start the
auxiliary ADC conversion (see the 10-Bit, 333ksps
Auxiliary ADC section for details). Use ENABLE-8
mode for faster enable and switching between shut-
down, idle, and standby states as well as switching
between FAST, SLOW, Rx and Tx modes.
Shutdown mode offers the most dramatic power sav-
ings by shutting down all the analog sections of the
MAX19708 and placing the Rx ADC digital outputs in
______________________________________________________________________________________ 23
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Table 10. Offset Control Bits for I and Q Channels (IOFFSET or QOFFSET Mode)
BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE
OFFSET 1 LSB =
(VFS / 1023)
P-P
IO5/QO5
IO4/QO4
IO3/QO3
IO2/QO2
IO1/QO1
IO0/QO0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
-31 LSB
-30 LSB
-29 LSB
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
-2 LSB
-1 LSB
0mV
0mV (Default)
1 LSB
2 LSB
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
29 LSB
30 LSB
31 LSB
Note: For transmit full-scale select of 410mꢀV 1 LSB = ꢁ820mꢀ
/ 1023) = 0.8016mꢀ. For transmit full scale select of 500mꢀV 1 LSB =
P-P
ꢁ1ꢀ
/ 1023) = 0.9775mꢀ.
P-P
Table 11. Common-Mode Select
(COMSEL Mode)
mode. When the Rx ADC outputs transition from tri-
state to ON, the last converted word is placed on the
digital outputs.
CM1
CM0
Tx PATH OUTPUT COMMON MODE (V)
In standby mode, the reference is powered, but the rest
of the device functions are off. The wake-up time from
standby mode is 17.5µs to enter Rx mode and 24µs to
enter Tx mode. When the Rx ADC outputs transition
from tri-state to active, the last converted word is
placed on the digital outputs.
0
0
1
1
0
1
0
1
1.40 (Default)
1.25
1.10
0.90
FAST and SLOW Rx and Tx Modes
In addition to the external Tx-Rx control, the MAX19708
also features SLOW and FAST modes for switching
between Rx and Tx operation. In FAST Tx mode, the Rx
ADC core is powered on but the ADC core digital out-
puts are tri-stated on the D0–D9 bus; likewise, in FAST
Rx mode, the transmit path (DAC core and Tx filter) is
powered on but the DAC core digital inputs are tri-stat-
ed on the D0–D9 bus. The switching time between Tx to
Rx or Rx to Tx is FAST because the converters are on
and do not have to recover from a power-down state. In
FAST mode, the switching time between Rx to Tx and Tx
to Rx is 0.5µs. However, power consumption is higher
tri-state mode. When the Rx ADC outputs transition
from tri-state to ON, the last converted word is placed
on the digital outputs. The Tx DAC previously stored
data is lost when coming out of shutdown mode. The
wake-up time from shutdown mode is dominated by the
time required to charge the capacitors at REFP, REFN,
and COM. In internal reference mode and buffered
external reference mode, the wake-up time is typically
82.2µs to enter Rx mode and 29µs to enter Tx mode.
In idle mode, the reference and clock distribution cir-
cuits are powered, but all other functions are off. The
Rx ADC outputs are forced to tri-state. The wake-up
time is 9.6µs to enter Rx mode and 7.6µs to enter Tx
24 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
in this mode because both the Tx and Rx cores are
and Tx modes. Using the T/R pin provides faster switch-
ing between Rx and Tx modes. To override the external
Tx-Rx control, program the MAX19708 through the serial
interface. During SHDN, IDLE, or STBY modes, the T/R
input is overridden. To restore external Tx-Rx control,
program bit E3 low and exit the SHDN, IDLE, or STBY
modes through the serial interface.
always on. To prevent bus contention in these states,
the Rx ADC output buffers are tri-stated during Tx and
the Tx DAC input bus is tri-stated during Rx.
In SLOW mode, the Rx ADC core is off during Tx; like-
wise the Tx DAC and filters are turned off during Rx to
yield lower power consumption in these modes. For
example, the power in SLOW Tx mode is 35.1mW. The
power consumption during Rx is 24mW compared to
41.1mW power consumption in FAST mode. However,
the recovery time between states is increased. The
switching time in SLOW mode between Rx to Tx is 7µs
and Tx to Rx is 8.1µs.
SPI Timing
The serial digital interface is a standard 3-wire connec-
tion (CS, SCLK, DIN) compatible with SPI/QSPI™/
MICROWIRE/DSP interfaces. Set CS low to enable the
serial data loading at DIN or output at DOUT. Following a
CS high-to-low transition, data is shifted synchronously,
most significant bit first, on the rising edge of the serial
clock (SCLK). After 16 bits are loaded into the serial
input register, data is transferred to the latch when CS
transitions high. CS must transition high for a minimum of
80ns before the next write sequence. The SCLK can idle
either high or low between transitions. Figure 7 shows
the detailed timing diagram of the 3-wire serial interface.
External T/R Switching Control vs.
Serial-Interface Control
Bit E3 in the ENABLE-16 or ENABLE-8 register deter-
mines whether the device Tx-Rx mode is controlled
externally through the T/R input (E3 = low) or through the
SPI command (E3 = high). By default, the MAX19708 is
in the external Tx-Rx control mode. In the external control
mode, use the T/R input (pin 27) to switch between Rx
QSPI is a trademark of Motorola, Inc.
16-BIT OR 8-BIT WRITE INTO SPI (DIN)
16-BIT OR 8-BIT WRITE
INTO SPI DURING
10-BIT READ OUT OF AUX-ADC (DOUT) WITH
SIMULTANEOUS 16-BIT WRITE INTO SPI (DIN)
AUX-ADC CONVERSION
t
CSS
t
CP
t
CS
CS
t
CSW
t
CONV
t
CL
t
t
CHZ
DCS
t
CSD
t
CH
t
DS
SCLK
t
CD
t
DH
MSB
BIT D11
(DIN)
MSB
D11 (16-BIT)
D3 (8-BIT)
LSB
BIT A0
(DIN)
D10 (16-BIT)
D2 (8-BIT)
LSB
A0
BIT D10
(DIN)
BIT D1
(DIN)
DIN
MSB
LSB
AUX-ADC
IS BUSY
DOUT
TRI-
STATED
BIT AD0
CLEARED
LSB
MSB
BIT D9
(DOUT)
LSB
BIT D0
(HELD)
DOUT = TRI-STATED WHEN
AUX-ADC IS IDLE
DOUT = ACTIVE WHEN
BIT AD0 IS SET
DOUT
BIT D0
AUX-ADC
DATA READY
(DOUT)
Figure 7. Serial-Interface Timing Diagram
______________________________________________________________________________________ 25
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
clock with low jitter and fast rise and fall times (< 2ns).
Mode-Recovery Timing
Specifically, sampling occurs on the rising edge of the
clock signal, requiring this edge to provide the lowest
possible jitter. Any significant clock jitter limits the SNR
performance of the on-chip Rx ADC as follows:
Figure 8 shows the mode-recovery timing diagram.
WAKE
t
is the wakeup time when exiting shutdown, idle,
or standby mode and entering Rx or Tx mode. t
ENABLE
is the recovery time when switching between either Rx
or Tx mode. t or t is the time for the Rx ADC
WAKE
ENABLE
to settle within 1dB of specified SINAD performance and
Tx DAC settling to 10 LSB error. t and t
times are measured after either the 16-bit serial com-
mand is latched into the MAX19708 by a CS transition
high (SPI controlled) or a T/R logic transition (external
Tx-Rx control). In FAST mode, the recovery time is 0.5µs
to switch between Tx or Rx modes.
⎛
⎞
1
SNR = 20 × log
WAKE
ENABLE
⎜
⎟
2 × π × f × t
⎝
⎠
IN
AJ
where f represents the analog input frequency and
IN
t
AJ
is the time of the clock jitter.
Clock jitter is especially critical for undersampling
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX19708 clock input operates
System Clock Input (CLK)
Both the Rx ADC and Tx DAC share the CLK input. The
CLK input accepts a CMOS-compatible signal level set
with an OV
/ 2 voltage threshold and accepts a 50%
DD
15% duty cycle.
by OV
from 1.8V to V . Since the interstage con-
DD
DD
version of the device depends on the repeatability of
the rising and falling edges of the external clock, use a
CS
SCLK
DIN
16-BIT SERIAL DATA INPUT
ADC DIGITAL OUTPUT.
SINAD SETTLES WITHIN 1dB
D0–D9
ID/QD
t
TO Rx MODE OR t
,
ENABLE RX
WAKE, SD, ST_
DAC ANALOG OUTPUT.
OUTPUT SETTLES TO 10 LSB ERROR
t
TO Tx MODE OR t
,
ENABLE TX
WAKE, SD, ST_
t
,
EXTERNAL T/R CONTROL
ENABLE TX
T/R
Rx - > Tx
t
,
EXTERNAL T/R CONTROL
ENABLE RX
T/R
Tx - > Rx
Figure 8. Mode-Recovery Timing Diagram
26 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
a conversion has no effect (see Table 12). Bit AD1
determines the internal reference of the auxiliary ADC
(see Table 13). Bits AD2 and AD3 determine the auxil-
iary ADC input source (see Table 14). Bits AD4, AD5,
and AD6 select the number of averages taken when a
single start-convert command is given. The conversion
time increases as the number of averages increases
(see Table 15). The conversion clock can be divided
down from the system clock by properly setting bits
AD7, AD8, and AD9 (see Table 16). The aux-ADC out-
put data can be written out of DOUT by setting bit
AD10 high (see Table 17).
12-Bit, Auxiliary Control DACs
The MAX19708 includes three 12-bit aux-DACs (DAC1,
DAC2, DAC3) with 1µs settling time for controlling vari-
able-gain amplifier (VGA), automatic gain-control
(AGC), and automatic frequency-control (AFC) func-
tions. The aux-DAC output range is 0.1V to 2.56V.
During power-up, the VGA and AGC outputs (DAC2
and DAC3) are at zero. The AFC DAC (DAC1) is at 1.1V
during power-up. The aux-DACs can be independently
controlled through the SPI bus, except during SHDN
mode where the aux-DACs are turned off completely
and the output voltage is set to zero. In STBY and IDLE
modes the aux-DACs maintain the last value. On wakeup
from SHDN, the aux-DACs resume the last values.
The aux-ADC features a 4:1 input multiplexer to allow
measurements on four input sources. The input sources
are selected by AD3 and AD2 (see Table 14). Two of
the multiplexer inputs (ADC1 and ADC2) can be con-
nected to external sources such as an RF power detec-
tor like the MAX2208 or temperature sensor like the
MAX6613. The other two multiplexer inputs are internal
Loading on the aux-DAC outputs should be carefully
observed to achieve specified settling time and stabili-
ty. The capacitive load must be kept to a maximum of
5pF including package and trace capacitance. The
resistive load must be greater than 200kΩ. If capacitive
loading exceeds 5pF, then add a 10kΩ resistor in
series with the output. Adding the series resistor helps
drive larger load capacitance (< 15pF) at the expense
of slower settling time.
connections to V
and OV
that monitor the power-
DD
DD
supply voltages. The internal V
and OV
connec-
DD
DD
tions are made through integrated resistor-dividers that
yield V / 2 and OV / 2 measurement results. The
DD
DD
aux-ADC voltage reference can be selected between
10-Bit, 333ksps Auxiliary ADC
The MAX19708 integrates a 333ksps, 10-bit aux-ADC
with an input 4:1 multiplexer. In the aux-ADC mode reg-
ister, setting bit AD0 begins a conversion with the auxil-
iary ADC. Bit AD0 automatically clears when the
conversion is complete. Setting or clearing AD0 during
an internal 2.048V bandgap reference or V (see
DD
Table 13). The V
reference selection is provided to
DD
allow measurement of an external voltage source with a
full-scale range extending beyond the 2.048V level. The
input source voltage range cannot extend above V
.
DD
Table 14. Auxiliary ADC Input Source
Table 12. Auxiliary ADC Convert
AD0
SELECTION
AD3
AD2
AUX-ADC INPUT SOURCE
0
1
Aux-ADC Idle (Default)
Aux-ADC Start-Convert
0
0
1
1
0
1
0
1
ADC1 (Default)
ADC2
V
/ 2
DD
OV
/ 2
DD
Table 13. Auxiliary ADC Reference
AD1
SELECTION
0
1
Internal 2.048V Reference (Default)
Internal V
Reference
DD
______________________________________________________________________________________ 27
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
The conversion requires 12 clock edges (1 for input
Table 15. Auxiliary ADC Averaging
sampling, 1 for each of the 10 bits, and 1 at the end for
loading into the serial output register) to complete one
conversion cycle (when no averaging is being done).
Each conversion of an average (when averaging is set
greater than 1) requires 12 clock edges. The conver-
sion clock is generated from the system clock input
(CLK). An SPI-programmable divider divides the sys-
tem clock by the appropriate divisor (set with bits AD7,
AD8, and AD9; see Table 16) and provides the conver-
sion clock to the auxiliary ADC. The auxiliary ADC has a
maximum conversion rate of 333ksps. The maximum
conversion clock frequency is 4MHz (333ksps x 12
clocks). Choose the proper divider value to keep the
conversion clock frequency under 4MHz, based upon
the system CLK frequency supplied to the MAX19708
AD6 AD5 AD4
AUX-ADC AVERAGING
1 Conversion (No Averaging) (Default)
Average of 2 Conversions
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
Average of 4 Conversions
Average of 8 Conversions
Average of 16 Conversions
Average of 32 Conversions
Average of 32 Conversions
X = Don’t care.
Table 16. Auxiliary ADC Clock (CLK)
Divider
(see Table 16). The total conversion time (t
) of the
CONV
auxiliary ADC can be calculated as t
= (12 x
CONV
N
x N
) / f
; where N
is the number of
AVG
DIV
CLK
AVG
AD9
0
AD8
0
AD7
0
AUX-ADC CONVERSION CLOCK
CLK Divided by 1 (Default)
CLK Divided by 2
averages (see Table 15), N
is the CLK divisor (see
DIV
Table 16), and f
is the system CLK frequency.
CLK
0
0
1
DOUT is normally in a tri-state condition. Upon setting
the auxiliary ADC start conversion bit (bit AD0), DOUT
becomes active and goes high, indicating that the aux-
ADC is busy. When the conversion cycle is complete
(including averaging), the data is placed into an output
register and DOUT goes low, indicating that the output
data is ready to be driven onto DOUT. When bit AD10 is
set (AD10 = 1), the aux-ADC enters a data output mode
where data is available on DOUT upon the next asser-
tion low of CS. The auxiliary ADC data is shifted out of
DOUT (MSB first) with the data transitioning on the
falling edge of the serial clock (SCLK). DOUT enters a
tri-state condition when CS is deasserted high. When bit
AD10 is cleared (AD10 = 0), the aux-ADC data is not
available on DOUT (see Table 17).
0
1
0
CLK Divided by 4
0
1
1
CLK Divided by 8
1
0
0
CLK Divided by 16
1
0
1
CLK Divided by 32
1
1
0
CLK Divided by 64
1
1
1
CLK Divided by 128
Table 17. Auxiliary ADC Data Output
Mode
AD10
SELECTION
0
Aux-ADC Data is Not Available on DOUT (Default)
DIN can be written independent of DOUT state. A 16-
bit instruction at DIN updates the device configuration.
To prevent modifying internal registers while reading
data from DOUT, hold DIN at a high state. This effec-
tively writes all ones into address 1111. Since address
1111 does not exist, no internal registers are affected.
Aux-ADC Enters Data Output Mode Where
Data is Available on DOUT
1
28 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Table 18. Reference Modes
V
REFIN
REFERENCE MODE
Internal Reference Mode. V
with a 0.33µF capacitor.
is internally generated to be 0.512V. Bypass REFP, REFN, and COM each
REF
> 0.8V x V
DD
Buffered External Reference Mode. An external 1.024V 10% reference voltage is applied to REFIN. V
is
REF
1.024V 10%
internally generated to be V
/ 2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass
REFIN
REFIN to GND with a 0.1µF capacitor.
Reference Configurations
25Ω
The MAX19708 features an internal precision 1.024V
bandgap reference that is stable over the entire power-
supply and temperature ranges. The REFIN input pro-
vides two modes of reference operation. The voltage at
IAP
0.1μF
22pF
V
IN
REFIN (V
) sets the reference operation mode
REFIN
(Table 18).
COM
0.33μF
0.1μF
In internal reference mode, connect REFIN to V
REF
REFP, and REFN are low-impedance outputs with
.
DD
V
is an internally generated 0.512V 4%. COM,
IAN
V
V
= V
= V
/ 2, V
/ 2 - V
= V
/ 2 + V
/ 2, and
REF
COM
REFN
DD
DD
REFP
DD
25Ω
25Ω
22pF
22pF
/ 2. Bypass REFP, REFN, and
REF
MAX19708
COM each with a 0.33µF capacitor. Bypass REFIN to
GND with a 0.1µF capacitor.
QAP
In buffered external reference mode, apply 1.024V
10% at REFIN. In this mode, COM, REFP, and REFN
0.1μF
V
IN
are low-impedance outputs with V
= V
/ 2,
COM
DD
V
V
= V
/ 2 + V / 4, and V
REFIN
= V
/ 2 -
REFP
REFIN
DD
REFN
DD
/ 4. Bypass REFP, REFN, and COM each with a
0.33μF
0.1μF
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF
capacitor. In this mode, the Tx path full-scale output is
proportional to the external reference. For example, if
QAN
the V
is increased by 10% (max), the Tx path full-
REFIN
25Ω
22pF
scale output is also increased by 10% or 451mV.
Applications Information
Using Balun Transformer AC-Coupling
An RF transformer (Figure 9) provides an excellent
solution to convert a single-ended signal source to a
fully differential signal for optimum ADC performance.
Connecting the center tap of the transformer to COM
Figure 9. Balun Transformer-Coupled Single-Ended-to-
Differential Input Drive for Rx ADC
pared to single-ended mode. Figure 10 shows an RF
transformer converting the MAX19708 Tx DAC differen-
tial analog outputs to single-ended.
provides a V
/ 2 DC level shift to the input. A 1:1
DD
transformer can be used, or a step-up transformer can
be selected to reduce the drive requirements. In gener-
al, the MAX19708 provides better SFDR and THD with
fully differential input signals than single-ended signals,
especially for high input frequencies. In differential
mode, even-order harmonics are lower as both inputs
(IAP, IAN, QAP, QAN) are balanced, and each of the
Rx ADC inputs only requires half the signal swing com-
Using Op-Amp Coupling
Drive the MAX19708 Rx ADC with op amps when a
balun transformer is not available. Figures 11 and 12
show the Rx ADC being driven by op amps for AC-cou-
pled single-ended and DC-coupled differential applica-
tions. Amplifiers such as the MAX4454 and MAX4354
provide high speed, high bandwidth, low noise, and
______________________________________________________________________________________ 29
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
low distortion to maintain the input signal integrity. The
op-amp circuit shown in Figure 12 can also be used to
interface with the Tx DAC differential analog outputs to
provide gain or buffering. The Tx DAC differential ana-
log outputs cannot be used in single-ended mode
because of the internally generated common-mode
level. Also, the Tx DAC analog outputs are designed to
drive a differential input stage with input impedance ≥
70kΩ. If single-ended outputs are desired, use an
amplifier to provide differential-to-single-ended conver-
sion and select an amplifier with proper input common-
mode voltage range.
IDP
V
OUT
MAX19708
IDN
QDP
V
OUT
TDD Mode
The MAX19708 is optimized to operate in TD-SCDMA
applications. When FAST mode is selected, the
MAX19708 can switch between Tx and Rx modes
through the T/R pin in typically 0.5µs. The Rx ADC and
Tx DAC operate independently. The Rx ADC and Tx
DAC digital bus are shared forming a single 10-bit par-
allel bus. Using the 3-wire serial interface or external
T/R pin, select between Rx mode to enable the Rx ADC
or Tx mode to enable the Tx DAC. When operating in
Rx mode, the Tx DAC bus is not enabled and in Tx
mode the Rx ADC bus is tri-stated, eliminating any
unwanted spurious emissions and preventing bus con-
tention. In TDD mode, the MAX19708 uses 41.1mW
QDN
Figure 10. Balun Transformer-Coupled Differential-to-Single-
Ended Output Drive for Tx DAC
REFP
1kΩ
1kΩ
R
50Ω
ISO
V
IN
0.1μF
IAP
C
22pF
IN
power in Rx mode at f
42.3mW in Tx mode.
= 11MHz and the DAC uses
CLK
100Ω
100Ω
COM
IAN
TD-SCDMA Application
REFN
0.1μF
Figure 13 illustrates a typical TD-SCDMA application
circuit. The MAX19708 is designed to interface directly
with the MAX2507 and MAX2392 radio front-ends to
provide a complete “RF-to-Bits” front-end solution. The
MAX19708 provides several features that allow direct
interface to the MAX2392 and MAX2507:
R
ISO
50Ω
C
22pF
IN
REFP
MAX19708
•
Integrated Tx filters reduce component count,
lower cost, and meet TD-SCDMA spectral mask
requirements
R
ISO
1kΩ
V
IN
0.1μF
50Ω
•
Programmable DC common-mode Tx output levels
eliminate discrete DC-level-shifting components
while preserving Tx DAC full dynamic range
QAP
C
22pF
IN
100Ω
100Ω
1kΩ
•
•
Optimized Tx full-scale output level eliminates dis-
crete amplifiers for I/Q gain control
REFN
0.1μF
R
50Ω
ISO
Tx-I/Q offset correction eliminates discrete trim
DACs for offset trim to improve sideband/carrier
suppression
QAN
C
IN
22pF
•
One microsecond settling time aux-DACs for VGA
and AGC control allow fast, accurate Tx power and
Rx gain control
Figure 11. Single-Ended Drive for Rx ADC
30 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
R4
R5
600Ω
600Ω
R
22Ω
ISO
R1
600Ω
IAN
C
IN
5pF
R2
600Ω
MAX19708
R6
R7
600Ω
600Ω
COM
R3
600Ω
R8
600Ω
R9
600Ω
R
ISO
22Ω
IAP
C
IN
5pF
R10
R11
600Ω
600Ω
Figure 12. Rx ADC DC-Coupled Differential Drive
10-BIT ADC
Rx-I
MAX2392
Rx
ENCODE
T/R
ZIF RECEIVER
Rx-Q
AGC
HALF-
DUPLEX
BUS
D9
D0
10-BIT DAC
Tx-I
MAX2507
DIRECT
MODULATOR
CLK
Tx
SOURCE
FILTER
DIGITAL
BASEBAND
ASIC
Tx-Q
PA DETECT
VGA
SCLK
DIN
12-BIT DAC
DAC1
SYSTEM
CONTROL
CLK DIST
SPI REG
TCXO
CS
SHDN
DAC2
DAC3
0V
REFIN
REFP
REFN
REF
1.024V
BUFFER
MAX19708
V
DD
DD
COM
ADC
10-BIT, 333ksps
DOUT
TEMPERATURE MEASURE
4:1 MUX
Figure 13. Typical Application Circuit for TD-SCDMA Radio
______________________________________________________________________________________ 31
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
input lines to each respective converter to minimize
channel-to-channel crosstalk. Keep all signal lines
short and free of 90° turns.
Grounding, Bypassing, and
Board Layout
The MAX19708 requires high-speed board layout design
techniques. Refer to the MAX19708 EV kit data sheet for
a board layout reference. Place all bypass capacitors as
close to the device as possible, preferably on the same
side of the board as the device, using surface-mount
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the device are measured using
the best-straight-line fit (DAC Figure 14a).
devices for minimum inductance. Bypass V
to GND
DD
with a 0.1µF ceramic capacitor in parallel with a 2.2µF
capacitor. Bypass OV to OGND with a 0.1µF ceramic
DD
capacitor in parallel with a 2.2µF capacitor. Bypass REFP,
REFN, and COM each to GND with a 0.33µF ceramic
capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
Multilayer boards with separated ground and power
planes yield the highest level of signal integrity. Use a
split ground plane arranged to match the physical loca-
tion of the analog ground (GND) and the digital output-
driver ground (OGND) on the device package.
Connect the MAX19708 exposed backside paddle to
GND plane. Join the two ground planes at a single
point so the noisy digital ground currents do not inter-
fere with the analog ground plane. The ideal location
for this connection can be determined experimentally
at a point along the gap between the two ground
planes. Make this connection with a low-value, surface-
mount resistor (1Ω to 5Ω), a ferrite bead, or a direct
short. Alternatively, all ground pins could share the
same ground plane, if the ground plane is sufficiently
isolated from any noisy digital system’s ground plane
(e.g., downstream output buffer or DSP ground plane).
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes (ADC) and a monotonic transfer function
(ADC and DAC) (DAC Figure 14b).
ADC Offset Error
Ideally, the midscale transition occurs at 0.5 LSB above
midscale. The offset error is the amount of deviation
between the measured transition point and the ideal
transition point.
DAC Offset Error
Offset error (Figure 14a) is the difference between the
ideal and actual offset point. The offset point is the out-
put value when the digital input is midscale. This error
affects all codes by the same amount and usually can
be compensated by trimming.
Route high-speed digital signal traces away from sensi-
tive analog traces. Make sure to isolate the analog
7
6
6
1 LSB
5
4
5
DIFFERENTIAL LINEARITY
ERROR (-0.25 LSB)
4
AT STEP
011 (0.5 LSB)
3
2
3
2
1
0
1 LSB
DIFFERENTIAL
LINEARITY ERROR (+0.25 LSB)
AT STEP
1
0
001 (0.25 LSB)
000
001
010
011
100
101
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
DIGITAL INPUT CODE
Figure 14b. Differential Nonlinearity
Figure 14a. Integral Nonlinearity
32 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
ADC Gain Error
Ideally, the ADC full-scale transition occurs at 1.5 LSB
below full scale. The gain error is the amount of devia-
tion between the measured transition point and the
ideal transition point with the offset error removed.
components to the Nyquist frequency excluding the
fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
ADC Dynamic Parameter Definitions
Aperture Jitter
Figure 15 shows the aperture jitter (t ), which is the
AJ
ENOB = (SINAD - 1.76) / 6.02
sample-to-sample variation in the aperture delay.
Aperture Delay
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 15).
2
2
2
2
2
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error) and results directly
from the ADC’s resolution (N bits):
⎡
⎢
⎤
⎥
(V +V +V +V +V )
2
3
4
5
6
THD = 20 x log
V
⎢
⎥
1
⎣
⎦
where V is the fundamental amplitude and V –V are
the amplitudes of the 2nd- through 6th-order harmonics.
1
2
6
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
SNR(max) = 6.02dB x N + 1.76dB (in dB)
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest spurious
component, excluding DC offset.
Signal-to-Noise and Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise. RMS noise includes all spectral
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
relative to the total input power when two tones, f and f ,
1
2
are present at the inputs. The intermodulation products
are (f f ), (2 ✕ f ), (2 ✕ f ), (2 ✕ f f ), (2 ✕ f f ).
1
2
1
2
1
2
2
1
The individual input tone levels are at -7dBFS.
CLK
3rd-Order Intermodulation (IM3)
IM3 is the power of the worst 3rd-order intermodulation
product relative to the input power of either input tone
ANALOG
INPUT
when two tones, f and f , are present at the inputs. The
1
2
3rd-order intermodulation products are (2 x f
f ). The individual input tone levels are at -7dBFS.
f ), (2 ✕ f
2 2
1
t
AD
1
t
AJ
SAMPLED
DATA (T/H)
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supply is changed 5%.
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
HOLD
TRACK
TRACK
T/H
Figure 15. T/H Aperture Timing
______________________________________________________________________________________ 33
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
limit the ADC’s performance. The input frequency is
(V2 +V2 +... +V2)
⎡
⎢
⎤
⎥
2
3
n
then swept up to the point where the amplitude of the
THD = 20 x log
digitized conversion result has decreased by 3dB. Note
that the T/H performance is usually the limiting factor
for the small-signal input bandwidth.
⎢
V
1
⎥
⎣
⎦
where V is the fundamental amplitude and V through
1
2
V are the amplitudes of the 2nd through nth harmonic
n
Full-Power Bandwidth
up to the Nyquist frequency.
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as the full-
power bandwidth frequency.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component up to the Nyquist frequency excluding DC.
DAC Dynamic Parameter Definitions
Total Harmonic Distortion
THD is the ratio of the RMS sum of the output harmonics
up to the Nyquist frequency divided by the fundamental:
Selector Guide
SAMPLING RATE
PART
DESCRIPTION
(Msps)
Dual 10-Bit Rx ADC, Dual 10-Bit Tx DAC, Integrated TD-SCDMA
Filters, Three 12-Bit Auxiliary DACs
MAX19700
7.5
11
Dual 10-Bit Rx ADC, Dual 10-Bit Tx DAC, Integrated TD-SCDMA
Filters, Three 12-Bit Auxiliary DACs, 10-Bit Auxiliary ADC with 4:1
Input Mux
MAX19708
Dual 10-Bit Rx ADC, Dual 10-Bit Tx DAC, Three 12-Bit Auxiliary
DACs, 10-Bit Auxiliary ADC with 4:1 Input Mux
†
†
MAX19705/MAX19706 /MAX19707
7.5/22/45
†
Future product—contact factory for availability.
34 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Functional Diagram
V
DD
= +2.7V TO +3.3V
OV = +1.8V TO +3.3V
DD
IAP
IAN
10-BIT
ADC
MAX19708
SHDN
T/R
QAP
QAN
10-BIT
ADC
D0–D9
HALF-
DUPLEX
BUS
IDP
IDN
10-BIT
DAC
FILTER
FILTER
QDP
QDN
10-BIT
DAC
SYSTEM
CLOCK
CLK
PROGRAMMABLE
OFFSET/GAIN/CM
SERIAL
INTERFACE
AND SYSTEM
CONTROL
DIN
SCLK
CS
12-BIT
DAC
DAC1
DAC2
DAC3
12-BIT
DAC
REFIN
REFP
REFN
COM
1.024V
REFERENCE
BUFFER
12-BIT
DAC
V
DD
0V
DD
ADC1
ADC2
10-BIT
ADC
DOUT
4:1 MUX
GND
OGND
______________________________________________________________________________________ 35
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
D2
D
C
L
b
D2/2
D/2
k
E/2
E2/2
C
(NE-1) X
e
E
E2
L
k
L
DETAIL A
e
(ND-1) X
e
DETAIL B
e
C
C
L
L
L
L1
L
L
e
e
DALLAS
SEMICONDUCTOR
PROPRIETARYINFORMATION
A
A1
A2
TITLE:
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
APPROVAL
REV.
DOCUMEN2T C1ON-T0RO1L N4O.4
D
2
1
36 ______________________________________________________________________________________
10-Bit, 11Msps, Ultra-Low-Power
Analog Front-End
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
DALLAS
SEMICONDUCTOR
PROPRIETARYINFORMATION
TITLE:
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
APPROVAL
REV.
DOCUMEN2T C1ON-T0RO1L N4O.4
D
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
Springer
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