MAX19710 [MAXIM]
10-Bit, 7.5Msps, Full-Duplex Analog Front-End; 10位， 7.5Msps ，全双工模拟前端
| 型号： | MAX19710 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 10-Bit, 7.5Msps, Full-Duplex Analog Front-End |
| 文件： | 总37页 (文件大小：818K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0526; Rev 0; 5/06
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
General Description
Features
♦ Dual 10-Bit, 7.5Msps Rx ADC and Dual 10-Bit,
The MAX19710 is an ultra-low-power, highly integrated
mixed-signal analog front-end (AFE) ideal for wideband
communication applications operating in full-duplex (FD)
mode. Optimized for high dynamic performance and
ultra-low power, the device integrates a dual 10-bit,
7.5Msps receive (Rx) ADC; dual 10-bit, 7.5Msps transmit
(Tx) DAC; three fast-settling 12-bit aux-DAC channels for
ancillary RF front-end control; and a 10-bit, 333ksps
housekeeping aux-ADC. The typical operating power in
FD mode is 30mW at a 7.5MHz clock frequency.
7.5Msps Tx DAC
♦ Ultra-Low Power
30mW at fCLK = 7.5MHz, FD Mode
21.3mW at fCLK = 7.5MHz, Slow Rx Mode
21.9mW at fCLK = 7.5MHz, Slow Tx Mode
Low-Current Standby and Shutdown Modes
♦ Programmable Tx DAC Common-Mode DC Level
and I/Q Offset Trim
♦ Excellent Dynamic Performance
SNR = 54.9dB at fIN = 3.3MHz (Rx ADC)
The Rx ADCs feature 54.8dB SINAD and 79.8dBc SFDR
at 3.3MHz input frequency with a 7.5MHz clock frequen-
cy. The analog I/Q input amplifiers are fully differential
SFDR = 73.8dBc at fOUT = 620kHz (Tx DAC)
♦ Three 12-Bit, 1μs Aux-DACs
and accept 1.024V
full-scale signals. Typical I/Q
P-P
♦ 10-Bit, 333ksps Aux-ADC with 4:1 Input Mux and
channel matching is 0.01ꢀ phase and 0.01dB gain.
Data Averaging
The Tx DACs feature 73.8dBc SFDR at f = 620kHz
OUT
♦ Excellent Gain/Phase Match
0.01° Phase, 0.01dB Gain (Rx ADC) at
fIN = 1.8MHz
and f
= 7.5MHz. The analog I-Q full-scale output volt-
CLK
age range is 400mV differential. The output DC com-
mon-mode voltage is from 0.89V to 1.36V. The I/Q
channel offset is adjustable to optimize radio lineup side-
band/carrier suppression. Typical I-Q channel matching
is 0.01dB gain and 0.15ꢀ phase.
♦ Multiplexed Parallel Digital I/O
♦ Serial-Interface Control
♦ Versatile Power-Control Circuits
Shutdown, Standby, Idle, Tx/Rx Disable
Two independent 10-bit parallel, high-speed digital
buses used by the Rx ADC and Tx DAC allow full-
duplex operation for frequency-division duplex applica-
tions. The Rx ADC and Tx DAC can be disabled
independently to optimize power management. A 3-wire
serial interface controls power-management modes, the
aux-DAC channels, and the aux-ADC channels.
♦ Miniature 56-Pin Thin QFN Package
(7mm x 7mm x 0.8mm)
Pin Configuration
TOP VIEW
The MAX19710 operates on a single 2.7V to 3.3V analog
supply and 1.8V to 3.3V digital I/O supply. The
MAX19710 is specified for the extended (-40ꢀC to
+85ꢀC) temperature range and is available in a 56-pin,
thin QFN package. The Selector Guide at the end of the
data sheet lists other pin-compatible versions in this AFE
family. For time-division duplex (TDD) applications, refer
to the MAX19705–MAX19708 AFE family of products.
42 41 40 39 38 37 36 35 34 33 32 31 30 29
28
27
26
25
24
23
22
21
ADC1
DAC3
DA3
DA2
DA1
DA0
43
44
DAC2 45
DAC1 46
V
47
OV
DD
DD
IDN 48
IDP 49
GND 50
OGND
AD9
Applications
MAX19710
AD8
V
51
20 AD7
19 AD6
18 AD5
17 AD4
16 AD3
15 AD2
DD
QDN 52
QDP 53
Broadband Access
Radio
Portable Communication
Equipment
REFIN 54
COM 55
REFN 56
Private Mobile Radio
EXPOSED PADDLE (GND)
Ordering Information
1
2
3
4
5
6
7
8
9
10 11 12 13 14
PART*
PIN-PACKAGE
56 Thin QFN-EP**
56 Thin QFN-EP**
PKG CODE
THIN QFN
NOTE: THE PIN 1 INDICATOR IS “+” FOR LEAD-FREE DEVICES.
MAX19710ETN
MAX19710ETN+
T5677-1
T5677-1
Functional Diagram and Selector Guide appear at end of
data sheet.
*All devices are specified over the -40ꢀC to +85ꢀC operating range.
**EP = Exposed paddle. +Denotes lead-free package.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
ABSOLUTE MAXIMUM RATINGS
V
DD
to GND, OV
to OGND ..............................-0.3V to +3.6V
DD
Continuous Power Dissipation (T = +70ꢀC)
A
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, DAC1, DAC2, DAC3 to GND.....................-0.3V to V
ADC1, ADC2 to GND.................................-0.3V to (V
REFP, REFN, REFIN, COM to GND ...........-0.3V to (V
AD0–AD9, DA0–DA9, SCLK, DIN, CS/WAKE,
56-Pin Thin QFN-EP (derate 27.8mW/ꢀC above +70ꢀC)2.22W
Thermal Resistance θ ..................................................36ꢀC/W
JA
Operating Temperature Range ...........................-40ꢀC to +85ꢀC
Junction Temperature......................................................+150ꢀC
Storage Temperature Range.............................-60ꢀC to +150ꢀC
Lead Temperature (soldering, 10s) .................................+300ꢀC
DD
+ 0.3V)
+ 0.3V)
DD
DD
CLK, DOUT to OGND .........................-0.3V to (OV
+ 0.3V)
DD
MAX9710
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
C
= C
= C
= 0.33µF, C < 5pF on all aux-DAC outputs, T = T
to T , unless otherwise noted. Typical values are at
MAX
REFP
REFN
COM
L
A
MIN
T
A
= +25ꢀC.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
Output Supply Voltage
V
2.7
1.8
3.0
3.3
V
V
DD
OV
V
DD
DD
FD mode: f
= 7.5MHz, f
= 620kHz
CLK
OUT
on both DAC channels;
= 1.875MHz on both ADC channels;
aux-DACs ON and at midscale, aux-ADC
ON
f
IN
10
7.3
7.1
12
9
SPI2-Tx mode: f
= 7.5MHz, f
=
CLK
OUT
620kHz on both DAC channels; Rx ADC
OFF; aux-DACs ON and at midscale, aux-
ADC ON
V
Supply Current
mA
DD
SPI1-Rx mode: f
= 7.5MHz, f
=
CLK
IN
1.875MHz on both ADC channels; Tx DAC
OFF (Tx DAC outputs at 0V); aux-DACs
ON and at midscale, aux-ADC ON
9
SPI4-Tx mode: f
= 7.5MHz, f
=
CLK
OUT
620kHz on both DAC channels; Rx ADC
ON (output tri-stated); aux-DACs ON and
at midscale, aux-ADC ON
9.7
12
2
_______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
= C = C = 0.33µF, C < 5pF on all aux-DAC outputs, T = T to T , unless otherwise noted. Typical values are at
C
REFP
= +25ꢀC.) (Note 1)
REFN
COM
L
A
MIN
MAX
T
A
PARAMETER
SYMBOL
CONDITIONS
SPI3-Rx mode: f = 7.5MHz, f
MIN
TYP
MAX
UNITS
=
IN
CLK
1.875MHz on both channels; Tx DAC ON
(Tx DAC outputs at midscale); aux-DACs
ON and at midscale, aux-ADC ON
9.5
12
mA
Standby mode: CLK = 0 or OV
;
DD
aux-DACs ON and at midscale,
aux-ADC ON
2.7
3.5
V
Supply Current
DD
Idle mode: f
and at midscale, aux-ADC ON
= 7.5MHz; aux-DACs ON
CLK
4.6
0.5
6
5
Shutdown mode: CLK = 0 or OV , or
DD
aux-ADC OFF
µA
FD mode: f
= 7.5MHz, f
= 620kHz
CLK
OUT
on both DAC channels; f = 1.875MHz on
IN
both ADC channels; aux-DACs ON and at
midscale, aux-ADC ON
0.94
0.90
mA
SPI1-Rx and SPI3-Rx modes: f
=
CLK
7.5MHz, f = 1.875MHz on both ADC
IN
channels; DAC input bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
SPI2-Tx and SPI4-Tx modes: f
=
CLK
7.5MHz, f
= 620kHz on both DAC
OUT
OV
Supply Current
DD
52
channels; ADC output bus tri-stated; aux-
DACs ON and at midscale, aux-ADC ON
Standby mode: CLK = 0 or OV ; aux-
DD
DACs ON and at midscale, aux-ADC ON
0.1
12.8
0.1
µA
Idle mode: f
= 7.5MHz; aux-DACs ON
CLK
and at midscale, aux-ADC ON
Shutdown mode: CLK = 0 or OV , or
DD
aux-ADC OFF
Rx ADC DC ACCURACY
Resolution
N
10
Bits
LSB
LSB
%FS
%FS
dB
Integral Nonlinearity
Differential Nonlinearity
Offset Error
INL
DNL
0.5
0.4
0.2
0.9
0.04
11
No missing codes over temperature (Note 2)
Residual DC offset error
-0.8
-5
+1.0
+5
Gain Error
Includes reference error
-5
+5
DC Gain Matching
Offset Matching
-0.15
+0.15
LSB
_______________________________________________________________________________________
3
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
= C = C = 0.33µF, C < 5pF on all aux-DAC outputs, T = T to T , unless otherwise noted. Typical values are at
C
REFP
= +25ꢀC.) (Note 1)
REFN
COM
L
A
MIN
MAX
T
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
30
MAX
UNITS
Gain Temperature Coefficient
ppm/ꢀC
Offset (V
5%)
0.2
DD
Power-Supply Rejection
PSRR
LSB
Gain (V
5%)
0.05
DD
MAX9710
Rx ADC ANALOG INPUT
Input Differential Range
V
Differential or single-ended inputs
Switched capacitor load
0.512
V
V
ID
Input Common-Mode Voltage
Range
V
V
/ 2
DD
CM
R
720
5
kΩ
IN
Input Impedance
C
pF
IN
Rx ADC CONVERSION RATE
Maximum Clock Frequency
f
(Note 3)
7.5
MHz
CLK
Channel IA
Channel QA
5
Clock
Cycles
Data Latency
5.5
Rx ADC DYNAMIC CHARACTERISTICS (Note 4)
f
f
f
f
f
f
f
f
f
f
= 1.875MHz
= 3.3MHz
53.2
53.1
64.2
54.8
54.9
54.7
54.8
73.9
79.8
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
Signal-to-Noise Ratio
SNR
SINAD
SFDR
THD
dB
dB
= 1.875MHz
= 3.3MHz
Signal-to-Noise and Distortion
Spurious-Free Dynamic Range
Total Harmonic Distortion
Third-Harmonic Distortion
Intermodulation Distortion
= 1.875MHz
= 3.3MHz
dBc
dBc
dBc
dBc
= 1.875MHz
= 3.3MHz
-71.7
-74.3
-76.8
-83.8
-62.8
= 1.875MHz
= 3.3MHz
HD3
f
f
= 1.8MHz, A
= -7dBFS;
= -7dBFS
IN1
IN2
IN1
IMD
-72
-83
= 1MHz, A
IN2
Third-Order Intermodulation
Distortion
f
f
= 1.8MHz, A
= -7dBFS;
= -7dBFS
IN1
IN2
IN1
IM3
dBc
ns
= 1MHz, A
IN2
Aperture Delay
3.5
2
Aperture Jitter
ps
RMS
Overdrive Recovery Time
1.5x full-scale input
2
ns
Rx ADC INTERCHANNEL CHARACTERISTICS
f
= 1.8MHz, A
= -0.5dBFS, f
=
INX,Y
INX,Y
INY,X
Crosstalk Rejection
-91
dB
1MHz, A
= -0.5dBFS (Note 5)
INY,X
Amplitude Matching
Phase Matching
f
= 1.8MHz, A = -0.5dBFS (Note 6)
0.01
0.01
dB
IN
IN
f
IN
= 1.8MHz, A = -0.5dBFS (Note 6)
Degrees
IN
4
_______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
= C = C = 0.33µF, C < 5pF on all aux-DAC outputs, T = T to T , unless otherwise noted. Typical values are at
C
REFP
= +25ꢀC.) (Note 1)
REFN
COM
L
A
MIN
MAX
T
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Tx DAC DC ACCURACY
Resolution
N
10
Bits
LSB
LSB
mV
Integral Nonlinearity
Differential Nonlinearity
Residual DC Offset
Full-Scale Gain Error
INL
DNL
0.3
0.2
1.2
1.6
Guaranteed monotonic (Note 2)
-0.75
-4
+0.75
+4
V
OS
-40
+40
mV
Tx DAC DYNAMIC PERFORMANCE
DAC Conversion Rate
f
(Note 3)
7.5
MHz
CLK
In-Band Noise Density
N
f
= 620kHz
-120
-79
dBFS/Hz
D
OUT
Third-Order Intermodulation
Distortion
IM3
f
= 620kHz, f
= 640kHz
dBc
pV•s
dBc
OUT1
OUT2
Glitch Impulse
10
Spurious-Free Dynamic Range to
Nyquist
SFDR
f
= 620kHz
61
73.8
OUT
Total Harmonic Distortion to
Nyquist
THD
SNR
f
f
= 620kHz
= 620kHz
-72.2
55.1
-59.7
+0.4
dBc
dB
OUT
OUT
Signal-to-Noise Ratio to Nyquist
Tx DAC INTERCHANNEL CHARACTERISTICS
I-to-Q Output Isolation
f
= 2MHz, f
= 2.2MHz
92
dB
dB
OUTX,Y
OUTY,X
Gain Mismatch Between I and Q
Channels
Measured at DC
-0.4
0.01
Phase Mismatch Between I and Q
Channels
f
= 620kHz
0.15
800
Degrees
OUT
Differential Output Impedance
Ω
Tx DAC ANALOG OUTPUT
Full-Scale Output Voltage
V
400
mV
V
FS
Bits CM1 = 0, CM0 = 0 (default)
Bits CM1 = 0, CM0 = 1
Bits CM1 = 1, CM0 = 0
Bits CM1 = 1, CM0 = 1
1.29
1.14
0.96
0.78
1.36
1.2
1.42
1.27
1.15
1.03
Output Common-Mode Voltage
V
COMD
1.05
0.89
Rx ADC–Tx DAC INTERCHANNEL CHARACTERISTICS
ADC f = f
= 1.8MHz, DAC f
=
INI
INQ
OUTI
Receive Transmit Isolation
92
dB
f
= 620kHz
OUTQ
AUXILIARY ADCs (ADC1, ADC2)
Resolution
N
10
Bits
_______________________________________________________________________________________
5
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
= C = C = 0.33µF, C < 5pF on all aux-DAC outputs, T = T to T , unless otherwise noted. Typical values are at
C
REFP
= +25ꢀC.) (Note 1)
REFN
COM
L
A
MIN
MAX
T
A
PARAMETER
SYMBOL
CONDITIONS
AD1 = 0 (default)
MIN
TYP
MAX
UNITS
2.048
Full-Scale Reference
V
V
REF
AD1 = 1
V
DD
0 to
MAX9710
Analog Input Range
V
V
REF
Analog Input Impedance
Input-Leakage Current
Measured at DC
500
kΩ
µA
Measured at unselected input from 0 to
0.1
V
REF
Gain Error
GE
ZE
Includes reference error, AD1 = 0
-5
+5
%FS
mV
Zero-Code Error
Differential Nonlinearity
Integral Nonlinearity
Supply Current
2
0.6
0.6
210
DNL
INL
LSB
LSB
µA
AUXILIARY DACs (DAC1, DAC2, DAC3)
Resolution
N
12
Bits
Integral Nonlinearity
INL
From code 100 to code 4000
1.25
0.65
LSB
Guaranteed monotonic over code 100 to
code 4000 (Note 2)
Differential Nonlinearity
DNL
-1.0
2.57
+1.2
0.2
LSB
R > 200kΩ
L
Output-Voltage Low
Output-Voltage High
DC Output Impedance
V
V
V
OL
V
R > 200kΩ
L
OH
DC output at midscale
4
1
Ω
From code 1024 to code 3072, within 10
LSB
Settling Time
µs
Glitch Impulse
From code 0 to code 4095
24
nV•s
Rx ADC–Tx DAC TIMING CHARACTERISTICS
CLK Rise to Channel-I Output Data
Valid
t
Figure 3 (Note 2)
Figure 3 (Note 2)
Figure 5 (Note 2)
5.5
6.5
10
8.2
9.3
11.5
13.0
ns
ns
ns
DOI
CLK Fall to Channel-Q Output
Data Valid
t
DOQ
I-DAC DATA to CLK Fall Setup
Time
t
DSI
Q-DAC DATA to CLK Rise Setup
Time
t
Figure 5 (Note 2)
Figure 5 (Note 2)
Figure 5 (Note 2)
10
0
ns
ns
ns
DSQ
CLK Fall to I-DAC Data Hold Time
t
DHI
CLK Rise to Q-DAC Data Hold
Time
t
0
DHQ
CLK Duty Cycle
50
15
%
%
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
20% to 80%
2.4
ns
6
_______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
C
= C
= C
= 0.33µF, C < 5pF on all aux-DAC outputs, T = T
to T , unless otherwise noted. Typical values are at
MAX
REFP
REFN
COM
L
A
MIN
T
A
= +25ꢀC.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figures 6 and 8, Note 2)
Falling Edge of CS/WAKE to Rising
Edge of First SCLK Time
t
10
ns
CSS
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Period
t
10
0
ns
ns
ns
ns
ns
ns
ns
DS
DH
CH
t
t
25
25
50
10
80
t
CL
CP
CS
t
t
SCLK to CS/WAKE Setup Time
CS/WAKE High Pulse Width
t
CSW
CS/WAKE High to DOUT
Active High
t
Bit AD0 set
200
4.3
ns
µs
CSD
CS/WAKE High to DOUT Low
(Aux-ADC Conversion Time)
Bit AD0 set, no averaging, f
CLK divider = 2
= 7.5MHz,
CLK
t
CONV
DOUT Low to CS/WAKE
Setup Time
t
t
Bit AD0, AD10 set
Bit AD0, AD10 set
Bit AD0, AD10 set
200
ns
ns
ns
DCS
SCLK Low to DOUT Data Out
t
14.5
CD
CS/WAKE High to DOUT High
Impedance
200
CHZ
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
500
From shutdown to Tx mode, DAC settles to
within 10 LSB error
26.2
Shutdown Wake-Up Time
(With CLK)
From aux-ADC enable to aux-ADC start
conversion
t
10
28
µs
WAKE,SD
From shutdown to aux-DAC output valid
From shutdown to FD mode, ADC settles
to within 1dB SINAD, DAC settles to within
10 LSB error
500
From idle to Rx mode, ADC settles to within
1dB SINAD
7.3
5.2
From idle to Tx mode, DAC settles to 10
LSB error
Idle Wake-Up Time
(With CLK)
t
µs
WAKE,ST0
From idle to FD mode, ADC settles to
within 1dB SINAD, DAC settles to within 10
LSB error
7.3
_______________________________________________________________________________________
7
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
= C = C = 0.33µF, C < 5pF on all aux-DAC outputs, T = T to T , unless otherwise noted. Typical values are at
C
REFP
= +25ꢀC.) (Note 1)
REFN
COM
L
A
MIN
MAX
T
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
From standby to Rx mode, ADC settles to
within 1dB SINAD
7.5
From standby to Tx mode, DAC settles to
10 LSB error
MAX9710
22.2
22.2
Standby Wake-Up Time
(With CLK)
t
µs
WAKE,ST1
From standby to FD mode, ADC settles to
within 1dB SINAD, DAC settles to within 10
LSB error
Enable Time from Tx to Rx,
Fast Mode
t
ADC settles to within 1dB SINAD
DAC settles to within 10 LSB error
ADC settles to within 1dB SINAD
DAC settles to within 10 LSB error
0.1
0.1
7.3
5.2
µs
µs
µs
µs
ENABLE,RX
Enable Time from Rx to Tx,
Fast Mode
t
ENABLE,TX
ENABLE,RX
Enable Time from Tx to Rx,
Slow Mode
t
Enable Time from Rx to Tx,
Slow Mode
t
ENABLE,TX
INTERNAL REFERENCE (V
Positive Reference
= V ; V
, V
, V
levels are generated internally)
REFIN
DD REFP REFN COM
V
V
- V
0.256
V
V
REFP
REFN
COM
Negative Reference
- V
-0.256
COM
V
/ 2
V
/ 2
DD
DD
Common-Mode Output Voltage
V
V
/ 2
V
COM
DD
2
- 0.15
+ 0.15
Maximum REFP/REFN/COM
Source Current
I
mA
SOURCE
Maximum REFP/REFN/COM
Sink Current
I
2
mA
V
SINK
Differential Reference Output
V
V
- V
REFN
+0.490 +0.512 +0.534
30
REF
REFP
Differential Reference Temperature
Coefficient
REFTC
ppm/ꢀC
BUFFERED EXTERNAL REFERENCE (external V
= 1.024V applied; V
, V
, V
levels are generated internally)
REFIN
REFP REFN COM
Reference Input Voltage
V
1.024
0.512
V
V
V
REFIN
Differential Reference Output
Common-Mode Output Voltage
V
V
- V
REFP REFN
DIFF
V
V
/ 2
COM
DD
Maximum REFP/REFN/COM
Source Current
I
2
mA
mA
SOURCE
Maximum REFP/REFN/COM
Sink Current
I
2
SINK
REFIN Input Current
-0.7
500
µA
REFIN Input Resistance
kΩ
8
_______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC input
DD
L
CLK
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output,
= C = C = 0.33µF, C < 5pF on all aux-DAC outputs, T = T to T , unless otherwise noted. Typical values are at
C
REFP
= +25ꢀC.) (Note 1)
REFN
COM
L
A
MIN
MAX
T
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CLK, SCLK, DIN, CS/WAKE, DA9–DA0)
Input High Threshold
Input Low Threshold
V
0.7 x OV
V
V
INH
DD
V
0.3 x OV
DD
INL
CLK, SCLK, DIN, CS/WAKE = OGND or
OV
-1
+1
DD
Input Leakage
DI
µA
pF
IN
DA9–DA0 = OV
-1
-5
+1
+5
DD
DA9–DA0 = OGND
Input Capacitance
DC
5
5
IN
DIGITAL OUTPUTS (AD9–AD0, DOUT)
Output-Voltage Low
V
I
I
= 200µA
0.2 x OV
DD
V
V
OL
SINK
Output-Voltage High
V
= 200µA
0.8 x OV
-1
OH
SOURCE
DD
Tri-State Leakage Current
Tri-State Output Capacitance
I
+1
µA
pF
LEAK
C
OUT
Note 1: Specifications from T = +25ꢀC to +85ꢀC guaranteed by production tests. Specifications at T < +25ꢀC guaranteed by
A
A
design and characterization.
Note 2: Guaranteed by design and characterization.
Note 3: The minimum clock frequency (f
) for the MAX19710 is 1.5MHz (typ). The minimum aux-ADC sample rate clock frequency
CLK
(A
) is determined by f
and the chosen aux-ADC clock-divider value. The minimum aux-ADC A
> 1.5MHz / 128 =
CLK
CLK
CLK
11.7kHz. The aux-ADC conversion time does not include the time to clock the serial data out of DOUT. The maximum con-
version time (for no averaging, NAVG = 1) will be t (max) = (12 x 1 x 128) / 1.5MHz = 1024µs.
CONV
Note 4: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec-
ond channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second
channel FFT test tones.
Note 6: Amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output
signals using a sine-wave fit.
_______________________________________________________________________________________
9
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
Typical Operating Characteristics
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC
DD
DD
L
CLK
input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC
output, C
= C
= C = 0.33µF, T = +25ꢀC, unless otherwise noted.)
REFP
REFN
COM A
Rx ADC CHANNEL-IA
TWO-TONE FFT PLOT
Rx ADC CHANNEL-QA FFT PLOT
Rx ADC CHANNEL-IA FFT PLOT
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
0
FUNDAMENTAL
f
A
= 1.8019362MHz
FUNDAMENTAL
= 1.8019362MHz
= -0.524dBFS
SINAD = 54.897dB
SNR = 54.927dB
THD = -76.609dBc
SFDR = 83.379dBc
IN
f
A
IN
IN
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
= -0.488dBFS
IN
f
f
IN2
IN1
SINAD = 54.773dB
SNR = 54.83dB
THD = -73.651dBc
SFDR = 77.541dBc
f
f
A
= 1.7471383MHz
= 1.8421213MHz
IN1
IN2
IN1
MAX9710
= A = -7dBFS
IN2
IMD = -64dBc
3
2
6
5
4
2
3
5
6
2f - f
4
2f - f
IN2 IN1
IN1 IN2
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY (MHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY (MHz)
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY (MHz)
Rx ADC CHANNEL-QA
TWO-TONE FFT PLOT
Rx ADC SIGNAL-TO-NOISE RATIO
vs. ANALOG INPUT FREQUENCY
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT FREQUENCY
0
57
56
55
54
53
52
51
50
57
56
55
54
53
52
51
50
f
f
IN2
IN1
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
IA
IA
f
f
A
= 1.7471383MHz
= 1.8421213MHz
IN1
IN2
IN1
= A = -7dBFS
IN2
IMD = -64dBc
QA
QA
2f - f
2f - f
IN2 IN1
IN1 IN2
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT FREQUENCY
Rx ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT FREQUENCY
Rx ADC SIGNAL-T0-NOISE RATIO
vs. ANALOG INPUT AMPLITUDE
90
85
80
75
70
65
60
55
50
60
55
50
45
40
35
30
25
20
90
85
80
75
70
65
60
55
50
f
= 1.875MHz
IN
QA
IA
IA
IA
QA
QA
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
-30
-25
-20
-15
-10
-5
0
0
10 20 30 40 50 60 70 80 90 100
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT AMPLITUDE (dBFS)
10 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Typical Operating Characteristics (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC
DD
DD
L
CLK
input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC
output, C = C = C = 0.33µF, T = +25ꢀC, unless otherwise noted.)
REFP
REFN
COM
A
Rx ADC TOTAL HARMONIC DISTORTION
vs. ANALOG INPUT AMPLITUDE
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. ANALOG INPUT AMPLITUDE
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. ANALOG INPUT AMPLITUDE
80
75
70
65
60
55
50
45
40
35
30
90
85
80
75
70
65
60
55
50
45
40
35
30
60
55
50
45
40
35
30
25
20
f
= 1.875MHz
IN
f
= 1.875MHz
IN
f
= 1.875MHz
IN
IA
QA
QA
IA
QA
IA
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
-30
-25
-20
-15
-10
-5
0
ANALOG INPUT AMPLITUDE (dBFS)
ANALOG INPUT AMPLITUDE (dBFS)
ANALOG INPUT AMPLITUDE (dBFS)
Rx ADC TOTAL HARMONIC DISTORTION
vs. SAMPLING FREQUENCY
Rx ADC SIGNAL-TO-NOISE RATIO
vs. SAMPLING FREQUENCY
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. SAMPLING FREQUENCY
85
80
75
70
65
60
55
57.0
56.5
56.0
55.5
55.0
54.5
54.0
53.5
53.0
52.5
52.0
57.0
56.5
56.0
55.5
55.0
54.5
54.0
53.5
53.0
52.5
52.0
f
= 1.875MHz
IN
f
= 1.875MHz
f
= 1.875MHz
IN
IN
IA
IA
IA
QA
QA
QA
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
SAMPLING FREQUENCY (MHz)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
SAMPLING FREQUENCY (MHz)
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
SAMPLING FREQUENCY (MHz)
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING FREQUENCY
Rx ADC SIGNAL-TO-NOISE RATIO
vs. CLOCK DUTY CYCLE
Rx ADC SIGNAL-TO-NOISE AND DISTORTION
RATIO vs. CLOCK DUTY CYCLE
58
57
56
55
54
53
52
90
85
80
75
70
65
60
55
58
57
56
55
54
53
52
f
= 1.875MHz
f = 1.875MHz
IN
f
= 1.875MHz
IN
IN
IA
IA
IA
QA
QA
QA
35
40
45
50
55
60
65
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
SAMPLING FREQUENCY (MHz)
35
40
45
50
55
60
65
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
______________________________________________________________________________________ 11
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
Typical Operating Characteristics (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC
DD
DD
L
CLK
input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC
output, C = C = C = 0.33µF, T = +25ꢀC, unless otherwise noted.)
REFP
REFN
COM
A
Rx ADC TOTAL HARMONIC DISTORTION
vs. CLOCK DUTY CYCLE
Rx ADC SPURIOUS-FREE DYNAMIC RANGE
vs. CLOCK DUTY CYCLE
Rx ADC OFFSET ERROR vs. TEMPERATURE
1.00
0.75
0.50
0.25
0
90
85
80
75
70
65
60
55
50
45
40
90
85
80
75
70
65
60
f
= 1.875MHz
IA
IN
f = 1.875MHz
IN
IA
MAX9710
QA
IA
QA
QA
-0.25
-0.50
-0.75
-1.00
-40
-15
10
35
60
85
35
40
45
50
55
60
65
35
40
45
50
55
60
65
TEMPERATURE (°C)
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
Tx DAC SPURIOUS-FREE DYNAMIC RANGE
vs. SAMPLING FREQUENCY
Tx DAC SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT FREQUENCY
Rx ADC GAIN ERROR vs. TEMPERATURE
90
85
80
75
70
65
60
55
2.00
1.75
1.50
1.25
1.00
0.75
0.50
0.25
0
90
85
80
75
70
65
60
f
= f / 10
OUT CLK
QD
QD
QA
ID
ID
IA
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
SAMPLING FREQUENCY (MHz)
-40
-15
10
35
60
85
0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8
OUTPUT FREQUENCY (MHz)
TEMPERATURE (°C)
Tx DAC SPURIOUS-FREE DYNAMIC RANGE
vs. OUTPUT AMPLITUDE
Tx DAC CHANNEL-ID SPECTRAL PLOT
Tx DAC CHANNEL-QD SPECTRAL PLOT
90
80
70
60
50
40
30
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
f
= 2.2MHz
f
= 2.2MHz
OUT
OUT
f
= 2MHz
OUT
QD
ID
-30
-25
-20
-15
-10
-5
0
0
0.76
1.52
2.28
3.04
3.80
0
0.76
1.52
2.28
3.04
3.80
OUTPUT AMPLITUDE (dBFS)
FREQUENCY (MHz)
FREQUENCY (MHz)
12 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Typical Operating Characteristics (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC
DD
DD
L
CLK
input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC
output, C
= C
= C
= 0.33µF, T = +25ꢀC, unless otherwise noted.)
COM A
REFP
REFN
Tx DAC CHANNEL-ID TWO-TONE
SPECTRAL PLOT
Tx DAC CHANNEL-QD TWO-TONE
SPECTRAL PLOT
SUPPLY CURRENT
vs. SAMPLING FREQUENCY
10.0
9.5
9.0
8.5
8.0
7.5
7.0
0
-10
-20
-30
-40
-50
-60
-70
-80
0
-10
-20
-30
-40
-50
-60
-70
-80
-90
FD MODE
f
f
= 600kHz,
= 800kHz
f
f
= 600kHz,
= 800kHz
OUT1
OUT2
OUT1
OUT2
f
f
= 1.875MHz
= 620kHz
IN
OUT
-90
0
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5
SAMPLING FREQUENCY (MHz)
0.76
1.52
2.28
3.04
3.80
0
0.76
1.52
2.28
3.04
3.80
FREQUENCY (MHz)
FREQUENCY (MHz)
Tx DAC INTEGRAL NONLINEARITY
Rx ADC INTEGRAL NONLINEARITY
Rx ADC DIFFERENTIAL NONLINEARITY
0.8
0.6
0.4
0.2
0
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
-0.2
-0.4
-0.6
-0.8
-0.25
-0.50
-0.75
-0.25
-0.50
-0.75
-1.00
-1.00
0
0
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
REFERENCE OUTPUT VOLTAGE
vs. TEMPERATURE
Tx DAC DIFFERENTIAL NONLINEARITY
AUX-DAC INTEGRAL NONLINEARITY
0.5
0.4
2.0
1.5
1.0
0.5
0
0.520
0.515
0.510
0.505
0.500
V
- V
REFN
REFP
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.5
-0.5
-1.0
-1.5
-2.0
0
128 256 384 512 640 768 896 1024
DIGITAL INPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL INPUT CODE
-40
-15
10
35
60
85
TEMPERATURE (°C)
______________________________________________________________________________________ 13
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
Typical Operating Characteristics (continued)
(V
= 3V, OV
= 1.8V, internal reference (1.024V), C ≈ 10pF on all digital outputs, f
= 7.5MHz (50% duty cycle), Rx ADC
DD
DD
L
CLK
input amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC
output, C = C = C = 0.33µF, T = +25ꢀC, unless otherwise noted.)
REFP
REFN
COM
A
AUX-DAC DIFFERENTIAL NONLINEARITY
AUX-ADC INTEGRAL NONLINEARITY
1.0
0.8
2.0
1.5
1.0
0.5
0
0.6
MAX9710
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.5
-1.0
-1.5
-2.0
0
512 1024 1536 2048 2560 3072 3584 4096
DIGITAL INPUT CODE
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SOURCE CURRENT
AUX-ADC DIFFERENTIAL NONLINEARITY
3.0
0.8
0.6
0.4
0.2
0
2.5
2.0
1.5
1.0
0.5
0
-0.2
-0.4
-0.6
-0.8
0.001
0.01
0.1
1
10
100
0
128 256 384 512 640 768 896 1024
DIGITAL OUTPUT CODE
OUTPUT SOURCE CURRENT (mA)
AUX-DAC OUTPUT VOLTAGE
vs. OUTPUT SINK CURRENT
AUX-DAC SETTLING TIME
MAX19710 toc42
3.0
2.5
2.0
1.5
1.0
0.5
0
STEP FROM CODE 1024 TO CODE 3072
1V/div
CS/WAKE
500mV/div
AUX-DAC
OUTPUT
400ns/div
0.001
0.01
0.1
1
10
100
OUTPUT SINK CURRENT (mA)
14 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Pin Description
PIN
NAME
FUNCTION
Positive Reference Voltage Input Terminal. Bypass with a 0.33µF capacitor to GND as close to REFP
as possible.
1
REFP
2, 8, 11, 39,
41, 47, 51
Analog Supply Voltage. Bypass V
a 0.1µF capacitor.
to GND with a combination of a 2.2µF capacitor in parallel with
DD
V
DD
3
IAP
IAN
Channel-IA Positive Analog Input. For single-ended operation, connect signal source to IAP.
Channel-IA Negative Analog Input. For single-ended operation, connect IAN to COM.
Analog Ground. Connect all GND pins to ground plane.
4
5, 7, 12, 40, 50
GND
CLK
QAN
QAP
6
9
Conversion Clock Input. Clock signal for both receive ADCs and transmit DACs.
Channel-QA Negative Analog Input. For single-ended operation, connect QAN to COM.
Channel-QA Positive Analog Input. For single-ended operation, connect signal source to QAP.
10
Receive ADC Digital Outputs. AD9 is the most significant bit (MSB) and AD0 is the least significant
bit (LSB).
13–22
23
AD0–AD9
OGND
Output-Driver Ground
Output-Driver Power Supply. Supply range from +1.8V to V . Bypass OV
DD
combination of a 2.2µF capacitor in parallel with a 0.1µF capacitor.
to OGND with a
DD
24
OV
DD
Transmit DAC Digital Inputs. DA9 is the most significant bit (MSB) and DA0 is the least significant bit
25–34
DA0–DA9
(LSB). DA0–DA9 are internally pulled up to OV
DD.
35
36
37
DOUT
DIN
Aux-ADC Digital Output
3-Wire Serial-Interface Data Input. Data is latched on the rising edge of SCLK.
3-Wire Serial-Interface Clock Input
SCLK
3-Wire Serial-Interface Chip-Select/WAKE Input. When the MAX19710 is in shutdown, CS/WAKE
controls the wake-up function. See the Wake-Up Function section.
38
CS/WAKE
42
43
44
45
46
48
49
52
53
54
55
ADC2
ADC1
DAC3
DAC2
DAC1
IDN
Selectable Auxiliary ADC Analog Input 2
Selectable Auxiliary ADC Analog Input 1
Auxiliary DAC3 Analog Output (V
Auxiliary DAC2 Analog Output (V
= 0 at Power-Up)
= 0 at Power-Up)
OUT
OUT
Auxiliary DAC1 Analog Output (AFC DAC, V
= 1.1V at Power-Up)
OUT
Tx Path Channel-ID Differential Negative Output
Tx Path Channel-ID Differential Positive Output
Tx Path Channel-QD Differential Negative Output
Tx Path Channel-QD Differential Positive Output
IDP
QDN
QDP
REFIN
COM
Reference Input. Connect to V
for internal reference.
DD
Common-Mode Voltage I/O. Bypass COM to GND with a 0.33µF capacitor.
Negative Reference Voltage Input Terminal. Rx ADC conversion range is (V
REFN to GND with a 0.33µF capacitor.
- V
). Bypass
REFP
REFN
56
—
REFN
EP
Exposed Paddle. Exposed paddle is internally connected to GND. Connect EP to the GND plane.
ential and accept 1.024V
full-scale signals. The Tx
P-P
Detailed Description
DAC analog outputs are fully differential with 400mV
full-scale output, selectable common-mode DC level,
and adjustable channel ID–QD offset trim.
The MAX19710 integrates a dual, 10-bit Rx ADC and a
dual, 10-bit Tx DAC while providing ultra-low power
and high dynamic performance at 7.5Msps conversion
rate. The Rx ADC analog input amplifiers are fully differ-
______________________________________________________________________________________ 15
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
The MAX19710 integrates three 12-bit auxiliary DACs
(aux-DACs) and a 10-bit, 333ksps auxiliary ADC (aux-
ADC) with 4:1 input multiplexer. The aux-DAC channels
feature 1µs settling time for fast AGC, VGA, and AFC
level setting. The aux-ADC features data averaging to
reduce processor overhead and a selectable clock-
divider to program the conversion rate.
MAX19710 operates from a single 2.7V to 3.3V analog
supply and a 1.8V to 3.3V digital supply.
Dual 10-Bit Rx ADC
The ADC uses a seven-stage, fully differential, pipelined
architecture that allows for high-speed conversion while
minimizing power consumption. Samples taken at the
inputs move progressively through the pipeline stages
every half clock cycle. Including the delay through the
output latch, the total clock-cycle latency is 5 clock
cycles for channel IA and 5.5 clock cycles for channel
The MAX19710 includes a 3-wire serial interface to con-
trol operating modes and power management. The seri-
al interface is SPI™ and MICROWIRE™ compatible.
The MAX19710 serial interface selects shutdown, idle,
standby, FD, transmit (Tx), and receive (Rx) modes, as
well as controls aux-DAC and aux-ADC channels.
MAX9710
QA. The ADC full-scale analog input range is
V
REF
with a V / 2 ( 0.8V) common-mode input range. V
DD
REF
is the difference between V
and V
. See the
REFN
REFP
The MAX19710 features two independent, high-speed,
10-bit buses for the Rx ADC and Tx DAC, which allow
full-duplex (FD) operation for frequency-division duplex
applications. Each bus can be disabled to optimize
power management through the 3-wire interface. The
Reference Configurations section for details.
Input Track-and-Hold (T/H) Circuits
Figure 1 displays a simplified diagram of the Rx ADC
input track-and-hold (T/H) circuitry. Both ADC inputs
(IAP, QAP, IAN, and QAN) can be driven either differen-
MICROWIRE is a trademark of National Semiconductor Corp.
SPI is a trademark of Motorola, Inc.
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
S4a
S4b
IAP
IAN
OUT
OUT
C2a
C2b
S4c
S1
C1b
S3b
S5b
COM
S2b
CLK
INTERNAL
NONOVERLAPPING
CLOCK SIGNALS
HOLD
HOLD
INTERNAL
BIAS
TRACK
TRACK
INTERNAL
BIAS
COM
S5a
S2a
C1a
S3a
S4a
S4b
QAP
QAN
OUT
C2a
C2b
S4c
S1
MAX19710
OUT
C1b
S3b
S5b
COM
S2b
INTERNAL
BIAS
Figure 1. Rx ADC Internal T/H Circuits
16 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Table 1. Rx ADC Output Codes vs. Input Voltage
DIFFERENTIAL INPUT
VOLTAGE
DIFFERENTIAL INPUT (LSB)
OFFSET BINARY (AD0–AD9)
OUTPUT DECIMAL CODE
V
V
x 512/512
x 511/512
511 (+Full Scale - 1 LSB)
510 (+Full Scale - 2 LSB)
+1
11 1111 1111
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
1023
1022
513
512
511
1
REF
REF
V
V
x 1/512
x 0/512
x 1/512
REF
REF
0 (Bipolar Zero)
-1
-V
REF
-V
x 511/512
x 512/512
-511 (-Full Scale + 1 LSB)
-512 (-Full Scale)
REF
REF
-V
0
nal (CLK) and the resulting data is multiplexed at the
AD0–AD9 outputs. Channel IA data is updated on the ris-
ing edge and channel QA data is updated on the falling
edge of CLK. Including the delay through the output
latch, the total clock-cycle latency is 5 clock cycles for
channel IA and 5.5 clock cycles for channel QA.
2 x V
REF
V
= V
- V
1 LSB =
REF
REFP REFN
1024
V
V
REF
REF
11 1111 1111
11 1111 1110
11 1111 1101
Digital Output Data (AD0–AD9)
10 0000 0001
10 0000 0000
01 1111 1111
AD0–AD9 are the Rx ADC digital logic outputs of the
(COM)
MAX19710. The logic level is set by OV
from 1.8V to
DD
V
DD
. The digital output coding is offset binary (Table 1).
Keep the capacitive load on the digital outputs AD0–AD9
as low as possible (< 15pF) to avoid large digital currents
feeding back into the analog portion of the MAX19710
and degrading its dynamic performance. Buffers on the
digital outputs isolate the outputs from heavy capacitive
loads. Adding 100Ω resistors in series with the digital out-
puts close to the MAX19710 will help improve ADC per-
formance. Refer to the MAX19710EVKIT schematic for an
example of the digital outputs driving a digital buffer
through 100Ω series resistors.
00 0000 0011
00 0000 0010
00 0000 0001
00 0000 0000
-512 -511 -510 -509
-1 0+
(COM)
INPUT VOLTAGE (LSB)
1
+512
+509 +510 +511
Figure 2. Rx ADC Transfer Function
During SHDN, IDLE, STBY, SPI2, and SPI4 states, digital
outputs AD0–AD9 are tri-stated.
tially or single-ended. Match the impedance of IAP and
IAN, as well as QAP and QAN, and set the input signal
Dual 10-Bit Tx DACs
The dual 10-bit digital-to-analog converters (Tx DACs)
operate with clock speeds up to 7.5MHz. The Tx DAC
digital inputs, DA0–DA9, are multiplexed on a single
10-bit transmit bus. The voltage reference determines
the Tx DAC full-scale voltage at IDP, IDN and QDP,
QDN analog outputs. See the Reference Configurations
section for setting the reference voltage.
common-mode voltage within the V
/ 2 ( 0.8V) Rx
DD
ADC range for optimum performance.
Rx ADC System Timing Requirements
Figure 3 shows the relationship between the clock, ana-
log inputs, and the resulting output data. Channels IA
and QA are sampled on the rising edge of the clock sig-
______________________________________________________________________________________ 17
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
5.5 CLOCK-CYCLE LATENCY (QA)
5 CLOCK-CYCLE LATENCY (IA)
IA
QA
t
CLK
t
CL
t
CH
MAX9710
CLK
t
DOQ
t
DOI
D0–D9
D0Q
D1I
D1Q
D2I
D2Q
D3I
D3Q
D4I
D4Q
D5I
D5Q
D6I
D6Q
Figure 3. Rx ADC System Timing Diagram
Table 2. Tx DAC Output Voltage vs. Input Codes
(Internal Reference Mode V
Full Scale)
= 1.024V, External Reference Mode V
= V
, V = 400 for 800mV
REFIN FS P-P
REFDAC
REFDAC
DIFFERENTIAL OUTPUT VOLTAGE (V)
OFFSET BINARY (DA0–DA9)
INPUT DECIMAL CODE
V
1023
1023
REFDAC
1024
V
×
×
11 1111 1111
1023
(
(
)
)
FS
V
1023
1023
REFDAC
1024
V
11 1111 1110
10 0000 0001
10 0000 0000
01 1111 1111
00 0000 0001
00 0000 0000
1022
513
512
511
1
FS
V
1023
1023
REFDAC
1024
V
×
×
(
(
)
)
FS
V
1023
1023
REFDAC
1024
V
FS
V
1023
1023
REFDAC
1024
V
×
(
)
FS
V
1023
1023
REFDAC
1024
V
×
×
(
(
)
)
FS
V
1023
1023
REFDAC
1024
0
V
FS
The Tx DAC outputs (IDN, IDP, QDN, QDP) are biased at
an adjustable common-mode DC level and designed to
drive a differential input stage with ≥ 70kΩ input imped-
ance. This simplifies the analog interface between RF
quadrature upconverters and the MAX19710. Many RF
upconverters require a 0.89V to 1.36V common-mode
bias. The MAX19710 common-mode DC bias eliminates
discrete level-setting resistors and code-generated level
shifting while preserving the full dynamic range of each
Tx DAC. The Tx DAC differential analog outputs can-
not be used in single-ended mode because of the
internally generated common-mode DC level. Table 2
shows the Tx DAC output voltage vs. input codes. Table
10 shows the selection of DC common-mode levels.
See Figure 4 for an illustration of the Tx DAC analog
output levels.
The Tx DAC also features independent DC offset trim on
each ID–QD channel. This feature is configured through
the SPI interface. The DC offset correction is used to opti-
mize sideband and carrier suppression in the Tx signal
path (see Table 9).
18 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
MAX19710
EXAMPLE:
Tx DAC
CH-ID
Tx RFIC INPUT REQUIREMENTS
• DC COMMON-MODE BIAS = 0.9V (MIN), 1.3V (TYP)
0°
• BASEBAND INPUT = 400mV DC-COUPLED
90°
Tx DAC
CH-QD
FULL SCALE = 1.56V
COMMON-MODE LEVEL
V
= 1.36V
COMD
SELECT CM1 = 0, CM0 = 0
= 1.36V
V
COMD
V
= 400mV
FS
ZERO SCALE = 1.16V
0V
Figure 4. Tx DAC Common-Mode DC Level at IDN, IDP or QDN, QDP Differential Outputs
CLK
t
t
DHQ
DSQ
Q: N - 2
I: N - 1
Q: N - 1
Q: N
I: N + 1
D0–D9
I: N
t
t
DHI
DSI
N - 2
N - 2
ID
N - 1
N - 1
N
N
QD
Figure 5. Tx DAC System Timing Diagram
______________________________________________________________________________________ 19
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
Tx DAC Timing
Figure 5 shows the relationship among the clock, input
data, and analog outputs. Channel ID data is latched
on the falling edge of the clock signal, and channel
QD data is latched on the rising edge of the clock sig-
nal, at which point both ID and QD outputs are simul-
taneously updated.
Auxiliary ADC section for details). Use ENABLE-8 mode
for faster enable and switching between shutdown, idle,
and standby states as well as switching between FAST,
SLOW, Rx and Tx modes and the FD mode.
The WAKEUP-SEL register selects the operating mode
that the MAX19710 is to enter immediately after coming
out of shutdown (Table 11). See the Wake-Up Function
section for more information.
3-Wire Serial Interface and
Operation Modes
Shutdown mode offers the most dramatic power sav-
ings by shutting down all the analog sections (including
the reference) of the MAX19710. In shutdown mode,
the Rx ADC digital outputs are in tri-state mode, the Tx
The 3-wire serial interface controls the MAX19710 oper-
ation modes as well as the three 12-bit aux-DACs and
the 10-bit aux-ADC. Upon power-up, program the
MAX19710 to operate in the desired mode. Use the 3-
wire serial interface to program the device for shutdown,
idle, standby, FD, Rx, Tx, aux-DAC controls, or aux-ADC
conversion. A 16-bit data register sets the mode control
as shown in Table 3. The 16-bit word is composed of
four control bits (A3–A0) and 12 data bits (D11–D0).
Data is shifted in MSB first (D11) and LSB last (A0) for-
mat. Table 4 shows the MAX19710 power-management
modes. Table 5 shows the SPI-controlled Tx, Rx, and FD
modes. The serial interface remains active in all modes.
MAX9710
DAC digital inputs are internally pulled to OV , and
DD
the Tx DAC outputs are at 0V. When the Rx ADC out-
puts transition from tri-state to active mode, the last
converted word is placed on the digital output bus. The
Tx DAC previously stored data is lost when coming out
of shutdown mode. The wake-up time from shutdown
mode is dominated by the time required to charge the
capacitors at REFP, REFN, and COM. In internal refer-
ence mode and buffered external reference mode, the
wake-up time is typically 500µs to enter Rx mode,
26.2µs to enter Tx mode, and 500µs to enter
FD mode.
SPI Register Description
Program the control bits, A3–A0, in the register as shown
in Table 3 to select the operating mode. Modify A3–A0
bits to select from ENABLE-16, Aux-DAC1, Aux-DAC2,
Aux-DAC3, IOFFSET, QOFFSET, COMSEL, Aux-ADC,
ENABLE-8, and WAKEUP-SEL modes. ENABLE-16 is
the default operating mode (see Table 6). This mode
allows for shutdown, idle, and standby states as well as
switching between FAST, SLOW, Rx and Tx modes.
Tables 4 and 5 show the required SPI settings for
each mode.
In all operating modes the Tx DAC inputs DA0–DA9 are
internally pulled to OV . To reduce the supply current of
DD
the MAX19710 in shutdown mode do not pull DA0–DA9
low. This consideration is especially important in shut-
down mode to achieve the lowest quiescent current.
In idle mode, the reference and clock distribution cir-
cuits are powered, but all other functions are off. The
Rx ADC outputs AD0–AD9 are forced to tri-state. The
Tx DAC DA0–DA9 inputs are internally pulled to OV
,
DD
while the Tx DAC outputs are at 0V. The wake-up time
is 7.3µs to enter Rx mode, 5.2µs to enter Tx mode, and
7.3µs to enter FD mode. When the Rx ADC outputs
transition from tri-state to active, the last converted
word is placed on the digital output bus.
In ENABLE-16 mode, the aux-DACs have independent
control bits E4, E5, and E6, and bit E9 enables the aux-
ADC. Table 7 shows the auxiliary DAC enable codes.
Table 8 shows the auxiliary ADC enable code. Bits E11
and E10 are reserved. Program bits E11 and E10 to
logic-low. Bits E3, E7, and E8 are not used.
In standby mode, the reference is powered but all other
device functions are off. The wake-up time from stand-
by mode is 7.5µs to enter Rx mode, 22.2µs to enter Tx
mode, and 22.2µs to enter FD mode. When the Rx ADC
outputs transition from tri-state to active, the last con-
verted word is placed on the digital output bus.
Modes aux-DAC1, aux-DAC2, and aux-DAC3 select the
aux-DAC channels named DAC1, DAC2, and DAC3 and
hold the data inputs for each DAC. Bits _D11–_D0 are
the data inputs for each aux-DAC and can be pro-
grammed through SPI. The MAX19710 also includes
two 6-bit registers that can be programmed to adjust the
offsets for the Tx DAC ID and QD channels indepen-
dently (see Table 9). Use the COMSEL mode to select
the output common-mode voltage with bits CM1 and
CM0 (see Table 10). Use the aux-ADC mode to start the
auxiliary ADC conversion (see the 10-Bit, 333ksps
FAST and SLOW Rx and Tx Modes
The MAX19710 features FAST and SLOW modes for
switching between Rx and Tx operation. In FAST Tx
mode, the Rx ADC core is powered on but the ADC digi-
tal outputs AD0–AD9 are tri-stated. The Tx DAC digital
bus is active and the DAC core is fully operational.
20 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Table 3. MAX19710 Mode Control
D11
D10
D9
D8
D7
12
D6
11
D5
10
D4
9
D3
8
D2
7
D1
6
D0 A3 A2 A1
A0
REGISTER
NAME
(MSB)
15
14
13
5
4
3
2
1 (LSB)
E11 = 0
Reserved Reserved
E10 = 0
ENABLE-16
E9
—
—
E6
E5
E4
—
E2
E1
E0
0
0
0
0
Aux-DAC1
Aux-DAC2
Aux-DAC3
IOFFSET
1D11
2D11
3D11
—
1D10
2D10
3D10
—
1D9 1D8 1D7 1D6 1D5 1D4 1D3 1D2 1D1 1D0
2D9 2D8 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0
3D9 3D8 3D7 3D6 3D5 3D4 3D3 3D2 3D1 3D0
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
—
—
—
—
—
—
—
—
—
—
—
—
IO5 IO4 IO3 IO2 IO1 IO0
QO5 QO4 QO3 QO2 QO1 QO0
QOFFSET
COMSEL
—
—
—
—
—
—
—
—
CM1 CM0
AD11 = 0
Reserved
Aux-ADC
AD10
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0
0
1
1
1
ENABLE-8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
E2
E1
E0
1
1
0
0
0
0
0
1
WAKEUP-SEL
W2
W1
W0
— = Not used.
Table 4. Power-Management Modes
ADDRESS
DATA BITS
FUNCTION (POWER
MANAGEMENT)
MODE
DESCRIPTION
COMMENT
A3 A2 A1 A0 E9* E2 E1 E0
Rx ADC = OFF
Tx DAC = OFF
(TX DAC outputs at 0V)
Aux-DAC = OFF
Aux-ADC = OFF
CLK = OFF
Device is in
complete shutdown.
1
0
0
0
SHDN
SHUTDOWN
REF = OFF
Rx ADC = OFF
Tx DAC = OFF
(TX DAC outputs at 0V)
Aux-DAC = Last State
CLK = ON
0000
(16-Bit Mode)
or
1000
(8-Bit Mode)
Fast turn-on time.
Moderate idle
power.
X**
X**
0
0
0
1
1
0
IDLE
IDLE
REF = ON
Rx ADC = OFF
Tx DAC = OFF
(TX DAC outputs at 0V)
Aux-DAC = Last State
CLK = OFF
Slow turn-on time.
Low standby power.
STBY
STANDBY
REF = ON
X = Don’t care.
*Bit E9 is not available in 8-bit mode.
**In IDLE and STBY modes, the aux-ADC can be turned on or off.
______________________________________________________________________________________ 21
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
Table 5. MAX19710 Tx, Rx, and FD Control Using SPI Commands
ADDRESS
DATA BITS
FUNCTION
(Tx-Rx SWITCHING SPEED)
MODE
DESCRIPTION
COMMENT
A3 A2 A1 A0 E2 E1 E0
Rx Mode:
Rx ADC = ON
Rx Bus = Enabled
Tx DAC = OFF
(Tx DAC outputs at 0V)
Tx Bus = OFF (all inputs
are pulled high)
Slow transition to Tx
mode from this
mode.
0
1
1
0
1
0
SPI1-Rx
SLOW
SLOW
Low power.
MAX9710
Tx Mode:
Slow transition to Rx
mode from this
mode.
Rx ADC = OFF
Rx Bus = Tri-state
Tx DAC = ON
Tx Bus = ON
SPI2-Tx
SPI3-Rx
Low power.
0000
(16-Bit Mode)
and
1000
(8-Bit Mode)
Rx Mode:
Rx ADC = ON
Rx Bus = Enabled
Tx DAC = ON
(Tx DAC outputs at
midscale)
Fast transition to Tx
mode from this
mode. Moderate
power.
1
0
1
FAST
Tx Bus = OFF (all inputs
are pulled high)
Tx Mode:
Fast transition to Rx
mode from this
mode. Moderate
power.
Rx ADC = ON
Rx Bus = Tri-state
Tx DAC = ON
Tx Bus = ON
1
1
0
SPI4-Tx
FAST
FD Mode:
Default Mode
Fast transition to any
mode. Moderate
power.
Rx ADC = ON
Rx Bus = ON
Tx DAC = ON
Tx Bus = ON
1
1
1
FD
FAST
In FAST Rx mode, the Tx DAC core is powered on. The
Tx DAC outputs are set to midscale. In this mode, the Tx
DAC input bus is disconnected from the DAC core and
In SLOW Tx mode, the Rx ADC core is powered off and
the ADC digital outputs AD0–AD9 are tri-stated. The Tx
DAC digital bus is active and the DAC core is fully oper-
ational. In SLOW Rx mode, the Tx DAC core is powered
off. The Tx DAC outputs are set to 0. In SLOW Rx mode,
the Tx DAC input bus is disconnected from the DAC
DA0–DA9 are internally pulled to OV . The Rx ADC
DD
digital bus is active and the ADC core is fully opera-
tional.
core and DA0–DA9 are internally pulled to OV . The
DD
In FAST mode, the switching time from Tx to Rx, or Rx to
Tx is minimized because the converters are on and do
not have to recover from a power-down state. In FAST
mode, the switching time from Rx to Tx and Tx to Rx is
0.1µs. Power consumption is higher in FAST mode
because both Tx and Rx cores are always on.
Rx ADC digital bus is active and the ADC core is fully
operational. The switching times for SLOW modes are
5.2µs for Rx to Tx and 7.3µs for Tx to Rx.
22 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Table 6. MAX19710 Default (Power-On) Register Settings
D11
D10
D9
14
0
D8
D7
D6
11
0
D5
10
0
D4
9
D3
8
D2
7
D1
D0
5
REGISTER
NAME
16
(MSB)
15
13
12
6
0
1
1
FD mode
0
1
ENABLE-16
0
0
0
0
0
1
0
0
—
0
—
1
—
1
Aux-ADC
= ON
Aux-DAC1 to
Aux-DAC3 = ON
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
Aux-DAC1
Aux-DAC2
Aux-DAC3
IOFFSET
DAC1 output set to 1.1V
0
0
0
0
0
0
0
0
DAC2 output set to 0V
0
0
0
0
0
DAC3 output set to 0V
0
0
—
—
—
—
—
—
—
—
—
—
—
—
No offset on channel ID
0
0
0
0
0
QOFFSET
COMSEL
—
No offset on channel QD
0
= 1.36V
0
—
0
—
0
—
0
—
0
—
0
—
0
—
0
—
—
V
COMD
0
0
0
Aux-ADC
0
Aux-ADC = ON, Conversion = IDLE, Aux-ADC REF = 2.048V, MUX = ADC1,
Averaging = 1, Clock Divider = 1, DOUT = Disabled
1
1
FD mode
1
1
1
ENABLE-8
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
WAKEUP-SEL
Wake-up state = FD mode
Table 8. Aux-ADC Enable Table
(ENABLE-16 Mode)
Table 7. Aux-DAC Enable Table
(ENABLE-16 Mode)
E9
0 (Default)
1
SELECTION
E6 E5
E4
Aux-DAC3
Aux-DAC2
Aux-DAC1
ON
Aux-ADC is Powered ON
Aux-ADC is Powered OFF
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
ON
ON
ON
1
ON
OFF
ON
0
ON
OFF
1
ON
OFF
OFF
ON
Power consumption in SLOW Tx mode is 21.9mW, and
21.3mW in SLOW Rx mode. Power consumption in FAST
Tx mode is 29.1mW, and 28.5mW in FAST Rx mode.
0
OFF
OFF
OFF
OFF
ON
1
ON
OFF
ON
0
OFF
FD Mode
The MAX19710 features an FD mode, which is ideal for
applications supporting frequency-division duplex. In
FD mode, both Rx ADC and Tx DAC, as well as their
1
OFF
OFF
0
Default mode
______________________________________________________________________________________ 23
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
Table 9. Offset Control Bits for ID and QD Channels (IOFFSET or QOFFSET Mode)
BITS IO5–IO0 WHEN IN IOFFSET MODE, BITS QO5–QO0 WHEN IN QOFFSET MODE
OFFSET 1 LSB =
(VFS / 1023)
P-P
IO5/QO5
IO4/QO4
IO3/QO3
IO2/QO2
IO1/QO1
IO0/QO0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
0
1
-31 LSB
-30 LSB
-29 LSB
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
MAX9710
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
-2 LSB
-1 LSB
0mV
0mV (Default)
1 LSB
2 LSB
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
0
0
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
29 LSB
30 LSB
31 LSB
Note: 1 LSB = (800mV
/ 1023) = 0.782mV.
P-P
Table 10. Common-Mode Select
(COMSEL Mode)
Table 11. WAKEUP-SEL Register
POWER MODE AFTER WAKE-UP
(WAKE-UP STATE)
W2
W1
W0
CM1
CM0
Tx PATH OUTPUT COMMON MODE (V)
Invalid Value. This value is ignored
when inadvertently written to the
WAKEUP-SEL register.
0
0
1
1
0
1
0
1
1.36 (Default)
1.20
0
0
0
1.05
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
IDLE
0.89
STBY
SPI1-SLOW Rx
SPI2-SLOW Tx
SPI3-FAST Rx
SPI4-FAST Tx
FD (Default)
respective digital buses, are active and the device can
receive and transmit simultaneously. Switching from FD
mode to other Rx or Tx modes is fast (0.1µs) since
the on-board converters are already powered.
Consequently, power consumption in this mode is the
maximum of all operating modes. In FD mode the
MAX19710 consumes 30mW.
function. At the first rising edge of CS/WAKE, the
MAX19710 is forced to a preset operating mode deter-
mined by the WAKEUP-SEL register. This mode is
termed the wake-up state. If the WAKEUP-SEL register
has not been programmed, the wake-up state for the
MAX19710 is FD mode by default (Tables 6, 11). The
WAKEUP-SEL register cannot be programmed with W2
Wake-Up Function
The MAX19710 uses the SPI interface to control the
operating modes of the device including the shutdown
and wake-up functions. Once the device has been
placed in shutdown through the appropriate SPI com-
mand, the first pulse on CS/WAKE performs a wake-up
24 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
t
CSW
CS/WAKE
t
t
t
CS
CSS
CP
SCLK
t
CH
t
CL
t
t
DH
DS
LSB
MSB
DIN
Figure 6. Serial-Interface Timing Diagram
CS/WAKE
SCLK
DIN
16-BIT SERIAL DATA INPUT
ADC DIGITAL OUTPUT SINAD
SETTLES TO WITHIN 1dB
AD0–AD9
ID/QD
t
TO Rx MODE OR t
,
ENABLE RX
WAKE,SD,ST_
DAC ANALOG OUTPUT
SETTLES TO 10 LSB ERROR
t
TO Tx MODE OR t
,
ENABLE TX
WAKE,SD,ST_
Figure 7. Mode-Recovery Timing Diagram
= 0, W1 = 0, and W0 = 0. If this value is inadvertently
written to the device, it is ignored and the register con-
tinues to store its previous value. Upon wake-up, the
MAX19710 enters the power mode determined by the
WAKEUP-SEL register, however, all other settings (Tx
DAC offset, Tx DAC common-mode voltage, aux-DAC
settings, aux-ADC state) are restored to their values
prior to shutdown.
serial clock (SCLK). After 16 bits are loaded into the serial
input register, data is transferred to the latch when
CS/WAKE transitions high. CS/WAKE must transition high
for a minimum of 80ns before the next write sequence.
SCLK can idle either high or low between transitions.
Figure 6 shows the detailed timing diagram of the 3-wire
serial interface.
Mode-Recovery Timing
Figure 7 shows the mode-recovery timing diagram.
The only SPI line that is monitored by the MAX19710
during shutdown is CS/WAKE. Any information transmit-
ted to the MAX19710 concurrent with the CS/WAKE
wake-up pulse is ignored.
t
is the wake-up time when exiting shutdown, idle,
WAKE
or standby mode and entering Rx, Tx, or FD mode.
is the recovery time when switching between
t
ENABLE
either Rx or Tx mode. t
or t
is the time for
WAKE
ENABLE
SPI Timing
The serial digital interface is a standard 3-wire connection
CS/WAKE, SCLK, DIN) compatible with SPI/QSPI™/
MICROWIRE/DSP interfaces. Set CS/WAKE low to enable
the serial data loading at DIN or output at DOUT. Following
a CS/WAKE high-to-low transition, data is shifted synchro-
nously, most significant bit first, on the rising edge of the
the Rx ADC to settle within 1dB of specified SINAD per-
formance and Tx DAC settling to 10 LSB error. t
WAKE
and t
times are measured after the 16-bit serial
ENABLE
command is latched into the MAX19710 by a CS/WAKE
transition high. In FAST mode, the recovery time is 0.1µs
to switch between Tx or Rx modes.
QSPI is a trademark of Motorola, Inc.
______________________________________________________________________________________ 25
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
Loading on the aux-DAC outputs should be carefully
System Clock Input (CLK)
Both the Rx ADC and Tx DAC share the CLK input. The
CLK input accepts a CMOS-compatible signal level set
observed to achieve the specified settling time and sta-
bility. The capacitive load must be kept to a maximum
of 5pF including package and trace capacitance. The
resistive load must be greater than 200kΩ. If capacitive
loading exceeds 5pF, then add a 10kΩ resistor in
series with the output. Adding the series resistor helps
drive larger load capacitance (< 15pF) at the expense
of slower settling time.
by OV
from 1.8V to V . Since the interstage con-
DD
DD
version of the device depends on the repeatability of
the rising and falling edges of the external clock, use a
clock with low jitter and fast rise and fall times (< 2ns).
Specifically, sampling occurs on the rising edge of the
clock signal, requiring this edge to provide the lowest
possible jitter. Any significant clock jitter limits the SNR
performance of the on-chip Rx ADC as follows:
10-Bit, 333ksps Auxiliary ADC
The MAX19710 integrates a 333ksps, 10-bit aux-ADC
with an input 4:1 multiplexer. In the aux-ADC mode reg-
ister, setting bit AD0 begins a conversion with the auxil-
iary ADC. Bit AD0 automatically clears when the
conversion is complete. Setting or clearing AD0 during
a conversion has no effect (see Table 12). Bit AD1
determines the internal reference of the auxiliary ADC
(see Table 13). Bits AD2 and AD3 determine the auxil-
iary ADC input source (see Table 14). Bits AD4, AD5,
and AD6 select the number of averages taken when a
single start-convert command is given. The conversion
time increases as the number of averages increases
(see Table 15). The conversion clock can be divided
down from the system clock by properly setting bits
AD7, AD8, and AD9 (see Table 16). The aux-ADC out-
put data can be written out of DOUT by setting bit
AD10 high (see Table 17).
MAX9710
⎛
⎞
1
SNR = 20 × log
⎜
⎟
2 × π × f × t
⎝
⎠
IN
AJ
where f represents the analog input frequency and
IN
t
AJ
is the time of the clock jitter.
Clock jitter is especially critical for undersampling
applications. Consider the clock input as an analog
input and route away from any analog input or other
digital signal lines. The MAX19710 clock input operates
with an OV
/ 2 voltage threshold and accepts a 50%
DD
10% duty cycle.
When the clock signal is stopped at CLK input (CLK =
0V or OV ), all internal registers hold their last value
DD
and the MAX19710 saves the last power-management
mode or Tx/Rx/FD command. All converter circuits (Rx
ADC, Tx DAC, aux-ADC, and aux-DACs) hold their last
value. When the clock signal is restarted at CLK, allow
7.5µs (clock wake-up time) for the internal clock circuit-
ry to settle before updating the Tx DAC, reading a valid
Rx ADC conversion result, or starting an aux-ADC con-
version. This ensures the converters (Rx ADC, Tx DAC,
aux-ADC) meet all dynamic performance specifica-
tions. The aux-DAC channels are not dependent on
CLK, so they may be updated when CLK is idle.
The aux-ADC features a 4:1 input multiplexer to allow
measurements on four input sources. The input sources
are selected by AD3 and AD2 (see Table 14). Two of
the multiplexer inputs (ADC1 and ADC2) can be con-
nected to external sources such as an RF power detec-
tor like the MAX2208 or temperature sensor like the
MAX6613. The other two multiplexer inputs are internal
connections to V
and OV
that monitor the power-
DD
DD
supply voltages. The internal V
and OV
connec-
DD
DD
tions are made through integrated dividers that yield
12-Bit, Auxiliary Control DACs
The MAX19710 includes three 12-bit aux-DACs (DAC1,
DAC2, DAC3) with 1µs settling time for controlling vari-
able-gain amplifier (VGA), automatic gain-control
(AGC), and automatic frequency-control (AFC) func-
tions. The aux-DAC output range is 0.2V to 2.57V as
V
/ 2 and OV / 2 measurement results. The aux-
DD
DD
ADC voltage reference can be selected between an
internal 2.048V bandgap reference or V (see Table
DD
13). The V
reference selection is provided to allow
DD
measurement of an external voltage source with a full-
scale range extending beyond the 2.048V level. The
defined by V
- V . During power-up, the VGA and
OL
OH
input source voltage range cannot extend above V
.
DD
AGC outputs (DAC2 and DAC3) are at zero. The AFC
DAC (DAC1) is at 1.1V during power-up. The aux-DACs
can be independently controlled through the SPI bus,
except during SHDN mode where the aux-DACs are
turned off completely and the output voltage is set to
zero. In STBY and IDLE modes the aux-DACs maintain
the last value. On wake-up from SHDN, the aux-DACs
resume the last values.
The conversion requires 12 clock edges (1 for input
sampling, 1 for each of the 10 bits, and 1 at the end for
loading into the serial output register) to complete one
conversion cycle (when no averaging is being done).
Each conversion of an average (when averaging is set
greater than 1) requires 12 clock edges. The conver-
sion clock is generated from the system clock input
(CLK). An SPI-programmable divider divides the system
26 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Table 12. Auxiliary ADC Convert
Table 16. Auxiliary ADC Clock (CLK)
Divider
AD0
SELECTION
0
1
Aux-ADC Idle (Default)
Aux-ADC Start-Convert
AD9
AD8
AD7
Aux-ADC CONVERSION CLOCK
CLK Divided by 1 (Default)
CLK Divided by 2
0
0
0
0
0
1
0
1
0
CLK Divided by 4
Table 13. Auxiliary ADC Reference
0
1
1
CLK Divided by 8
AD1
SELECTION
1
0
0
CLK Divided by 16
0
1
Internal 2.048V Reference (Default)
1
0
1
CLK Divided by 32
Internal V
Reference
DD
1
1
0
CLK Divided by 64
1
1
1
CLK Divided by 128
Table 14. Auxiliary ADC Input Source
AD3
AD2
Aux-ADC INPUT SOURCE
ADC1 (Default)
ADC2
Table 17. Auxiliary ADC Data Output
Mode
0
0
1
1
0
1
0
1
AD10
SELECTION
V
/ 2
DD
0
Aux-ADC Data is Not Available on DOUT (Default)
OV
/ 2
DD
Aux-ADC Enters Data Output Mode Where
Data is Available on DOUT
1
Table 15. Auxiliary ADC Averaging
Reading DOUT from the Aux-ADC
AD6 AD5 AD4
Aux-ADC AVERAGING
1 Conversion (No Averaging) (Default)
Average of 2 Conversions
DOUT is normally in a high-impedance condition. Upon
setting the auxiliary ADC start conversion bit (bit AD0),
DOUT becomes active and goes high, indicating that
the aux-ADC is busy. When the conversion cycle is
complete (including averaging), the data is placed into
an output register and DOUT goes low, indicating that
the output data is ready to be driven onto DOUT. When
bit AD10 is set (AD10 = 1), the aux-ADC enters a data
output mode where data is available at DOUT on the
next low assertion of CS/WAKE. The auxiliary ADC data
is shifted out of DOUT (MSB first) with the data transi-
tioning on the falling edge of the serial clock (SCLK).
Since a DOUT read requires 16 bits, DOUT holds the
value of the last conversion data bit for the last 6 bits (6
least significant bits) following the aux-ADC conversion
data. DOUT enters a high-impedance state when
CS/WAKE is deasserted high. When bit AD10 is cleared
(AD10 = 0), the aux-ADC data is not available on DOUT
(see Table 17).
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
X
Average of 4 Conversions
Average of 8 Conversions
Average of 16 Conversions
Average of 32 Conversions
Average of 32 Conversions
X = Don’t care.
clock by the appropriate divisor (set with bits AD7,
AD8, and AD9; see Table 16) and provides the conver-
sion clock to the auxiliary ADC. The auxiliary ADC has a
maximum conversion rate of 333ksps. The maximum
conversion clock frequency is 4MHz (333ksps x 12
clocks). Choose the proper divider value to keep the
conversion clock frequency under 4MHz, based upon
the system CLK frequency supplied to the MAX19710
After the aux-ADC completes a conversion, the data
result is loaded to an output register waiting to be shift-
ed out. No further conversions are possible until data is
shifted out. This means that if the first conversion com-
mand sets AD10 = 0, AD0 = 1, then it cannot be fol-
lowed by conversion commands setting AD10 = 0, AD0
= 1 or AD10 = 1, AD0 = 1. If this sequence of com-
mands is inadvertently used then DOUT is disabled. To
resume normal operation set AD0 = 0.
(see Table 16). The total conversion time (t
) of the
= (12 x
CONV
auxiliary ADC can be calculated as t
CONV
is the number of
is the CLK divisor (see
is the system CLK frequency.
N
x N
) / f
; where N
AVG
DIV
CLK
AVG
averages (see Table 15), N
DIV
Table 16), and f
CLK
______________________________________________________________________________________ 27
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
The fastest method to perform sequential conversions
with the aux-ADC is by sending consecutive com-
mands setting AD10 = 1, AD0 = 1. With this sequence
the CS/WAKE falling edge shifts data from the previous
conversion on to DOUT and the rising edge of
CS/WAKE loads the next conversion command at DIN.
Allow enough time for each conversion to complete
before sending the next conversion command. See
Figure 8 for single and continuous conversion examples.
1. SINGLE AUX-ADC CONVERSION WITH CONVERSION DATA READOUT AT A LATER TIME
t
t
t
CHZ
CSD
CD
CS/WAKE
MAX9710
1
0
16
1
1
16
1
0
16
1
1
10 11
DIN SET HIGH DURING SINGLE READ
D9 D1 D0 D0 HELD
16
SCLK
DIN
0
1
0
1
1
1
0
0
1
1
DOUT
AD10 = 0, AD0 = 1,
PERFORM CONVERSION,
DOUT DISABLED
AUX-ADC REGISTER
ADDRESS
IF AUX-ADC CONVERSION
CONVERSION RESULT DATA
BIT D0 IS HELD FOR THE SIX
LEAST SIGNIFICANT BITS
DOES NOT NEED TO BE
READ IMMEDIATELY, THE SPI
INTERFACE IS FREE AND
CAN BE USED FOR OTHER
FUNCTIONS, SUCH AS
HOUSEKEEPING AUX-DAC
ADJUSTMENT, ETC.
AUX-ADC REGISTER
ADDRESS
FIRST FALLING EDGE OF
CS/WAKE AFTER DOUT IS
ENABLED STARTS SHIFTING THE
AUX-ADC CONVERSION DATA ON
THE FALLING EDGE OF SCLK
DOUT TRANSITIONS TO
HIGH IMPEDANCE
DOUT TRANSITIONS FROM
HIGH IMPEDANCE TO LOGIC-
HIGH INDICATING START OF
CONVERSION
AD10 = 1, AD0 = 0,
AUX-ADC IDLE
10-BIT AUX-ADC
CONVERSION RESULT IS
SHIFTED OUT ON DOUT ON
THE FALLING EDGE OF SCLK
MSB FIRST
(NO CONVERSION),
DOUT ENABLED AND
CONVERSION DATA IS
SHIFTED OUT ON NEXT
CS/WAKE FALLING EDGE
DOUT TRANSITIONS LOW
INDICATING END OF CONVERSION,
DATA IS AVAILABLE AND CAN BE
SHIFTED OUT IF DOUT IS ENABLED,
AD0 CLEARED
2. CONTINUOUS AUX-ADC CONVERSIONS
t
CONV
CS/WAKE
t
DCS
1
16
1
1
0
10 11 12 13 14 15 16
1
10 11 12 13 14 15 16
SCLK
DIN
0
0
1
0
1
1
1
1
0
1
1
1
0
1
1
0
1
1
1
D9
D1 D0
D0 HELD
D9
D1 D0
D0 HELD
DOUT
AD10 = 1, AD0 = 1,
PERFORM CONVERSION,
DOUT ENABLED
AD10 = 1, AD0 = 1,
PERFORM CONVERSION,
DOUT ENABLED
AD10 = 1, AD0 = 1,
PERFORM CONVERSION,
DOUT ENABLED
FIRST 10-BIT AUX-ADC
CONVERSION RESULT IS
SHIFTED OUT ON DOUT ON
THE FALLING EDGE OF SCLK
MSB FIRST
SECOND 10-BIT AUX-ADC
CONVERSION RESULT IS
SHIFTED OUT ON DOUT ON
THE FALLING EDGE OF SCLK
MSB FIRST
AUX-ADC REGISTER
ADDRESS
DOUT TRANSITIONS FROM
HIGH IMPEDANCE TO LOGIC-
HIGH INDICATING START OF
FIRST CONVERSION
DOUT TRANSITIONS HIGH
INDICATING START OF
SECOND CONVERSION
DOUT TRANSITIONS HIGH
INDICATING START OF
THIRD CONVERSION
DOUT TRANSITIONS LOW
INDICATING END OF FIRST
CONVERSION, DATA IS AVAILABLE
AND CAN BE SHIFTED OUT IF DOUT
IS ENABLED, AD0 CLEARED
DOUT TRANSITIONS LOW
INDICATING END OF SECOND
CONVERSION, DATA IS AVAILABLE
AND CAN BE SHIFTED OUT IF DOUT
IS ENABLED, AD0 CLEARED
DOUT TRANSITIONS LOW
INDICATING END OF THIRD
CONVERSION, DATA IS AVAILABLE
AND CAN BE SHIFTED OUT IF DOUT
IS ENABLED, AD0 CLEARED
Figure 8. Aux-ADC Conversions Timing
28 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
DIN can be written independent of DOUT state. A 16-bit
Reference Configurations
The MAX19710 features an internal precision 1.024V-
bandgap reference that is stable over the entire power-
supply and temperature ranges. The REFIN input
provides two modes of reference operation. The volt-
instruction at DIN updates the device configuration. To
prevent modifying internal registers while reading data
from DOUT, hold DIN at a high state (only applies if
sequential aux-ADC conversions are not executed).
This effectively writes all ones into address 1111. Since
address 1111 does not exist, no internal registers
are affected.
age at REFIN (V
mode (Table 18).
) sets the reference operation
REFIN
In internal reference mode, connect REFIN to V
REF
level. COM, REFP, and REFN are low-impedance out-
.
DD
V
is an internally generated 0.512V 4% reference
25Ω
puts with V
= V
DD
/ 2, V
REF
= V
/ 2 + V
/ 2,
REF
COM
= V
DD
/ 2 - V
REFP
DD
IAP
and V
/ 2. Bypass REFP, REFN,
REFN
0.1μF
22pF
and COM each with a 0.33µF capacitor. Bypass REFIN
to GND with a 0.1µF capacitor.
V
IN
In buffered external reference mode, apply 1.024V
10% at REFIN. In this mode, COM, REFP, and REFN
COM
IAN
0.33μF
0.1μF
are low-impedance outputs with V
= V
/ 2,
COM
REFN
DD
DD
V
V
= V
/ 2 + V / 4, and V
REFIN
= V
/ 2 -
REFP
REFIN
DD
/ 4. Bypass REFP, REFN, and COM each with a
0.33µF capacitor. Bypass REFIN to GND with a 0.1µF
capacitor. In this mode, the Tx path full-scale output is
proportional to the external reference. For example, if
25Ω
22pF
22pF
MAX19710
the V
is increased by 10% (max), the Tx path full-
REFIN
25Ω
scale output is also increased by 10% or 440mV.
QAP
Applications Information
0.1μF
V
IN
Using Balun Transformer AC-Coupling
An RF transformer (Figure 9) provides an excellent
solution to convert a single-ended signal source to a
fully differential signal for optimum ADC performance.
Connecting the center tap of the transformer to COM
0.33μF
0.1μF
provides a V
/ 2 DC level shift to the input. A 1:1
DD
transformer can be used, or a step-up transformer can
be selected to reduce the drive requirements. In gener-
al, the MAX19710 provides better SFDR and THD with
fully differential input signals than single-ended signals,
especially for high input frequencies. In differential
mode, even-order harmonics are lower as both inputs
(IAP, IAN, QAP, QAN) are balanced, and each of the
QAN
25Ω
22pF
Figure 9. Balun Transformer-Coupled Single-Ended-to-
Differential Input Drive for Rx ADC
Table 18. Reference Modes
V
REFIN
REFERENCE MODE
Internal Reference Mode. V
with a 0.33µF capacitor.
is internally generated to be 0.512V. Bypass REFP, REFN, and COM each
REF
> 0.8V x V
DD
Buffered External Reference Mode. An external 1.024V 10% reference voltage is applied to REFIN. V
is
REF
1.024V 10%
internally generated to be V
/ 2. Bypass REFP, REFN, and COM each with a 0.33µF capacitor. Bypass
REFIN
REFIN to GND with a 0.1µF capacitor.
______________________________________________________________________________________ 29
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
Rx ADC inputs only requires half the signal swing com-
pared to single-ended mode. Figure 10 shows an RF
transformer converting the MAX19710 Tx DAC differen-
tial analog outputs to single-ended.
IDP
IDN
V
OUT
Using Op-Amp Coupling
Drive the MAX19710 Rx ADC with op amps when a
balun transformer is not available. Figures 11 and 12
show the Rx ADC being driven by op amps for AC-cou-
pled single-ended and DC-coupled differential applica-
tions. Amplifiers such as the MAX4454 and MAX4354
provide high speed, high bandwidth, low noise, and
low distortion to maintain the input signal integrity. The
op-amp circuit shown in Figure 12 can also be used to
interface with the Tx DAC differential analog outputs to
provide gain or buffering. The Tx DAC differential ana-
log outputs cannot be used in single-ended mode
because of the internally generated common-mode
level. Also, the Tx DAC analog outputs are designed to
drive a differential input stage with input impedance ≥
70kΩ. If single-ended outputs are desired, use an
amplifier to provide differential-to-single-ended conver-
sion and select an amplifier with proper input common-
mode voltage range.
MAX19710
QDP
V
OUT
MAX9710
QDN
Figure 10. Balun Transformer-Coupled Differential-to-Single-
Ended Output Drive for Tx DAC
REFP
1kΩ
1kΩ
R
50Ω
ISO
V
IN
0.1μF
FDD Application
Figure 13 illustrates a typical FDD application circuit. The
MAX19710 interfaces directly with a ZIF radio front-end to
provide a complete “RF-to-Bits” solution for FDD applica-
tions such as private mobile radio (PMR), broadband
access radio, and proprietary radio systems. The
MAX19710 provides several system benefits to digital
baseband developers:
IAP
C
22pF
IN
100Ω
100Ω
COM
IAN
REFN
0.1μF
R
ISO
50Ω
•
•
•
•
•
•
•
Fast Time-to-Market
C
22pF
IN
High-Performance, Low-Power Analog Functions
Low-Risk, Proven Analog Front-End Solution
No Mixed-Signal Test Times
No NRE Charges
REFP
MAX19710
R
ISO
1kΩ
V
IN
0.1μF
No IP Royalty Charges
50Ω
QAP
Enables Digital Baseband and Scale with 65nm to
90nm CMOS
C
IN
22pF
100Ω
100Ω
1kΩ
Grounding, Bypassing, and
Board Layout
The MAX19710 requires high-speed board layout design
techniques. Refer to the MAX19710 EV kit data sheet for a
board layout reference. Place all bypass capacitors as
close to the device as possible, preferably on the same
side of the board as the device, using surface-mount
REFN
0.1μF
R
ISO
50Ω
QAN
C
IN
22pF
devices for minimum inductance. Bypass V
to GND
DD
with a 0.1µF ceramic capacitor in parallel with a 2.2µF
Figure 11. Single-Ended Drive for Rx ADC
30 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
R4
R5
600Ω
600Ω
R
22Ω
ISO
R1
600Ω
IAN
C
IN
5pF
R2
600Ω
MAX19710
R6
R7
600Ω
600Ω
COM
R3
600Ω
R8
600Ω
R9
600Ω
R
ISO
22Ω
IAP
C
IN
5pF
R10
R11
600Ω
600Ω
Figure 12. Rx ADC DC-Coupled Differential Drive
capacitor. Bypass OV
to OGND with a 0.1µF ceramic
from any noisy digital system’s ground plane (e.g.,
downstream output buffer or DSP ground plane).
DD
capacitor in parallel with a 2.2µF capacitor. Bypass REFP,
REFN, and COM each to GND with a 0.33µF ceramic
capacitor. Bypass REFIN to GND with a 0.1µF capacitor.
Route high-speed digital signal traces away from sensi-
tive analog traces. Make sure to isolate the analog
input lines to each respective converter to minimize
channel-to-channel crosstalk. Keep all signal lines short
and free of 90ꢀ turns.
Multilayer boards with separated ground and power
planes yield the highest level of signal integrity. Use a
split ground plane arranged to match the physical loca-
tion of the analog ground (GND) and the digital output-
driver ground (OGND) on the device package. Connect
the MAX19710 exposed backside paddle to the GND
plane. Join the two ground planes at a single point so
the noisy digital ground currents do not interfere with
the analog ground plane. The ideal location for this
connection can be determined experimentally at a
point along the gap between the two ground planes.
Make this connection with a low-value, surface-mount
resistor (1Ω to 5Ω), a ferrite bead, or a direct short.
Alternatively, all ground pins could share the same
ground plane, if the ground plane is sufficiently isolated
Dynamic Parameter Definitions
ADC and DAC Static Parameter Definitions
Integral Nonlinearity (INL)
Integral nonlinearity is the deviation of the values on an
actual transfer function from a straight line. This straight
line can be either a best-straight-line fit or a line drawn
between the end points of the transfer function, once
offset and gain errors have been nullified. The static lin-
earity parameters for the device are measured using
the best-straight-line fit (DAC Figure 14a).
______________________________________________________________________________________ 31
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
V
DD
= 2.7V TO 3.3V
OV = 1.8V TO V
DD
DD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
IAP
10-BIT
ADC
DATA MUX
IAN
QAP
MAX9710
10-BIT
ADC
QAN
IDP
FDD ZIF
TRANSCEIVER
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
10-BIT
DAC
DATA MUX
IDN
DIGITAL
BASEBAND
ASIC
QDP
QDN
10-BIT
DAC
AGC
SYSTEM
CLOCK
CLK
PROGRAMMABLE
OFFSET/CM
CS/WAKE
SCLK
DIN
SERIAL
INTERFACE
AND SYSTEM
CONTROL
DAC1
12-BIT
AUX-DAC
TCXO
DAC2
DAC3
12-BIT
AUX-DAC
DOUT
REFIN
REFP
COM
REFN
1.024V
REFERENCE
BUFFER
12-BIT
AUX-DAC
ADC1
ADC2
BATTERY VOLTAGE MONITOR
TEMPERATURE MEASUREMENT
10-BIT
AUX-ADC
MAX19710
V
DD
/ 2
OV / 2
DD
GND
OGND
Figure 13. Typical FDD Application Circuit
32 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Differential Nonlinearity (DNL)
7
6
Differential nonlinearity is the difference between an
actual step width and the ideal value of 1 LSB. A DNL
error specification of less than 1 LSB guarantees no
missing codes (ADC) and a monotonic transfer function
(ADC and DAC) (DAC Figure 14b).
5
4
ADC Offset Error
Ideally, the midscale transition occurs at 0.5 LSB above
midscale. The offset error is the amount of deviation
between the measured transition point and the ideal
transition point.
AT STEP
011 (0.5 LSB)
3
2
1
0
AT STEP
001 (0.25 LSB)
DAC Offset Error
Offset error (Figure 14a) is the difference between the
ideal and actual offset point. The offset point is the out-
put value when the digital input is midscale. This error
affects all codes by the same amount and usually can
be compensated by trimming.
000 001 010 011 100 101 110 111
DIGITAL INPUT CODE
Figure 14a. Integral Nonlinearity
ADC Gain Error
Ideally, the ADC full-scale transition occurs at 1.5 LSB
below full scale. The gain error is the amount of devia-
tion between the measured transition point and the
ideal transition point with the offset error removed.
6
5
4
1 LSB
DIFFERENTIAL LINEARITY
ERROR (-0.25 LSB)
ADC Dynamic Parameter Definitions
Aperture Jitter
3
Figure 15 shows the aperture jitter (t ), which is the
AJ
1 LSB
sample-to-sample variation in the aperture delay.
2
1
0
Aperture Delay
Aperture delay (t ) is the time defined between the
AD
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 15).
DIFFERENTIAL
LINEARITY ERROR (+0.25 LSB)
000
001
010
011
100
101
DIGITAL INPUT CODE
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error) and results directly
from the ADC’s resolution (N bits):
Figure 14b. Differential Nonlinearity
CLK
SNR(max) = 6.02 x N + 1.76
(in dB)
ANALOG
INPUT
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first five harmonics, and the DC offset.
t
AD
t
AJ
SAMPLED
DATA (T/H)
HOLD
TRACK
TRACK
Signal-to-Noise and Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise. RMS noise includes all spectral
T/H
Figure 15. T/H Aperture Timing
______________________________________________________________________________________ 33
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
components to the Nyquist frequency excluding the
Power-Supply Rejection
Power-supply rejection is defined as the shift in offset
and gain error when the power supply is changed 5%.
fundamental and the DC offset.
Effective Number of Bits (ENOB)
ENOB specifies the dynamic performance of an ADC at a
specific input frequency and sampling rate. An ideal
ADC’s error consists of quantization noise only. ENOB for
a full-scale sinusoidal input waveform is computed from:
Small-Signal Bandwidth
A small -20dBFS analog input signal is applied to an
ADC in such a way that the signal’s slew rate does not
limit the ADC’s performance. The input frequency is
then swept up to the point where the amplitude of the
digitized conversion result has decreased by 3dB. Note
that the T/H performance is usually the limiting factor
for the small-signal input bandwidth.
ENOB = (SINAD - 1.76) / 6.02
Total Harmonic Distortion (THD)
THD is typically the ratio of the RMS sum of the first five
harmonics of the input signal to the fundamental itself.
This is expressed as:
MAX9710
Full-Power Bandwidth
A large -0.5dBFS analog input signal is applied to an
ADC, and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by 3dB. This point is defined as the full-
power bandwidth frequency.
2
2
2
3
2
2
5
2
6
⎡
⎢
⎣
⎤
⎥
⎦
(V +V +V +V +V )
4
THD = 20 x log
V
⎢
⎥
1
where V is the fundamental amplitude and V –V are
1
2
6
the amplitudes of the 2nd- through 6th-order harmonics.
DAC Dynamic Parameter Definitions
Total Harmonic Distortion
THD is the ratio of the RMS sum of the output harmonics
up to the Nyquist frequency divided by the fundamental:
Third Harmonic Distortion (HD3)
HD3 is defined as the ratio of the RMS value of the third
harmonic component to the fundamental input signal.
(V2 +V2 +...+V2)
⎡
⎢
⎤
⎥
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest spurious
component, excluding DC offset.
2
3
n
THD = 20 x log
V
1
⎢
⎥
⎣
⎦
where V is the fundamental amplitude and V through
1
2
V are the amplitudes of the 2nd through nth harmonic
n
Intermodulation Distortion (IMD)
IMD is the total power of the intermodulation products
up to the Nyquist frequency.
Spurious-Free Dynamic Range
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component up to the Nyquist frequency excluding DC.
relative to the total input power when two tones, f
IN1
and f , are present at the inputs. The intermodulation
IN2
products are (f
f
), (2 ✕ f ), (2 ✕ f ), (2 ✕ f
IN1
IN2 IN1 IN2 IN1
). The individual input tone levels
f
), (2 ✕ f
f
IN2
IN2
IN1
are at -7dBFS.
3rd-Order Intermodulation (IM3)
IM3 is the power of the worst 3rd-order intermodulation
product relative to the input power of either input tone
when two tones, f
and f , are present at the inputs.
IN1
IN2
The 3rd-order intermodulation products are (2 x f
IN1
f
), (2 ✕ f
IN2
f
). The individual input tone levels
IN2
IN1
are at-7dBFS.
Selector Guide
PART
SAMPLING RATE (Msps)
INTEGRATED CDMA Tx FILTERS
MAX19710
MAX19711
MAX19712
MAX19713
7.5
11
22
45
No
Yes
No
No
34 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Functional Diagram
V
DD
= 2.7V TO 3.3V
OV = 1.8V TO V
DD
DD
IAP
IAN
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
10-BIT
ADC
DATA MUX
QAP
QAN
10-BIT
ADC
DA0
DA1
DA2
DA3
DA4
DA5
DA6
DA7
DA8
DA9
IDP
IDN
10-BIT
DAC
DATA MUX
QDP
QDN
10-BIT
DAC
SYSTEM
CLOCK
CLK
PROGRAMMABLE
OFFSET/GAIN/CM
CS/WAKE
SCLK
DIN
SERIAL
INTERFACE
AND SYSTEM
CONTROL
12-BIT
AUX-DAC
DAC1
DAC2
DAC3
12-BIT
AUX-DAC
DOUT
REFIN
REFP
REFN
COM
1.024V
REFERENCE
BUFFER
12-BIT
AUX-DAC
ADC1
ADC2
10-BIT
AUX-ADC
MAX19710
V
DD
/ 2
OV / 2
DD
GND
OGND
______________________________________________________________________________________ 35
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
E
DETAIL A
(NE-1) X
e
E/2
MAX9710
k
e
D/2
C
(ND-1) X
e
D2
D
L
D2/2
b
L
E2/2
C
L
k
DETAIL B
E2
e
C
C
L
L
L
L1
L
L
e
e
A
A1
A2
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
1
21-0144
E
2
36 ______________________________________________________________________________________
10-Bit, 7.5Msps, Full-Duplex
Analog Front-End
MAX9710
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
32, 44, 48, 56L THIN QFN, 7x7x0.8mm
2
21-0144
E
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 37
© 2006 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
Jackson
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