MAX17117ETJ+ [MAXIM]
Switching Controller, Current-mode, 1.6A, 1400kHz Switching Freq-Max, BICMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-32;
| 型号： | MAX17117ETJ+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | Switching Controller, Current-mode, 1.6A, 1400kHz Switching Freq-Max, BICMOS, 5 X 5 MM, ROHS COMPLIANT, TQFN-32 信息通信管理 开关 |
| 文件： | 总22页 (文件大小：1319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5241; Rev 0; 4/10
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
S High-Performance Operational Amplifier
General Description
The MAX17117 includes a high-performance step-up
regulator, a 350mA low-dropout (LDO) linear regulator,
a high-speed operational amplifier, and a high-voltage
level-shifting scan driver with gate-shading control. The
device is optimized for thin-film transistor (TFT) liquid-
crystal display (LCD) applications.
200mA Output Short-Circuit Current
40V/µs Slew Rate
16MHz, -3dB Bandwidth
Low-Dropout Linear Regulator
High-Accuracy Output Voltage (1.0%)
S High-Voltage Drivers with Scan Logic
+35V to -15V Outputs
40V Maximum Voltage Swing
Gate-Shading Control
The step-up DC-DC converter provides the regulated
supply voltage for panel source-driver ICs. The high
1.2MHz switching frequency allows the use of ultra-small
inductors and ceramic capacitors. The current-mode
control architecture provides a fast-transient response to
pulsed loads typical of source driver loads. The step-up
regulator features an adjustable soft-start and an adjust-
able cycle-by-cycle current limit.
S Thermal-Overload Protection
S 32-Pin, 5mm x 5mm, Thin QFN Package
Simplified Operating Circuit
V
V
VGL
GHON
The high-current operational amplifier is designed to
drive the LCD backplane (VCOM). The amplifier features
high output current (Q200mA typ), fast slew rate (40V/Fs
typ), wide bandwidth (16MHz typ), and rail-to-rail inputs
and outputs.
V
IN
V
MAIN
IN
LX
PGND
The low-voltage LDO linear regulator has an integrated
0.8Ipass element and can provide at least 350mA. The
output voltage is accurate within Q1%.
SETUP
CONTROLLER
ENA
FB
COMP
SS
LDOADJ
AGND
(EP)
LINEAR
REGULATOR
The high-voltage, level-shifting scan driver with gate-
shading control is designed to drive the TFT panel gate
drivers. Its seven outputs swing 40V (maximum) between
+35V (maximum) and -15V (minimum) and can swiftly
drive capacitive loads.
LDOO
MAX17117
V
LOGIC
OPAS
OUT
GATE-
SHADING
TIMING
TO VCOM
BACKPLANE
OP
DTS
CONTROL
POS
GHON
V
GHON
The MAX17117 is available in a 32-pin, 5mm x 5mm, thin
QFN package with a maximum thickness of 0.8mm for
thin LCD panels.
ST
CK1
CK3
CK5
STH
CKH1
CKH3
CKH5
Ordering Information
PART
TEMP RANGE
PIN-PACKAGE
MAX17117ETJ+
-40NC to +85NC
32 TQFN-EP*
S1
SYSTEM
S3
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
S5
SCAN DRIVER AND
GATE-SHADING
CONTROL LOGIC
RO
PANEL
Applications
Notebook Computer Displays
CK2
CK4
CK6
CKH2
CKH4
CKH6
Features
S 2.3V to 5.5V IN Supply-Voltage Range
S2
S4
S 1.2MHz Current-Mode Step-Up Regulator
Fast-Transient Response
S6
RE
High-Accuracy Reference (1%)
Integrated 16V, 2A, 200mI MOSFET
High Efficiency (> 85%)
VGLC
VGL
V
VGL
Adjustable Cycle-by-Cycle Current Limit
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
ABSOLUTE MAXIMUM RATINGS
IN, ENA, FB, COMP, SS, DTS, LDOADJ, ST,
GHON and VGL RMS Current Rating..................................0.8A
VGLC, STH, and CKH1–CKH6 RMS Current Rating ...........0.8A
LX, PGND RMS Current Rating............................................1.6A
CK1–CK6, LDOO to AGND...............................-0.3V to +7.5V
PGND to AGND....................................................-0.3V to +0.3V
LX, OPAS to PGND ...............................................-0.3V to +18V
GHON to PGND ....................................................-0.3V to +45V
VGL to PGND ....................................................... -20V to +0.3V
GHON to VGL.................................................................... +45V
STH, CKH1–CKH6, VGLC, RO,
Continuous Power Dissipation (T = +70NC)
A
32-Pin TQFN (derate 24.9mW/NC above +70NC).......1990mW
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -65NC to +160NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
RE to VGL .........................................-0.3V to (V
OUT, POS to PGND ..............................-0.3V to (V
+ 0.3V)
+ 0.3V)
GHON
OPAS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +3V, Circuit of Figure 1, V
= +8.5V, V
= +24V, V
= -6.2V, V = V _ = 0V, T = 0NC to +85NC, unless otherwise
IN
OPAS
GHON
VGL
ST
CK
A
noted. Typical values are at T = +25NC.)
A
PARAMETER
IN Input Voltage Range
IN Undervoltage-Lockout
CONDITIONS
MIN
TYP
MAX
UNITS
2.3
5.5
V
V
IN
rising, typical hysteresis = 150mV
1.80
2.00
2.20
V
Threshold
V
V
V
V
V
= 1.3V, LX not switching
= 1.2V, LX switching
1.0
2.5
0.7
100
20
2.5
5
FB
IN Quiescent Current
mA
FB
IN Standby Current
= V
= V
= V
= 0V, V = 5.5V, V
= 4V
2
mA
FA
FA
NC
ENA
ENA
ENA
VGL
VGL
VGL
IN
GHON
GHON
GHON
GHON Standby Current
OPAS Standby Current
Thermal Shutdown
= 0V, V = 5.5V, V
= 4V
= 4V
200
50
IN
= 0V, V = 5.5V, V
IN
Temperature rising
145
170
STEP-UP REGULATOR
Output Voltage Range
OPAS Overvoltage Threshold
Operating Frequency
Oscillator Maximum Duty Cycle
FB Regulation Voltage
FB Fault-Trip Level
V
15
18
V
V
IN
OPAS rising
16.5
1000
91
17
1200
94
1400
97
kHz
%
No load
1.227
1.05
1.240
1.10
160
-0.2
0.1
1.252
1.15
V
Falling edge
V
Fault-Trigger Delay
ms
%
FB Load Regulation
0 < I
< full load
LOAD
FB Line Regulation
V
V
= 2.5V to 5.5V, T = +25NC
0.25
200
280
2.4
500
20
%/V
nA
FS
A
IN
A
FB Input-Bias Current
FB Transconductance
LX Current Limit
= 1.24V, T = +25NC
65
FB
A
DI
= Q2.5FA, FB = COMP
75
160
2
COMP
1.6
R
ENA
= 10kW, duty cycle = 60%
LX On-Resistance
I
LX
= 1A
200
10
mI
FA
V/A
FA
LX Input-Bias Current
Current-Sense Transresistance
Soft-Start Pullup Current
V = 13.5V, T = +25NC
LX A
0.10
2
0.20
4
0.30
6
2
______________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
ELECTRICAL CHARACTERISTICS (continued)
(V = +3V, Circuit of Figure 1, V
= +8.5V, V
= +24V, V
= -6.2V, V = V _ = 0V, T = 0NC to +85NC, unless otherwise
IN
OPAS
GHON
VGL
ST
CK
A
noted. Typical values are at T = +25NC.)
A
PARAMETER
VCOM BUFFER
CONDITIONS
MIN
5
TYP
MAX
UNITS
OPAS Voltage Range
15
V
OPAS Supply Current
V
= V
/2, no load
0.8
1.2
mA
POS
OUT
OUT
OPAS
V
V
OPAS
- 100
OPAS
- 50
OUT Voltage Swing High
OUT Voltage Swing Low
OUT Short-Circuit Current
I
I
= 5mA
= 5mA
mV
mV
mA
50
100
Sourcing, short to V
/2 - 1V
OPAS
100
100
-50
-15
200
200
Sinking, short to V
/2 + 1V
OPAS
POS Input-Bias Current
POS Input-Offset Voltage
Gain-Bandwidth Product
-3dB Bandwidth
V
V
= V
= V
/2, T = +25NC
+50
+15
nA
mV
POS
OUT
OPAS
A
/2
OPAS
8
MHz
MHz
R
= 10kI, C
= 10pF
16
LOAD
LOAD
5V pulse applied to POS, OUT measured from 10% to
90%
Slew Rate
10
40
V/Fs
HIGH-VOLTAGE SCAN DRIVER
GHON Voltage Range
12
35
-3
V
V
VGL Voltage Range
-15
GHON-to-VGL Voltage Range
GHON Supply Current
VGL Supply Current
V
- V
40
V
GHON
VGL
CK1 through CK6 and ST low
CK1 through CK6 and ST low
350
550
FA
FA
I
-500
100
-300
Output Impedance Low
Output Impedance High
STH, CKH_, VGLC, I
STH, CKH_, VGLC, I
= -20mA
= +20mA
80
80
OUT
OUT
I
CKH1, CKH3, CKH5, I = 10mA
100
100
RE
Gate-Shading Switch Resistance
RO, RE Resistance Range
I
I
CKH2, CKH4, CKH6, I
= 10mA
RO
Propagation Delay from ST
Rising Edge to STH Rising Edge
C
C
= 100pF, R
= 100pF, R
= 0I
= 0I
100
100
200
200
ns
LOAD
LOAD
Propagation Delay from ST
Falling Edge to STH Falling Edge
ns
ns
LOAD
LOAD
Propagation Delay from CK_
Rising Edge to CKH_ Rising
Edge
C
LOAD
= 100pF, R
= 100pF, R
= 0I
= 0I
100
100
200
200
LOAD
Propagation Delay from CK_
Falling Edge to CKH_ Falling
Edge
C
C
ns
LOAD
LOAD
= 5nF, R
= 0I; V
= 30V,
LOAD
LOAD
GHON
STH, VGLC, CKH_ Rise Time
STH, VGLC, CKH_ Fall Time
0.5
0.5
1
1
Fs
Fs
V
VGL
= -10V; measured from 10% to 90%
C
LOAD
= 5nF, R
= 0I; V
= 30V,
LOAD
GHON
V
VGL
= -10V; measured from 10% to 90%
STH, CKH_ Operating Frequency
Range
C
LOAD
= 5nF, R
= 0I
100
kHz
LOAD
_______________________________________________________________________________________
3
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
ELECTRICAL CHARACTERISTICS (continued)
(V = +3V, Circuit of Figure 1, V
= +8.5V, V
= +24V, V
= -6.2V, V = V _ = 0V, T = 0NC to +85NC, unless otherwise
IN
OPAS
GHON
VGL
ST
CK
A
noted. Typical values are at T = +25NC.)
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
GATE-SHADING TIMING CONTROL
Gate-Shading Detection
Threshold
DTS falling
100
150
mV
Gate-Shading Detection Current
DTS Switch Resistance
DTS Rising Edge Threshold
DTS Falling Edge Threshold
LDO
V
V
= 0.5V
5
10
10
15
50
µA
I
DTS
DTS
= 1.3V, I
= 1mA
DTS
1.215
1.240
100
1.265
150
V
mV
LDOO Output Voltage Range
Dropout Voltage
1.8
V
V
mV
%/V
%/V
A
IN
V
V
V
V
= 3.3V, V
= 1.1V, I = 350mA
LDOO
300
0.1
500
0.3
IN
LDOADJ
LDOO Line Regulation
LDOO Load Regulation
LDOO Current Limit
= 2.8V to 5.5V, V
= 2.5V, I
= 100mA
IN
LDOO
LDOO
= 2.5V, I
= 1mA to 300mA
0.2
0.5
LDOO
LDOADJ
LDOO
= 1.0V
= 1.3V, T = +25NC
0.4
0.62
1.240
100
0.8
LDOADJ Feedback Voltage
LDOADJ Input-Bias Current
DIGITAL INPUTS
1.227
1.252
200
V
V
nA
LDOADJ
A
0.7 x
ST, CK_ Input High Level
ST, CK_ Input Low Level
1.8V < V
1.8V < V
1.8V < V
< 5.5V
< 5.5V
< 3.0V
V
V
LDOO
LDOO
LDOO
V
LDOO
0.3 x
V
LDOO
0.7 x
V
V
V
V
ENA Input Logic-High Level
LDOO
V
> 3.0V
2.1
LDOO
0.3 x
1.8V < V
< 3.0V
LDOO
V
ENA Input Logic-Low Level
ENA Resistor Range
LDOO
0.8
V
> 3.0V
V
LDOO
0
200
kI
ELECTRICAL CHARACTERISTICS
(V = +3V, Circuit of Figure 1, V
IN
= +8.5V, V
= +24V, V
= -6.2V, V = V
= 0V, T = -40NC to +85NC, unless oth-
CK_ A
OPAS
GHON
VGL
ST
erwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
IN Input Voltage Range
2.3
5.5
V
IN Undervoltage-Lockout
Threshold
V
IN
rising, typical hysteresis = 150mV
1.80
2.20
V
V
V
V
V
V
= 1.3V, LX not switching
= 1.2V, LX switching
2.5
5
FB
IN Quiescent Current
mA
FB
IN Standby Current
GHON Standby Current
OPAS Standby Current
Thermal Shutdown
= V
= V
= V
= 0V, V = 5.5V, V
= 4V
= 4V
= 4V
2
mA
FA
FA
NC
ENA
ENA
ENA
VGL
VGL
VGL
IN
GHON
GHON
GHON
= 0V, V = 5.5V, V
160
50
IN
= 0V, V = 5.5V, V
IN
Temperature rising
145
4
______________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
ELECTRICAL CHARACTERISTICS (continued)
(V = +3V, Circuit of Figure 1, V
IN
= +8.5V, V
= +24V, V
= -6.2V, V = V
= 0V, T = -40NC to +85NC, unless oth-
CK_ A
OPAS
GHON
VGL
ST
erwise noted.)
PARAMETER
STEP-UP REGULATOR
Output Voltage Range
OPAS Overvoltage Threshold
Operating Frequency
Oscillator Maximum Duty Cycle
FB Regulation Voltage
FB Fault-Trip Level
CONDITIONS
MIN
TYP
MAX
UNITS
V
IN
15
18
V
V
OPAS rising
16.5
1000
91
1400
97
kHz
%
No load
1.227
1.05
1.252
1.15
0.3
V
Falling edge
V
FB Line Regulation
V
V
= 2.5V to 5.5V, T = +25NC
%/V
nA
FS
A
IN
A
FB Input-Bias Current
FB Transconductance
LX Current Limit
= 1.3V, T = +25NC
200
280
2.4
FB
A
DI
= Q2.5FA, FB = COMP
75
COMP
V
FB
= 1.2V, duty cycle = 60%
1.6
LX On-Resistance
I
= 1A
500
20
mI
FA
V/A
FA
LX
LX Input-Bias Current
Current-Sense Transresistance
Soft-Start Pullup Current
VCOM BUFFER
V
= 13.5V, T = +25NC
LX A
0.10
2
0.30
6
OPAS Voltage Range
OPAS Supply Current
5
15
V
V
= V
/2, no load
1.2
mA
POS
OUT
OUT
OPAS
V
OPAS
- 100
OUT Voltage Swing High
OUT Voltage Swing Low
OUT Short-Circuit Current
I
I
= 5mA
mV
mV
mA
= 5mA
100
Sourcing, short to V
/2 - 1V
OPAS
100
100
-50
-15
Sinking, short to V
/2 + 1V
OPAS
POS Input-Bias Current
POS Input-Offset Voltage
V
V
= V
= V
/2, T = +25NC
+50
+15
nA
POS
OUT
OPAS
A
/2
OPAS
mV
5V pulse applied to POS, OUT measured from 10% to
90%
Slew Rate
10
V/Fs
HIGH-VOLTAGE SCAN DRIVER
GHON Voltage Range
12
35
-3
V
V
VGL Voltage Range
-15
GHON-to-VGL Voltage Range
GHON Supply Current
VGL Supply Current
V
- V
40
V
GHON
VGL
CK1 through CK6 and ST low
CK1 through CK6 and ST low
550
FA
FA
I
-500
100
Output Impedance Low
Output Impedance High
STH, CKH_, VGLC, I
STH, CKH_, VGLC, I
= -20mA
= +20mA
80
80
OUT
OUT
I
CKH1, CKH3, CKH5, I = 10mA
100
100
RE
Gate-Shading Switch Resistance
RO, RE Resistance Range
I
I
CKH2, CKH4, CKH6, I
= 10mA
RO
Propagation Delay from ST
Rising Edge to STH Rising Edge
C
LOAD
= 100pF, R
= 0I
200
ns
LOAD
_______________________________________________________________________________________
5
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
ELECTRICAL CHARACTERISTICS (continued)
(V = +3V, Circuit of Figure 1, V
IN
= +8.5V, V
= +24V, V
= -6.2V, V = V
= 0V, T = -40NC to +85NC, unless oth-
CK_ A
OPAS
GHON
VGL
ST
erwise noted.)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Propagation Delay from ST
Falling Edge to STH Falling Edge
C
C
= 100pF, R
= 100pF, R
= 0I
= 0I
200
ns
LOAD
LOAD
Propagation Delay from CK_
Rising Edge to CKH_ Rising Edge
200
200
ns
ns
LOAD
LOAD
Propagation Delay from CK_
Falling Edge to CKH_ Falling
Edge
C
C
= 100pF, R
= 0I
LOAD
LOAD
= 5nF, R
= 0I; V
= 30V,
LOAD
LOAD
GHON
STH, VGLC, CKH_ Rise Time
STH, VGLC, CKH_ Fall Time
1
1
Fs
Fs
V
VGL
= -10V; measured from 10% to 90%
C
LOAD
= 5nF, R
= 0I; V
= 30V,
LOAD
GHON
V
VGL
= -10V; measured from 10% to 90%
STH, CKH_ Operating Frequency
Range
C
LOAD
= 5nF, R
= 0I
100
kHz
LOAD
GATE-SHADING TIMING CONTROL
Gate-Shutdown Detection
Threshold
DTS falling
100
10
150
mV
Gate-Shutdown Detection Current V
= 0.5V
5
15
50
µA
I
DTS
DTS
DTS Switch Resistance
DTS Rising Edge Threshold
DTS Falling Edge Threshold
LDO
V
= 1.3V, I
= 1mA
DTS
1.210
1.265
150
V
mV
LDOO Output Voltage Range
Dropout Voltage
1.8
V
V
IN
V
V
V
V
= 3.3V, V
= 1.1V, I = 350mA
LDOO
500
0.3
mV
IN
LDOADJ
LDOO Line Regulation
LDOO Load Regulation
LDOO Current Limit
= 2.8V to 5.5V, V
= 2.5V, I
= 100mA
IN
LDOO
LDOO
%/V
%/V
A
= 2.5V, I
= 1mA to 300mA
0.5
LDOO
LDOADJ
LDOO
= 1.0V
= 1.3V, T = +25NC
0.4
0.8
LDOADJ Feedback Voltage
LDOADJ Input-Bias Current
DIGITAL INPUTS
1.227
1.252
200
V
V
nA
LDOADJ
A
0.7 x
ST, CK_ Input High Level
ST, CK_ Input Low Level
1.8V < V
1.8V < V
1.8V < V
< 5.5V
< 5.5V
< 3.0V
V
V
LDOO
LDOO
LDOO
V
LDOO
0.3 x
V
LDOO
0.7 x
V
ENA Input Logic-High Level
LDOO
V
V
> 3.0V
2.1
LDOO
0.3 x
1.8V < V
< 3.0V
LDOO
V
ENA Input Logic-Low Level
ENA Resistor Range
LDOO
0.8
V
V
> 3.0V
LDOO
0
200
kI
6
______________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
STEP-UP REGULATOR EFFICIENCY
STEP-UP REGULATOR LINE REGULATION
vs. INPUT VOLTAGE
STEP-UP REGULATOR OUTPUT LOAD
REGULATION vs. LOAD CURRENT
vs. LOAD CURRENT
100
0.25
0.20
0.15
0.10
0.05
0
0.10
0
V
= 5.0V
IN
V
= 5.0V
IN
90
80
70
60
50
40
I
= 200mA
MAIN
-0.10
-0.20
-0.30
-0.40
-0.50
V
= 2.3V
IN
V
IN
= 2.3V
V
= 3.0V
= 8.5V
IN
I
= 0mA
MAIN
V
IN
= 3.0V
100
V
MAIN
1
10
100
1000
2.3 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5
IN VOLTAGE (V)
1
10
1000
LOAD CURRENT (mA)
LOAD CURRENT (mA)
STEP-UP CONVERTER PEAK INDUCTOR
STEP-UP REGULATOR LOAD-TRANSIENT
CURRENT LIMIT vs. R
RESPONSE (20mA TO 300mA)
ENA
MAX17117 toc05
3.0
2.5
2.0
1.5
1.0
0.5
V
LX
0V
10V/div
INDUCTOR
CURRENT
1A/div
0A
0V
V
MAIN
(AC-COUPLED)
200mV/div
V
V
V
= 3.3V
IN
= 8.5V
MAIN
I
MAIN
= 2.5V
LDO
200mA/div
L1 = 10µH
L1 = 10µH
R
C
20mA
= 56.2kI
= 1000pF
COMP
COMP
0
50
100
150
(kI)
200
250
100µs/div
R
ENA
STEP-UP REGULATOR PULSED
LOAD-TRANSIENT RESPONSE (20mA TO 1A)
LDO OUTPUT LOAD REGULATION
vs. LOAD CURRENT
MAX17117 toc06
0.10
0
V
IN
= 5.0V
V
LX
0V
10V/div
INDUCTOR
CURRENT
500mA/div
-0.10
-0.20
-0.30
-0.40
-0.50
V
= 3.0V
IN
0A
0V
V
MAIN
(AC-COUPLED)
100mV/div
I
MAIN
1A/div
20mA
L1 = 10µH
R
= 56.2kI
COMP
10µs/div
1
10
100
1000
C
= 1000pF
COMP
LOAD CURRENT (mA)
_______________________________________________________________________________________
7
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
Typical Operating Characteristics (continued)
(T = +25°C, unless otherwise noted.)
A
POWER-UP SEQUENCE
LDO LINE REGULATION
vs. INPUT VOLTAGE
(CK1 AND ST CONNECTED TO V
)
LDO
MAX17117 toc09
V
0.15
0.12
0.09
0.06
0.03
0
IN
5V/div
V
LDO
0V
0V
5V/div
V
MAIN
10V/div
V
GHON
0V
20V/div
I
= 250mA
LDO
0V
0V
V
VGL
10V/div
V
STH
50V/div
0V
V
CKH1
50V/div
I
= 100mA
LDO
0V
0V
V
VGLC
20V/div
2.7 3.0 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4
IN VOLTAGE (V)
40ms/div
OPERATIONAL AMPLIFIER
OPERATIONAL AMPLIFIER
LOAD-TRANSIENT RESPONSE
LARGE-SIGNAL STEP RESPONSE
MAX17117 toc10
MAX17117 toc11
V
VCOM
(AC-COUPLED)
1V/div
V
POS
2V/div
0mV
0mA
0V
0V
V
VCOM
2V/div
I
VCOM
100mA/div
2µs/div
200ns/div
OPERATIONAL AMPLIFIER
CKH_ OUTPUT WAVEFORMS WITH LOGIC
SMALL-SIGNAL STEP RESPONSE
INPUT AND GATE-SHADING CONTROL
MAX17117 toc12
MAX17117 toc13
V
CK1
5V/div
0V
0V
0V
V
CK2
5V/div
V
POS
0mV
0mV
(AC-COUPLED)
100mV/div
V
DTS
2V/div
V
CKH1
20V/div
V
VCOM
0V
0V
(AC-COUPLED)
100mV/div
V
CKH2
20V/div
200ns/div
4µs/div
8
______________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
Pin Configuration
TOP VIEW
24 23 22 21 20 19 18 17
16
15
PGND 25
LX 26
STH
CKH1
14 CKH2
27
28
29
30
31
32
ENA
IN
CKH3
CKH4
13
12
MAX17117
LDOO
LDOADJ
DTS
11 CKH5
EP
10
9
CKH6
VGLC
+
SS
1
2
3
4
5
6
7
8
THIN QFN
Pin Description
PIN
NAME
FUNCTION
CK5–CK1,
CK6
1–5, 7
Level-Shifter Logic-Level Inputs
Start-Pulse, Level-Shifter Logic-Level Input
6
8
ST
RE
Gate-Shading Discharge for CKH2, CKH4, and CKH6
VGL Voltage Output
9
VGLC
10–15
16
CKH6–CKH1 Level-Shifter Outputs
STH
Start-Pulse Level-Shifter Output
Gate-Off Supply. VGL is the negative supply voltage for the STH, CKH1–CKH6, and VGLC high-volt-
age driver outputs. Bypass to PGND with a minimum of 0.1FF ceramic capacitor.
17
18
VGL
Gate-On Supply. GHON is the positive supply voltage for the STH, CKH1–CKH6, and VGLC high-
voltage scan-driver outputs. Bypass to PGND with a minimum of 0.1FF ceramic capacitor.
GHON
19
20
21
RO
Gate-Shading Discharge for CKH1, CKH3, and CKH5
Operational Amplifier Output
OUT
POS
Operational Amplifier Noninverting Input
Operational Amplifier Supply Input. Connect to V
greater ceramic capacitor.
(Figure 1) and bypass to AGND with a 0.1FF or
MAIN
22
23
24
OPAS
COMP
FB
Compensation for Error Amplifier. Connect a series RC from this pin to AGND. Typical values are
56kI and 1000pF.
Step-Up Regulator Feedback. Reference voltage is 1.24V nominal. Connect the midpoint of an exter-
nal resistor-divider to FB and minimize trace area. Set V
according to V
= 1.24V (1 + R1/R2).
MAIN
MAIN
_______________________________________________________________________________________
9
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
Pin Description (continued)
PIN
25
NAME
PGND
LX
FUNCTION
Power Ground. Source connection of the internal step-up regulator power switch.
Switching Node. Connect inductor/catch diode here and minimize trace area for lowest EMI.
26
Chip-Enable Control and OCP Set Input. When ENA = low, the step-up converter and op amp are
disabled, the LDO remains active, and the level-shifter outputs are high impedance.
27
28
ENA
IN
Step-Up Regulator and Low-Dropout Regulator Supply. Bypass IN to AGND with a 1FF or greater
ceramic capacitor.
29
30
31
32
LDOO
LDOADJ
DTS
Internal Linear Regulator Output. Bypass LDOO to AGND with a 1FF capacitor.
Linear Regulator Feedback Input. Reference voltage is 1.24V nominal.
Gate-Shading Discharge Time Adjust
SS
Step-Up Regulator Soft-Start Control
Exposed Backside Pad. Connect to the analog ground plane for proper electrical and thermal
performance.
—
EP
10 _____________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
D3
0.1µF
V
GHON
23V, 25mA
0.22µF
D2
86.6I
D4
0.1µF
0.1µF
V
VGL
-6.0V, 10mA
6.2V,
200mW
2.2µF
D5
0.22µF
L1
10µH
D1
V
MAIN
V
IN
8.5V, 200mA
C3
10µF
C2
1µF
IN
C4
10µF
C5
10µF
C6
10µF
LX
R
ENA
62kI
ENA
PGND
R
1
102kI
R5
51.1kI
FB
LDOADJ
R
COMP
56.2kI
COMP
R6
49.9kI
R2
17.4kI
C
COMP
SS
1000pF
LDOO
C
SS
V
LOGIC
AGND
(EP)
0.33µF
C1
R
SET
1µF
29.4kI
DTS
OPAS
MAX17117
C
SET
0.1µF
100pF
OUT
POS
TO VCOM
BACKPLANE
R3
56.2k
GHON
V
GHON
I
0.1µF
R4
56.2kI
STH
ST
CK1
CK3
CK5
CKH1
CKH3
CKH5
R
0
1kI
RO
SYSTEM
PANEL
CK2
CK4
CK6
VGL
CKH2
CKH4
CKH6
RE
R
1kI
E
V
VGL
0.1µF
VGLC
Figure 1. Typical Application Circuit
______________________________________________________________________________________ 11
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
Table 1. Component List
Typical Application Circuit
DESIGNATION
DESCRIPTION
The MAX17117 typical application circuit (Figure 1) gen-
erates a +8.5V source-driver supply and approximately
+23V and -6V gate-driver supplies for TFT displays. The
input voltage range for the IC is from +2.3V to +5.5V,
but the circuit in Figure 1 is designed to run from 2.5V to
3.6V. Table 1 lists the recommended components and
Table 2 lists the component suppliers.
1FF ±10%, 16V X5R ceramic capacitors
(0603)
Murata GRM188R61C105K
TDK C1608X5R1C105K
C1, C2
10FF Q10%, 10V X5R ceramic capacitor
(0805)
C3
C4, C5, C6
D1
TDK C2012X5R1A106K
Murata GRM21BR61A106K
Detailed Description
The MAX17117 includes a high-performance step-up
regulator, a 350mA low-dropout (LDO) linear regulator,
a high-speed operational amplifier, and a high-voltage,
level-shifting scan driver with gate-shading control.
Figure 2 shows the functional diagram.
10FF Q10%, 16V X5R ceramic capaci-
tors (1206)
Murata GRM31CR61C106K
TDK C3216X5R1C106K
Step-Up Regulator
The step-up regulator employs a peak current-mode
control architecture with a fixed 1.2MHz switching fre-
quency that maximizes loop bandwidth and provides
a fast-transient response to pulsed loads found in
source drivers of TFT LCD panels. The high switching
frequency allows the use of low-profile inductors and
ceramic capacitors to minimize the thickness of LCD
panel designs. The integrated high-efficiency MOSFET
reduces the number of external components required.
1A, 30V Schottky diode (S-Flat)
Central CMMSH1-40 LEAD FREE
Nihon EP10QY03
Toshiba CRS02 (TE85L, Q, M)
200mA, 100V dual diodes (SOT23)
Fairchild MMBD4148SE (Top Mark: D4)
Central CMPD7000+ (Top Mark: C5C)
D2, D3, D4
6.2V, 200mW zener diode (SOD-323)
ROHM UDZSTE-176.2B
Fairchild MM3Z6V2B
D5
L1
The output voltage can be set from V to 15V with an
IN
external resistive voltage-divider.
10FH, 1.85A, 74.4mI inductor (6mm x
6mm x 3mm)
Sumida CDRH5D28RHPNP-100M
Table 2. Component Suppliers
SUPPLIER
Central Semiconductor Corp.
Fairchild Semiconductor
WEBSITE
www.centralsemi.com
www.fairchildsemi.com
www.murata-northamerica.com
www.niec.co.jp
Murata Electronics North America, Inc.
Nihon Inter Electronics Corp.
ROHM Co., Ltd.
www.rohm.com
Sumida Corp.
www.sumida.com
TDK Corp.
www.component.tdk.com
www.toshiba.com/taec
Toshiba America Electronic Components, Inc.
12 _____________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
V
GHON
V
VGL
V
MAIN
V
IN
IN
LX
PGND
ENA
FB
SET-UP
CONTROLLER
COMP
SS
LDOADJ
AGND
(EP)
LINEAR
REGULATOR
LDOO
MAX17117
V
LOGIC
OPAS
OUT
GATE-
SHADING
TIMING
TO VCOM
BACKPLANE
OP
DTS
CONTROL
S
DTS
POS
GHON
V
GHON
ST
CK1
CK3
CK5
STH
CKH1
CKH3
CKH5
S1
SYSTEM
S3
S5
SCAN DRIVER
AND GATE-
SHADING
RO
PANEL
CONTROL LOGIC
CK2
CK4
CK6
CKH2
CKH4
CKH6
S2
S4
S6
RE
VGLC
VGL
V
VGL
Figure 2. Functional Diagram
______________________________________________________________________________________ 13
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
The regulator controls the output voltage and the power
delivered to the output by modulating the duty cycle (D)
of the internal power MOSFET in each switching cycle.
The duty cycle of the MOSFET is approximated by:
its magnetic field. Once the sum of the current-feedback
signal and the slope compensation exceed the COMP
voltage, the controller resets the flip-flop and turns off
the MOSFET. Since the inductor current is continuous,
a transverse potential develops across the inductor that
turns on the diode (D1). The voltage across the inductor
then becomes the difference between the output voltage
and the input voltage. This discharge condition forces
the current through the inductor to ramp back down,
transferring the energy stored in the magnetic field to the
output capacitor and the load. The MOSFET remains off
for the rest of the clock cycle.
V
− V
IN
MAIN
V
D ≈
MAIN
Figure 3 shows the step-up regulator block diagram.
An error amplifier compares the signal at FB to 1.24V
and changes the COMP output. The voltage at COMP
determines the current trip point each time the internal
MOSFET turns on. As the load varies, the error amplifier
sources or sinks current to the COMP output accord-
ingly to produce the inductor peak current necessary to
service the load. To maintain stability at high duty cycles,
a slope compensation signal is summed with the current-
sense signal.
Undervoltage Lockout (UVLO)
The UVLO circuit compares the input voltage at IN with
the UVLO threshold (2.0V typ) to ensure that the input
voltage is high enough for reliable operation. The 150mV
(typ) hysteresis prevents supply transients from caus-
ing a restart. Once the input voltage exceeds the UVLO
rising threshold, startup begins. When the input voltage
falls below the UVLO falling threshold, the controller
turns off the main step-up regulator.
On the rising edge of the internal clock, the controller sets
a flip-flop, turning on the n-channel MOSFET and apply-
ing the input voltage across the inductor. The current
through the inductor ramps up linearly, storing energy in
LX
CLOCK
LOGIC AND
DRIVER
PGND
ILIM
COMPARATOR
I
LIMIT
SLOPE COMP
PWM
COMPARATOR
1.2MHz
OSCILLATOR
CURRENT
SENSE
FB
TO FAULT LOGIC
ERROR AMP
1.10V
FAULT
COMPARATOR
1.24V
COMP
Figure 3. Step-Up Regulator Block Diagram
14 _____________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
Overvoltage Protection
The MAX17117 monitors OPAS for an overvoltage con-
dition. If the OPAS voltage is above 17V (typ), the
MAX17117 disables the gate driver of the step-up regula-
tor and prevents the internal MOSFET from switching. The
OPAS overvoltage condition does not set the fault latch.
Short-Circuit Current Limit
The operational amplifier limits short-circuit current to
approximately Q200mA (typ) if the output is directly
shorted to OPAS or to AGND. If the short-circuit condi-
tion persists, the junction temperature of the IC rises until
it reaches the thermal-shutdown threshold (+170NC typ).
Once the junction temperature reaches the thermal-shut-
down threshold, an internal thermal sensor immediately
shuts down all outputs until the input voltage is cycled
off, then on again.
Overcurrent Protection
The step-up regulator features an adjustable cycle-
by-cycle current limit. The inductor current is sensed
through the LX switch during the LX switch on-time. If
the peak inductor current rises above the current-limit
Driving Pure Capacitive Loads
The operational amplifier is typically used to drive the
LCD backplane (VOUT) or the gamma-correction-divider
string. The LCD backplane consists of a distributed
series capacitance and resistance, a load that can be
easily driven by the operational amplifier. However, if the
operational amplifier is used in an application with a pure
capacitive load, steps must be taken to ensure stable
operation. As the operational amplifier’s capacitive load
increases, the amplifier’s bandwidth decreases and gain
peaking increases. A 5I to 50I small resistor placed
between VOUT and the capacitive load reduces peak-
ing, but also reduces the gain. An alternative method
of reducing peaking is to place a series RC network
(snubber) in parallel with the capacitive load. The RC
network does not continuously load the output or reduce
the gain. Typical values of the resistor are between 100I
and 200Iand the typical value of the capacitor is 10pF.
threshold set by R , the LX switch immediately turns
ENA
off until the next switching cycle, effectively limiting the
peak-inductor current each cycle.
Soft-Start
The soft-start feature effectively limits the inrush current
at startup by slowly raising the regulation voltage of the
step-up converter’s feedback pin (V ) at a rate deter-
FB
mined by the selection of the soft-start capacitor (C ).
SS
At startup, once ENA is pulled high through R
, an
ENA
internal 4FA (typ) current source begins to charge the
soft-start capacitor (C ), slowly bringing up the volt-
SS
age at the soft-start pin (V ). V follows V for V <
SS
FB
SS
SS
1.24V. Once V exceeds 1.24V, V remains at 1.24V,
SS
FB
allowing V
to reach its full regulation voltage.
MAIN
Fault Protection
During steady-state operation, the MAX17117 monitors
the FB voltage. If the FB voltage falls below 1.1V (typ),
the MAX17117 activates an internal fault timer. If there is
a continuous fault more than 160ms (typ), the MAX17117
sets the fault latch, turning off all outputs except LDOO.
Once the fault condition is removed, cycle the input volt-
age to clear the fault latch and reactivate the device. The
fault-detection circuit is disabled during the soft-start time.
High-Voltage Scan Driver
The high-voltage, level-shifting scan driver with gate-
shading control is designed to drive the TFT panel
gate drivers. Its seven outputs swing 40V (maximum)
between +35V (maximum) and -15V (minimum) and can
swiftly drive capacitive loads. The driver outputs (STH,
CKH_) swing between their power-supply rails (GHON
and VGL), according to the input logic levels on their
corresponding inputs (ST, CK_) except during a gate-
shading period. During a gate-shading period, a CKH_
output driver becomes high impedance and an internal
switch connected between the CKH_ output’s capaci-
tive load and either RO or RE closes (S1–S6) whenever
the state of its corresponding CK_ input is logic-low.
This allows part of an output’s GHON-to-VGL transition
to be completed by partially discharging its capacitive
load through an external resistor attached to either RO
or RE for a duration set by the gate-shading period. See
Figure 4.
Operational Amplifier
The MAX17117 has an operational amplifier that is
typically used to drive the LCD backplane (VCOM) or
the gamma-correction-divider string. The operational
amplifier features Q200mA (typ) output short-circuit cur-
rent, 40V/Fs (typ) slew rate, and 16MHz (typ) bandwidth.
While the op amp is a rail-to-rail input and output design,
its accuracy is significantly degraded for input voltages
within 1V of its supply rails (OPAS and AGND).
______________________________________________________________________________________ 15
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
If the gate-shading control is enabled, a gate-shading
period is initiated by a falling edge of a CK_ input when-
the states of the CKH_ outputs are always determined by
their corresponding CK_ input logic states. See Figure 5.
ever V
is less than 100mV. Once the gate-shading
DTS
Low-Dropout Linear Regulator (LDO)
The MAX17117 has an integrated 0.8I pass element
and can provide at least 350mA. The output voltage is
accurate within Q1%.
period is initiated, a switch across C
allowing C
reaches 1.24V, S
gate-shading period is terminated, and the CKH_ output
states are directly determined by their corresponding
CK_ input logic states again. Once a gate-shading
period is initiated, V
sequently discharge back below 100mV, before the next
CK_ falling can activate a new gate-shading period.
(S
) opens,
. Once V
SET DTS
SET DTS
to be charged through R
SET
closes to discharge C , the
SET
DTS
Thermal-Overload Protection
When the junction temperature exceeds T = +170NC
J
must charge to 1.24V and sub-
DTS
(typ), a thermal sensor activates a fault-protection latch,
which shuts down all outputs, allowing the IC to cool
down. All outputs remain off until the IC cools and the
input voltage is cycled below, then back above the IN
UVLO threshold.
By configuring R
gate-shading period time duration is determined by R
and C
as shown in Figure 1, the
SET
SET
SET
and C
and V
(see the Setting the Gate-Shading
SET
LDOO
The thermal-overload protection protects the IC in the
event of fault conditions. For continuous operation, do
not exceed the absolute maximum junction temperature
Period Time Duration section). The gate-shading control
can be disabled by removing R
. If R
is removed,
SET
SET
rating of T = +150NC.
J
CKH1
CK1
CK2
CK3
CK4
CK5
CK6
CKH3
CKH5
S1
S3
S5
R
O
LEVEL SHIFTER
AND
GATE-SHADING
LOGIC
RO
MAX17117
CKH2
LDOO
LDO
CKH4
CKH6
R
SET
DTS
C
SET
S2
S
DTS
S4
S6
R
E
RE
Figure 4. Scan-Driver Block Diagram
16 _____________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
CK1
CK2
CK3
CK4
CK5
CK6
DTS
0
0
0
0
0
0
1.24V
0
0
CKH1
CKH2
CKH3
CKH4
0
0
0
0
0
CKH5
CKH6
Figure 5. Scan-Driver Operation with Gate-Shading Control Enabled
______________________________________________________________________________________ 17
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
of the maximum load current of the step-up regulator’s
output plus the contributions from the positive and nega-
tive charge pumps:
Design Procedure
Main Step-Up Regulator
Inductor Selection
The minimum inductance value, peak current rating, and
series resistance are factors to consider when select-
ing the inductor. These factors influence the converter’s
efficiency, maximum output-load capability, transient-
response time, and output-voltage ripple. Physical size
and cost are also important factors to be considered.
I
= I
+ n
×I
+ (n
+1)×I
VP VP
MAIN(EFF) MAIN(MAX)
VN VN
where I
rent, n
is the maximum step-up output cur-
MAIN(MAX)
is the number of negative charge-pump stag-
VN
VP
es, n is the number of positive charge-pump stages,
VN
is the positive charge-pump output current, assuming
the initial pump source for I is V
I
is the negative charge-pump output current, and I
VP
The maximum output current, input voltage, output volt-
age, and switching frequency determine the inductor
value. Very high-inductance values minimize the current
ripple and therefore reduce the peak current, which
decreases core losses in the inductor and I2R losses in
the entire power path. However, large inductor values
also require more energy storage and more turns of wire,
which increase physical size and can increase I2R loss-
es in the inductor. Low-inductance values decrease the
physical size but increase the current ripple and peak
current. Finding the best inductor involves choosing the
best compromise among circuit efficiency, inductor size,
and cost.
.
MAIN
VP
Calculate the approximate inductor value using the
typical input voltage (V ), the maximum output cur-
rent (I
from an appropriate curve in the Typical Operating
Characteristics, the desired switching frequency (f ),
and an estimate of LIR based on the above discussion:
IN
), the expected efficiency (E
) taken
TYP
MAIN(EFF)
OSC
2
V
V
− V
η
TYP
LIR
IN
MAIN
× f
MAIN(EFF) OSC
IN
L =
V
I
MAIN
Choose an available inductor value from an appropriate
inductor family. Calculate the maximum DC input current
at the minimum input voltage V
using conserva-
The equations used here include a constant called LIR,
which is the ratio of the inductor peak-to-peak ripple cur-
rent to the average DC inductor current at the full-load
current. The best trade-off between inductor size and
circuit efficiency for step-up regulators generally has an
LIR between 0.3 and 0.5. However, depending on the
AC characteristics of the inductor core material and ratio
of inductor resistance to other power-path resistances,
the best LIR can shift up or down. If the inductor resis-
tance is relatively high, more ripple can be accepted to
reduce the number of turns required and increase the
wire diameter. If the inductor resistance is relatively low,
increasing inductance to lower the peak current can
decrease losses throughout the power path. If extremely
thin high-resistance inductors are used, as is common
for LCD panel applications, the best LIR can increase to
between 0.5 and 1.0.
IN(MIN)
tion of energy and the expected efficiency at that operat-
ing point (E ) taken from an appropriate curve in the
MIN
Typical Operating Characteristics:
I
× V
MAIN(EFF)
MAIN
I
=
IN(DC,MAX)
V
× η
IN(MIN)
MIN
Calculate the ripple current at that operating point and
the peak current required for the inductor:
V
× V
− V
(
)
IN(MIN)
MAIN IN(MIN)
I
=
RIPPLE
L × V
× f
MAIN OSC
I
RIPPLE
2
I
= I
+
PEAK IN(DC,MAX)
The inductor’s saturation current rating and the
MAX17117 LX current limit should exceed I and the
inductor’s DC current rating should exceed I
For good efficiency, choose an inductor with less than
0.1I series resistance.
PEAK
Once a physical inductor is chosen, higher and lower
values of the inductor should be evaluated for efficiency
improvements in typical operating regions.
.
IN(DC,MAX)
In Figure 1, the LCD’s gate-on and gate-off supply
voltages are generated from two unregulated charge
pumps driven by the step-up regulator’s LX node. The
additional load on LX must therefore be considered in
the inductance and current calculations. The effective
Considering the typical application circuit, the maximum
load current (I ) is 200mA, with an 8.5V output
MAIN(MAX)
and a typical input voltage of 3.3V. The effective full-load
step-up current is:
I = 200mA +1×10mA + (2 +1)×25mA = 285mA
MAIN(EFF)
maximum output current, I
becomes the sum
MAIN(EFF),
18 _____________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
Choosing an LIR of 0.2 and estimating efficiency of 85%
at this operating point:
the output-voltage ripple is typically dominated by
. The voltage rating and temperature charac-
V
RIPPLE(C)
teristics of the output capacitor must also be considered.
2
3.3V
8.5V
8.5V − 3.3V
0.285A ×1.2MHz 0.2
0.85
L =
≈ 9.7µH
Input-Capacitor Selection
The input capacitor (C3) reduces the current peaks
drawn from the input supply and reduces noise injec-
tion into the IC. A 10FF ceramic capacitor is used in the
typical application circuit (Figure 1) because of the high
source impedance seen in typical lab setups. Actual
applications usually have much lower source impedance
since the step-up regulator often runs directly from the
output of another regulated supply.
A 10FH inductor is chosen. Then, using the circuit’s
minimum input voltage (3.0V) and estimating efficiency
of 83% at that operating point:
0.285A × 8.5V
3V × 0.83
I
=
≈ 0.973A
IN(DC,MAX)
The ripple current and the peak current at that input volt-
age are:
Rectifier Diode
The MAX17117 high switching frequency demands a
high-speed rectifier. Schottky diodes are recommended
for most applications because of their fast recovery time
and low forward voltage. In general, a 1A Schottky diode
complements the internal MOSFET well.
3V × 8.5V − 3V
(
)
I
=
≈ 0.162A
RIPPLE
10µH× 8.5V ×1.2MHz
0.162A
I
= 0.973A +
=1.05A
PEAK
2
Output-Voltage Selection
The output voltage of the main step-up regulator is
adjusted by connecting a resistive voltage-divider from
Peak Inductor Current-Limit Setting
between the ENA pin and the LDOO
Connecting R
ENA
output, as shown in Figure 1, allows the inductor peak
current limit to be adjusted up to 2A max by choosing the
the output (V ) to AGND with the center tap con-
MAIN
nected to FB (see Figure 1). Select R2 in the 10kI to
50kI range. Calculate R1 with the following equation:
appropriate R
resistor with the following equation:
ENA
(V
−1.25V)(80000)
LDOO
V
MAIN
R
≈
ENA
R1= R2 ×
−1
I
OCP
V
REF
The above threshold set by R
the step-up converter’s input voltage, output voltage,
varies depending on
ENA
Place R1 and R2 close to the IC such that the connec-
tions between these components and the FB pin are kept
as short as possible.
and duty cycle. Place R
connection between R
as possible.
close to the IC such that the
ENA
and the ENA pin is as short
ENA
Loop Compensation
Choose R
to set the high-frequency integrator gain
COMP
Output Capacitor Selection
for fast-transient response. Choose C
to set the
COMP
The total output-voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the ohmic ripple due
to the capacitor’s equivalent series resistance (ESR):
integrator zero to maintain loop stability.
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
V
= V
+ V
1.45k × V × V
× C
RIPPLE
RIPPLE(C) RIPPLE(ESR)
IN MAIN
OUT
R
≈
COMP
L ×I
MAIN(MAX)
I
V
− V
f
MAIN
MAIN
IN
MAIN OSC
V
≈
RIPPLE(C)
40 × V
×L ×I
C
V
MAIN
MAIN(MAX)
OUT
C
≈
COMP
2
(V ) ×R
and:
IN
COMP
V
≈I
R
RIPPLE(ESR) PEAK ESR(COUT)
To further optimize transient response, vary R
in
COMP
20% steps and C
transient-response waveforms.
in 50% steps while observing
COMP
where I
is the peak inductor current (see the
PEAK
Inductor Selection section). For ceramic capacitors,
______________________________________________________________________________________ 19
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
Gate-Shading Discharge Resistors
For proper operation, choose R and R discharge
Operational Amplifier Output Voltage
Using the buffer configuration as shown in Figure 1, the
output voltage of the operational amplifier is adjusted by
connecting a resistive voltage-divider from the output
O
E
resistors that are greater than 100I. Place R and R
O
E
close to the IC such that the connections between these
components and their respective pins are kept as short
as possible.
(V ) to AGND with the center tap connected to POS
MAIN
(see Figure 1). Select R3 in the 10kI to 100kI range.
Calculate R4 with the following equation:
Applications Information
V
Power Dissipation
An IC’s maximum power dissipation depends on the
thermal resistance from the die to the ambient environ-
ment and the ambient temperature. The thermal resis-
tance depends on the IC package, PCB copper area,
other thermal mass, and airflow.
MAIN
R3 = R4 × 1−
V
OUT
Place R3 and R4 close to the IC such that the connec-
tions between these components and the POS pin are
kept as short as possible.
The MAX17117, with its exposed backside paddle sol-
dered to 1in2 of PCB copper, can dissipate approximate-
ly 1990mW into +70NC still air. More PCB copper, cooler
ambient air, and more airflow increase the possible
dissipation, while less copper or warmer air decreases
the IC’s dissipation capability. The major components of
power dissipation are the power dissipated in the step-
up regulator and the power dissipated by the operational
amplifiers.
LDO Output Voltage
The output voltage of the LDO is adjusted by connect-
ing a resistive voltage-divider from the output (V
)
LDOO
to AGND with the center tap connected to LDOADJ
(see Figure 1). Select R6 in the 10kI to 50kI range.
Calculate R5 with the following equation:
V
LDOO
1.24V
R5 = R6 ×
−1
The MAX17117’s largest on-chip power dissipation
occurs in the step-up switch, the VCOM amplifier, the
CKH_ level shifters, and the LDO.
Place R5 and R6 close to the IC such that the connec-
tions between these components and the LDOADJ pin
are kept as short as possible.
Step-Up Regulator
The largest portions of the power dissipated by the
step-up regulator are the internal MOSFET, the induc-
tor, and the output diode. If the step-up regulator with
3.3V input and 285mA output has approximately 85%
efficiency, approximately 5% of the power is lost in the
internal MOSFET, approximately 3% in the inductor, and
approximately 5% in the output diode. The remaining
few percent are distributed among the input and out-
put capacitors and the PCB traces. If the input power
is approximately 2.85W, the power lost in the internal
MOSFET is approximately 143mW.
Connect a 1FF low ESR capacitor between LDOO and
AGND to ensure stability and to provide good output-
transient performance.
Scan Driver
Setting the Gate-Shading Period Time Duration
To set the gate-shading period time duration, configure
R
and C as shown in Figure 1. Choose a C
SET SET
SET
value greater than 35pF, then calculate the required
value that gives the desired gate-shading period
R
SET
time duration with the following equation:
−t
R
=
Operational Amplifier
The power dissipated in the operational amplifier
depends on the output current, the output voltage, and
the supply voltage:
SET
1.24V
ln 1−
× C
SET
V
LDOO
Increase or decrease C
as needed and repeat the
SET
PD
= I
× V
− V
AVDD VCOM
(
)
above calculation to achieve the desired gate-shading
period time duration, while ensuring C remains great-
SOURCE
PD
VCOM_SOURCE
SET
= I
× V
VCOM
SINK
VCOM_SINK
er than 35pF and R
is within the 8kIto 100kIrange.
SET
Place R
and C
close to the IC such that the con-
SET
SET
where I
_
is the output current sourced by
VCOM SOURCE
nections between these components and the DTS pin
are kept as short as possible.
the operational amplifier, and I
current that the operational amplifier sinks. In a typical
_
is the output
VCOM SINK
20 _____________________________________________________________________________________
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
case where the supply voltage is 8.5V and the output
voltage is 4.25V with an output source current of 30mA,
the power dissipated is 128mW.
ripple and noise spikes. Create an analog ground
plane (AGND) consisting of all the feedback-divider
ground connections; the operational-amplifier-divid-
er ground connection; the OPAS bypass capacitor
ground connection; the COMP, SS, and SET capaci-
tor ground connections; and the device’s exposed
backside pad. Connect the AGND and PGND islands
by connecting the PGND pin directly to the exposed
backside pad. Make no other connections between
these separate ground planes.
LDO
The power dissipated in the LDO depends on the LDO’s
output current, input voltage, and output voltage:
PD
= I
× V − V
(
)
LDO LDOO IN LDOO
Scan-Driver Outputs
The power dissipated by the six CKH_ scan-driver out-
puts depends on the scan frequency, the capacitive load
on each output, and the difference between the GHON
and VGL supply voltages:
• Place the feedback voltage-divider resistors as close
as possible to their respective feedback pins. The
divider’s center trace should be kept short. Placing
the resistors far away causes the feedback trace to
become an antenna that can pick up switching noise.
Care should be taken to avoid running the feedback
trace near LX or the switching nodes in the charge
pumps.
2
PD
= 6 × f
× C
× V
(
− V
)
SCAN
SCAN
PANEL
GHON VGL
If the scan frequency is 50kHz, the load of the six CKH_
outputs is 3.4nF, and the supply voltage difference is
30V, then the power dissipated is 0.92W.
• Place the IN pin bypass capacitor as close as pos-
sible to the device. The ground connections of the
IN bypass capacitor should be connected directly to
AGND at the backside pad of the IC.
PCB Layout and Grounding
Careful PCB layout is important for proper operation. Use
the following guidelines for good PCB layout:
• Minimize the length and maximize the width of the
traces between the output capacitors and the load for
best transient responses.
• Minimize the area of high-current loops by placing the
inductor, output diode, and output capacitors near the
input capacitors and near LX and PGND. The high-
current input loop goes from the positive terminal of
the input capacitor to the inductor, to the IC’s LX pin,
out of PGND, and to the input capacitor’s negative ter-
minal. The high-current output loop is from the positive
terminal of the input capacitor to the inductor, to the
output diode (D1), to the positive terminal of the output
capacitors, reconnecting between the output capaci-
tor and input capacitor ground terminals. Connect
these loop components with short, wide connections.
Avoid using vias in the high-current paths. If vias are
unavoidable, use many vias in parallel to reduce resis-
tance and inductance.
• Minimize the size of the LX node while keeping it wide
and short. Keep the LX node away from the feedback
node and analog ground. Use DC traces as a shield
if necessary.
Refer to the MAX17117 Evaluation Kit for an example of
proper board layout.
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
• Create a power ground island (PGND) consisting of
the input and output capacitor grounds, PGND pin,
and any charge-pump components. Connect all these
together with short, wide traces or a small ground
plane. Maximizing the width of the power ground trac-
es improves efficiency and reduces output-voltage
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
32 TQFN-EP
T3255N+1
21-0140
______________________________________________________________________________________ 21
Internal-Switch Boost Regulator with Integrated
7-Channel Scan Driver, Op Amp, and LDO
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
4/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
22
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
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