MAX1711EEG [MAXIM]
High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs; 高速，数字可调，降压型控制器，用于笔记本电脑
| 型号： | MAX1711EEG |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs |
| 文件： | 总28页 (文件大小：299K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-4781; Rev 0; 11/98
Hig h -S p e e d , Dig it a lly Ad ju s t e d
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0/MAX71
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX1710/MAX1711 s te p -d own c ontrolle rs a re
intended for core CPU DC-DC converters in notebook
computers. They feature a triple-threat combination of
ultra-fast transient response, high DC accuracy, and
hig h e ffic ie nc y ne e de d for le a d ing-e dg e CPU c ore
power supplies. Maxim’s proprietary QUICK-PWM™
quick-response, constant-on-time PWM control scheme
handles wide input/output voltage ratios with ease and
provides 100ns “instant-on” response to load transients
while maintaining a relatively constant switching fre-
quency.
♦ Ultra-High Efficiency
♦ No Current-Sense Resistor (Lossless I
)
LIMIT
♦ QUICK-PWM with 100ns Load-Step Response
♦ ±1% V Accuracy over Line and Load
OUT
♦ 4-Bit On-Board DAC (MAX1710)
♦ 5-Bit On-Board DAC (MAX1711)
♦ 0.925V to 2V Output Adjust Range (MAX1711)
♦ 2V to 28V Battery Input Range
High DC precision is ensured by a 2-wire remote-sens-
ing scheme that compensates for voltage drops in both
ground bus and the supply rail. An on-board, digital-to-
analog converter (DAC) sets the output voltage in com-
pliance with Mobile Pentium II® CPU specifications.
♦ 200/300/400/550kHz Switching Frequency
♦ Remote GND and V
Sensing
OUT
♦ Over/Undervoltage Protection
♦ 1.7ms Digital Soft-Start
The MAX1710 achieves high efficiency at a reduced
cost by eliminating the current-sense resistor found in
traditional current-mode PWMs. Efficiency is further
enhanced by an ability to drive very large synchronous-
rectifier MOSFETs.
♦ Drives Large Synchronous-Rectifier FETs
♦ 2V ±1% Reference Output
♦ Power-Good Indicator
Single-stage buck conversion allows these devices to
directly step down high-voltage batteries for the highest
possible efficiency. Alternatively, 2-stage conversion
(stepping down the +5V system supply instead of the
battery) at a higher switching frequency allows the mini-
mum possible physical size.
♦ Small 24-Pin QSOP Package
Ord e rin g In fo rm a t io n
PART
TEMP. RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
24 QSOP
MAX1710EEG
MAX1711EEG
The MAX1710 and MAX1711 are identical except that
the MAX1711 has a 5-bit DAC rather than a 4-bit DAC.
Also, the MAX1711 has a fixed overvoltage protection
24 QSOP
Min im a l Op e ra t in g Circ u it
threshold at V
= 2.25V and undervoltage protection
OUT
at V
= 0.8V, whereas the MAX1710 has variable
BATTERY
4.5V TO 28V
OUT
thresholds that track V
. The MAX1711 is intended
OUT
+5V INPUT
for a p p lic a tions whe re the DAC c od e ma y c ha ng e
dynamically.
V
CC
OVP*
V
DD
V+
SHDN
FBS
Ap p lic a t io n s
BST
DH
Notebook Computers
Docking Stations
ILIM
GNDS
OUTPUT
0.925V TO 2V
(MAX1711)
MAX1710
MAX1711
CPU Core DC-DC Converters
Single-Stage (BATT to V
Converters
CORE)
REF
CC
LX
DL
Two-Stage (+5V to V
) Converters
CORE
D0
PGND
D1
QUICK-PWM is a trademark of Maxim Integrated Products.
Mobile Pentium II is a registered trademark of Intel Corp.
D/A
D2
INPUTS
FB
D3
SKIP
*MAX1710 ONLY
**MAX1711 ONLY
D4**
Pin Configuration appears at end of data sheet.
GND
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
For small orders, phone 1-800-835-8769.
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ABSOLUTE MAXIMUM RATINGS
V+ to GND..............................................................-0.3V to +30V
, V to GND .....................................................-0.3V to +6V
LX to BST..................................................................-6V to +0.3V
REF Short Circuit to GND...........................................Continuous
V
CC DD
PGND to GND.....................................................................±0.3V
SHDN, PGOOD to GND ...........................................-0.3V to +6V
OVP, ILIM, FB, FBS, CC, REF, D0–D4,
Continuous Power Dissipation (T = +70°C)
A
24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-65°C to +165°C
Lead Temperature (soldering, 10sec) .............................+300°C
GNDS, TON to GND..............................-0.3V to (V + 0.3V)
CC
SKIP to GND (Note 1).................................-0.3V to (V + 0.3V)
CC
DL to PGND................................................-0.3V to (V + 0.3V)
DD
BST to GND............................................................-0.3V to +36V
DH to LX .....................................................-0.3V to (BST + 0.3V)
Note 1: SKIP may be forced below -0.3V, temporarily exceeding the absolute maximum rating, for the purpose of debugging proto-
type breadboards using the no-fault test mode. Limit the current drawn to -5mA maximum.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V
= 15V, V = V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted.)
BATT
CC
DD
A
PARAMETER
CONDITIONS
MIN
2
TYP
MAX
28
UNIT
0/MAX71
Battery voltage, V+
Input Voltage Range
V
V
V
4.5
-1
5.5
1
CC, DD
DAC codes from 1.3V to 2V
V
= 4.5V to 28V, includes
BATT
DC Output Voltage Accuracy
%
DAC codes from 0.925V
to 1.275V
load regulation error
-1.2
1.2
Load Regulation Error
I
= 0 to 7A
9
3
5
mV
mV
mV
µA
kΩ
µA
ms
LOAD
Remote Sense Voltage Error
Line Regulation Error
FB-FBS or GNDS-GND = 0 to 25mV
= 4.5V to 5.5V, V = 4.5V to 28V
V
CC
BATT
FB Input Bias Current
FB (MAX1710 only) or FBS
-0.2
130
-1
0.2
240
1
FB Input Resistance (MAX1711)
GNDS Input Bias Current
Soft-Start Ramp Time
180
1.7
160
200
290
425
400
600
<1
Rising edge of SHDN to full I
LIM
TON = GND (550kHz)
TON = REF (400kHz)
TON = open (300kHz)
140
175
260
380
180
225
320
470
500
950
5
V
= 24V,
BATT
On-Time
FB = 2V
(Note 2)
ns
TON = V (200kHz)
CC
Minimum Off-Time
(Note 2)
ns
Quiescent Supply Current (V
)
)
Measured at V , FB forced above the regulation point
µA
µA
µA
µA
µA
CC
CC
Quiescent Supply Current (V
Measured at V , FB forced above the regulation point
DD
DD
Quiescent Battery Supply Current Measured at V+
25
40
Shutdown Supply Current (V
)
)
<1
5
SHDN = 0
SHDN = 0
CC
Shutdown Supply Current (V
<1
5
DD
Shutdown Battery Supply
Current
<1
2
5
µA
SHDN = 0, measured at V+ = 28V, V = V = 0 or 5V
CC
DD
Reference Voltage
V
= 4.5V to 5.5V, no external REF load
= 0 to 50µA
1.98
10
2.02
0.01
V
V
CC
Reference Load Regulation
REF Sink Current
I
REF
REF in regulation
µA
V
REF Fault Lockout Voltage
Falling edge, hysteresis = 40mV
1.6
2
_______________________________________________________________________________________
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0/MAX71
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V
= 15V, V = V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted.)
BATT
CC
DD
A
PARAMETER
CONDITIONS
MIN
10.5
2.21
TYP
12.5
2.25
MAX
14.5
2.29
UNIT
%
With respect to unloaded output voltage (MAX1710)
(MAX1711)
Overvoltage Trip Threshold
V
Overvoltage Fault Propagation
Delay
FB forced 2% above trip threshold
1.5
µs
With respect to unloaded output voltage (MAX1710)
(MAX1711)
65
70
75
%
V
Output Undervoltage Protection
Threshold
0.76
0.8
0.84
Output Undervoltage Protection
Time
10
90
30
ms
From SHDN signal going high
Current-Limit Threshold
(Positive Direction, Fixed)
LX to PGND, ILIM tied to V
100
110
mV
CC
R
R
= 100kΩ
= 400kΩ
40
50
60
LIM
LIM
Current-Limit Threshold
(Positive Direction, Adjustable)
LX to PGND
mV
mV
mV
170
200
230
Current-Limit Threshold
(Negative Direction)
LX to PGND, T = +25°C
A
-150
-120
-80
Current-Limit Threshold
(Zero Crossing)
LX to PGND
3
PGOOD Propagation Delay
PGOOD Output Low Voltage
PGOOD Leakage Current
Thermal Shutdown Threshold
FB forced 2% below PGOOD trip threshold, falling edge
1.5
µs
V
I
= 1mA
0.4
1
SINK
High state, forced to 5.5V
Hysteresis = 10°C
µA
°C
150
V
Undervoltage Lockout
Rising edge, hysteresis = 20mV,
PWM disabled below this level
CC
4.1
4.4
5
V
Ω
Ω
Threshold
DH Gate-Driver On-Resistance
BST-LX forced to 5V
DL, high state
DL Gate-Driver On-Resistance
(Pull-Up)
5
DL Gate-Driver On-Resistance
(Pull-Down)
DL, low state
0.5
1
1.7
Ω
DH Gate-Driver Source/Sink
Current
DH forced to 2.5V, BST-LX forced to 5V
A
DL Gate-Driver Sink Current
DL forced to 2.5V
DL forced to 2.5V
DL rising
3
1
A
A
DL Gate-Driver Source Current
35
26
Dead Time
ns
mA
%
DH rising
SKIP Input Current Logic
Threshold
To enable no-fault mode, T = +25°C
A
-1.5
-0.1
-3
Measured at FB with respect to unloaded output voltage,
falling edge, hysteresis = 1%
PGOOD Trip Threshold
-8
-5
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
2.4
V
V
D0–D4, SHDN, SKIP, OVP
D0–D4, SHDN, SKIP, OVP
SHDN, SKIP, OVP
0.8
1
-1
3
µA
µA
Logic Input Pull-Up Current
D0–D4, each forced to GND
5
10
_______________________________________________________________________________________
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ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V
= 15V, V = V = 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted.)
BATT
CC
DD
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
V
TON V Level
TON logic input high level
V
- 0.4
CC
CC
TON Float Voltage
TON logic input upper-mid-range level
TON logic input lower-mid-range level
TON logic input low level
3.15
3.85
2.35
0.5
3
V
TON Reference Level
TON GND Level
1.65
V
V
TON Logic Input Current
TON only, forced to GND or V
-3
µA
CC
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 1, V
=15V, V = V = 5V, SKIP = GND, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
BATT
CC
DD
A
PARAMETER
CONDITIONS
MIN
2
TYP
MAX
28
UNIT
V
Battery voltage, V+
Input Voltage Range
V
V
4.5
-1.5
5.5
CC, DD
0/MAX71
DAC codes from 1.32V to 2V
1.5
%
V
BATT
= 4.5V to 28V, for all
DC Output Voltage Accuracy
D/A codes, includes load
regulation error
DAC codes from 0.925V to
1.275V
-1.7
1.7
%
TON = GND (550kHz)
140
175
260
380
180
225
320
470
500
950
2.02
15
V
= 24V,
BATT
TON = REF (400kHz)
TON = open (300kHz)
On-Time
FB = 2V
(Note 2)
ns
TON = V (200kHz)
CC
Minimum Off-Time
(Note 2)
ns
µA
V
Quiescent Supply Current (V
)
Measured at V , FB forced above the regulation point
CC
CC
Reference Voltage
V
CC
= 4.5V to 5.5V, no external REF load
1.98
10
With respect to unloaded output voltage (MAX1710)
(MAX1711)
%
V
Overvoltage Trip Threshold
2.20
65
2.30
75
With respect to unloaded output voltage (MAX1710)
(MAX1711)
%
V
Output Undervoltage
Protection Threshold
0.75
0.85
Current-Limit Threshold
(Positive Direction, Fixed)
LX to PGND, ILIM tied to V
85
115
mV
mV
V
CC
R
R
= 100kΩ
= 400kΩ
35
65
LIM
LIM
Current-Limit Threshold
(Positive Direction, Adjustable)
LX to PGND
160
240
V
CC
Undervoltage Lockout
Rising edge, hysteresis = 20mV, PWM disabled below
this level
4.1
2.4
4.4
Threshold
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
V
V
D0–D4, SHDN, SKIP, OVP
D0–D4, SHDN, SKIP, OVP
SHDN, SKIP, OVP
0.8
1
-1
3
µA
µA
Logic Input Pull-Up Current
D0–D4, each forced to GND
10
4
_______________________________________________________________________________________
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S t e p -Do w n Co n t ro lle rs fo r No t e b o o k CP Us
0/MAX71
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 1, V
=15V, V = V = 5V, SKIP = GND, T = -40°C to +85°C, unless otherwise noted.) (Note 3)
BATT
CC
DD
A
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNIT
Measured at FB with respect to unloaded output voltage,
falling edge, hysteresis = 1%
PGOOD Trip Threshold
-8.5
-2.5
%
PGOOD Output Low Voltage
PGOOD Leakage Current
I
= 1mA
0.4
1
V
SINK
High state, forced to 5.5V
µA
Note 2: On-Time and Off-Time specifications are measured from 50% point to 50% point at the DH pin with LX forced to 0V, BST
forced to 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching
speeds.
Note 3: Specifications from -40°C to 0°C are guaranteed but not production tested.
__________________________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(7A CPU supply circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
EFFICIENCY vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
(V = 1.6V, f = 300kHz)
EFFICIENCY vs. LOAD CURRENT
(V = 1.3V, f = 300kHz)
(V = 2.0V, f = 300kHz)
O
O
O
100
90
80
70
60
50
40
100
90
80
70
60
50
40
100
90
80
70
60
50
40
V
= 4.5V
IN
V
IN
= 4.5V
V = 4.5V
IN
V
IN
= 7V
V
IN
= 7V
V
IN
= 7V
V
IN
= 15V
V
= 15V
IN
V
IN
= 15V
V
IN
= 24V
V
= 24V
IN
V
IN
= 24V
0.01
0.1
1
10
0.01
0.1
1
10
0.01
0.1
1
10
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
FREQUENCY vs. LOAD CURRENT
EFFICIENCY vs. LOAD CURRENT
FREQUENCY vs. INPUT VOLTAGE
(I = 7A)
(V = 1.6V)
O
(V = 1.6V, f = 550kHz)
O
O
350
300
250
200
150
100
50
100
90
80
70
60
50
40
320
318
316
314
312
310
308
306
304
302
300
V
= 4.5V
IN
V
= 15V, PWM MODE
IN
V
= 7V
IN
V
IN
= 4.5V, SKIP MODE
V = 2.0V
O
V = 1.6V
O
V
= 15V
IN
V
IN
= 15V, SKIP MODE
V
IN
= 24V
TON = OPEN
1 10
TON = OPEN
20 25 30
0
0.01
0.1
1
10
0.01
0.1
LOAD CURRENT (A)
0
5
10
15
LOAD CURRENT (A)
INPUT VOLTAGE (V)
_______________________________________________________________________________________
5
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_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(7A CPU supply circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
FREQUENCY vs. TEMPERATURE
CURRENT-LIMIT TRIP POINT
vs. TEMPERATURE
(V = 15V, V = 2.0V)
ON-TIME vs. TEMPERATURE
IN
O
315
310
305
300
295
290
285
474
472
470
468
466
464
462
460
458
456
30
25
20
15
10
5
I = 1A
I = 7A
O
O
I
= 400kΩ
LIM
I = 4A
O
I
= V
LIM CC
I = 4A OR 7A
O
I
= 100kΩ
LIM
TON = OPEN
-60 -40 -20
I = 1A
O
0
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
0/MAX71
INDUCTOR CURRENT PEAKS AND
VALLEYS vs. INPUT VOLTAGE
(AT CURRENT-LIMIT POINT)
CONTINUOUS TO DISCONTINUOUS
INDUCTOR CURRENT POINT
vs. INPUT VOLTAGE
NO-LOAD SUPPLY CURRENTS
vs. INPUT VOLTAGE
(SKIP MODE, f = 300kHz)
14.0
13.5
13.0
12.5
12.0
11.5
11.0
10.5
10.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
I
CC
V = 2.0V
O
I
PEAK
V = 1.6V
O
V = 1.3V
O
I
BATT
I
VALLEY
I
DD
0
5
10
15
20
25
30
0
5
10
15
20
25
30
0
5
10
15
20
25
30
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
NO-LOAD SUPPLY CURRENTS
vs. INPUT VOLTAGE
(SKIP MODE, f = 550kHz)
NO-LOAD SUPPLY CURRENTS
vs. INPUT VOLTAGE
(PWM MODE, f = 300kHz)
NO-LOAD SUPPLY CURRENTS
vs. INPUT VOLTAGE
(PWM MODE, f = 550kHz)
20
18
16
14
12
10
8
0.7
20
18
16
14
12
10
8
I
DD
I
CC
0.6
0.5
0.4
0.3
0.2
0.1
0
I
DD
I
I
BAT
BATT
I
BAT
6
6
4
4
I
DD
2
I
2
I
CC
CC
0
0
0
5
10
15
20
25
30
0
5
10
15
20
25
30
0
5
10
15
20
25
30
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
6
_______________________________________________________________________________________
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0/MAX71
_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(7A CPU supply circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
LOAD-TRANSIENT RESPONSE
LOAD-TRANSIENT RESPONSE
(WITH INTEGRATOR)
LOAD-TRANSIENT RESPONSE
(WITHOUT INTEGRATOR)
(WITH INTEGRATOR)
A
B
A
B
A
B
10µs/div
10µs/div
10µs/div
V
IN
= 15V, V = 1.6V, I = 0A TO 7A
V
IN
= 15V, V = 1.6V, I = 30mA, TO 7A
V = 15V, V = 1.6V, I = 30mA TO 7A
IN O O
O
O
O
O
A = V , AC COUPLED, 50mV/div
A = V , AC COUPLED, 50mV/div
A = V , AC COUPLED, 50mV/div
OUT
OUT
OUT
B = INDUCTOR CURRENT, 5A/div
B = INDUCTOR CURRENT, 5A/div
B = INDUCTOR CURRENT, 5A/div
LOAD-TRANSIENT RESPONSE
(WITH INTEGRATOR)
LOAD-TRANSIENT RESPONSE
(WITH INTEGRATOR)
START-UP WAVEFORM
A
A
A
B
C
B
C
B
C
500µs/div
20µs/div
20µs/div
A = SHDN
V
IN
= 4.5V, V = 2V, I = 30mA TO 7A
V = 4.5V, V = 1.3V, I = 30mA TO 7A
IN O O
O
O
B = V , 0.5V/div
A = V , AC COUPLED, 50mV/div
A = V , AC COUPLED, 50mV/div
OUT
OUT
OUT
C = INDUCTOR CURRENT, 5A/div
B = INDUCTOR CURRENT, 5A/div
C = DL, 10V/div
B = INDUCTOR CURRENT, 5A/div
C = DL, 10V/div
_______________________________________________________________________________________
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_____________________________Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(7A CPU supply circuit of Figure 1, T = +25°C, unless otherwise noted.)
A
LOAD-TRANSIENT RESPONSE
SHUTDOWN WAVEFORM
OUTPUT OVERLOAD WAVEFORM
CERAMIC C
OUT
A
B
A
B
C
A
B
C
D
C
5µs/div
L = 0.7µH, V = 1.6V, V = 15V, C = 47µF (x4), f = 550kHz
5µs/div
50µs/div
V
= 1.6V
IN
OUT
IN
OUT
V
= 15V, V = 1.6V, I = 7A
OUT
IN
0
0
A = V , AC COUPLED, 100mV/div
A = V , AC COUPLED, 2V/div
OUT
A = V , 0.5V/div
0/MAX71
OUT
B = INDUCTOR CURRENT, 5A/div
C = DL, 5V/div
B = V , 0.5V/div
OUT
B = INDUCTOR CURRENT, 5A/div
C = SHDN, 2V/div
C = INDUCTOR CURRENT, 5A/div
D = DL, 5V/div
P in De s c rip t io n
PIN
NAME
FUNCTION
Battery Voltage Sense Connection. V+ is used only for PWM one-shot timing. DH on-time is inversely propor-
tional to V+ input voltage over a range of 2V to 28V.
1
CC
Shutdown Control Input, active low. SHDN cannot withstand the battery voltage. In shutdown mode, DL is
2
3
SHDN
forced to V in order to enforce overvoltage protection, even when powered down (unless OVP is high).
DD
Fast Feedback Input, normally connected to V . FB is connected to the bulk output filter capacitors local-
OUT
FB
ly at the power supply. An external resistor-divider can optionally set the output voltage.
Feedback Remote-Sense Input, normally connected to V directly at the load. FBS internally connects to
OUT
4
FBS
the integrator that fine-tunes the DC output voltage. Tie FBS to V to disable all three integrator amplifiers.
CC
Tie FBS to FB (or disable the integrators) when externally adjusting the output voltage with a resistor-divider.
Integrator Capacitor Connection. Connect a 100pF to 1000pF (470pF typical) capacitor to GND to set the
integration time constant.
5
6
CC
Current-Limit Threshold Adjustment. Connects to an external resistor to GND. The LX-PGND current-limit
threshold defaults to +100mV if ILIM is tied to V . The current-limit threshold is 1/10 of the voltage forced at
CC
ILIM
ILIM. In adjustable mode the threshold is V = RLIM · 5µA/10.
TH
Analog Supply Voltage Input for PWM Core, 4.5V to 5.5V. Bypass V to GND with a 0.1µF minimum
CC
capacitor.
7
8
V
CC
On-Time Selection Control Input. This is a four-level input that sets the K factor to determine DH on-time.
TON
REF
GND = 550kHz, REF = 400kHz, open = 300kHz, V
= 200kHz.
CC
2.0V Reference Output. Bypass REF to GND with a 0.22µF minimum capacitor. REF can source 50µA for
external loads. Loading REF degrades FB accuracy according to the REF load-regulation error
(see Electrical Characteristics).
9
8
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0/MAX71
P in De s c rip t io n (c o n t in u e d )
PIN
NAME
FUNCTION
10
GND
Analog Ground
Ground Remote-Sense Input, normally connected to ground directly at the load. GNDS internally con-
nects to the integrator that fine-tunes the ground offset voltage.
11
GNDS
12
13
14
15
PGOOD
DL
Open-Drain Power-Good Output.
Low-Side Gate-Driver Output, swings 0 to V
.
DD
PGND
Power Ground. Also used as the inverting input for the current-limit comparator.
Supply Voltage Input for the DL gate driver, 4.5V to 5.5V
V
DD
16
Overvoltage-Protection Disable Control Input (Table 3). GND = normal operation and overvoltage
protection active, V = overvoltage protection disabled.
CC
OVP
(MAX1710)
16
D4
DAC Code Input, MSB, 5µA internal pull-up to V (Tables 1 and 2).
CC
(MAX1711)
17
18
19
20
D3
D2
D1
D0
DAC Code Input. 5µA internal pull-up to V
.
CC
DAC Code Input. 5µA internal pull-up.
DAC Code Input. 5µA internal pull-up.
DAC Code Input LSB. 5µA internal pull-up.
Low-Noise-Mode Selection Control Input. Low-noise forced-PWM mode causes inductor current
recirculation at light loads and suppresses pulse-skipping operation. Normal operation prevents
current recirculation. SKIP can also be used to disable both overvoltage and undervoltage protection
21
22
SKIP
circuits and clear the fault latch (Figure 6). GND = normal operation, V = low-noise mode. Do not
CC
leave SKIP floating.
Boost Flying-Capacitor Connection. An optional resistor in series with BST allows the DH pull-up
current to be adjusted (Figure 5). This technique of slowing the LX rise time can be used to prevent
accidental turn-on of the low-side MOSFET due to excessive gate-drain capacitance.
BST
Inductor Connection. LX serves as the lower supply rail for the DH high-side gate driver. Also used
for the noninverting input to the current-limit comparator as well as the skip-mode zero-crossing com-
parator.
23
24
LX
DH
High-Side Gate-Driver Output. Swings LX to BST.
S t a n d a rd Ap p lic a t io n Circ u it
De t a ile d De s c rip t io n
The standard application circuit (Figure 1) generates a
low-voltage, high-power rail for supplying up to 7A to the
The MAX1710/MAX1711 buck controllers are targeted
for low-voltage, high-current CPU power supplies for
notebook computers. CPU cores typically exhibit 0 to
10A or greater load steps when the clock is throttled.
The proprietary QUICK-PWM pulse-width modulator in
the MAX1710/MAX1711 is specifically designed for han-
dling these fast load steps while maintaining a relatively
constant operating frequency and inductor operating
point over a wide range of input voltages. The QUICK-
PWM architecture circumvents the poor load-transient
timing problems of fixed-frequency current-mode PWMs
core CPU V
in a notebook computer. This DC-DC
CC
converter steps down a battery or AC adapter voltage to
sub-2V levels with high efficiency and accuracy, and
represents a good compromise between size, efficiency,
and cost.
See the MAX1710 EV kit manual for a list of components
and suppliers.
_______________________________________________________________________________________
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V
BATT
4.5V TO 28V
+5V
BIAS SUPPLY
C5
1µF
C6
1µF
R1
20Ω
C1 3 x 10µF/30V
15
7
D2
CMPSH-3
V
V
DD
CC
1
22
24
V+
BST
DH
PANASONIC
ETQP6F2R0HFA
ON/OFF
CONTROL
2
SHDN
SKIP
Q1
L1
V
OUT
21
2µH
LOW-NOISE
CONTROL
C7
0.1µF
1.25V TO 2V AT 7A (MAX1710)
0.925V TO 2V AT 7A (MAX1711)
C2
20
19
18
D3
23
13
14
3 x 470µF
KEMET T510
D0
D1
D2
D3
MAX1710
MAX1711
LX
DL
(OPTIONAL OVP
REVERSE-POLARITY
CLAMP)
0/MAX71
DAC
INPUTS
D1
Q2
17
16
8
PGND
D4**
TON
REF
C4
1µF
9
3
FB
4
FBS
C3
470pF
5
11
CC
GNDS
+5V
R4
1k
10
GND
R2
100k
Q1 = IRF7807
Q2 = IRF7805
D1, D3 = MBRS130T3 (OPTIONAL)
C1 = Sanyo OS-CON (30SC10M)
12
POWER-GOOD
INDICATOR
ILIM OVP* PGOOD
16
6
TO V
CC
R3
(OPTIONAL)
* MAX1710 ONLY
** MAX1711 ONLY
Figure 1. Standard Application Circuit
while also avoiding the problems caused by widely vary-
ing switching frequencies in conventional constant-on-
time and constant-off-time PWM schemes.
capability is needed, the +5V supply can be generated
with an external linear regulator such as the MAX1615.
The battery and +5V bias inputs can be tied together if
the input source is a fixed 4.5V to 5.5V supply. If the +5V
bias supply is powered up prior to the battery supply, the
enable signal (SHDN) must be delayed until the battery
voltage is present in order to ensure start-up. The +5V
+5 V Bia s S u p p ly (V
a n d V
)
DD
CC
The MAX1710/MAX1711 requires an external +5V bias
supply in addition to the battery. Typically, this +5V bias
supply is the notebook’s 95% efficient 5V system supply.
Keeping the bias supply external to the IC improves effi-
ciency and eliminates the cost associated with the +5V
linear regulator that would otherwise be needed to sup-
ply the PWM circuit and gate drivers. If stand-alone
bias supply must provide V and gate-drive power, so
CC
the maximum current drawn is:
I
= I + f · (Q + Q ) = 15mA to 30mA (typ)
CC G1 G2
BIAS
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V
BATT
2V TO 28V
R
LIM
V+
I
LIM
TOFF
V
CC
+5V
MAX1710
1-SHOT
TON
5µA
FROM
D/A
ON-TIME
COMPUTE
TRIG
Q
BST
TON
S
Q
Q
TRIG
DH
LX
R
CURRENT
LIMIT
1-SHOT
Σ
OVP
ERROR
AMP
OUTPUT
SKIP
ZERO CROSSING
REF
10k
V
+5V
DD
SHDN
CC
70k
DL
REF
S
Q
PGND
R
g
m
g
m
g
m
FB
GNDS
FBS
FB
REF
+12%
REF
-30%
REF
-5%
CHIP SUPPLY
V
CC
+5V
PGOOD
R-2R
2V
REF
REF
D/A CONVERTER
S1
S2
TIMER
Q
GND
OVP/UVLO
LATCH
D0 D1 D2 D3
Figure 2. MAX1710 Functional Diagram
where I
is 600µA typical, f is the switching frequency,
the filter capacitor’s ESR to act as the current-sense
resistor, so the output ripple voltage provides the PWM
ramp signal. The control algorithm is simple: the high-
side switch on-time is determined solely by a one-shot
whose period is inversely proportional to input voltage
and directly proportional to output voltage. Another one-
shot sets a minimum off-time (400ns typical). The on-time
one-shot is triggered if the error comparator is low, the
CC
and Q
and Q
are the MOSFET data sheet total
G1
G2
gate-charge specification limits at V = 5V.
GS
Fre e -Ru n n in g , Co n s t a n t -On -Tim e P WM
Co n t ro lle r w it h In p u t Fe e d -Fo rw a rd
The QUICK-PWM control architecture is an almost fixed-
frequency, constant-on-time current-mode type with volt-
age feed-forward (Figure 2). This architecture relies on
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Table 1. MAX1710 FB Output Voltage
DAC Codes
Table 2. MAX1711 FB Output Voltage
DAC Codes
OUTPUT
VOLTAGE (V)
OUTPUT
VOLTAGE (V)
D4
D3
D2
D1
D0
D3
D2
D1
D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.00
1.95
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2.00
1.95
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
1.45
1.40
1.35
1.30
1.25
1.90
1.85
1.80
1.75
1.70
1.65
1.60
1.55
1.50
0/MAX71
1.45
1.40
1.35
1.30
Shutdown 3*
1.275
1.250
1.225
1.200
1.175
1.150
1.125
1.100
1.075
1.050
1.025
1.000
0.975
0.950
0.925
Shutdown 3*
low-side switch current is below the current-limit thresh-
old, and the minimum off-time one-shot has timed out.
On -Tim e On e -S h o t (TON)
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to battery and output voltage. The high-side
switch on-time is inversely proportional to the battery
voltage as measured by the V+ input, and directly pro-
portional to the output voltage as set by the DAC code.
This algorithm results in a nearly constant switching fre-
quency despite the lack of a fixed-frequency clock gen-
erator. The benefits of a constant switching frequency
are twofold: first, the frequency can be selected to avoid
noise-sensitive regions such as the 455kHz IF band;
second, the inductor ripple-current operating point
remains relatively constant, resulting in easy design
methodology and predictable output voltage ripple.
* See Table 3
On-Time = K (V
+ 0.075V) / V
IN
OUT
settings due to fixed propagation delays and is approxi-
mately ±12.5% at 550kHz and 400kHz, and ±10% at the
two slower settings. This translates to reduced switch-
ing-frequency accuracy at higher frequencies. (see
Table 5). Switching frequency increases as a function of
load current due to the increasing drop across the low-
where K is set by the TON pin-strap connection and
0.075V is an approximation to accommodate for the
expected drop across the low-side MOSFET switch.
One-shot timing error increases for the shorter on-time
12 ______________________________________________________________________________________
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0/MAX71
side MOSFET, which causes a faster inductor-current
d is c ha rg e ra mp . The on-time s g ua ra nte e d in the
Electrical Characteristics are influenced by switching
delays in the external high-side power MOSFET. The
exact switching frequency will depend on gate charge,
internal gate resistance, source inductance, and DH out-
put drive characteristics.
average value of the output ripple waveform. If the inte-
grator amplifiers are disabled, V is regulated at the
OUT
valleys of the output ripple waveform. This creates a
slight load-regulation characteristic in which the output
voltage rises approximately 1% (up to 1/2 the peak
amplitude of the ripple waveform as a limit) when under
light loads.
Two external factors that can influence switching-fre-
quency accuracy are resistive drops in the two conduc-
tion loops (including inductor and PC board resistance)
and the dead-time effect. These effects are the largest
contributors to the change of frequency with changing
load current. The dead-time effect is a notable disconti-
nuity in the switching frequency as the load current is
varied (see Typical Operating Characteristics). It occurs
whenever the inductor current reverses, most commonly
at light loads with SKIP high. With reversed inductor cur-
rent, the inductor’s EMF causes LX to go high earlier
than normal, extending the on-time by a period equal to
the low-to-high dead time. For loads above the critical
conduction point, the actual switching frequency is:
Integrators have both beneficial and detrimental charac-
teristics. While they do correct for drops due to DC bus
resistance and tighten the DC output voltage tolerance
limits b y a ve ra g ing the p e a k-to-p e a k outp ut
ripple, they can interfere with achieving the fastest possi-
b le loa d -tra ns ie nt re s p ons e . The fa s te s t tra ns ie nt
response is achieved when all three integrators are dis-
a b le d . This works ve ry we ll whe n the MAX1710/
MAX1711 circuit can be placed very close to the CPU.
There is often a connector, or at least many milliohms of
PC board trace resistance, between the DC-DC convert-
er and the CPU. In these cases, the best strategy is to
place most of the bulk bypass capacitors close to the
CPU, with just one capacitor on the other side of the
connector near the MAX1710/MAX1711 to control ripple
if the CPU card is unplugged. In this situation, the
remote-sense lines and integrators provide a real benefit.
V
+ V
DROP1
OUT
f =
t
(V + V
)
ON IN
DROP2
where V
is the sum of the parasitic voltage drops
DROP1
When both GNDS and FBS are tied to V
three integrators are disabled, CC can be left uncon-
nected, which eliminates a component.
so that all
CC
in the inductor discharge path, including synchronous
rectifier, inductor, and PC board resistances; V
is
DROP2
the sum of the resistances in the charging path, and t
is the on-time calculated by the MAX1710/MAX1711.
ON
Au t o m a t ic P u ls e -S k ip p in g S w it c h o ve r
At light loads, an inherent automatic switchover to PFM
takes place. This switchover is effected by a comparator
that truncates the low-side switch on-time at the inductor
current’s zero crossing. This mechanism causes the
threshold between pulse-skipping PFM and non-skip-
ping PWM operation to coincide with the boundary
between continuous and discontinuous inductor-current
operation (also known as the “critical conduction” point;
see Continuous to Discontinuous Inductor Current Point
vs . Inp ut Volta g e g ra p hs in the Typ ic a l Op e ra ting
Characteristics). For a battery range of 7V to 24V this
threshold is relatively constant, with only a minor depen-
dence on battery voltage.
In t e g ra t o r Am p lifie rs (CC)
There are three integrator amplifiers that provide a fine
adjustment to the output regulation point. One amplifier
monitors the difference between GNDS and GND, while
another monitors the difference between FBS and FB.
The third amplifier integrates the difference between REF
and the DAC output. These three transconductance
amplifiers’ outputs are directly summed inside the chip,
so the integration time constant can be set easily with a
capacitor. The g of each amplifier is 160µmho (typical).
m
The integrator block has an ability to move and correct
the output voltage by about -2%, +4%. For each amplifi-
er, the differential input voltage range is about ±50mV
total, including DC offset and AC ripple. The voltage
gain of each integrator is about 80V/V.
K
I
≈
LOAD(SKIP)
2L
where K is the On-Time Scale factor (see Table 5). The
load-current level at which PFM/PWM crossover occurs,
The FBS amplifier corrects for DC voltage drops in PC
board traces and connectors in the output bus path
between the DC-DC converter and the load. The GNDS
amplifier performs a similar DC correction task for the
output ground bus. The third amplifier provides an aver-
I
, is equal to 1/2 the peak-to-peak ripple cur-
LOAD(SKIP)
rent, which is a function of the inductor value (Figure 3).
For example, in the standard application circuit with t
ON
= 300ns at 24V, V
= 2V, and L = 2µH, switchover to
OUT
aging function that forces V
to be regulated at the
OUT
pulse-skipping operation occurs at I
= 1.65A or
LOAD
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-I
PEAK
∆i
∆t
V
-V
BATT OUT
=
L
-I
PEAK
I
LOAD
I
= I
/2
LOAD PEAK
I
LIMIT
LX-PGND I
THRESHOLD = 100mV (NOMINAL, DEFAULT)
LIMIT
VOLTAGE DROP ACROSS Q2
0
TIME
0
ON-TIME
TIME
Figure 4. ‘‘Valley’’ Current-Limit Threshold Point
Figure 3. Pulse-Skipping/Discontinuous Crossover Point
about 1/4 full load. The crossover point occurs at an
even lower value if a swinging (soft-saturation) inductor
is used.
the c urre nt-s e ns e s ig na l is a b ove the c urre nt-limit
threshold, the PWM is not allowed to initiate a new cycle
(Figure 4). The actual peak current is greater than the
current-limit threshold by an amount equal to the induc-
tor ripple current. Therefore the exact current-limit char-
acteristic and maximum load capability are a function of
the MOSFET on-resistance, inductor value, and battery
voltage. The reward for this uncertainty is robust, loss-
less overcurrent sensing. When combined with the UVP
protection circuit, this current-limit method is effective in
almost every circumstance.
0/MAX71
The switching waveforms may appear noisy and asyn-
chronous when light loading causes pulse-skipping
operation, but this is a normal operating condition that
results in high light-load efficiency. Trade-offs in PFM
noise vs. light-load efficiency can be made by varying
the inductor value. Generally, low inductor values pro-
duce a broader efficiency vs. load curve, while higher
values result in higher full-load efficiency (assuming that
the coil resistance remains fixed) and less output voltage
ripple. Penalties for using higher inductor values include
la rg e r p hys ic a l s ize a nd d e g ra d e d loa d -tra ns ie nt
response (especially at low input voltage levels).
There is also a negative current limit that prevents exces-
sive reverse inductor currents when V
is sinking cur-
OUT
re nt. The ne g a tive c urre nt-limit thre s hold is s e t to
approximately 120% of the positive current limit, and
therefore tracks the positive current limit when ILIM is
adjusted.
SKIP
Fo rc e d -P WM Mo d e (
= Hig h )
The low-noise, forced-PWM mode (SKIP driven high) dis-
ables the zero-crossing comparator, which controls the
low-side switch on-time. This causes the low-side gate-
drive waveform to become the complement of the high-
s id e g a te -d rive wa ve form. This in turn c a us e s the
inductor current to reverse at light loads, as the PWM
The current-limit threshold can be adjusted with an exter-
nal resistor (R ) at ILIM. A precision 5µA pull-up cur-
LIM
rent source at ILIM sets a voltage drop on this resistor,
a d jus ting the c urre nt-limit thre s hold from 50mV to
200mV. In the adjustable mode, the current-limit thresh-
old voltage is precisely 1/10th the voltage seen at ILIM.
loop strives to maintain a duty ratio of V /V . The
OUT IN
Therefore, choose R
equal to 2kΩ/mV of the current-
LIM
benefit of forced-PWM mode is to keep the switching fre-
quency fairly constant, but it comes at a cost: the no-
load battery current can be as high as 40mA or more.
limit threshold. The threshold defaults to 100mV when
ILIM is tied to V . The logic threshold for switchover to
CC
the 100mV default value is approximately V - 1V.
CC
Forced-PWM mode is most useful for reducing audio-fre-
quency noise, improving load-transient response, pro-
viding sink-current capability for dynamic output voltage
adjustment, and improving the cross-regulation of multi-
ple-output applications that use a flyback transformer or
coupled inductor.
The a d jus ta b le c urre nt limit c a n a c c ommod a te
MOSFETs with atypical on-resistance characteristics
(see Design Procedure).
A capacitor in parallel with R
soft-start function.
can provide a variable
LIM
Cu rre n t -Lim it Circ u it (ILIM)
The current-limit circuit employs a unique “valley” cur-
rent-sensing algorithm that uses the on-state resistance
of the low-side MOSFET as a current-sensing element. If
Carefully observe the PC board layout guidelines to
ensure that noise and DC errors don’t corrupt the cur-
rent-sense signals seen by LX and PGND. The IC must
be mounted close to the low-side MOSFET with short,
14 ______________________________________________________________________________________
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0/MAX71
direct traces making a Kelvin sense connection to the
source and drain terminals.
and forces the DL gate driver high (in order to enforce
output overvoltage protection) until V rises above
CC
4.2V, whereupon an internal digital soft-start timer begins
to ramp up the maximum allowed current limit. The ramp
occurs in five steps: 20%, 40%, 60%, 80%, and 100%,
with 100% current available after 1.7ms ±50%.
MOS FET Ga t e Drive rs (DH, DL)
The DH and DL drivers are optimized for driving moder-
ate-size, high-side and larger, low-side power MOSFETs.
This is consistent with the low duty factor seen in the
A continuously adjustable, analog soft-start function can
notebook CPU environment, where a large V
- V
BATT
OUT
be realized by adding a capacitor in parallel with R
at
LIM
differential exists. An adaptive dead-time circuit monitors
the DL output and prevents the high-side FET from turn-
ing on until DL is fully off. There must be a low-resis-
tance, low-inductance path from the DL driver to the
MOSFET gate in order for the adaptive dead-time circuit
to work properly. Otherwise, the sense circuitry in the
MAX1710/MAX1711 will interpret the MOSFET gate as
“off” while there is actually still charge left on the gate.
Use very short, wide traces measuring 10 to 20 squares
(50 to 100 mils wide if the MOSFET is 1 inch from the
MAX1710/MAX1711).
ILIM. This soft-start method requires a minimum interval
between power-down and power-up to allow R
charge the capacitor.
to dis-
LIM
P o w e r-Go o d Ou t p u t (P GOOD)
The output (FB) is continuously monitored for undervolt-
age by the PGOOD comparator, except in shutdown or
standby mode. The -5% undervoltage trip threshold is
measured with respect to the nominal unloaded output
voltage, as set by the DAC. If the DAC code increases in
steps greater than 1LSB, it is likely that PGOOD will
momentarily go low. In shutdown and standby modes,
PGOOD is actively held low. The PGOOD output is a true
open-drain type with no parasitic ESD diodes. Note that
the PGOOD undervoltage detector is completely inde-
pendent of the output UVP fault detector.
The dead time at the other edge (DH turning off) is deter-
mined by a fixed 35ns (typical) internal delay.
The internal pull-down transistor that drives DL low is
robust, with a 0.5Ω typical on-resistance. This helps pre-
vent DL from being pulled up during the fast rise-time of
the inductor node, due to capacitive coupling from the
drain to the gate of the massive low-side synchronous-
rectifier MOSFET. However, you might still encounter
some combinations of high- and low-side FETs that will
cause excessive gate-drain coupling, which can lead to
efficiency-killing, EMI-producing shoot-through currents.
This can often be remedied by adding a resistor in series
with BST, which increases the turn-on time of the high-
side FET without degrading the turn-off time.
Ou t p u t Ove rvo lt a g e P ro t e c t io n (OVP )
The overvoltage protection circuit is designed to protect
against a shorted high-side MOSFET by drawing high
current and blowing the battery fuse. The FB node is
continuously monitored for overvoltage. The overvoltage
trip threshold tracks the DAC code setting. If the output
is more than 12.5% above the nominal regulation point
for the MAX1710 (2.25V absolute for the MAX1711),
overvoltage protection (OVP) is triggered and the circuit
shuts down. The DL low-side gate-driver output is then
DAC Co n ve rt e r (D0 –D4 )
The digital-to-analog converter (DAC) programs the out-
put voltage. It receives a digital code from pins on the
CPU module that are either hard-wired to GND or left
open-circuit. Note that the codes don’t match any desk-
top VRM codes. The MAX1710/MAX1711 contain weak
internal pull-ups on each input in order to eliminate exter-
nal resistors.
latched high until SHDN is toggled or V
power is
CC
cycled below 1V. This action turns on the synchronous-
rectifier MOSFET with 100% duty and, in turn, rapidly dis-
charges the output filter capacitor and forces the output
to ground.
If the condition that caused the overvoltage (such as a
shorted high-side MOSFET) persists, the battery fuse will
blow. Note that DL going high can have the effect of
causing output polarity reversal, due to energy stored in
the output LC at the instant OVP activates. If the load
can’t tolerate being forced to a negative voltage, it may
be desirable to place a power Schottky diode across the
output to act as a reverse-polarity clamp (Figure 1). The
MAX1710/MAX1711 itself can be affected by the FB pin
going below ground, with the negative voltage coupling
into SHDN. It may be necessary to add 1kΩ resistors in
series with FB and FBS (Figure 7).
When changing MAX1710 DAC codes while powered
up, the over/undervoltage protection features can be
activated if the code is changed more than 1LSB at a
time. For applications needing the capability of changing
DAC codes “on-the-fly,” use the MAX1711.
P OR, UVLO, a n d S o ft -S t a rt
Power-on reset (POR) occurs when V
rises above
CC
approximately 2V, resetting the fault latch and soft-start
counter, and preparing the PWM for operation. V
CC
undervoltage lockout (UVLO) circuitry inhibits switching
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Table 3. Operating Mode Truth Table
DL
MODE
COMMENTS
SHDN SKIP OVP
0
0
X
X
0
1
High
Shutdown1 Low-power shutdown state. DL is forced to V , enforcing OVP. I < 1µA typ.
DD
CC
Low-power shutdown state. DL is forced to GND, disabling OVP. I < 1µA typ.
CC
Exiting shutdown triggers a soft-start cycle.
Low
Low
Shutdown2
Shutdown3 DAC code = X1111 (see Table 2) DL is forced to PGND, DH is forced to LX. The
1
X
X
(MAX1711
only)
MAX1711 eventually goes into UVP fault mode as the load current discharges the
output.
Test mode with OVP, UVP, and thermal faults disabled and latches cleared.
Otherwise normal operation, with automatic PWM/PFM switchover for pulse
skipping at light loads (Figure 6).
Below
GND
1
1
1
1
1
X
1
Switching
Switching
Switching
Switching
High
No Fault
No OVP
OVP faults disabled and OVP latch cleared. Otherwise normal operation,
with SKIP controlling PWM/PFM switchover.
X
Low-noise operation with no automatic switchover. Fixed-frequency PWM action
is forced regardless of load. Inductor current reverses at light load levels.
Run (PWM),
Low Noise
V
CC
X
X
X
I
CC
draw = 750µA typ. I draw = 15mA typ.
DD
0/MAX71
Run
Normal operation with automatic PWM/PFM switchover for pulse skipping at light
GND
X
(PFM/PWM) loads. I = 600µA typ. I draw = load dependent.
CC
DD
Fault latch has been set by OVP, output UVLO, or thermal shutdown. Device will
Fault
remain in FAULT mode until V power is cycled, SKIP is forced below ground,
CC
or SHDN is toggled.
a variable current limit. If the MAX1710 output (FB) is
under 70% of the nominal value 20ms after coming out of
shutdown, the PWM is latched off and won’t restart until
Table 4. Frequency Selection Guidelines
FREQUENCY
(kHz)
TYPICAL
APPLICATION
COMMENT
V
p owe r is c yc le d or SHDN is tog g le d . For the
CC
MAX1711, the nominal UVP trip threshold is fixed at 0.8V.
4-cell Li+ notebook Use for absolute best
CPU core efficiency.
200
No -Fa u lt Te s t Mo d e
The over/undervoltage protection features can compli-
cate the process of debugging prototype breadboards,
since there are (at most) a few milliseconds in which to
determine what went wrong. Therefore, a test mode is
provided to totally disable the OVP, UVP, and thermal
shutdown features, and clear to the fault latch if it has
been previously set. The PWM operates as if SKIP were
grounded (PFM/PWM mode).
4-cell Li+ notebook Considered mainstream
300
CPU core
by current standards.
Useful in 4-cell systems
for lighter loads than the
CPU or where size is key.
3-cell Li+ notebook
CPU core
400
550
Good operating point for
compound buck designs
or desktop circuits.
+5V-input notebook
CPU core
The no-fault test mode is entered by sinking 1.5mA
from SKIP via an external negative voltage source in
series with a resistor (Figure 6). SKIP is clamped to
GND with a silicon diode, so choose the resistor value
DL is also kept high continuously when V
UVLO is
CC
a c tive a s we ll a s in Shutd own1 mod e (Ta b le 3).
Overvoltage protection can be defeated via the OVP
input (MAX1710 only) or via a SKIP test mode (see Pin
Description).
equal to (V
- 0.65V) / 1.5mA.
FORCE
De s ig n P ro c e d u re
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency and
inductor operating point (ripple current ratio). The prima-
Ou t p u t Un d e rvo lt a g e P ro t e c t io n (UVP )
The output undervoltage protection function is similar to
foldback current limiting, but employs a timer rather than
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+5V
V
BATT
APPROXIMATELY
-0.65V
MAX1710
MAX1711
5Ω
BST
DH
SKIP
1.5mA
V
FORCE
MAX1710
MAX1711
LX
GND
Figure 5. Reducing the Switching-Node Rise Time
Figure 6. Disabling Over/Undervoltage Protection (Test Mode)
ry design trade-off lies in choosing a good switching fre-
quency and inductor operating point, and the following
four factors dictate the rest of the design:
es zero with every cycle at maximum load). Inductor
values lower than this grant no further size-reduction
benefit.
1) Input voltage range. The ma ximum va lue
The MAX1710/MAX1711’s pulse-skipping algorithm
initiates skip mode at the critical-conduction point. So,
the inductor operating point also determines the load-
current value at which PFM/PWM switchover occurs.
The optimum point is usually found between 20% and
50% ripple current.
(V
) must accommodate the worst-case high
BATT(MAX)
AC adapter voltage. The minimum value (V
)
BATT(MIN)
must account for the lowest battery voltage after
drops due to connectors, fuses, and battery selector
switches. If there is a choice at all, lower input volt-
ages result in better efficiency.
The ind uc tor rip p le c urre nt a ls o imp a c ts tra ns ie nt-
2) Maximum load current. There are two values to con-
response performance, especially at low V
- V
BATT
OUT
sider. The peak load current (I ) determines
LOAD(MAX)
differentials. Low inductor values allow the inductor cur-
rent to slew faster, replenishing charge removed from the
output filter capacitors by a sudden load step. The
amount of output sag is also a function of the maximum
duty factor, which can be calculated from the on-time
and minimum off-time:
the instantaneous component stresses and filtering
re q uire me nts , a nd thus d rive s outp ut c a p a c itor
selection, inductor saturation rating, and the design
of the current-limit circuit. The continuous load cur-
rent (I
) determines the thermal stresses and
LOAD
thus d rive s the s e le c tion of inp ut c a p a c itors ,
MOSFETs, and other critical heat-contributing com-
ponents. Modern notebook CPUs generally exhibit
2
(∆I
)
L
LOAD(MAX)
V
=
SAG
2 C DUTY (V
− V
)
F
BATT(MIN)
OUT
I
= I
· 80%.
LOAD
LOAD(MAX)
3) Switching frequency. This choice determines the
basic trade-off between size and efficiency. The opti-
mal frequency is largely a function of maximum input
voltage, due to MOSFET switching losses that are
In d u c t o r S e le c t io n
The switching frequency (on-time) and operating point
(% ripple or LIR) determine the inductor value as follows:
V
OUT
2
proportional to frequency and VBATT . The optimum
L =
f LIR I
LOAD(MAX)
fre q ue nc y is a ls o a moving ta rg e t, d ue to ra p id
improvements in MOSFET technology that are making
higher frequencies more practical (Table 4).
Example: I
= 7A, V
ripple current or LIR = 0.5.
= 2V, f = 300kHz, 50%
LOAD(MAX)
OUT
4) Inductor operating point. This c hoic e p rovid e s
trade-offs between size vs. efficiency. Low inductor
values cause large ripple currents, resulting in the
smallest size, but poor efficiency and high output
noise. The minimum practical inductor value is one
that causes the circuit to operate at the edge of criti-
cal conduction (where the inductor current just touch-
2V
L =
= 1.9µH (2µH)
300kHz 0.5 7A
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Ferrite
cores are often the best choice, although powdered iron
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is cheap and can work well at 200kHz. The core must be
Vp -p
large enough not to saturate at the peak inductor current
(I ).
R
≤
ESR
PEAK
LIR I
LOAD(MAX)
I
= I
+ (LIR / 2) · I
PEAK
LOAD(MAX) LOAD(MAX)
The actual microfarad capacitance value required relates
to the physical size needed to achieve low ESR, as well
as to the chemistry of the capacitor technology. Thus, the
capacitor is usually selected by ESR and voltage rating
rather than by capacitance value (this is true of tantalums,
OS-CONs, and other electrolytics).
S e t t in g t h e Cu rre n t Lim it
The minimum c urre nt-limit thre s hold mus t b e g re a t
enough to support the maximum load current when the
current limit is at the minimum tolerance value. The valley
of the inductor current occurs at I
of the ripple current, therefore:
minus half
LOAD(MAX)
When using low-capacity filter capacitors such as ceram-
ic or polymer types, capacitor size is usually determined
by the capacity needed to prevent the overvoltage pro-
tection circuit from being tripped when transitioning from
a full-load to a no-load condition. The capacitor must be
large enough to prevent the inductor’s stored energy from
launching the output above the overvoltage protection
threshold. Generally, once enough capacitance is added
to meet the overshoot requirement, undershoot at the ris-
I
> I
- (LIR / 2) · I
LOAD(MAX) LOAD(MAX)
LIMIT(LOW)
where I
= minimum current-limit threshold volt-
LIMIT(LOW)
age divided by the R
minimum current-limit threshold (100mV default setting)
is 90mV. Use the worst-case maximum value for R
from the MOSFET Q2 data sheet, and add some margin
for the rise in R with temperature. A good general
rule is to allow 0.5% additional resistance for each °C of
temperature rise.
of Q2. For the MAX1710, the
DS(ON)
DS(ON)
0/MAX71
DS(ON)
ing load edge is no longer a problem (see also V
SAG
equation under Design Procedure).
With integrators disabled, the amount of overshoot due to
stored inductor energy can be calculated as:
Examining the 7A notebook CPU circuit example with a
maximum R
= 15mΩ at high temperature reveals
DS(ON)
the following:
2
2
C
V
+L I
OUT OUT PEAK
∆V =
− V
OUT
I
= 90mV / 15mΩ = 6A
LIMIT(LOW)
C
OUT
6A is greater than the valley current of 5.25A, so the cir-
cuit can easily deliver the full rated 7A using the default
100mV nominal ILIM threshold.
where I
is the peak inductor current. To absolutely
PEAK
minimize the overshoot, disable the integrator first, since
the inherent delay of the integrator can cause extra “run-
on” switching cycles to occur after the load change.
When adjusting the current limit, use a 1% tolerance R
resistor to prevent a significant increase of errors in the
current-limit tolerance.
LIM
Ou t p u t Ca p a c it o r S t a b ilit y Co n s id e ra t io n s
Stability is determined by the value of the ESR zero rela-
tive to the switching frequency. The point of instability is
given by the following equation:
Output Ca pa c itor Se le c tion
The output filter capacitor must have low enough effective
series resistance (ESR) to meet output ripple and load-
transient requirements, yet have high enough ESR to sat-
isfy stability requirements. Also, the capacitance value
must be high enough to absorb the inductor energy
going from a full-load to no-load condition without tripping
the overvoltage protection circuit.
f
f
=
ESR
π
1
where f
=
ESR
2 π R
C
F
ESR
In CPU V
converters and other applications where
CORE
the output is subject to violent load transients, the output
capacitor’s size depends on how much ESR is needed to
prevent the output from dipping too low under a load
transient. Ignoring the sag due to finite capacitance:
For a typical 300kHz application, the ESR zero frequency
must be well below 95kHz, preferably below 50kHz.
Tantalum and OS-CON capacitors in widespread use at
the time of publication have typical ESR zero frequencies
of 15kHz. In the design example used for inductor selec-
tion, the ESR needed to support 50mVp-p ripple is
50mV/3.5A = 14.2mΩ. Three 470µF/4V Kemet T510 low-
ESR tantalum capacitors in parallel provide 15mΩ max
ESR. Their typical combined ESR results in a zero at
14.1kHz, well within the bounds of stability.
V
DIP
LOAD(MAX)
R
≤
ESR
I
In non-CPU applications, the output capacitor’s size
depends on how much ESR is needed to maintain an
acceptable level of output voltage ripple:
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0/MAX71
Don’t put high-value ceramic capacitors directly across
ensure that the conduction losses at minimum input volt-
age don’t exceed the package thermal limits or violate
the overall thermal budget. Check to ensure that con-
duction losses plus switching losses at the maximum
input voltage don’t exceed the package ratings or violate
the overall thermal budget.
the fast feedback inputs (FB to GND) without taking pre-
cautions to ensure stability. Large ceramic capacitors
can have a high ESR zero frequency and cause erratic,
unstable operation. However, it’s easy to add enough
series resistance simply by placing the capacitors a cou-
ple of inches downstream from the junction of the induc-
tor a nd FB p in (s e e the All-Ce ra mic -Ca p a c itor
Application section).
Choose a low-side MOSFET (Q2) that has the lowest
possible R , comes in a moderate to small pack-
DS(ON)
age (i.e., SO-8), and is reasonably priced. Ensure that
the MAX1710/MAX1711 DL gate driver can drive Q2; in
other words, check that the gate isn’t pulled up by the
high-side switch turning on due to parasitic drain-to-gate
c a p a c ita nc e , c a us ing c ros s -c ond uc tion p rob le ms .
Switching losses aren’t an issue for the low-side MOS-
FET, since it’s a zero-voltage switched device when
used in the buck topology.
Unstable operation manifests itself in two related but dis-
tinctly different ways: double-pulsing and fast-feedback
loop instability.
Double-pulsing occurs due to noise on FB or because
the ESR is so low that there isn’t enough voltage ramp in
the output voltage (FB) signal. This “fools” the error com-
parator into triggering a new cycle immediately after the
400ns minimum off-time period has expired. Double-
pulsing is more annoying than harmful, resulting in noth-
ing worse than increased output ripple. However, it can
indicate the possible presence of loop instability, which
is caused by insufficient ESR.
MOS FET P o w e r Dis s ip a t io n
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET, the worst-case
power dissipation due to resistance occurs at minimum
battery voltage:
Loop instability can result in oscillations at the output
after line or load perturbations that can trip the overvolt-
age protection latch or cause the output voltage to fall
below the tolerance limit.
2
PD(Q1) = (V
/ V
) · I
· R
DS(ON)
OUT
BATT(MIN)
LOAD
Generally, a small high-side MOSFET is desired in order
to re d uc e s witc hing los s e s a t hig h inp ut volta g e s .
The easiest method for checking stability is to apply a
very fast zero-to-max load transient (see MAX1710
Evaluation Kit manual) and carefully observe the output
voltage ripple envelope for overshoot and ringing. It
can help to simultaneously monitor the inductor current
with an AC current probe. Don’t allow more than one
cycle of ringing after the initial step-response under- or
overshoot.
However, the R
power-dissipation limits often limits how small the MOS-
FET can be. Again, the optimum occurs when the switch-
ing (AC) losses equal the conduction (R
High-side switching losses don’t usually become an
issue until the input is greater than approximately 15V.
required to stay within package
DS(ON)
) losses.
DS(ON)
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
CV2F switching loss equation. If the high-side MOSFET
In p u t Ca p a c it o r S e le c t io n
The inp ut c a p a c itor mus t me e t the rip p le c urre nt
you’ve chosen for adequate R
at low battery volt-
DS(ON)
requirement (I
) imposed by the switching currents.
RMS
ages becomes extraordinarily hot when subjected to
, you must reconsider your choice of MOS-
Non-tantalum chemistries (ceramic, aluminum, or OS-
CON) are preferred due to their resistance to power-up
surge currents.
V
BATT(MAX)
FET.
Calculating the power dissipation in Q1 due to switching
losses is difficult, since it must allow for difficult to quanti-
fy factors that influence the turn-on and turn-off times.
These factors include the internal gate resistance, gate
charge, threshold voltage, source inductance, and PC
board layout characteristics. The following switching loss
calculation provides only a very rough estimate and is no
substitute for breadboard evaluation, preferably including
a sanity check using a thermocouple mounted on Q1.
V
(V
− V
)
OUT BATT
V
OUT
I
=I
LOAD
RMS
BATT
P o w e r MOS FET S e le c t io n
Most of the following MOSFET guidelines focus on the
challenge of obtaining high load-current capability (>5A)
when using high-voltage (>20V) AC adapters. Low-cur-
rent applications usually require less attention.
For maximum efficiency, choose a high-side MOSFET
(Q1) that has conduction losses equal to the switching
losses at the optimum battery voltage (15V). Check to
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+5V
V
IN
= 7V TO 24V*
0.1µF
20Ω
C1
1µF
V
DD
V+
V
CC
5Ω
ON/OFF
SHDN
SKIP
BST
DH
Q1
Q2
0.5µH
R1
R2
1.6V AT 7A
CPU
0.1µF
MAX1711
LX
D0
D1
D2
D3
D4
C2
DAC
INPUTS
DL
PGND
GND
FB
0.22µF
1k
REF
CC
1k
1k
0/MAX71
FBS
470pF
GNDS
TON
C1 = 4 x 4.7µF/25V TAIYO YUDEN (TMK325BJ475K)
C2 = 6 x 47µF/10V TAIYO YUDEN (LMK550BJ476KM)
1nF
R1 + R2 = 5mΩ MINIMUM OF PCB TRACE RESISTANCE (TOTAL)
* FOR HIGHER MINIMUM INPUT VOLTAGE,
* LESS OUTPUT CAPACITANCE IS REQUIRED.
Figure 7. All-Ceramic-Capacitor Application
current limit and cause the fault latch to trip. To protect
against this possibility, you must “overdesign” the circuit
Table 5. Approximate K-Factors Errors
TON
K
APPROXIMATE
K-FACTOR
MIN V
BATT
to tolerate I
= I
+ (LIR / 2) · I
,
LOAD
LIMIT(HIGH)
LOAD(MAX)
SETTING FACTOR
AT V
= 2V
OUT
where I
is the maximum valley current allowed
LIMIT(HIGH)
(kHz)
200
(µs-V)
5
ERROR (%)
(V)
2.6
2.9
3.2
3.6
by the current-limit circuit, including threshold tolerance
a nd on-re s is ta nc e va ria tion. This me a ns tha t the
MOSFETs must be very well heatsinked. If short-circuit
protection without overload protection is enough, a nor-
±10
±10
300
3.3
2.5
1.8
400
±12.5
±12.5
mal I
value can be used for calculating component
LOAD
stresses.
550
Choose a Schottky diode D1 having a forward voltage
low enough to prevent the Q2 MOSFET body diode from
turning on during the dead time. As a general rule, a
diode having a DC current rating equal to 1/3 of the load
current is sufficient. This diode is optional, and if efficien-
cy isn’t critical it can be removed.
2
C
V
f I
LOAD
RSS BATT(MAX)
PD(switching) =
I
GATE
where C
and I
is the reverse transfer capacitance of Q1
is the peak gate-drive source/sink current (1A
RSS
GATE
Ap p lic a t io n Is s u e s
typical).
Dro p o u t P e rfo rm a n c e
The output voltage adjust range for continuous-conduc-
tion operation is restricted by the non-adjustable 500ns
(max) minimum off-time one-shot. For best dropout per-
formance, use the slowest (200kHz) on-time setting.
When working with low input voltages, the duty-factor
limit must be calculated using worst-case values for on
and off-times. Manufacturing tolerances and internal
For the low-side MOSFET, Q2, the worst-case power dis-
sipation always occurs at maximum battery voltage:
2
· R
LOAD DS(ON)
PD(Q2) = (1 - V
/ V
) · I
OUT
BATT(MAX)
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
but are not quite high enough to exceed the
LOAD(MAX)
20 ______________________________________________________________________________________
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0/MAX71
tor. In some cases, there may be no room for electrolyt-
V
BATT
ics, creating a need for a DC-DC design that uses noth-
ing but ceramics.
DH
The all-ceramic-capacitor application of Figure 7 has the
same basic performance as the 7A Standard Application
Circuit, but replaces the tantalum output capacitors with
ceramics. This design relies on having a minimum of
5mΩ parasitic PC board trace resistance in series with
the capacitor in order to reduce the ESR zero frequency.
This small amount of resistance is easily obtained by
locating the MAX1710/MAX1711 circuit two or three inch-
es away from the CPU, and placing all the ceramic
capacitors close to the CPU. Resistance values higher
tha n 5mΩ jus t imp rove the s ta b ility (whic h c a n b e
observed by examining the load-transient response
c ha ra c te ris tic a s s hown in the Typ ic a l Op e ra ting
Characteristics). Avoid adding excess PC board trace
resistance, as there’s an efficiency penalty. 5mΩ is suffi-
cient for the 7A circuit.
V
OUT
MAX1710
DL
R1
R2
FB
FBS
1k
GNDS
Figure 8. Setting V
with a Resistor-Divider
OUT
Outp ut ove rs hoot d e te rmine s the minimum outp ut
capacitance requirement. In this example, the switching
frequency has been increased to 550kHz and the induc-
tor value has been reduced to 0.5µH (compared to
300kHz and 2µH for the standard 7A circuit) in order to
minimize the energy transferred from inductor to capaci-
tor during load-step recovery. Even so, the amount of
overshoot is high enough (80mV) that for the MAX1710,
it’s wise to disable OVP or use the MAX1711 with its fixed
2.25V overvoltage protection threshold to avoid tripping
the fault latch (see the overshoot equation in the Output
Capacitor Selection section). The efficiency penalty for
operating at 550kHz is about 2% to 3%, depending on
the input voltage.
propagation delays introduce an error to the TON K-fac-
tor. This error is higher at higher frequencies (Table 5).
Also, keep in mind that transient response performance
of buck regulators operated close to dropout is poor,
and bulk output capacitance must often be added (see
V
SAG
equation in the Design Procedure).
Dropout Design Example: V
= 3V min, V
=
OUT
BATT
2V, f = 300kHz. The required duty is (V
+ V ) /
OUT
SW
(V
BATT
- V ) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The
SW
worst-case on-time is (V
+ 0.075) / V
· K =
OUT
BATT
2.075V / 3V · 3.35µs-V · 90% = 2.08µs. The IC duty-fac-
tor limitation is:
t
ON(MIN)
Two optional 1kΩ resistors are placed in series with FB
and FBS. These resistors prevent the negative output
volta g e s p ike (tha t re s ults from trip p ing OVP) from
pulling SHDN low via its internal ESD diode, which tends
to clear the fault latch, causing “hiccup” restarts.
DUTY =
= 2.08µs + 500ns = 80.6%
t
+ t
ON(MIN) OFF(MAX)
which meets the required duty.
Remember to include inductor resistance and MOSFET
S e t t in g V
w it h a Re s is t o r-Divid e r
OUT
on-state voltage drops (V ) when doing worst-case
SW
The output voltage can be adjusted with a resistor-
divider rather than the DAC if desired (Figure 8). The
drawback of this practice is that the on-time doesn’t
automatically receive correct compensation for changing
output voltage levels. This can result in variable switch-
ing frequency as the resistor ratio is changed and/or
excessive switching frequency. The equation for adjust-
ing the output voltage is:
dropout duty-factor calculations.
All-Ce ra m ic -Ca p a c it o r Ap p lic a t io n
Ceramic capacitors have advantages and disadvan-
tages. They have ultra-low ESR, are non-combustible,
are relatively small, and are nonpolarized. On the other
hand, they’re expensive and brittle, and their ultra-low
ESR characteristic can result in excessively high ESR
zero frequencies (affecting stability). In addition, they
can cause output overshoot when going abruptly from
full-load to no-load conditions, unless there are some
bulk tantalum or electrolytic capacitors in parallel to
absorb the stored energy in the induc-
R1
V
= V −1% 1+
FB
(
)
OUT
R2
______________________________________________________________________________________ 21
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V
IN
4.5V TO 5.5V
1µF
20Ω
C1
4 x 10µF/25V
1µF
V+ V
I
V
DD
LIM CC
SHDN
D0
ON/OFF
BST
DH
IRF7805
D1
D/A
INPUTS
D2
V
OUT
0.1µF
L1
0.5µH
1.6V AT 7A
D3
C2
D4**
MAX1710
MAX1711
LX
3 x 470µF
KEMET
T510
0.22µF
470pF
REF
CC
DL
IRF7805
PGND
0/MAX71
FB
V
CC
1k
GND
1k
TO REMOTE
LOAD
100k
GNDS
FBS
PGOOD
TON SKIP OVP*
* MAX1710 ONLY
** MAX1711 ONLY
Figure 9. 5V-Powered, 7A CPU Buck Regulator
where V is the currently selected DAC value. When
FB
decreases and isn’t compensated for by a change in on-
time. 3.3V is about the maximum limit to the practical
adjustment range; even at the slowest TON setting and
with the DAC set to 2V, the switching rate will exceed
600kHz.
using external resistors, FBS remote sensing is not rec-
ommended, but GNDS remote sensing is still possible.
Connect FBS to FB and GNDS to remote ground loca-
tion. In resistor-adjusted circuits, the DAC code should
be set as close as possible to the actual output voltage
so that the switching frequency doesn’t become exces-
sive. For highest accuracy, use the MAX1710 when
The trip threshold for output overvoltage protection
scales with the nominal output voltage setting.
adjusting V
with external resistors. The MAX1710 FB
2 -S t a g e (5 V-P o w e re d ) No t e b o o k CP U
Bu c k Re g u la t o r
OUT
node has very high impedance, while the MAX1711 has
a 180kΩ ±35% FB impedance, which degrades V
accuracy.
OUT
The most efficient and overall cost-effective solution for
stepping down a high-voltage battery to very low output
voltage is to use a single-stage buck regulator that’s
powered directly from the battery. However, there may
be situations where the battery bus can’t be routed near
the CPU, or where space constraints dictate the smallest
possible local DC-DC converter. In such cases, the 5V-
powered circuit of Figure 9 may be appropriate. The
reduced input voltage allows a higher switching frequen-
cy and a much smaller inductor value.
Ad ju s t in g V
Ab o ve 2 V
OUT
The feed-forward circuit that makes the on-time depen-
dent on battery voltage maintains a nearly constant
switching frequency as V , I
are changed. This works extremely well as long as FB is
connected directly to the output.
, and the DAC code
IN LOAD
When the output is adjusted higher than 2V with a resis-
tor-divider, the switching frequency can be increased to
relatively unreasonable levels as the actual off-time
22 ______________________________________________________________________________________
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0/MAX71
Dyn a m ic DAC Co d e Ch a n g e s
(MAX1 7 1 1 )
Hig h -P o w e r, Dyn a m ic a lly
Ad ju s t a b le CP U Ap p lic a t io n
Changing the output voltage dynamically by switching
DAC c od e s “on-the -fly” c a n b e us e d to he lp ma ke
power-savings/performance trade-offs in the host sys-
tem. Several important design issues arise from this
practice.
The MAX1711 V
regulator of Figure 10 is designed
CORE
to have its output voltage switched between 1.3V and
1.45V in less than 100µs, while causing a minimum level
of input surge current. To this end, the output capacitors
were selected for having the correct value to a) support
the needed ESR, b) prevent excess load-recovery over-
shoot, and c) minimize input surge currents.
First, know that attempting to slew the output upward
quickly causes large current surges at the battery as the
IC goes into output current limiting during the transition.
Surge currents can be controlled either by counting the
DAC code slowly (50kHz or slower rate suggested), or
The optional 74HC86 exclusive-OR gate detects code
transitions on each of the four most-significant DAC
inputs. The transition detector output goes to a precision
pulse stretcher, a timer which extends the pulse for 75µs
(nominal). This signal then feeds three circuits: the
power-good detector, the SKIP input, and the ILIM cur-
rent-limit control input, thus reducing the current-limit
threshold during the transition interval (in order to reduce
b a tte ry c urre nt s urg e s ). Like wis e , SKIP g oing hig h
asserts forced PWM mode in order to drag the output
voltage down to the new value. Forced PWM mode is
incompatible with good light-load efficiency due to
inductor-current recirculation losses and gate-drive loss-
es. Therefore, SKIP is driven high only during the 100µs
max transition interval.
by modulating the I
current-limit threshold.
LIM
The DAC inputs must be driven quickly to the new value
so the device doesn’t wrongly interpret a disallowed
DAC code from the transitory value. Use 100ns maxi-
mum rise and fall times.
Selecting the output capacitors in dynamically adjusted
V
CORE
applications can be tricky due to trade-offs
between capacitor capacity and ESR. In other words, if
the capacitor has sufficiently low ESR to meet the load-
transient response specification, its large capacity may
cause excessive input surge currents. On the other
hand, a purely ceramic capacitor may not have enough
capacity to prevent overvoltage during the transition from
full- to no-load condition (see the overshoot equation
under Output Capacitor Selection). It may be necessary
to mix capacitor types or use specialized capacitors
such as those shown in Figure 7 in order to achieve the
required ESR while staying within the min/max capaci-
tance value window.
The power-good output signal is the logical OR of the
75µs timer signal and the MAX1711 PGOOD signal. The
internal PGOOD detector circuit monitors only output
und e rvolta g e ; PGOOD will p rob a b ly g o low d uring
upward transitions, but not downward. The final power-
good output will always go low for at least 75µs due to
the timer signal.
Load current capability is 15A peak and 12A continuous
ove r a 10V to 22V inp ut ra ng e . All thre e MOSFETs
require good heatsinking. See the MAX1711 EV Kit
Manual for a complete bill of materials.
If the minimum load is very light, it may be necessary to
assert forced PWM mode (via SKIP) during the transition
period to guarantee some output sink current capability.
Otherwise, the output voltage won’t ramp downwards
until pulled down by external load current.
P C Bo a rd La yo u t Gu id e lin e s
Careful PC board layout is critical to achieving low
switching losses and clean, stable operation. The switch-
ing power stage requires particular attention (Figure 11).
If possible, mount all of the power components on the
top side of the board with their ground terminals flush
against one another. Follow these guidelines for good
PC board layout:
Using forced PWM mode repeatedly to ensure sink cur-
rent capability can have side effects, however. The ener-
gy taken from the output by the synchronous rectifier
isn’t lost, but is instead returned to the input. If the fre-
quency of the high-to-low output voltage transition is high
enough, efficiency will be degraded by the resistive “fric-
tion” losses associated with shuttling energy between
input and output capacitors. Also, if the output is being
overdriven by an external source (such as an external
docking-station power supply), forced PWM mode may
cause the battery voltage to become pumped up, possi-
bly overvoltaging the battery.
•
Keep the high-current paths short, especially at the
ground terminals. This practice is essential for stable,
jitter-free operation.
•
Tie GND and PGND together close to the IC. Carefully
follow the grounding instructions under step 4 of the
Layout Procedure.
______________________________________________________________________________________ 23
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+5V INPUT
V
BATT
6 x 10µF/25V CERAMIC
10V TO 22V
0.1µF
1µF
20Ω
7
15
1
V
DD
V+
V
CC
2Ω
22
24
CMPSH3
BST
0.22µF
DH
IRF7805
REF
9
5
470pF
0.1µF
MAX1711
CC
23
13
10
LX
DL
GND
1µH/20A
OUTPUT
+1.5V AT 15A
ON/OFF
LSB
2
20
19
18
17
16
10X
220µF
4V
20µF
CERAMIC
SHDN
D0
14
PGND
2 x IRF7805
OS-CON
D1
DAC
3
0/MAX71
D2
FB
INPUTS
4
FBS
D3
11
12
GNDS
PGOOD
SKIP
MSB
1k
D4
8
21
TON
N.C.
I
LIM
6
40k
1%
2N7002
POWERGOOD
200k
1%
2N7002
+3.3V
0.1µF
TRANSITION DETECTOR
100k
1%
49.9k
1%
3M
12
14
11
A4
B4
V
CC
1k
13
Y4
Y3
100k
1%
1000pF
1N4148
9
A3
B3
1k
10
8
6
3
MAX986
820pF
5%
1000pF
1N4148
+3.3V
4
5
47CH86
2N7002
30k
A2
B2
1k
Y2
Y1
30k
1000pF
1N4148
1N4148
1
2
A1
B1
1k
GND
7
100k
100k
2N7002
1000pF
2N7002
TIMER BLOCK
Figure 10. 15A Dynamically Adjustable Notebook CPU Supply with Battery-Surge Current Limiting
24 ______________________________________________________________________________________
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V
BATT
GND IN
ALL ANALOG GROUNDS
CONNECT TO GND ONLY
VIA TO PGND
NEAR Q2 SOURCE
MAX1710
MAX1711
VIA TO GNDS
V
CC
CIN
GND
OUT
CC
Q1
REF
D1
Q2
COUT
V
DD
I
LIM
V
OUT
GND
VIA TO SOURCE
OF Q2
CONNECT GND TO PGND
BENEATH IC, 1 POINT ONLY.
SPLIT ANALOG GND PLANE AS SHOWN.
VIA TO FBS
L1
VIA TO FB
NEAR COUT+
VIA TO LX
NOTES: "STAR" GROUND IS USED.
D1 IS DIRECTLY ACROSS Q2.
INDUCTOR DISCHARGE PATH HAS LOW DC RESISTANCE
Figure 11. Power-Stage PC Board Layout Example
•
Keep the power traces and load connections short.
This practice is essential for high efficiency. The use
of thick copper PC boards (2 oz. vs. 1 oz.) can en-
hance full-load efficiency by 1% or more. Correctly
routing PC board traces is a difficult task that must be
approached in terms of fractions of centimeters,
where a single milliohm of excess trace resistance
causes a measurable efficiency penalty.
made longer than the discharge path. For example,
it’s better to allow some extra distance between the
input capacitors and the high-side MOSFET than to
allow distance between the inductor and the low-side
MOSFET or between the inductor and the output filter
capacitor.
•
Ensure that the FB connection to C
is short and
OUT
direct. However, in some cases it may be desirable to
deliberately introduce some trace length between the
FB inductor node and the output filter capacitor (see
the All-Ceramic-Capacitor Application section).
•
•
LX and PGND connections to Q2 for current limiting
must be made using Kelvin sense connections in
order to guarantee the current-limit accuracy. With
SO-8 MOSFETs, this is best done by routing power to
the MOSFETs from outside using the top copper
layer, while tying in PGND and LX inside (underneath)
the SO-8 package.
•
•
Route high-speed switching nodes away from sensi-
tive analog areas (CC, REF, ILIM).
Make all pin-strap control input connections (SKIP,
ILIM, etc.) to GND or V rather than PGND or V
.
CC
DD
When trade-offs in trace lengths must be made, it’s
preferable to allow the inductor charging path to be
______________________________________________________________________________________ 25
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where all the high-power components go; the PGND
La yo u t P ro c e d u re
1) Place the power components first, with ground termi-
nals adjacent (Q2 source, CIN-, COUT-, D1 anode). If
possible, make all these connections on the top layer
with wide, copper-filled areas.
plane, where the PGND pin and V bypass capaci-
DD
tor go; and an analog GND plane, where sensitive
analog components go. The analog ground plane
and PGND plane must meet only at a single point
directly beneath the IC. These two planes are then
connected to the high-power output ground with a
2) Mount the controller IC adjacent to MOSFET Q2,
preferably on the back side opposite Q2 in order to
keep LX-PGND current-sense lines and the DL gate-
drive line short and wide. The DL gate trace must be
short and wide, measuring 10 to 20 squares (50 to
100 mils wide if the MOSFET is 1 inch from the con-
troller IC).
short connection from V
cap/PGND to the source
DD
of the low-side MOSFET, Q2 (the middle of the star
ground). This point must also be very close to the out-
put capacitor ground terminal.
5) Connect the output power planes (V
and system
CORE
ground planes) directly to the output filter capacitor
positive and negative terminals with multiple vias.
Place the entire DC-DC converter circuit as close to
the CPU as is practical.
3) Group the gate-drive components (BST diode and
capacitor, V
bypass capacitor) together near the
DD
controller IC.
4) Make the DC-DC controller ground connections as
shown in Figure 11. This diagram can be viewed as
having three separate ground planes: output ground,
0/MAX71
P in Co n fig u ra t io n s
TOP VIEW
TOP VIEW
V+
SHDN
FB
1
2
3
4
5
6
7
8
9
24 DH
23 LX
22 BST
21 SKIP
20 D0
19 D1
18 D2
17 D3
16 D4
V+
SHDN
FB
1
2
3
4
5
6
7
8
9
24 DH
23 LX
22 BST
21 SKIP
20 D0
19 D1
18 D2
17 D3
16 OVP
FBS
FBS
MAX1711
MAX1710
CC
CC
ILIM
ILIM
V
CC
V
CC
TON
REF
TON
REF
GND 10
GNDS 11
PGOOD 12
15 V
DD
GND 10
GNDS 11
PGOOD 12
15 V
DD
14 PGND
13 DL
14 PGND
13 DL
QSOP
QSOP
26 ______________________________________________________________________________________
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0/MAX71
P a c k a g e In fo rm a t io n
______________________________________________________________________________________ 27
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NOTES
0/MAX71
28 ______________________________________________________________________________________
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