MAX1711EEG-T_技术文档

19-4781; Rev 1; 7/00

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

General Description

Features

The MAX1710/MAX1711 step-down controllers are

intended for core CPU DC-DC converters in notebook

computers. They feature a triple-threat combination of

ultra-fast transient response, high DC accuracy, and

high efficiency needed for leading-edge CPU core

power supplies. Maxim’s proprietary Quick-PWM™

quick-response, constant-on-time PWM control scheme

handles wide input/output voltage ratios with ease and

provides 100ns “instant-on” response to load transients

while maintaining a relatively constant switching fre-

quency.

o Ultra-High Efficiency

o No Current-Sense Resistor (Lossless I

)

LIMIT

o Quick-PWM with 100ns Load-Step Response

1ꢀ ꢁ Accuracy over Line and Load

o

OUT

o 4-Bit On-Board DAC (MAX1710)

o 5-Bit On-Board DAC (MAX1711/MAX1712)

o 0.925ꢁ to 2ꢁ Output Adjust Range

(MAX1711/MAX1712)

High DC precision is ensured by a 2-wire remote-sens-

ing scheme that compensates for voltage drops in both

the ground bus and supply rail. An on-board, digital-to-

analog converter (DAC) sets the output voltage in com-

pliance with Mobile Pentium II^®CPU specifications.

o 2ꢁ to 28ꢁ Battery Input Range

o 200/300/400/550kHz Switching Frequency

o Remote GND and ꢁ

Sensing

OUT

o Over/Undervoltage Protection

o 1.7ms Digital Soft-Start

The MAX1710 achieves high efficiency at a reduced

cost by eliminating the current-sense resistor found in

traditional current-mode PWMs. Efficiency is further

enhanced by an ability to drive very large synchronous-

rectifier MOSFETs.

o Drive Large Synchronous-Rectifier FETs

o 2ꢁ 1ꢀ Reference Output

o Power-Good Indicator

Single-stage buck conversion allows these devices to

directly step down high-voltage batteries for the highest

possible efficiency. Alternatively, 2-stage conversion

(stepping down the +5V system supply instead of the

battery) at a higher switching frequency allows the mini-

mum possible physical size.

o Small 24-Pin QSOP Package

Ordering Information

PART

TEMP. RANGE

-40°C to +85°C

PIN-PACKAGE

MAX1710EEG

MAX1711EEG

24 QSOP

The MAX1710/MAX1711 are identical except that the

MAX1711 have 5-bit DACs and the MAX1710 has a 4-

bit DAC. Also, the MAX1711 has a fixed overvoltage

24 QSOP

protection threshold at V

= 2.25V and undervoltage

OUT

Minimal Operating Circuit

protection at V

= 0.8V whereas the MAX1710 has

OUT

variable thresholds that track V

. The MAX1711 is

BATTERY

4.5V TO 28V

OUT

intended for applications where the DAC code may

change dynamically.

+5V INPUT

V

OVP*

V

CC

DD

V+

Applications

SHDN

FBS

Notebook Computers

Docking Stations

BST

DH

ILIM

GNDS

OUTPUT

0.925V TO 2V

CPU Core DC-DC Converters

(MAX1711/MAX1712)

MAX1710

MAX1711

MAX1712

Single-Stage (BATT to V

Converters

CORE)

REF

CC

LX

DL

Two-Stage (+5V to V

) Converters

CORE

D0

PGND

D1

D/A

INPUTS

Quick-PWM is a trademark of Maxim Integrated Products.

Mobile Pentium II is a registered trademark of Intel Corp.

D2

FB

D3

SKIP

D4**

GND

*MAX1710 ONLY

**MAX1711/MAX1712 ONLY

Pin Configurations appear at end of data sheet.

________________________________________________________________ Maxim Integrated Products

1

For price, delivery, and to place orders, please contact Maxim Distribution at 1-888-629-4642,

or visit Maxim’s website at www.maxim-ic.com.

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

ABSOLUTE MAXIMUM RATINGS

V+ to GND..............................................................-0.3V to +30V

DH to LX .....................................................-0.3V to (BST + 0.3V)

LX to BST..................................................................-6V to +0.3V

REF Short Circuit to GND...........................................Continuous

V

, V

to GND .....................................................-0.3V to +6V

CC DD

PGND to GND..................................................................... 0.3V

SHDN, PGOOD to GND ...........................................-0.3V to +6V

OVP, ILIM, FB, FBS, CC, REF, D0–D4,

Continuous Power Dissipation (T = +70°C)

A

24-Pin QSOP (derate 9.5mW/°C above +70°C)..........762mW

Operating Temperature Range ...........................-40°C to +85°C

Junction Temperature......................................................+150°C

Storage Temperature Range.............................-65°C to +165°C

Lead Temperature (soldering, 10s) .................................+300°C

GNDS, TON to GND..............................-0.3V to (V

SKIP to GND (Note 1).................................-0.3V to (V

DL to PGND................................................-0.3V to (V

+ 0.3V)

CC

DD

BST to GND............................................................-0.3V to +36V

Note 1: SKIP may be forced below -0.3V, temporarily exceeding the absolute maximum rating, for the purpose of debugging proto-

type breadboards using the no-fault test mode. Limit the current drawn to -5mA maximum.

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V

= 15V, V

= V

= 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted.)

DD A

BATT

CC

PARAMETER

CONDITIONS

MIN

2

TYP

MAX

28

UNIT

Battery voltage, V+

Input Voltage Range

V

4.5

-1

5.5

1

CC, DD

DAC codes from 1.3V to 2V

V

BATT

= 4.5V to 28V, includes

DC Output Voltage Accuracy

%

DAC codes from 0.925V

to 1.275V

load regulation error

-1.2

1.2

Load Regulation Error

Remote-Sense Voltage Error

Line Regulation Error

I

= 0 to 7A

9

3

5

mV

µA

LOAD

FB - FBS or GNDS - GND = 0 to 25mV

= 4.5V to 5.5V, V = 4.5V to 28V

V

CC

BATT

FB Input Bias Current

FB (MAX1710 only) or FBS

-0.2

130

-1

0.2

240

1

FB Input Resistance

(MAX1711/MAX1712)

180

kΩ

GNDS Input Bias Current

Soft-Start Ramp Time

µA

ms

1.7

160

200

290

425

400

600

<1

Rising edge of SHDN to full I

LIM

TON = GND (550kHz)

TON = REF (400kHz)

TON = open (300kHz)

140

175

260

380

180

225

320

470

500

950

5

V

= 24V,

BATT

On-Time

FB = 2V

(Note 2)

ns

TON = V

(200kHz)

CC

Minimum Off-Time

(Note 2)

ns

µA

Quiescent Supply Current (V

)

Measured at V , FB forced above the regulation point

CC

Measured at V , FB forced above the regulation point

DD

Quiescent Battery Supply Current Measured at V+

25

40

Shutdown Supply Current (V

)

<1

5

SHDN = 0

CC

DD

<1

5

Shutdown Battery Supply

Current

<1

2

5

µA

SHDN = 0, measured at V+ = 28V, V

= V

= 0 or 5V

DD

CC

Reference Voltage

V

CC

= 4.5V to 5.5V, no external REF load

1.98

10

2.02

0.01

V

Reference Load Regulation

REF Sink Current

I

= 0 to 50µA

REF

REF in regulation

µA

V

REF Fault Lockout Voltage

Falling edge, hysteresis = 40mV

1.6

2

_______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V

= 15V, V

= V

= 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted.)

DD A

BATT

CC

PARAMETER

CONDITIONS

MIN

10.5

2.21

TYP

12.5

2.25

MAX

14.5

2.29

UNIT

%

With respect to unloaded output voltage (MAX1710)

(MAX1711/MAX1712)

Overvoltage Trip Threshold

V

Overvoltage Fault Propagation

Delay

FB forced 2% above trip threshold

1.5

µs

With respect to unloaded output voltage (MAX1710)

(MAX1711/MAX1712)

65

0.76

70

0.8

75

0.84

%

V

Output Undervoltage Protection

Threshold

Output Undervoltage Protection

Time

10

90

30

ms

mV

From SHDN signal going high

Current-Limit Threshold

(Positive Direction, Fixed)

LX to PGND, ILIM tied to V

100

110

CC

R

= 100kΩ

= 400kΩ

40

50

60

LIM

Current-Limit Threshold

(Positive Direction, Adjustable)

LX to PGND

mV

170

200

230

LIM

Current-Limit Threshold

(Negative Direction)

LX to PGND, T = +25°C

A

-150

-120

-80

Current-Limit Threshold

(Zero Crossing)

LX to PGND

3

PGOOD Propagation Delay

PGOOD Output Low Voltage

PGOOD Leakage Current

Thermal Shutdown Threshold

FB forced 2% below PGOOD trip threshold, falling edge

1.5

µs

V

I

= 1mA

0.4

1

SINK

High state, forced to 5.5V

Hysteresis = 10°C

µA

°C

150

V

Undervoltage Lockout

Rising edge, hysteresis = 20mV,

PWM disabled below this level

CC

4.1

4.4

5

V

Ω

Threshold

DH Gate-Driver On-Resistance

BST-LX forced to 5V

DL, high state

DL Gate-Driver On-Resistance

(Pullup)

5

DL Gate-Driver On-Resistance

(Pulldown)

DL, low state

0.5

1

1.7

Ω

DH Gate-Driver Source/Sink

Current

DH forced to 2.5V, BST-LX forced to 5V

A

DL Gate-Driver Sink Current

DL forced to 2.5V

DL rising

3

1

A

DL Gate-Driver Source Current

35

26

Dead Time

ns

mA

%

DH rising

SKIP Input Current Logic

Threshold

To enable no-fault mode, T = +25°C

A

-1.5

-0.1

-3

Measured at FB with respect to unloaded output voltage,

falling edge, hysteresis = 1%

PGOOD Trip Threshold

-8

-5

Logic Input High Voltage

Logic Input Low Voltage

Logic Input Current

2.4

V

D0–D4, SHDN, SKIP, OVP

SHDN, SKIP, OVP

0.8

1

-1

3

µA

Logic Input Pullup Current

D0–D4, each forced to GND

5

10

_______________________________________________________________________________________

3

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V

= 15V, V

= V

= 5V, SKIP = GND, T = 0°C to +85°C, unless otherwise noted.)

DD A

BATT

CC

PARAMETER

Level

CONDITIONS

MIN

TYP

MAX

UNIT

V

TON V

TON logic input high level

V

- 0.4

CC

TON Float Voltage

TON logic input upper-midrange level

TON logic input lower-midrange level

TON logic input low level

3.15

3.85

2.35

0.5

3

V

TON Reference Level

TON GND Level

1.65

V

TON Logic Input Current

TON only, forced to GND or V

-3

µA

CC

ELECTRICAL CHARACTERISTICS

(Circuit of Figure 1, V

= 15V, V = V

= 5V, SKIP = GND, T = -40°C to +85°C, unless otherwise noted.) (Note 3)

DD A

BATT

CC

PARAMETER

CONDITIONS

MIN

2

TYP

MAX

28

UNIT

V

Battery voltage, V+

Input Voltage Range

V

4.5

-1.5

5.5

1.5

CC, DD

DAC codes from 1.32V to 2V

%

V

BATT

= 4.5V to 28V, for all

DC Output Voltage Accuracy

D/A codes, includes load

regulation error

DAC codes from 0.925V to

1.275V

-1.7

1.7

%

TON = GND (550kHz)

140

175

260

380

180

225

320

470

500

950

2.02

15

V

= 24V,

BATT

TON = REF (400kHz)

TON = open (300kHz)

On-Time

FB = 2V

(Note 2)

ns

TON = V

(200kHz)

CC

Minimum Off-Time

(Note 2)

ns

µA

V

Quiescent Supply Current (V

)

Measured at V , FB forced above the regulation point

CC

Reference Voltage

V

CC

= 4.5V to 5.5V, no external REF load

1.98

10

With respect to unloaded output voltage (MAX1710)

(MAX1711/MAX1712)

%

V

Overvoltage Trip Threshold

2.20

65

2.30

75

With respect to unloaded output voltage (MAX1710)

(MAX1711/MAX1712)

%

V

Output Undervoltage

Protection Threshold

0.75

0.85

Current-Limit Threshold

(Positive Direction, Fixed)

LX to PGND, ILIM tied to V

85

115

mV

V

CC

R

= 100kΩ

35

65

LIM

Current-Limit Threshold

(Positive Direction, Adjustable)

LX to PGND

= 400kΩ

160

240

V

CC

Undervoltage Lockout

Rising edge, hysteresis = 20mV, PWM disabled below

this level

4.1

2.4

4.4

Threshold

Logic Input High Voltage

Logic Input Low Voltage

Logic Input Current

V

D0–D4, SHDN, SKIP, OVP

SHDN, SKIP, OVP

0.8

1

-1

3

µA

Logic Input Pullup Current

D0–D4, each forced to GND

10

4

_______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, V

= 15V, V = V

= 5V, SKIP = GND, T = -40°C to +85°C, unless otherwise noted.) (Note 3)

DD A

BATT

CC

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNIT

Measured at FB with respect to unloaded output voltage,

falling edge, hysteresis = 1%

PGOOD Trip Threshold

-8.5

-2.5

%

PGOOD Output Low Voltage

PGOOD Leakage Current

I

= 1mA

0.4

1

V

SINK

High state, forced to 5.5V

µA

Note 2: On-Time and Off-Time specifications are measured from 50% point to 50% point at the DH pin with LX forced to 0V, BST

forced to 5V, and a 250pF capacitor connected from DH to LX. Actual in-circuit times may differ due to MOSFET switching

speeds.

Note 3: Specifications from -40°C to 0°C are guaranteed but not production tested.

__________________________________________Typical Operating Characteristics

(7A CPU supply circuit of Figure 1, T = +25°C, unless otherwise noted.)

A

EFFICIENCY vs. LOAD CURRENT

(V = 2.0V, f = 300kHz)

EFFICIENCY vs. LOAD CURRENT

(V = 1.6V, f = 300kHz)

EFFICIENCY vs. LOAD CURRENT

(V = 1.3V, f = 300kHz)

O

100

90

80

70

60

50

40

100

90

80

70

60

50

40

100

90

80

70

60

50

40

V

IN

= 4.5V

V

IN

= 4.5V

V = 4.5V

IN

V

IN

= 7V

V

IN

= 7V

V

IN

= 7V

V

IN

= 15V

V

IN

= 15V

V

IN

= 15V

V

IN

= 24V

V

IN

= 24V

V

IN

= 24V

0.01

0.1

1

10

0.01

0.1

1

10

0.01

0.1

1

10

LOAD CURRENT (A)

FREQUENCY vs. LOAD CURRENT

EFFICIENCY vs. LOAD CURRENT

FREQUENCY vs. INPUT VOLTAGE

(I = 7A)

(V = 1.6V)

O

(V = 1.6V, f = 550kHz)

O

350

300

250

200

150

100

50

100

90

80

70

60

50

40

320

318

316

314

312

310

308

306

304

302

300

V

= 4.5V

IN

V

= 15V, PWM MODE

IN

V

= 7V

IN

V

IN

= 4.5V, SKIP MODE

V

= 2.0V

O

V

= 1.6V

O

V

IN

= 15V

V

IN

= 15V, SKIP MODE

V

= 24V

IN

TON = OPEN

1 10

TON = OPEN

25 30

0

0.01

0.1

1

10

0.01

0.1

LOAD CURRENT (A)

0

5

10

15

20

LOAD CURRENT (A)

INPUT VOLTAGE (V)

_______________________________________________________________________________________

5

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

_____________________________Typical Operating Characteristics (continued)

(7A CPU supply circuit of Figure 1, T = +25°C, unless otherwise noted.)

A

CURRENT-LIMIT TRIP POINT

vs. TEMPERATURE

FREQUENCY vs. TEMPERATURE

ON-TIME vs. TEMPERATURE

(V = 15V, V = 2.0V)

IN

O

474

472

470

468

466

464

462

460

458

456

30

25

20

15

10

5

315

310

305

300

295

290

285

I

O

= 1A

I

= 7A

= 4A

O

I

= 400kΩ

LIM

I

= V

CC

LIM

I

O

= 4A OR 7A

I

= 100kΩ

LIM

TON = OPEN

-60 -40 -20

I

= 1A

O

0

-60 -40 -20

0

20 40 60 80 100

-60 -40 -20

0

20 40 60 80 100

0

20 40 60 80 100

TEMPERATURE (°C)

INDUCTOR CURRENT PEAKS AND

VALLEYS vs. INPUT VOLTAGE

(AT CURRENT-LIMIT POINT)

CONTINUOUS TO DISCONTINUOUS

INDUCTOR CURRENT POINT

vs. INPUT VOLTAGE

NO-LOAD SUPPLY CURRENTS

vs. INPUT VOLTAGE

(SKIP MODE, f = 300kHz)

14.0

13.5

13.0

12.5

12.0

11.5

11.0

10.5

10.0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

I

CC

V

O

= 2.0V

I

PEAK

V

O

= 1.6V

V

O

= 1.3V

I

BATT

I

VALLEY

15

I

DD

0

5

10

20

25

30

0

5

10

15

20

25

30

0

5

10

15

20

25

30

INPUT VOLTAGE (V)

NO-LOAD SUPPLY CURRENTS

vs. INPUT VOLTAGE

(PWM MODE, f = 300kHz)

NO-LOAD SUPPLY CURRENTS

vs. INPUT VOLTAGE

(PWM MODE, f = 550kHz)

NO-LOAD SUPPLY CURRENTS

vs. INPUT VOLTAGE

(SKIP MODE, f = 550kHz)

20

18

16

14

12

10

8

20

18

16

14

12

10

8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

I

DD

I

CC

I

DD

I

BAT

I

BATT

I

BAT

6

4

2

I

2

I

CC

DD

0

5

10

15

20

25

30

0

5

10

15

20

25

30

0

5

10

15

20

25

30

INPUT VOLTAGE (V)

6

_______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

_____________________________Typical Operating Characteristics (continued)

(7A CPU supply circuit of Figure 1, T = +25°C, unless otherwise noted.)

A

LOAD-TRANSIENT RESPONSE

(WITH INTEGRATOR)

LOAD-TRANSIENT RESPONSE

(WITHOUT INTEGRATOR)

(WITH INTEGRATOR)

A

B

A

B

A

B

10µs/div

V

= 15V, V = 1.6V, I = 0A TO 7A

OUT

V

= 15V, V = 1.6V, I = 30mA TO 7A

OUT

V

= 15V, V = 1.6V, I = 30mA TO 7A

OUT

IN

O

IN

O

IN

O

A = V , AC-COUPLED, 50mV/div

B = INDUCTOR CURRENT, 5A/div

LOAD-TRANSIENT RESPONSE

(WITH INTEGRATOR)

LOAD-TRANSIENT RESPONSE

(WITH INTEGRATOR)

STARTUP WAVEFORM

A

B

C

20µs/div

500µs/div

V

= 4.5V, V = 2V, I = 30mA TO 7A

OUT

V = 4.5V, V = 1.3V, I = 30mA TO 7A

IN O O

A = SHDN

IN

O

A = V , AC-COUPLED, 50mV/div

B = V , 0.5V/div

OUT

B = INDUCTOR CURRENT, 5A/div

C = DL, 10V/div

B = INDUCTOR CURRENT, 5A/div

C = DL, 10V/div

C = INDUCTOR CURRENT, 5A/div

_______________________________________________________________________________________

7

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

_____________________________Typical Operating Characteristics (continued)

(7A CPU supply circuit of Figure 1, T = +25°C, unless otherwise noted.)

A

OUTPUT OVERLOAD WAVEFORM

SHUTDOWN WAVEFORM

LOAD-TRANSIENT RESPONSE

CERAMIC C

OUT

A

B

A

B

C

A

B

D

C

50µs/div

5µs/div

= 1.6V, V = 15V, C

V

= 1.6V

IN

L = 0.7µH, V

= 47µF (x4), f = 550kHz

OUT

IN

OUT

V = 15V, V = 1.6V, I = 7A

IN 0 0

A = V , AC-COUPLED, 2V/div

A = V , AC-COUPLED, 100mV/div

OUT

A = V , 0.5V/div

OUT

B = V , 0.5V/div

OUT

B = INDUCTOR CURRENT, 5A/div

C = DL, 5V/div

B = INDUCTOR CURRENT, 5A/div

C = INDUCTOR CURRENT, 5A/div

C = SHDN, 2V/div

D = DL, 5V/div

Pin Description

NAME

FUNCTION

Battery Voltage Sense Connection. V+ is used only for PWM one-shot timing. DH on-time is inversely propor-

tional to V+ input voltage over a range of 2V to 28V.

1

2

3

V+

Shutdown Control Input, active low. SHDN cannot withstand the battery voltage. In shutdown mode, DL is

SHDN

forced to V

in order to enforce overvoltage protection, even when powered down (unless OVP is high).

DD

Fast Feedback Input, normally connected to V

. FB is connected to the bulk output filter capacitors local-

OUT

FB

ly at the power supply. An external resistor-divider can optionally set the output voltage.

Feedback Remote-Sense Input, normally connected to V directly at the load. FBS internally connects to

OUT

4

FBS

the integrator that fine tunes the DC output voltage. Tie FBS to V

to disable all three integrator amplifiers.

CC

Tie FBS to FB (or disable the integrators) when externally adjusting the output voltage with a resistor-divider.

Integrator Capacitor Connection. Connect a 100pF to 1000pF (470pF typical) capacitor to GND to set the

integration time constant.

5

6

CC

Current-Limit Threshold Adjustment. Connects to an external resistor to GND. The LX-PGND current-limit

threshold defaults to +100mV if ILIM is tied to V . The current-limit threshold is 1/10 of the voltage forced at

ILIM

CC

✕

ILIM. In adjustable mode, the threshold is V = R

5µA/10.

TH

LIM

Analog Supply Voltage Input for PWM Core, 4.5V to 5.5V. Bypass V

capacitor.

to GND with a 0.1µF minimum

CC

7

8

V

CC

On-Time Selection Control Input. This is a four-level input that sets the K factor to determine DH on-time.

GND = 550kHz, REF = 400kHz, open = 300kHz, ꢁ = 200kHz.

TON

REF

CC

2.0V Reference Output. Bypass REF to GND with a 0.22µF minimum capacitor. REF can source 50µA for

external loads. Loading REF degrades FB accuracy according to the REF load-regulation error

(see Electrical Characteristics).

9

8

_______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

Pin Description (continued)

NAME

FUNCTION

10

GND

Analog Ground

Ground Remote-Sense Input, normally connected to ground directly at the load. GNDS internally con-

nects to the integrator that fine tunes the ground offset voltage.

11

GNDS

12

13

14

15

PGOOD

DL

Open-Drain Power-Good Output

Low-Side Gate-Driver Output, swings 0 to V

DD

PGND

Power Ground. Also used as the inverting input for the current-limit comparator.

Supply Voltage Input for the DL Gate Driver, 4.5V to 5.5V

V

DD

16

Overvoltage-Protection Disable Control Input (Table 4). GND = normal operation and overvoltage

OVP

(MAX1710)

protection active, V = overvoltage protection disabled.

CC

16

(MAX1711/

MAX1712)

D4

DAC Code Input, MSB. 5µA internal pullup to V

(Tables 1, 2, and 3).

CC

17

18

19

20

D3

D2

D1

D0

DAC Code Input. 5µA internal pullup to V

DAC Code Input. 5µA internal pullup.

.

CC

DAC Code Input LSB. 5µA internal pullup.

Low-Noise-Mode Selection Control Input. Low-noise forced-PWM mode causes inductor current

recirculation at light loads and suppresses pulse-skipping operation. Normal operation prevents

current recirculation. SKIP can also be used to disable both overvoltage and undervoltage protection

21

22

SKIP

circuits and clear the fault latch (Figure 6). GND = normal operation, V

= low-noise mode. Do not

CC

leave SKIP floating.

Boost Flying-Capacitor Connection. An optional resistor in series with BST allows the DH pullup

current to be adjusted (Figure 5). This technique of slowing the LX rise time can be used to prevent

accidental turn-on of the low-side MOSFET due to excessive gate-drain capacitance.

BST

Inductor Connection. LX serves as the lower supply rail for the DH high-side gate driver. Also used

for the noninverting input to the current-limit comparator, as well as the skip-mode zero-crossing com-

parator.

23

24

LX

DH

High-Side Gate-Driver Output. Swings LX to BST.

Standard Application Circuit

Detailed Description

The standard application circuit (Figure 1) generates a

low-voltage, high-power rail for supplying up to 7A to the

The MAX1710/MAX1711/MAX1712 buck controllers are

targeted for low-voltage, high-current CPU power sup-

plies for notebook computers. CPU cores typically exhib-

it 0A to 10A or greater load steps when the clock is

throttled. The proprietary Quick-PWM pulse-width modu-

lator in the MAX1710/MAX1711/MAX1712 is specifically

designed for handling these fast load steps while main-

taining a relatively constant operating frequency and

inductor operating point over a wide range of input volt-

ages. The Quick-PWM architecture circumvents the poor

load-transient timing problems of fixed-frequency cur-

core CPU V

in a notebook computer. This DC-DC

CC

converter steps down a battery or AC adapter voltage to

sub-2V levels with high efficiency and accuracy, and

represents a good compromise between size, efficiency,

and cost.

See the MAX1710 EV kit manual for a list of components

and suppliers.

_______________________________________________________________________________________

9

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

V

BATT

4.5V TO 28V

+5V

BIAS SUPPLY

C5

1µF

C6

1µF

R1

20Ω

C1 3 x 10µF/30V

15

7

D2

CMPSH-3

V

DD

CC

1

22

24

V+

BST

DH

PANASONIC

ON/OFF

2

ETQP6F2R0HFA

CONTROL

SHDN

SKIP

Q1

L1

2µH

V

OUT

21

1.25V TO 2V AT 7A (MAX1710)

0.925V TO 2V AT 7A (MAX1711)

1.1V TO 1.85V AT 7A (MAX1712)

D3

LOW-NOISE

CONTROL

C7

0.1µF

C2

20

19

18

23

13

14

3 x 470µF

KEMET T510

D0

D1

D2

D3

MAX1710

MAX1711

MAX1712

LX

DL

(OPTIONAL OVP

REVERSE-POLARITY

CLAMP)

DAC

INPUTS

Q2

D1

17

16

8

PGND

D4**

TON

REF

C4

1µF

9

3

FB

FBS

4

C3

470pF

5

11

CC

GNDS

+5V

R4

1k

10

GND

R2

100k

Q1 = IRF7807

12

POWER-GOOD

INDICATOR

ILIM OVP* PGOOD

16

Q2 = IRF7805

D1, D3 = MBRS130T3 (OPTIONAL)

C1 = SANYO OS-CON (30SC10M)

6

TO V

CC

R3

(OPTIONAL)

*MAX1710 ONLY

**MAX1711/MAX1712 ONLY

Figure 1. Standard Application Circuit

rent-mode PWMs while also avoiding the problems

caused by widely varying switching frequencies in con-

ventional constant-on-time and constant-off-time PWM

schemes.

needed to supply the PWM circuit and gate drivers. If

stand-alone capability is needed, the +5V supply can be

generated with an external linear regulator such as the

MAX1615.

The battery and +5V bias inputs can be tied together if

the input source is a fixed 4.5V to 5.5V supply. If the +5V

bias supply is powered up prior to the battery supply, the

enable signal (SHDN) must be delayed until the battery

voltage is present in order to ensure startup. The +5V

+5V Bias Supply (V

and V

)

CC

DD

The MAX1710/MAX1711/MAX1712 require an external

+5V bias supply in addition to the battery. Typically, this

+5V bias supply is the notebook’s 95% efficient 5V sys-

tem supply. Keeping the bias supply external to the IC

improves efficiency and eliminates the cost associated

with the +5V linear regulator that would otherwise be

bias supply must provide V

and gate-drive power, so

CC

the maximum current drawn is:

10 ______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

V

BATT

2V TO 28V

R

LIM

V+

I

LIM

TOFF

V

CC

+5V

MAX1710

1-SHOT

TON

5µA

FROM

D/A

ON-TIME

COMPUTE

TRIG

Q

BST

TON

S

R

Q

TRIG

DH

LX

CURRENT

LIMIT

1-SHOT

Σ

OVP

ERROR

AMP

OUTPUT

SKIP

ZERO CROSSING

REF

10k

V

+5V

DD

SHDN

CC

70k

DL

REF

S

R

Q

PGND

g

m

g

m

g

m

FB

GNDS

FBS

FB

REF

+12%

REF

-30%

REF

-5%

CHIP SUPPLY

V

CC

+5V

PGOOD

R-2R

2V

REF

D/A CONVERTER

S1

S2

TIMER

Q

GND

OVP/UVLO

LATCH

D0

D1 D2

D3

Figure 2. MAX1710 Functional Diagram

✕

I

= I + f (Q + Q ) = 15mA to 30mA (typ)

age feed-forward (Figure 2). This architecture relies on

the filter capacitor’s ESR to act as the current-sense

resistor, so the output ripple voltage provides the PWM

ramp signal. The control algorithm is simple: the high-

side switch on-time is determined solely by a one-shot

whose period is inversely proportional to input voltage

and directly proportional to output voltage. Another one-

shot sets a minimum off-time (400ns typ). The on-time

one-shot is triggered if the error comparator is low, the

BIAS

CC

G1

G2

where I

and Q

is 600µA (typ), f is the switching frequency,

CC

G1

and Q

are the MOSFET data sheet total

G2

gate-charge specification limits at V = 5V.

GS

Free-Running, Constant-On-Time PWM

Controller with Input Feed-Forward

The Quick-PWM control architecture is an almost fixed-

frequency, constant-on-time current-mode type with volt-

______________________________________________________________________________________ 11

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

Table 1. MAX1710 FB Output ꢁoltage

DAC Codes

Table 2. MAX1711 FB Output ꢁoltage

DAC Codes

OUTPUT

ꢁOLTAGE (ꢁ)

OUTPUT

ꢁOLTAGE (ꢁ)

D4

D3

D2

D1

D0

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.00

1.95

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2.00

1.95

1.90

1.85

1.80

1.75

1.70

1.65

1.60

1.55

1.50

1.45

1.40

1.35

1.30

1.25

1.90

1.85

1.80

1.75

1.70

1.65

1.60

1.55

1.50

1.45

1.40

1.35

1.30

Shutdown3*

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

1.075

1.050

1.025

1.000

0.975

0.950

0.925

Shutdown3*

low-side switch current is below the current-limit thresh-

old, and the minimum off-time one-shot has timed out.

On-Time One-Shot (TON)

The heart of the PWM core is the one-shot that sets the

high-side switch on-time. This fast, low-jitter, adjustable

one-shot includes circuitry that varies the on-time in

response to battery and output voltage. The high-side

switch on-time is inversely proportional to the battery

voltage as measured by the V+ input, and directly pro-

portional to the output voltage as set by the DAC code.

This algorithm results in a nearly constant switching fre-

quency despite the lack of a fixed-frequency clock gen-

erator. The benefits of a constant switching frequency

are twofold: first, the frequency can be selected to avoid

noise-sensitive regions such as the 455kHz IF band;

second, the inductor ripple-current operating point

remains relatively constant, resulting in easy design

methodology and predictable output voltage ripple:

*See Table 4.

On-Time = K (V

+ 0.075V) / V

IN

OUT

settings due to fixed propagation delays and is approxi-

mately 12.5% at 550kHz and 400kHz, and 10% at the

two slower settings. This translates to reduced switch-

ing-frequency accuracy at higher frequencies (Table 5).

Switching frequency increases as a function of load cur-

rent due to the increasing drop across the low-side

where K is set by the TON pin-strap connection and

0.075V is an approximation to accommodate for the

expected drop across the low-side MOSFET switch.

One-shot timing error increases for the shorter on-time

12 ______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

resistance, source inductance, and DH output drive

characteristics.

Table 3. MAX1712 FB Output ꢁoltage

DAC Codes (ꢁRM 9.0)

Two external factors that can influence switching-fre-

quency accuracy are resistive drops in the two conduc-

tion loops (including inductor and PC board resistance)

and the dead-time effect. These effects are the largest

contributors to the change of frequency with changing

load current. The dead-time effect is a notable disconti-

nuity in the switching frequency as the load current is

varied (see Typical Operating Characteristics). It occurs

whenever the inductor current reverses, most commonly

at light loads with SKIP high. With reversed inductor cur-

rent, the inductor’s EMF causes LX to go high earlier

than normal, extending the on-time by a period equal to

the low-to-high dead time. For loads above the critical

conduction point, the actual switching frequency is:

OUTPUT

ꢁOLTAGE (ꢁ)

D4

D3

D2

D1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

1.850

1.825

1.800

1.775

1.750

1.725

1.700

1.675

1.650

1.625

1.600

1.575

1.550

1.525

1.500

1.475

1.450

1.425

1.400

1.375

1.350

1.325

1.300

1.275

1.250

1.225

1.200

1.175

1.150

1.125

1.100

Shutdown3*

V

+ V

DROP1

OUT

f =

t

(V + V

)

ON IN

DROP2

where V

is the sum of the parasitic voltage drops

DROP1

in the inductor discharge path, including synchronous

rectifier, inductor, and PC board resistances; V

DROP2

is the sum of the resistances in the charging path,

and t is the on-time calculated by the MAX1710/

ON

MAX1711/MAX1712.

Integrator Amplifiers (CC)

There are three integrator amplifiers that provide a fine

adjustment to the output regulation point. One amplifier

monitors the difference between GNDS and GND, while

another monitors the difference between FBS and FB.

The third amplifier integrates the difference between

REF and the DAC output. These three transconductance

amplifiers’ outputs are directly summed inside the chip,

so the integration time constant can be set easily with a

capacitor. The g of each amplifier is 160µmho (typ).

m

The integrator block has an ability to move and correct

the output voltage by about -2%, +4%. For each amplifi-

er, the differential input voltage range is about 50mV

total, including DC offset and AC ripple. The voltage

gain of each integrator is about 80V/V.

The FBS amplifier corrects for DC voltage drops in PC

board traces and connectors in the output bus path

between the DC-DC converter and the load. The GNDS

amplifier performs a similar DC correction task for the

output ground bus. The third amplifier provides an aver-

*See Table 4.

aging function that forces V

to be regulated at the

OUT

MOSFET, which causes a faster inductor-current dis-

charge ramp. The on-times guaranteed in the Electrical

Characteristics are influenced by switching delays in the

external high-side power MOSFET. The exact switching

frequency will depend on gate charge, internal gate

average value of the output ripple waveform. If the inte-

grator amplifiers are disabled, V is regulated at the

OUT

valleys of the output ripple waveform. This creates a

slight load-regulation characteristic in which the output

______________________________________________________________________________________ 13

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

threshold is relatively constant, with only a minor depen-

∆i

∆t

V

- V

dence on battery voltage.

BATT OUT

=

L

-I

PEAK

K

I

≈

LOAD(SKIP)

2L

where K is the On-Time Scale factor (Table 6). The load-

current level at which PFM/PWM crossover occurs,

LOAD(SKIP)

I

= I

/2

LOAD PEAK

I

, is equal to 1/2 the peak-to-peak ripple cur-

rent, which is a function of the inductor value (Figure 3).

For example, in the standard application circuit with t

ON

= 300ns at 24V, V

= 2V, and L = 2µH, switchover to

OUT

pulse-skipping operation occurs at I

= 1.65A or

LOAD

0

ON-TIME

TIME

about 1/4 full load. The crossover point occurs at an

even lower value if a swinging (soft-saturation) inductor

is used.

Figure 3. Pulse-Skipping/Discontinuous Crossover Point

voltage rises approximately 1% (up to 1/2 the peak

amplitude of the ripple waveform as a limit) when under

light loads.

The switching waveforms may appear noisy and asyn-

chronous when light loading causes pulse-skipping

operation, but this is a normal operating condition that

results in high light-load efficiency. Trade-offs in PFM

noise vs. light-load efficiency can be made by varying

the inductor value. Generally, low inductor values pro-

duce a broader efficiency vs. load curve, while higher

values result in higher full-load efficiency (assuming that

the coil resistance remains fixed) and less output voltage

ripple. Penalties for using higher inductor values include

larger physical size and degraded load-transient

response (especially at low input voltage levels).

Integrators have both beneficial and detrimental char-

acteristics. While they do correct for drops due to DC

bus resistance and tighten the DC output voltage toler-

ance limits by averaging the peak-to-peak output

ripple, they can interfere with achieving the fastest pos-

sible load-transient response. The fastest transient

response is achieved when all three integrators are dis-

abled. This works very well when the MAX1710/

MAX1711/MAX1712 circuit can be placed very close to

the CPU.

SKIP

Forced-PWM Mode (

= High)

There is often a connector, or at least many milliohms of

PC board trace resistance, between the DC-DC convert-

er and the CPU. In these cases, the best strategy is to

place most of the bulk bypass capacitors close to the

CPU, with just one capacitor on the other side of the con-

nector near the MAX1710/MAX1711/MAX1712 to control

ripple if the CPU card is unplugged. In this situation, the

remote-sense lines and integrators provide a real benefit.

The low-noise, forced-PWM mode (SKIP driven high) dis-

ables the zero-crossing comparator, which controls the

low-side switch on-time. This causes the low-side gate-

drive waveform to become the complement of the high-

side gate-drive waveform. This in turn causes the

inductor current to reverse at light loads, as the PWM

loop strives to maintain a duty ratio of V

/V . The

OUT IN

benefit of forced-PWM mode is to keep the switching fre-

quency fairly constant, but it comes at a cost: the no-

load battery current can be as high as 40mA or more.

When FBS is connected to V

tors are disabled, CC can be left unconnected, which

eliminates a component.

so that all three integra-

CC

Forced-PWM mode is most useful for reducing audio-fre-

quency noise, improving load-transient response, pro-

viding sink-current capability for dynamic output voltage

adjustment, and improving the cross-regulation of multi-

ple-output applications that use a flyback transformer or

coupled inductor.

Current-Limit Circuit (ILIM)

The current-limit circuit employs a unique “valley” cur-

rent-sensing algorithm that uses the on-state resistance

of the low-side MOSFET as a current-sensing element. If

the current-sense signal is above the current-limit

threshold, the PWM is not allowed to initiate a new cycle

(Figure 4). The actual peak current is greater than the

current-limit threshold by an amount equal to the induc-

Automatic Pulse-Skipping Switchover

At light loads, an inherent automatic switchover to PFM

takes place. This switchover is effected by a comparator

that truncates the low-side switch on-time at the inductor

current’s zero crossing. This mechanism causes the

threshold between pulse-skipping PFM and nonskipping

PWM operation to coincide with the boundary between

continuous and discontinuous inductor-current operation

(also known as the “critical conduction” point;

see Continuous to Discontinuous Inductor Current Point

vs. Input Voltage graph in the Typical Operating

Characteristics). For a battery range of 7V to 24V, this

14 ______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

tor ripple current. Therefore the exact current-limit char-

MOSFET Gate Drivers (DH, DL)

The DH and DL drivers are optimized for driving moder-

ate-size, high-side and larger, low-side power MOSFETs.

This is consistent with the low duty factor seen in the

acteristic and maximum load capability are a function of

the MOSFET on-resistance, inductor value, and battery

voltage. The reward for this uncertainty is robust, loss-

less overcurrent sensing. When combined with the UVP

protection circuit, this current-limit method is effective in

almost every circumstance.

notebook CPU environment, where a large V

- V

OUT

BATT

differential exists. An adaptive dead-time circuit monitors

the DL output and prevents the high-side FET from turn-

ing on until DL is fully off. There must be a low-resis-

tance, low-inductance path from the DL driver to the

MOSFET gate in order for the adaptive dead-time circuit

to work properly. Otherwise, the sense circuitry in the

MAX1710/MAX1711/MAX1712 will interpret the MOSFET

gate as “off” while there is actually still charge left on the

gate. Use very short, wide traces measuring 10 to 20

squares (50 to 100 mils wide if the MOSFET is 1 inch

from the MAX1710/MAX1711/MAX1712).

-I

PEAK

I

LOAD

I

LIMIT

The dead time at the other edge (DH turning off) is deter-

mined by a fixed 35ns (typ) internal delay.

LX-PGND I

THRESHOLD = 100mV (NOMINAL, DEFAULT)

LIMIT

VOLTAGE DROP ACROSS Q2

The internal pulldown transistor that drives DL low is

robust, with a 0.5Ω (typ) on-resistance. This helps pre-

vent DL from being pulled up during the fast rise time of

the inductor node, due to capacitive coupling from the

drain to the gate of the massive low-side synchronous-

rectifier MOSFET. However, you might still encounter

some combinations of high- and low-side FETs that will

cause excessive gate-drain coupling, which can lead to

efficiency-killing, EMI-producing shoot-through currents.

This can often be remedied by adding a resistor in series

with BST, which increases the turn-on time of the high-

side FET without degrading the turn-off time (Figure 5).

0

TIME

Figure 4.”Valley’’ Current-Limit Threshold Point

There is also a negative current limit that prevents exces-

sive reverse inductor currents when V

rent. The negative current-limit threshold is set to

approximately 120% of the positive current limit, and

therefore tracks the positive current limit when ILIM is

adjusted.

is sinking cur-

OUT

The current-limit threshold can be adjusted with an exter-

nal resistor (R ) at ILIM. A precision 5µA pullup current

LIM

source at ILIM sets a voltage drop on this resistor,

adjusting the current-limit threshold from 50mV to

200mV. In the adjustable mode, the current-limit thresh-

old voltage is precisely 1/10th the voltage seen at ILIM.

+5V

V

BATT

5Ω

BST

Therefore, choose R

equal to 2kΩ/mV of the current-

LIM

limit threshold. The threshold defaults to 100mV when

DH

ILIM is tied to V . The logic threshold for switchover to

CC

the 100mV default value is approximately V - 1V.

CC

The adjustable current limit can accommodate

MOSFETs with atypical on-resistance characteristics

(see Design Procedure).

MAX1710

MAX1711

MAX1712

LX

A capacitor in parallel with R

soft-start function.

can provide a variable

LIM

Figure 5. Reducing the Switching-Node Rise Time

Carefully observe the PC board layout guidelines to

ensure that noise and DC errors don’t corrupt the cur-

rent-sense signals seen by LX and PGND. The IC must

be mounted close to the low-side MOSFET with short,

direct traces making a Kelvin-sense connection to the

source and drain terminals.

DAC Converter (D0–D4)

The DAC programs the output voltage. It receives a digi-

tal code from pins on the CPU module that are either

hard-wired to GND or left open-circuit. The

MAX1710/MAX1711/MAX1712 contain weak internal

______________________________________________________________________________________ 15

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

Table 4. Operating Mode Truth Table

DL

MODE

COMMENTS

SHDN SKIP OVP

0

X

0

1

High

Shutdown1 Low-power shutdown state. DL is forced to V , enforcing OVP. I

< 1µA typ.

DD

CC

Low-power shutdown state. DL is forced to GND, disabling OVP. I

Exiting shutdown triggers a soft-start cycle.

CC

Low

Shutdown2

Shutdown3 DAC code = X1111 (MAX1711), DAC code = 11111 (MAX1712) (Table 2). DL is

(MAX1711/ forced to PGND, DH is forced to LX. The MAX1711/MAX1712 eventually goes

1

X

MAX1712)

into UVP fault mode as the load current discharges the output.

Test mode with OVP, UVP, and thermal faults disabled and latches cleared.

Otherwise normal operation, with automatic PWM/PFM switchover for pulse

skipping at light loads (Figure 6).

Below

GND

1

X

1

X

Switching

High

No fault

OVP faults disabled and OVP latch cleared. Otherwise normal operation,

with SKIP controlling PWM/PFM switchover.

X

No OVP

Low-noise operation with no automatic switchover. Fixed-frequency PWM action

is forced regardless of load. Inductor current reverses at light load levels.

Run (PWM),

Low Noise

V

CC

I

draw = 750µA typ. I

draw = 15mA typ.

CC

DD

Run

Normal operation with automatic PWM/PFM switchover for pulse skipping at light

= 600µA typ. I draw = load dependent.

GND

X

(PFM/PWM) loads. I

CC

DD

Fault latch has been set by OVP, output UVLO, or thermal shutdown. Device will

Fault

remain in FAULT mode until V

power is cycled, SKIP is forced below ground,

CC

or SHDN is toggled.

POR, UVLO, and Soft-Start

Table 5. Frequency Selection Guidelines

Power-on reset (POR) occurs when V

rises above

CC

approximately 2V, resetting the fault latch and soft-start

counter, and preparing the PWM for operation. V

CC

FREQUENCY

(kHz)

TYPICAL

APPLICATION

COMMENT

undervoltage lockout (UVLO) circuitry inhibits switching

and forces the DL gate driver high (in order to enforce

4-cell Li+ notebook Use for absolute best

CPU core efficiency.

200

300

output overvoltage protection) until V

rises above

CC

4-cell Li+ notebook Considered mainstream

4.2V, whereupon an internal digital soft-start timer begins

to ramp up the maximum allowed current limit. The ramp

occurs in five steps: 20%, 40%, 60%, 80%, and 100%,

with 100% current available after 1.7ms 50%.

CPU core

by current standards.

Useful in 4-cell systems

for lighter loads than the

CPU or where size is key.

3-cell Li+ notebook

CPU core

400

550

A continuously adjustable, analog soft-start function can

be realized by adding a capacitor in parallel with R

at

Good operating point for

compound buck designs

or desktop circuits.

LIM

+5V-input notebook

CPU core

ILIM. This soft-start method requires a minimum interval

between power-down and power-up to allow R

charge the capacitor.

to dis-

LIM

pullups on each input in order to eliminate external resis-

tors.

Power-Good Output (PGOOD)

The output (FB) is continuously monitored for undervolt-

age by the PGOOD comparator, except in shutdown or

standby mode. The -5% undervoltage trip threshold is

measured with respect to the nominal unloaded output

voltage, as set by the DAC. If the DAC code increases in

steps greater than 1LSB, it is likely that PGOOD will

momentarily go low. In shutdown and standby modes,

PGOOD is actively held low. The PGOOD output is a true

When changing MAX1710 DAC codes while powered

up, the over/undervoltage protection features can be

activated if the code is changed more than 1LSB at a

time. For applications needing the capability of changing

DAC codes “on-the-fly,” use the MAX1711/MAX1712.

16 ______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

open-drain type with no parasitic ESD diodes. Note that

the PGOOD undervoltage detector is completely inde-

pendent of the output UVP fault detector.

APPROXIMATELY

-0.65V

MAX1710

MAX1711

MAX1712

Output Overvoltage Protection (OVP)

The OVP circuit is designed to protect against a short-

ed high-side MOSFET by drawing high current and

blowing the battery fuse. The FB node is continuously

monitored for overvoltage. The overvoltage trip thresh-

old tracks the DAC code setting. If the output is more

than 12.5% above the nominal regulation point for

the MAX1710 (2.25V absolute for the MAX1711/

MAX1712), overvoltage protection OVP is triggered and

the circuit shuts down. The DL low-side gate-driver out-

SKIP

1.5mA

V

FORCE

GND

Figure 6. Disabling Over/Undervoltage Protection (Test Mode)

put is then latched high until SHDN is toggled or V

CC

power is cycled below 1V. This action turns on the syn-

chronous-rectifier MOSFET with 100% duty and, in turn,

rapidly discharges the output filter capacitor and forces

the output to ground.

been previously set. The PWM operates as if SKIP were

grounded (PFM/PWM mode).

The no-fault test mode is entered by sinking 1.5mA

from SKIP via an external negative voltage source in

series with a resistor (Figure 6). SKIP is clamped to

GND with a silicon diode, so choose the resistor value

If the condition that caused the overvoltage (such as a

shorted high-side MOSFET) persists, the battery fuse will

blow. Note that DL going high can have the effect of

causing output polarity reversal, due to energy stored in

the output LC at the instant OVP activates. If the load

can’t tolerate being forced to a negative voltage, it may

be desirable to place a power Schottky diode across the

output to act as a reverse-polarity clamp (Figure 1). The

MAX1710/MAX1711/MAX1712 themselves can be

affected by the FB pin going below ground, with the neg-

ative voltage coupling into SHDN. It may be necessary to

add 1kΩ resistors in series with FB and FBS (Figure 7).

equal to (V

- 0.65V) / 1.5mA.

FORCE

Design Procedure

Firmly establish the input voltage range and maximum

load current before choosing a switching frequency and

inductor operating point (ripple current ratio). The prima-

ry design trade-off lies in choosing a good switching fre-

quency and inductor operating point, and the following

four factors dictate the rest of the design:

DL is also kept high continuously when V

UVLO is

1) Input voltage range. The maximum value (V

CC

BATT

active as well as in Shutdown1 mode (Table 4).

Overvoltage protection can be defeated via the OVP

input (MAX1710 only) or via a SKIP test mode (see Pin

Description).

) must accommodate the worst-case high AC

(MAX)

adapter voltage. The minimum value (V

)

BATT(MIN)

must account for the lowest battery voltage after

drops due to connectors, fuses, and battery selector

switches. If there is a choice at all, lower input volt-

ages result in better efficiency.

Output Undervoltage Protection (UVP)

The output UVP function is similar to foldback current

limiting, but employs a timer rather than a variable cur-

rent limit. If the MAX1710 output (FB) is under 70% of the

nominal value 20ms after coming out of shutdown, the

2) Maximum load current. There are two values to con-

sider. The peak load current (I ) determines

LOAD(MAX)

the instantaneous component stresses and filtering

requirements, and thus drives output capacitor

selection, inductor saturation rating, and the design

of the current-limit circuit. The continuous load cur-

PWM is latched off and won’t restart until V

power is

CC

cycled or SHDN is toggled. For the MAX1711/MAX1712,

the nominal UVP trip threshold is fixed at 0.8V.

rent (I

) determines the thermal stresses and

LOAD

thus drives the selection of input capacitors,

MOSFETs, and other critical heat-contributing com-

ponents. Modern notebook CPUs generally exhibit

✕

No-Fault Test Mode

The over/undervoltage protection features can compli-

cate the process of debugging prototype breadboards

since there are (at most) a few milliseconds in which to

determine what went wrong. Therefore, a test mode is

provided to totally disable the OVP, UVP, and thermal

shutdown features, and clear to the fault latch if it has

I

= I

80%.

LOAD

LOAD(MAX)

3) Switching frequency. This choice determines the

basic trade-off between size and efficiency. The opti-

mal frequency is largely a function of maximum input

______________________________________________________________________________________ 17

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

voltage, due to MOSFET switching losses that are

Setting the Current Limit

The minimum current-limit threshold must be great

enough to support the maximum load current when the

current limit is at the minimum tolerance value. The valley

2

proportional to frequency and VBATT . The optimum

frequency is also a moving target, due to rapid

improvements in MOSFET technology that are making

higher frequencies more practical (Table 5).

of the inductor current occurs at I

of the ripple current, therefore:

minus half

LOAD(MAX)

4) Inductor operating point. This choice provides

trade-offs between size vs. efficiency. Low inductor

values cause large ripple currents, resulting in the

smallest size, but poor efficiency and high output

noise. The minimum practical inductor value is one

that causes the circuit to operate at the edge of criti-

cal conduction (where the inductor current just touch-

es zero with every cycle at maximum load). Inductor

values lower than this grant no further size-reduction

benefit.

✕

I

> I

- (LIR / 2)

I

LOAD(MAX)

LIMIT(LOW)

LOAD(MAX)

where I

= minimum current-limit threshold volt-

LIMIT(LOW)

age divided by the R

of Q2. For the MAX1710, the

DS(ON)

minimum current-limit threshold (100mV default setting)

is 90mV. Use the worst-case maximum value for R

DS(ON)

from the MOSFET Q2 data sheet, and add some margin

for the rise in R with temperature. A good general

DS(ON)

rule is to allow 0.5% additional resistance for each °C of

temperature rise.

The MAX1710/MAX1711/MAX1712s’ pulse-skipping

algorithm initiates skip mode at the critical-conduction

point. So, the inductor operating point also determines

the load-current value at which PFM/PWM switchover

occurs. The optimum point is usually found between

20% and 50% ripple current.

Examining the 7A notebook CPU circuit example with a

maximum R

= 15mΩ at high temperature reveals

DS(ON)

the following:

I

= 90mV / 15mΩ = 6A

LIMIT(LOW)

The inductor ripple current also impacts transient-

6A is greater than the valley current of 5.25A, so the cir-

cuit can easily deliver the full rated 7A using the default

100mV nominal ILIM threshold.

response performance, especially at low V

- V

OUT

BATT

differentials. Low inductor values allow the inductor cur-

rent to slew faster, replenishing charge removed from the

output filter capacitors by a sudden load step. The

amount of output sag is also a function of the maximum

duty factor, which can be calculated from the on-time

and minimum off-time:

When adjusting the current limit, use a 1% tolerance R

LIM

resistor to prevent a significant increase of errors in the

current-limit tolerance.

Output Capacitor Selection

The output filter capacitor must have low enough effective

series resistance (ESR) to meet output ripple and load-

transient requirements, yet have high enough ESR to sat-

isfy stability requirements. Also, the capacitance value

must be high enough to absorb the inductor energy

going from a full-load to no-load condition without tripping

the OVP circuit.

2

(∆I

) × L

LOAD(MAX)

V

=

SAG

2 × C × DUTY (V

− V

)

F

BATT(MIN)

OUT

Inductor Selection

The switching frequency (on-time) and operating point

(% ripple or LIR) determine the inductor value as follows:

In CPU V

converters and other applications where

V

CORE

OUT

L =

the output is subject to violent load transients, the output

capacitor’s size depends on how much ESR is needed to

prevent the output from dipping too low under a load

transient. Ignoring the sag due to finite capacitance:

f × LIR × I

LOAD(MAX)

Example: I

= 7A, V

= 2V, f = 300kHz, 50%

LOAD(MAX)

ripple current or LIR = 0.5:

OUT

V

DIP

LOAD(MAX)

2V

R

≤

ESR

L =

= 1.9µH (2µH)

I

300kHz × 0.5 × 7A

In non-CPU applications, the output capacitor’s size

depends on how much ESR is needed to maintain an

acceptable level of output voltage ripple:

Find a low-loss inductor having the lowest possible DC

resistance that fits in the allotted dimensions. Ferrite

cores are often the best choice, although powdered iron

is cheap and can work well at 200kHz. The core must be

large enough not to saturate at the peak inductor current

Vp-p

R

≤

ESR

LIR × I

LOAD(MAX)

(I

):

PEAK

✕

I

= I

+ (LIR / 2)

I

LOAD(MAX)

PEAK

LOAD(MAX)

18 ______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

The actual microfarad capacitance value required relates

unstable operation. However, it’s easy to add enough

series resistance by placing the capacitors a couple of

inches downstream from the junction of the inductor and

FB pin (see the All-Ceramic-Capacitor Application sec-

tion).

to the physical size needed to achieve low ESR, as well

as to the chemistry of the capacitor technology. Thus, the

capacitor is usually selected by ESR and voltage rating

rather than by capacitance value (this is true of tantalums,

OS-CONs, and other electrolytics).

Unstable operation manifests itself in two related but dis-

tinctly different ways: double-pulsing and fast-feedback

loop instability.

When using low-capacity filter capacitors such as ceram-

ic or polymer types, capacitor size is usually determined

by the capacity needed to prevent the overvoltage pro-

tection circuit from being tripped when transitioning from

a full-load to a no-load condition. The capacitor must be

large enough to prevent the inductor’s stored energy from

launching the output above the overvoltage protection

threshold. Generally, once enough capacitance is added

to meet the overshoot requirement, undershoot at the ris-

Double-pulsing occurs due to noise on FB or because

the ESR is so low that there isn’t enough voltage ramp in

the output voltage (FB) signal. This “fools” the error com-

parator into triggering a new cycle immediately after the

400ns minimum off-time period has expired. Double-

pulsing is more annoying than harmful, resulting in noth-

ing worse than increased output ripple. However, it can

indicate the possible presence of loop instability, which

is caused by insufficient ESR.

ing load edge is no longer a problem (see also V

equation under Design Procedure).

SAG

With integrators disabled, the amount of overshoot due to

stored inductor energy can be calculated as:

Loop instability can result in oscillations at the output

after line or load perturbations that can trip the overvolt-

age protection latch or cause the output voltage to fall

below the tolerance limit.

2





C

× V

+L × I

OUT

OUT PEAK

C

∆V =

− V

OUT









OUT

The easiest method for checking stability is to apply a

very fast zero-to-max load transient (see MAX1710

Evaluation Kit manual) and carefully observe the output

voltage ripple envelope for overshoot and ringing. It

can help to simultaneously monitor the inductor current

with an AC current probe. Don’t allow more than one

cycle of ringing after the initial step-response under- or

overshoot.





where I

is the peak inductor current. To absolutely

PEAK

minimize the overshoot, disable the integrator first, since

the inherent delay of the integrator can cause extra “run-

on” switching cycles to occur after the load change.

Output Capacitor Stability Considerations

Stability is determined by the value of the ESR zero rela-

tive to the switching frequency. The point of instability is

given by the following equation:

Input Capacitor Selection

The input capacitor must meet the ripple current

requirement (I

) imposed by the switching currents.

RMS

f

π

Nontantalum chemistries (ceramic, aluminum, or OS-

CON) are preferred due to their resistance to power-up

surge currents:

f

=

ESR

1

where f

=

ESR

2 × π × R

× C

F













ESR

V

(V

− V

)

OUT BATT

OUT

I

= I

LOAD

RMS

V

For a typical 300kHz application, the ESR zero frequency

must be well below 95kHz, preferably below 50kHz.

Tantalum and OS-CON capacitors in widespread use at

the time of publication have typical ESR zero frequencies

of 15kHz. In the design example used for inductor selec-

tion, the ESR needed to support 50mVp-p ripple is

50mV/3.5A = 14.2mΩ. Three 470µF/4V Kemet T510 low-

ESR tantalum capacitors in parallel provide 15mΩ max

ESR. Their typical combined ESR results in a zero at

14.1kHz, well within the bounds of stability.

BATT

Power MOSFET Selection

Most of the following MOSFET guidelines focus on the

challenge of obtaining high load-current capability (>5A)

when using high-voltage (>20V) AC adapters. Low-cur-

rent applications usually require less attention.

For maximum efficiency, choose a high-side MOSFET

(Q1) that has conduction losses equal to the switching

losses at the optimum battery voltage (15V). Check to

ensure that the conduction losses at minimum input volt-

age don’t exceed the package thermal limits or violate

the overall thermal budget. Check to ensure that con-

duction losses plus switching losses at the maximum

Don’t put high-value ceramic capacitors directly across

the fast feedback inputs (FB to GND) without taking pre-

cautions to ensure stability. Large ceramic capacitors

can have a high ESR zero frequency and cause erratic,

______________________________________________________________________________________ 19

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

+5V

V

IN

= 7V TO 24V*

0.1µF

20Ω

C1

1µF

V

V+

V

CC

DD

5Ω

ON/OFF

SHDN

SKIP

BST

DH

Q1

Q2

0.5µH

R1

R2

1.6V AT 7A

CPU

0.1µF

MAX1711

MAX1712

LX

D0

D1

D2

D3

D4

C2

DAC

INPUTS

DL

PGND

GND

FB

0.22µF

1k

REF

CC

FBS

470pF

GNDS

TON

C1 = 4 x 4.7µF/25V TAIYO YUDEN (TMK325BJ475K)

1nF

C2 = 6 x 47µF/10V TAIYO YUDEN (LMK550BJ476KM)

R1 + R2 = 5mΩ MINIMUM OF PC BOARD TRACE RESISTANCE (TOTAL)

*FOR HIGHER MINIMUM INPUT VOLTAGE,

*LESS OUTPUT CAPACITANCE IS REQUIRED.

Figure 7. All-Ceramic-Capacitor Application

MOSFET Power Dissipation

Table 6. Approximate K-Factors Errors

Worst-case conduction losses occur at the duty factor

extremes. For the high-side MOSFET, the worst-case

power dissipation due to resistance occurs at minimum

battery voltage:

TON

K

APPROXIMATE

K-FACTOR

MIN ꢁ

BATT

= 2ꢁ

SETTING FACTOR

AT ꢁ

OUT

(kHz)

200

300

400

550

(µs-ꢁ)

5

ERROR (ꢀ)

(ꢁ)

2.6

2.9

3.2

3.6

10

2

✕

PD(Q1) = (V

/ V

)

I

R

DS(ON)

OUT

BATT(MIN)

LOAD

3.3

2.5

1.8

Generally, a small high-side MOSFET is desired in order

to reduce switching losses at high input voltages.

12.5

However, the R

required to stay within package

DS(ON)

power-dissipation limits often limits how small the MOS-

FET can be. Again, the optimum occurs when the switch-

input voltage don’t exceed the package ratings or violate

the overall thermal budget.

ing (AC) losses equal the conduction (R

) losses.

DS(ON)

High-side switching losses don’t usually become an

issue until the input is greater than approximately 15V.

Choose a low-side MOSFET (Q2) that has the lowest

possible R , comes in a moderate to small pack-

DS(ON)

Switching losses in the high-side MOSFET can become

an insidious heat problem when maximum AC adapter

voltages are applied, due to the squared term in the

CV²F switching loss equation. If the high-side MOSFET

age (i.e., SO-8), and is reasonably priced. Ensure that

the MAX1710/MAX1711/MAX1712 DL gate driver can

drive Q2; in other words, check that the gate isn’t pulled

up by the high-side switch turning on due to parasitic

drain-to-gate capacitance, causing cross-conduction

problems. Switching losses aren’t an issue for the low-

side MOSFET since it’s a zero-voltage switched device

when used in the buck topology.

you’ve chosen for adequate R

at low battery volt-

DS(ON)

ages becomes extraordinarily hot when subjected to

, you must reconsider your choice of MOS-

V

BATT(MAX)

FET.

Calculating the power dissipation in Q1 due to switching

losses is difficult, since it must allow for difficult-to-quanti-

20 ______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

fy factors that influence the turn-on and turn-off times.

These factors include the internal gate resistance, gate

charge, threshold voltage, source inductance, and PC

board layout characteristics. The following switching loss

calculation provides only a very rough estimate and is no

substitute for breadboard evaluation, preferably including

a sanity check using a thermocouple mounted on Q1:

and bulk output capacitance must often be added (see

equation in the Design Procedure).

V

SAG

Dropout Design Example: ꢁ

= 3ꢁ min, ꢁ

=

OUT

BATT

2ꢁ, f = 300kHz. The required duty is (V

+ V ) /

SW

OUT

(V

- V ) = (2V + 0.1V) / (3.0V - 0.1V) = 72.4%. The

BATT

SW

✕

worst-case on-time is (V

+ 0.075) / V

K =

OUT

BATT

✕

2.075V / 3V 3.35µs-V 90% = 2.08µs. The IC duty-fac-

tor limitation is:

2

C

× V

× f × I

LOAD

RSS

BATT(MAX)

PD(switching) =

t

ON(MIN)

I

DUTY =

= 2.08µs + 500ns = 80.6%

GATE

t

+ t

ON(MIN) OFF(MAX)

where C is the reverse transfer capacitance of Q1

RSS

and I

typ).

is the peak gate-drive source/sink current (1A

which meets the required duty.

GATE

Remember to include inductor resistance and MOSFET

For the low-side MOSFET, Q2, the worst-case power dis-

sipation always occurs at maximum battery voltage:

on-state voltage drops (V ) when doing worst-case

SW

dropout duty-factor calculations.

2

✕

PD(Q2) = (1 - V

/ V

)

I

R

DS(ON)

OUT

BATT(MAX)

LOAD

All-Ceramic-Capacitor Application

Ceramic capacitors have advantages and disadvan-

tages. They have ultra-low ESR, are noncombustible, are

relatively small, and are nonpolarized. On the other

hand, they’re expensive and brittle, and their ultra-low

ESR characteristic can result in excessively high ESR

zero frequencies (affecting stability). In addition, they

can cause output overshoot when going abruptly from

full-load to no-load conditions, unless there are some

bulk tantalum or electrolytic capacitors in parallel to

absorb the stored energy in the inductor. In some cases,

there may be no room for electrolytics, creating a need

for a DC-DC design that uses nothing but ceramics.

The absolute worst case for MOSFET power dissipation

occurs under heavy overloads that are greater than

I

but are not quite high enough to exceed the

LOAD(MAX)

current limit and cause the fault latch to trip. To protect

against this possibility, you must “overdesign” the circuit

✕

to tolerate I

= I

+ (LIR / 2)

I

,

LOAD

LIMIT(HIGH)

LOAD(MAX)

where I

is the maximum valley current allowed

LIMIT(HIGH)

by the current-limit circuit, including threshold tolerance

and on-resistance variation. This means that the

MOSFETs must be very well heatsinked. If short-circuit

protection without overload protection is enough, a nor-

mal I

value can be used for calculating component

LOAD

stresses.

The all-ceramic-capacitor application of Figure 7 has the

same basic performance as the 7A Standard Application

Circuit, but replaces the tantalum output capacitors with

ceramics. This design relies on having a minimum of

5mΩ parasitic PC board trace resistance in series with

the capacitor in order to reduce the ESR zero frequency.

This small amount of resistance is easily obtained by

locating the MAX1710/MAX1711/MAX1712 circuit 2 or 3

inches away from the CPU, and placing all the ceramic

capacitors close to the CPU. Resistance values higher

than 5mΩ just improve the stability (which can be

observed by examining the load-transient response

characteristic as shown in the Typical Operating

Characteristics). Avoid adding excess PC board trace

resistance because there’s an efficiency penalty; 5mΩ is

sufficient for the 7A circuit.

Choose a Schottky diode D1 having a forward voltage

low enough to prevent the Q2 MOSFET body diode from

turning on during the dead time. As a general rule, a

diode having a DC current rating equal to 1/3 of the load

current is sufficient. This diode is optional, and if efficien-

cy isn’t critical it can be removed.

Application Issues

Dropout Performance

The output voltage adjust range for continuous-conduc-

tion operation is restricted by the nonadjustable 500ns

(max) minimum off-time one-shot. For best dropout per-

formance, use the slowest (200kHz) on-time setting.

When working with low input voltages, the duty-factor

limit must be calculated using worst-case values for on-

and off-times. Manufacturing tolerances and internal

propagation delays introduce an error to the TON K-fac-

tor. This error is higher at higher frequencies (Table 6).

Also, keep in mind that transient response performance

of buck regulators operated close to dropout is poor,

Output overshoot determines the minimum output

capacitance requirement. In this example, the switching

frequency has been increased to 550kHz and the induc-

tor value has been reduced to 0.5µH (compared to

300kHz and 2µH for the standard 7A circuit) in order to

______________________________________________________________________________________ 21

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

minimize the energy transferred from inductor to capaci-

tor during load-step recovery. Even so, the amount of

overshoot is high enough (80mV) that for the MAX1710,

it’s wise to disable OVP or use the MAX1711/MAX1712

with their fixed 2.25V overvoltage protection threshold to

avoid tripping the fault latch (see the overshoot equation

in the Output Capacitor Selection section). The efficiency

penalty for operating at 550kHz is about 2% to 3%,

depending on the input voltage.

sive. For highest accuracy, use the MAX1710 when

adjusting V

with external resistors. The MAX1710 FB

OUT

node has very high impedance, while the MAX1711/

MAX1712 have a 180kΩ 35% FB impedance, which

degrades V

accuracy.

OUT

Adjusting V

OUT

Above 2V

The feed-forward circuit that makes the on-time depen-

dent on battery voltage maintains a nearly constant

switching frequency as V , I

, and the DAC code

IN LOAD

Two optional 1kΩ resistors are placed in series with FB

and FBS. These resistors prevent the negative output

voltage spike (that results from tripping OVP) from

pulling SHDN low via its internal ESD diode, which tends

to clear the fault latch, causing “hiccup” restarts.

are changed. This works extremely well as long as FB is

connected directly to the output.

When the output is adjusted higher than 2V with a resis-

tor-divider, the switching frequency can be increased to

relatively unreasonable levels as the actual off-time

decreases and isn’t compensated for by a change in on-

time; 3.3V is about the maximum limit to the practical

adjustment range. Even at the slowest TON setting and

with the DAC set to 2V, the switching rate will exceed

600kHz.

Setting V

OUT

with a Resistor-Divider

The output voltage can be adjusted with a resistor-

divider rather than the DAC if desired (Figure 8). The

drawback of this practice is that the on-time doesn’t

automatically receive correct compensation for changing

output voltage levels. This can result in variable switch-

ing frequency as the resistor ratio is changed and/or

excessive switching frequency. The equation for adjust-

ing the output voltage is:

The trip threshold for output overvoltage protection

scales with the nominal output voltage setting.

2-Stage (5V-Powered) Notebook CPU

Buck Regulator

R1

R2





The most efficient and overall cost-effective solution for

stepping down a high-voltage battery to very low output

voltage is to use a single-stage buck regulator that’s

powered directly from the battery. However, there may

be situations where the battery bus can’t be routed near

the CPU, or where space constraints dictate the smallest

possible local DC-DC converter. In such cases, the 5V-

powered circuit of Figure 9 may be appropriate. The

reduced input voltage allows a higher switching frequen-

cy and a much smaller inductor value.

V

= V −1% 1+



FB

(

)







OUT

where V is the currently selected DAC value. When

FB

using external resistors, FBS remote sensing is not rec-

ommended, but GNDS remote sensing is still possible.

Connect FBS to FB and GNDS to remote ground loca-

tion. In resistor-adjusted circuits, the DAC code should

be set as close as possible to the actual output voltage

so that the switching frequency doesn’t become exces-

V

BATT

Dynamic DAC Code Changes

(MAX1711/MAX1712)

Changing the output voltage dynamically by switching

DAC codes “on-the-fly” can be used to help make

power-savings/performance trade-offs in the host sys-

tem. Several important design issues arise from this

practice.

DH

DL

V

OUT

MAX1710

MAX1711

MAX1712

R1

R2

First, know that attempting to slew the output upward

quickly causes large current surges at the battery as the

IC goes into output current limiting during the transition.

Surge currents can be controlled either by counting the

DAC code slowly (50kHz or slower rate suggested), or

FB

FBS

by modulating the I

current-limit threshold.

LIM

1k

The DAC inputs must be driven quickly to the new value

so the device doesn’t wrongly interpret a disallowed

GNDS

Figure 8. Setting V

with a Resistor-Divider

OUT

22 ______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

V

IN

4.5V TO 5.5V

1µF

20Ω

C1

1µF

4 x 10µF/25V

V+

V

DD

I

V

CC

LIM

SHDN

D0

ON/OFF

BST

DH

IRF7805

D1

D/A

INPUTS

D2

V

OUT

1.6V AT 7A

0.1µF

L1

D3

0.5µH

C2

D4**

MAX1710

MAX1711

MAX1712

LX

3 x 470µF

KEMET

T510

0.22µF

470pF

REF

CC

DL

IRF7805

PGND

FB

V

CC

1k

GND

1k

TO REMOTE

LOAD

100k

GNDS

FBS

PGOOD

TON SKIP OVP*

*MAX1710 ONLY

**MAX1711 ONLY

Figure 9. 5V-Powered, 7A CPU Buck Regulator

DAC code from the transitory value. Use 100ns maxi-

mum rise and fall times.

Using forced PWM mode repeatedly to ensure sink cur-

rent capability can have side effects, however. The ener-

gy taken from the output by the synchronous rectifier

isn’t lost, but is instead returned to the input. If the fre-

quency of the high-to-low output voltage transition is high

enough, efficiency will be degraded by the resistive “fric-

tion” losses associated with shuttling energy between

input and output capacitors. Also, if the output is being

overdriven by an external source (such as an external

docking-station power supply), forced PWM mode may

cause the battery voltage to become pumped up, possi-

bly overvoltaging the battery.

Selecting the output capacitors in dynamically adjusted

V

applications can be tricky due to trade-offs

CORE

between capacitor capacity and ESR. In other words, if

the capacitor has sufficiently low ESR to meet the load-

transient response specification, its large capacity may

cause excessive input surge currents. On the other

hand, a purely ceramic capacitor may not have enough

capacity to prevent overvoltage during the transition from

full- to no-load condition (see the overshoot equation

under Output Capacitor Selection). It may be necessary

to mix capacitor types or use specialized capacitors

such as those shown in Figure 7 in order to achieve the

required ESR while staying within the min/max capaci-

tance value window.

High-Power, Dynamically

Adjustable CPU Application

The MAX1711/MAX1712 V

regulator of Figure 10 is

CORE

designed to have its output voltage switched between

1.3V and 1.45V in less than 100µs, while causing a mini-

mum level of input surge current. To this end, the output

capacitors were selected for having the correct value to

a) support the needed ESR, b) prevent excess load-

If the minimum load is very light, it may be necessary to

assert forced PWM mode (via SKIP) during the transition

period to guarantee some output sink current capability.

Otherwise, the output voltage won’t ramp downwards

until pulled down by external load current.

______________________________________________________________________________________ 23

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

+5V INPUT

V

BATT

6 x 10µF/25V CERAMIC

10V TO 22V

0.1µF

1µF

20Ω

7

15

1

V

V+

V

DD

CC

2Ω

22

24

CMPSH3

BST

0.22µF

DH

IRF7805

REF

9

5

470pF

0.1µF

MAX1711

MAX1712

CC

23

13

10

LX

DL

GND

1µH/20A

OUTPUT

+1.5V AT 15A

ON/OFF

LSB

2

20

19

18

17

16

10x

220µF

4V

20µF

CERAMIC

SHDN

D0

14

PGND

2 x IRF7805

OS-CON

D1

DAC

INPUTS

3

D2

FB

4

FBS

D3

11

12

GNDS

PGOOD

SKIP

MSB

1k

D4

8

21

TON

N.C.

I

LIM

6

40k

1%

2N7002

POWERGOOD

200k

1%

2N7002

+3.3V

0.1µF

TRANSITION DETECTOR

100k

1%

49.9k

3MΩ

12

13

14

11

1%

A4

B4

V

CC

Y4

1k

100k

1%

1000pF

1N4148

9

A3

B3

1k

1000pF

10

8

6

3

MAX986

Y3

Y2

Y1

820pF

5%

1N4148

74HC86

+3.3V

4

5

2N7002

30k

A2

B2

1k

1000pF

30k

1N4148

1

2

A1

B1

1k

1000pF

GND

7

100k

2N7002

TIMER BLOCK

Figure 10.15A Dynamically Adjustable Notebook CPU Supply with Battery-Surge Current Limiting

24 ______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

V

BATT

GND IN

ALL ANALOG GROUNDS

CONNECT TO GND ONLY.

VIA TO PGND

NEAR Q2 SOURCE

MAX1710

MAX1711

MAX1712

VIA TO GNDS

V

CC

CIN

GND

OUT

CC

Q1

REF

D1

Q2

COUT

V

DD

I

LIM

V

OUT

GND

VIA TO SOURCE

OF Q2

CONNECT GND TO PGND

BENEATH IC, 1 POINT ONLY.

SPLIT ANALOG GND PLANE AS SHOWN.

VIA TO FBS

L1

VIA TO FB

NEAR COUT+

VIA TO LX

NOTES: "STAR" GROUND IS USED.

D1 IS DIRECTLY ACROSS Q2.

INDUCTOR DISCHARGE PATH HAS LOW DC RESISTANCE.

Figure 11. Power-Stage PC Board Layout Example

recovery overshoot, and c) minimize input surge cur-

rents.

signal. The internal PGOOD detector circuit monitors

only output undervoltage; PGOOD will probably go low

during upward transitions, but not downward. The final

power-good output will always go low for at least 75µs

due to the timer signal.

The optional 74HC86 exclusive-OR gate detects code

transitions on each of the four most-significant DAC

inputs. The transition detector output goes to a precision

pulse stretcher, a timer that extends the pulse for 75µs

(nominal). This signal then feeds three circuits: the

power-good detector, the SKIP input, and the ILIM cur-

rent-limit control input, thus reducing the current-limit

threshold during the transition interval (in order to reduce

battery current surges). Likewise, SKIP going high

asserts forced PWM mode in order to drag the output

voltage down to the new value. Forced PWM mode is

incompatible with good light-load efficiency due to

inductor-current recirculation losses and gate-drive loss-

es. Therefore, SKIP is driven high only during the 100µs

max transition interval.

Load current capability is 15A peak and 12A continuous

over a 10V to 22V input range. All three MOSFETs

require good heatsinking. See the MAX1711 EV kit man-

ual for a complete bill of materials.

PC Board Layout Guidelines

Careful PC board layout is critical to achieving low

switching losses and clean, stable operation. The

switching power stage requires particular attention

(Figure 11). If possible, mount all of the power compo-

nents on the top side of the board with their ground ter-

minals flush against one another. Follow these

guidelines for good PC board layout:

The power-good output signal is the logical OR of the

75µs timer signal and the MAX1711/MAX1712 PGOOD

______________________________________________________________________________________ 25

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

• Keep the high-current paths short, especially at the

ground terminals. This practice is essential for stable,

jitter-free operation.

Layout Procedure

1) Place the power components first, with ground termi-

nals adjacent (Q2 source, CIN-, COUT-, D1 anode). If

possible, make all these connections on the top layer

with wide, copper-filled areas.

• Connect GND and PGND together close to the IC.

Carefully follow the grounding instructions under step

4 of the Layout Procedure.

2) Mount the controller IC adjacent to MOSFET Q2,

preferably on the back side opposite Q2 to keep LX-

PGND current-sense lines and the DL gate-drive line

short and wide. The DL gate trace must be short and

wide, measuring 10 to 20 squares (50 to 100 mils

wide if the MOSFET is 1 inch from the controller IC).

• Keep the power traces and load connections short.

This practice is essential for high efficiency. The use

of thick copper PC boards (2 oz vs. 1 oz) can en-

hance full-load efficiency by 1% or more. Correctly

routing PC board traces is a difficult task that must be

approached in terms of fractions of centimeters,

where a single milliohm of excess trace resistance

causes a measurable efficiency penalty.

3) Group the gate-drive components (BST diode and

capacitor, V

bypass capacitor) together near the

DD

controller IC.

• LX and PGND connections to Q2 for current limiting

must be made using Kelvin sense connections in

order to guarantee the current-limit accuracy. With

SO-8 MOSFETs, this is best done by routing power to

the MOSFETs from outside using the top copper

layer, while tying in PGND and LX inside (underneath)

the SO-8 package.

4) Make the DC-DC controller ground connections as

shown in Figure 11. This diagram can be viewed as

having three separate ground planes: output ground,

where all the high-power components go; the PGND

plane, where the PGND pin and V

bypass capaci-

DD

tor go; and an analog GND plane, where sensitive

analog components go. The analog ground plane

and PGND plane must meet only at a single point

directly beneath the IC. These two planes are then

connected to the high-power output ground with a

• When trade-offs in trace lengths must be made, it’s

preferable to allow the inductor charging path to be

made longer than the discharge path. For example,

it’s better to allow some extra distance between the

input capacitors and the high-side MOSFET than to

allow distance between the inductor and the low-side

MOSFET or between the inductor and the output filter

capacitor.

short connection from V

cap/PGND to the source

DD

of the low-side MOSFET, Q2 (the middle of the star

ground). This point must also be very close to the out-

put capacitor ground terminal.

5) Connect the output power planes (V

and system

CORE

ground planes) directly to the output filter capacitor

positive and negative terminals with multiple vias.

Place the entire DC-DC converter circuit as close to

the CPU as is practical.

• Ensure that the FB connection to C

is short and

OUT

direct. However, in some cases it may be desirable to

deliberately introduce some trace length between the

FB inductor node and the output filter capacitor (see

the All-Ceramic-Capacitor Application section).

• Route high-speed switching nodes away from sensi-

tive analog areas (CC, REF, ILIM).

• Make all pin-strap control input connections (SKIP,

ILIM, etc.) to GND or V

rather than PGND or V

.

CC

DD

26 ______________________________________________________________________________________

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

Pin Configurations

TOP VIEW

V+

SHDN

FB

1

2

3

4

5

6

7

8

9

24 DH

23 LX

22 BST

21 SKIP

20 D0

19 D1

18 D2

17 D3

16 OVP

V+

SHDN

FB

1

2

3

4

5

6

7

8

9

24 DH

23 LX

22 BST

21 SKIP

20 D0

19 D1

18 D2

17 D3

16 D4

FBS

CC

FBS

CC

MAX1710

MAX1711

MAX1712

ILIM

V

CC

V

CC

TON

REF

TON

REF

GND 10

GNDS 11

PGOOD 12

15 V

DD

GND 10

GNDS 11

PGOOD 12

15 V

DD

14 PGND

13 DL

14 PGND

13 DL

QSOP

______________________________________________________________________________________ 27

High-Speed, Digitally Adjusted

Step-Down Controllers for Notebook CPUs

Package Information

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600

Printed USA

is a registered trademark of Maxim Integrated Products.


型号：	MAX1711EEG-T
厂家：	Rochester Electronics
描述：	SWITCHING CONTROLLER, 550kHz SWITCHING FREQ-MAX, PDSO24, 0.150 INCH, 0.025 INCH PITCH, QSOP-24 输入元件开关光电二极管
文件：	总29页 (文件大小：1119K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MAX1711EEG-T [ROCHESTER]

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