MAX1286ETA+ [MAXIM]
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| 型号： | MAX1286ETA+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
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19-2231; Rev 0; 10/01
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
Ge n e ra l De s c rip t io n
Fe a t u re s
The MAX1286–MAX1289 are low-cost, micropower, seri-
al output 12-bit analog-to-digital converters (ADCs)
available in a tiny 8-pin SOT23. The MAX1286/MAX1288
op e ra te with a s ing le + 5V s up p ly. The MAX1287/
MAX1289 op e ra te with a s ing le + 3V s up p ly. The
devices feature a successive-approximation ADC, auto-
matic shutdown, fast wakeup (1.4µs), and a high-speed
3-wire interface. Power consumption is only 0.5mW
♦ Single-Supply Operation
+3V (MAX1287/MAX1289)
+5V (MAX1286/MAX1288)
♦ Autoshutdown Between Conversions
♦ Low Power
245µA at 150ksps
150µA at 100ksps
15µA at 10ksps
2µA at 1ksps
(V
= + 2.7V) a t the ma ximum s a mp ling ra te of
DD
150ksps. AutoShutdown™ (0.2µA) between conversions
re s ults in re d uc e d p owe r c ons ump tion a t s lowe r
throug hp ut ra te s . The MAX1286/MAX1287 p rovid e
2-channel, single-ended operations and accept input
0.2µA in Shutdown
♦ True-Differential Track/Hold, 150kHz Sampling Rate
signals from 0 to V . The MAX1288/MAX1289 accept
♦ Software-Configurable Unipolar/Bipolar
Conversion (MAX1288/MAX1289 Only)
♦ SPI/QSPI/MICROWIRE–Compatible Interface for
DSPs and Processors
REF
true-differential inputs ranging from 0 to V
. Data is
REF
accessed using an external clock through the 3-wire
SPI™/QSPI™/MICROWIRE™–compatible serial inter-
face. Excellent dynamic performance, low power, ease
of use, and small package size make these converters
ideal for portable battery-powered data-acquisition
applications, and for other applications that demand low
power consumption and minimal space.
♦ Internal Conversion Clock
♦ 8-Pin SOT23 Package
Ap p lic a t io n s
Ord e rin g In fo rm a t io n
Low-Power Data Acquisition
TEMP.
PIN-
TOP
PART
Portable Temperature Monitors
Flowmeters
RANGE
PACKAGE
MARK
MAX1286EKA-T
MAX1287EKA-T
MAX1288EKA-T
MAX1289EKA-T
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
8 SOT23-8
8 SOT23-8
8 SOT23-8
8 SOT23-8
AAFA
AAEW
AAFC
AAEY
Touch Screens
P in Co n fig u ra t io n
TOP VIEW
V
1
2
3
4
8
7
6
5
SCLK
DOUT
CNVST
REF
DD
AIN1 (AIN+)
AIN2 (AIN-)
GND
MAX1286
MAX1287
MAX1288
MAX1289
SOT23
AutoShutdown is a trademark of Maxim Integrated Products, Inc.
SPI and QSPI are trademarks of Motorola, Inc.
( ) ARE FOR THE MAX1288/MAX1289
MICROWIRE is a trademark of National Semiconductor Corp.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
ABSOLUTE MAXIMUM RATINGS
V
to GND..............................................................-0.3V to +6V
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
DD
CNVST, SCLK, DOUT to GND....................-0.3V to (V + 0.3V)
REF, AIN1 (AIN+), AIN2 (AIN-) to GND......-0.3V to (V + 0.3V)
DD
DD
Maximum Current into Any Pin............................................50mA
Continuous Power Dissipation (T = +70°C)
A
8-Pin SOT23 (derate 9.70mW/°C above T = +70°C) ...696mW
A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V = +2.7V to +3.6V, V
= +2.5V for MAX1287/MAX1289, or VDD = +4.75V to +5.25V, V
= +4.096V for MAX1286/MAX1288,
DD
REF
REF
0.1µF capacitor at REF, f
= 8MHz (50% duty cycle), AIN- = GND for MAX1288/MAX1289. T = T
to T
unless otherwise
SCLK
A
MIN
MAX,
noted. Typical values at T = +25°C.)
A
PARAMETER
DC ACCURACY (Note 1)
Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
12
Bits
LSB
Relative Accuracy (Note 2)
Differential Nonlinearity
Offset Error
INL
±1.0
±1.0
±4
DNL
No missing codes over temperature
LSB
±2
LSB
Gain Error (Note 3)
±2
±4
LSB
Gain Temperature Coefficient
Offset Temperature Coefficient
Channel-to-Channel Offset Matching
Channel-to-Channel Gain Matching
Input Common-Mode Rejection
±0.4
±0.4
±0.1
±0.1
±0.1
ppm/°C
ppm/°C
LSB
LSB
CMR
V
CM
= 0V to V ; zero scale input
mV
DD
DYNAMIC SPECIFICATIONS: (f (sine-wave) = 10kHz, V = 4.096Vp-p for MAX1086/MAX1088 or V = 2.5V
IN
IN
IN
p-p
for MAX1087/MAX1089, 150ksps, f
= 8MHz, (50% duty cycle) AIN- = GND for MAX1088/MAX1089)
SCLK
Signal to Noise Plus Distortion
SINAD
70
dB
dB
Total Harmonic Distortion
(up to the 5th harmonic)
THD
-80
Spurious-Free Dynamic Range
Full-Power Bandwidth
Full-Linear Bandwidth
CONVERSION RATE
Conversion Time
SFDR
80
1
dB
MHz
kHz
-3dB point
SINAD > 56dB
100
t
Does not include t
3.7
1.4
µs
µs
CONV
ACQ
T/H Acquisition Time
Aperture Delay
t
ACQ
30
ns
Aperture Jitter
<50
ps
Maximum Serial Clock Frequency
Duty Cycle
f
8
MHz
%
SCLK
30
70
ANALOG INPUT
Unipolar
Bipolar
0
V
REF
Input Voltage Range (Note 4)
V
-V
/2
V
/2
REF
REF
2
_______________________________________________________________________________________
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
ELECTRICAL CHARACTERISTICS (continued)
(V = +2.7V to +3.6V, V
= +2.5V for MAX1287/MAX1289, or VDD = +4.75V to +5.25V, V
= +4.096V for MAX1286/MAX1288,
DD
REF
REF
0.1µF capacitor at REF, f
= 8MHz (50% duty cycle), AIN- = GND for MAX1288/MAX1289. T = T
to T
unless otherwise
SCLK
A
MIN
MAX,
noted. Typical values at T = +25°C.)
A
PARAMETER
Input Leakage Current
SYMBOL
CONDITIONS
MIN
TYP
±0.01
34
MAX
UNITS
µA
Channel not selected or conversion stopped
±1
Input Capacitance
pF
EXTERNAL REFERENCE INPUT
V
DD
Input Voltage Range
V
REF
1.0
V
+50mV
V
= +2.5V at 150ksps
16
26
30
45
±1
REF
Input Current
I
V
REF
= +4.096V at 150ksps
µA
REF
Acquisition/Between conversions
DIGITAL INPUTS/OUTPUTS (SCLK, CNVST, DOUT)
±0.01
Input Low Voltage
Input High Voltage
Input Leakage Current
Input Capacitance
V
0.8
V
V
IL
V
IH
V
-1
DD
I
L
±0.01
15
±1.0
µA
pF
V
C
IN
I
= 2mA
= 4mA
0.4
0.8
SINK
Output Low Voltage
Output High Voltage
V
OL
I
V
SINK
V
-0.5
DD
V
OH
I
= 1.5mA
V
SOURCE
Three-State Leakage Current
Three-State Output Capacitance
POWER REQUIREMENTS
CNVST = GND
CNVST = GND
±0.05
15
±10
µA
pF
C
OUT
MAX1086/MAX1088
MAX1087/MAX1089
4.75
2.7
5.0
3.0
245
150
15
5.25
3.6
Positive Supply Voltage
Positive Supply Current
Positive Supply Rejection
V
V
DD
f
=150ksps
=100ksps
=10ksps
=1ksps
350
SAMPLE
f
SAMPLE
V
= +3V
= +5V
DD
f
SAMPLE
f
2
SAMPLE
f
=150ksps
=100ksps
=10ksps
=1ksps
320
215
22
400
I
DD
µA
mV
SAMPLE
f
SAMPLE
V
DD
f
SAMPLE
f
2.5
0.2
±0.3
±0.4
SAMPLE
Shutdown
5
V
DD
= 5V ±5%; full-scale input
±1.0
±1.2
PSR
V
DD
= +2.7V to +3.6V; full-scale input
_______________________________________________________________________________________
3
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
TIMING CHARACTERISTICS (Figures 1, 2, and 5)
(V = +2.7V to +3.6V, V
= +2.5V, 0.1µF capacitor at REF, or V = +4.75V to +5.25V for MAX1286/MAX1288, V = +4.096V,
DD
REF
DD
REF
0.1µF capacitor at REF, f
= 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289. T = T
to T unless otherwise
MAX,
SCLK
A
MIN
noted. Typical values at T = +25°C.)
A
PARAMETERS
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to DOUT Transition
SCLK Rise to DOUT Disable
CNVST Rise to DOUT Enable
CNVST Fall to MSB Valid
CNVST Pulse Width
SYMBOL
CONDITIONS
MIN
38
TYP
MAX
UNITS
ns
t
CH
t
38
ns
CL
t
C
C
C
C
= 30pF
= 30pF
= 30pF
= 30pF
60
500
80
ns
DOT
DOD
LOAD
LOAD
LOAD
LOAD
t
100
30
ns
t
ns
DOE
t
3.7
µs
CONV
t
ns
CSW
Note 1: Unipolar mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: Offset nulled.
Note 4: The absolute input voltage range for the analog inputs is from GND to V
.
DD
• • •
CNVST
SCLK
t
CH
t
CSW
t
CL
• • •
t
t
DOT
t
DOD
DOE
HIGH-Z
HIGH-Z
DOUT
• • •
Figure 1. Detailed Serial-Interface Timing Sequence
V
DD
6kΩ
DOUT
DOUT
6kΩ
C
L
C
L
GND
a) HIGH -Z TO V , V TO V , AND V TO HIGH -Z
GND
b) HIGH -Z TO V , V TO V , AND V TO HIGH -Z
OH OL
OH
OH
OL OH
OL
OL
Figure 2. Load Circuits for Enable/Disable Times
_______________________________________________________________________________________
4
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s
(V
DD
= +3V, V
= +2.5V for MAX1287/MAX1289. V
= +5V, V
= +4.096V for MAX1286/MAX1288; 0.1µF capacitor at REF,
REF
DD
REF
f
= 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289, T = +25°C, unless otherwise noted.)
A
SCLK
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
INTEGRAL NONLINEARITY
vs. OUTPUT CODE
1.0
0.8
1.0
0.8
1.0
MAX1286/MAX1288
MAX1287/MAX1289
MAX1287/MAX1289
0.8
0.6
0.6
0.6
0.4
0.4
0.4
0.2
0.2
0.2
0
0
0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
500 1000 1500 2000 2500 3000 3500 4000 4500
OUTPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 4500
OUTPUT CODE
0
500 1000 1500 2000 2500 3000 3500 4000 4500
OUTPUT CODE
SUPPLY CURRENT
vs. SAMPLING RATE
SUPPLY CURRENT
vs. SAMPLING RATE
DIFFERENTIAL NONLINEARITY
vs. OUTPUT CODE
1.0
0.8
1000
100
10
1
1000
100
10
MAX1286/MAX1288
MAX1287/MAX1289
MAX1286/MAX1288
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
1
0
0.1
100
1
100
1
0
0.1
10
1000
0
0.1
10
1000
0
500 1000 1500 2000 2500 3000 3500 4000 4500
OUTPUT CODE
SAMPLING RATE (ksps)
SAMPLING RATE (ksps)
SUPPLY CURRENT
vs. TEMPERATURE
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
430
380
300
MAX1286
360
340
320
300
280
260
240
220
200
180
250
200
150
100
50
380
330
280
230
180
0
-40 -20
0
20
40
60
80
2.7
3.2
3.7
4.2
(V)
4.7
5.2
2.7
3.2
3.7
4.2
(V)
4.7
5.2
TEMPERATURE (°C)
V
DD
V
DD
_______________________________________________________________________________________
5
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
Typ ic a l Op e ra t in g Ch a ra c t e ris t ic s (c o n t in u e d )
(V
DD
= +3V, V
= +2.5V for MAX1287/MAX1284. V
= +5V, V
= +4.096V for MAX1286/MAX1288; 0.1µF capacitor at REF,
REF
DD
REF
f
= 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289, T = +25°C, unless otherwise noted.)
A
SCLK
SHUTDOWN CURRENT
vs. TEMPERATURE
OFFSET ERROR
vs. TEMPERATURE
OFFSET ERROR
vs. SUPPLY VOLTAGE
300
1.00
0.80
1.0
0.8
250
200
150
100
50
0.60
0.6
0.40
0.4
0.2
0.20
0.00
0
-0.20
-0.40
-0.60
-0.80
-1.00
-0.2
-0.4
-0.6
-0.8
-1.0
0
-40 -20
0
20
40
60
80
-40 -20
0
20
40
60
80
2.7
3.2
3.7
4.2
(V)
4.7
5.2
TEMPERATURE (°C)
TEMPERATURE (°C)
V
DD
GAIN ERROR
GAIN ERROR
vs. TEMPERATURE
FFT PLOT (SINAD)
vs. SUPPLY VOLTAGE
2.0
1.6
2.0
20
0
1.6
1.2
1.2
-20
-40
-60
-80
-100
-120
-140
0.8
0.8
0.4
0.4
0
0
-0.4
-0.8
-1.2
-1.6
-2.0
-0.4
-0.8
-1.2
-1.6
-2.0
-40 -20
0
20
40
60
80
2.7
3.2
3.7
4.2
(V)
4.7
5.2
0
15k
30k
45k
60k
TEMPERATURE (°C)
V
DD
FREQUENCY (Hz)
6
_______________________________________________________________________________________
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
P in De s c rip t io n
NAME
PIN
FUNCTION
MAX1286 MAX1288
MAX1287 MAX1289
Positive Supply Voltage. +2.7V to +3.6V (MAX1287/MAX1289); +4.75V to +5.25V
(MAX1286/MAX1288). Bypass with a 0.1µF capacitor to GND.
1
2
3
4
5
V
V
DD
DD
AIN1
AIN2
GND
REF
AIN+
AIN-
GND
REF
Analog Input Channel 1 (MAX1286/MAX1287) or Positive Analog Input (MAX1288/MAX1289)
Analog Input Channel 2 (MAX1286/MAX1287) or Negative Analog Input (MAX1288/MAX1289)
Ground
External Reference Voltage Input. Sets the analog voltage range. Bypass with a 0.1µF
capacitor to GND.
Conversion Start. A rising edge powers up the IC and places it in track mode. At the falling
edge of CNVST, the device enters hold mode and begins conversion. CNVST also selects the
input channel (MAX1286/MAX1287) or input polarity (MAX1288/MAX1289).
6
CNVST
CNVST
Serial Data Output. DOUT transitions the falling edge of SCLK. DOUT goes low at the start of a
conversion and presents the MSB at the completion of a conversion. DOUT goes high
impedance once data has been fully clocked out.
7
8
DOUT
SCLK
DOUT
SCLK
Serial Clock Input. Clocks out data at DOUT MSB first.
The serial interface provides easy interfacing to micro-
De t a ile d De s c rip t io n
processors (µPs). Figure 3 shows the simplified internal
structure for the MAX1286/MAX1287 (2 channels, sin-
gle ended) and the MAX1288/MAX1289 (1 channel,
true differential).
The MAX1286–MAX1289 ADCs us e a s uc c e s s ive -
approximation conversion (SAR) technique and an on-
c hip tra c k-a nd -hold (T/H) s truc ture to c onve rt a n
analog signal into a 12-bit digital result.
Tru e -Diffe re n t ia l An a lo g In p u t T/H
The e q uiva le nt c irc uit of Fig ure 4 s hows the
MAX1286–MAX1289s’ input architecture, which is com-
posed of a T/H, input multiplexer, comparator, and
switched-capacitor DAC. The T/H enters its tracking
mode on the rising edge of CNVST. The positive input
capacitor is connected to AIN1 or AIN2 (MAX1286/
MAX1287) or AIN+ (MAX1288/MAX1289). The negative
inp ut c a p a c itor is c onne c te d to GND (MAX1286/
MAX1287) or AIN- (MAX1288/MAX1289). The T/H
enters its hold mode on the falling edge of CNVST and
the difference between the sampled positive and nega-
tive input voltages is converted. The time required for
the T/H to acquire an input signal is determined by how
quickly its input capacitance is charged. If the input
signal’s source impedance is high, the acquisition time
lengthens, and CNVST must be held high for a longer
MAX1286–MAX1289
OSCILLATOR
CNVST
SCLK
INPUT SHIFT
REGISTER
CONTROL
AIN1
(AIN+)
12-BIT
SAR
ADC
DOUT
T/H
AIN2
(AIN-)
REF
period of time. The acquisition time, t
, is the maxi-
ACQ
mum time needed for the signal to be acquired, plus
the power-up time. It is calculated by the following
equation:
( ) ARE FOR MAX1288/MAX1289
Figure 3. Simplified Functional Diagram
t
= 9 x (R + R ) x 24pF + t
S IN PWR
ACQ
_______________________________________________________________________________________
7
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
If all 12 bits of data are not clocked out before CNVST
is driven high, AIN2 is selected for the next conversion.
REF
GND
DAC
AIN2
AIN1 (AIN+)
S e le c t in g Un ip o la r o r Bip o la r Co n ve rs io n s
(MAX1 2 8 8 /MAX1 2 8 9 )
Initia te true -d iffe re ntia l c onve rs ions with the
MAX1288/MAX1289s ’ unip ola r a nd b ip ola r mod e s ,
using the CNVST pin. AIN+ and AIN- are sampled at
the falling edge of CNVST. In unipolar mode, AIN+ can
CIN+
CIN-
COMPARATOR
+
HOLD
-
e xc e e d AIN- b y up to V
. The outp ut forma t is
REF
RIN-
RIN+
HOLD
GND (AIN-)
s tra ig ht b ina ry. In b ip ola r mod e , e ithe r inp ut c a n
exceed the other by up to V /2. The output format is
REF
HOLD
/2
two’s complement.
TRACK
V
DD
Note: In both modes, AIN+ and AIN- must not exceed
( ) ARE FOR MAX1288/MAX1289
V
DD
by more than 50mV or be lower than GND by more
than 50mV.
Figure 4. Equivalent Input Circuit
If unipolar mode is desired (Figure 5a), drive CNVST
high to power up the ADC and place the T/H in track
mod e with AIN+ a nd AIN- c onne c te d to the inp ut
where R = 1.5kΩ, R is the source impedance of the
IN
S
input signal, and t
device.
= 1µs is the power-up time of the
PWR
capacitors. Hold CNVST high for t
to fully acquire
ACQ
the signal. Drive CNVST low to place the T/H in hold
mode. The ADC then performs a conversion and shut-
down automatically. The MSB is available at DOUT
after 3.7µs. Data can then be clocked out using SCLK.
Clock out all 12 bits of data before driving CNVST high
for the next conversion. If all 12 bits of data are not
clocked out before CNVST is driven high, bipolar mode
is selected for the next conversion.
Note: t
is never less than 1.4µs and any source
ACQ
impedance below 300Ω does not significantly affect the
ADC’s AC performance. A high-impedance source can
be accommodated either by lengthening t
or by
ACQ
placing a 1µF capacitor between the positive and neg-
ative analog inputs.
S e le c t in g AIN1 o r AIN2
(MAX1 2 8 6 /MAX1 2 8 7 )
Select one of the MAX1286/MAX1287s’ two positive
input channels using the CNVST pin. If AIN1 is desired
(Figure 5a), drive CNVST high to power up the ADC
and place the T/H in track mode with AIN1 connected
to the positive input capacitor. Hold CNVST high for
If bipolar mode is desired (Figure 5b), drive CNVST
high for at least 30ns. Next, drive it low for at least 30ns
and then high again. This places the T/H in track mode
with AIN+ and AIN- connected to the input capacitors.
Now hold CNVST high for t
to fully acquire the sig-
ACQ
nal. Drive CNVST low to place the T/H in hold mode.
The ADC then performs a conversion and shutdown
a utoma tic a lly. The MSB is a va ila b le a t DOUT a fte r
3.7µs. Data can then be clocked out using SCLK. If all
12 bits of data are not clocked out before CNVST is dri-
ven high, bipolar mode is selected for the next conver-
sion.
t
to fully acquire the signal. Drive CNVST low to
ACQ
place the T/H in hold mode. The ADC then performs a
conversion and shutdown automatically. The MSB is
a va ila b le a t DOUT a fte r 3.7µs . Da ta c a n the n b e
clocked out using SCLK. Clock out all 12 bits of data
before driving CNVST high for the next conversion. If all
12 bits of data are not clocked out before CNVST is dri-
ven high, AIN2 is selected for the next conversion.
In p u t Ba n d w id t h
The ADC’s input tracking circuitry has a 1MHz small-
signal bandwidth, so it is possible to digitize high-
speed transient events and measure periodic signals
with bandwidths exceeding the ADC’s sampling rate by
using undersampling techniques. To avoid high-fre-
quency signals being aliased into the frequency band
of interest, anti-alias filtering is recommended.
If AIN2 is desired (Figure 5b), drive CNVST high for at
least 30ns. Next, drive it low for at least 30ns, and then
high again. This powers up the ADC and places the
T/H in track mode with AIN2 connected to the positive
input capacitor. Now hold CNVST high for t
to fully
ACQ
acquire the signal. Drive CNVST low to place the T/H in
hold mode. The ADC then performs a conversion and
shutdown automatically. The MSB is available at DOUT
after 3.7µs. Data can then be clocked out using SCLK.
8
_______________________________________________________________________________________
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
t
CONV
t
ACQ
CNVST
1
4
8
12
SCLK
DOUT
HIGH-Z
B11
MSB
B0
LSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
HIGH-Z
SAMPLING INSTANT
Figure 5a. Single Conversion AIN1 vs. GND (MAX1286/MAX1287), Unipolar Mode AIN+ vs. AIN- (MAX1288/MAX1289)
t
CONV
t
ACQ
CNVST
1
4
8
12
SCLK
DOUT
HIGH-Z
B11
MSB
B0
LSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
HIGH-Z
SAMPLING INSTANT
Figure 5b. Single Conversion AIN2 vs. GND (MAX1286/MAX1287), Bipolar Mode AIN+ vs. AIN- (MAX1288/MAX1289)
An a lo g In p u t P ro t e c t io n
Internal protection diodes that clamp the analog input to
and GND allow the analog input pins to swing from
GND - 0.3V to V + 0.3V without damage. Both inputs
In t e rn a l Clo c k
The MAX1286–MAX1289 operate from an internal oscilla-
tor, which is accurate within 10% of the 4MHz specified
clock rate. This results in a worst-case conversion time of
3.7µs. The internal clock releases the system micro-
processor from running the SAR conversion clock and
allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0 to
8MHz.
V
DD
DD
must not exceed V
by more than 50mV or be lower
DD
than GND by more than 50mV for accurate conversions.
If an off-channel analog input voltage exceeds the
supplies, limit the input current to 2mA.
_______________________________________________________________________________________
9
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
Ou t p u t Da t a Fo rm a t
Figures 5a and 5b illustrate the conversion timing for the
MAX1286–MAX1289. The 12-bit conversion result is out-
p ut in MSB-firs t forma t. Da ta on DOUT tra ns itions
on the falling edge of SCLK. All 12 bits must be clocked
out before CNVST transitions again. For the MAX1288/
MAX1289, data is straight binary for unipolar mode and
two’s complement for bipolar mode. For the MAX1286/
MAX1287, data is always straight binary.
Ex t e rn a l Re fe re n c e
An external reference is required for the MAX1286–
MAX1289. Use a 0.1µF bypass capacitor for best per-
formance. The reference input structure allows a volt-
age range of +1V to V + 50mV.
DD
Conne c tion to Sta nda rd Inte rfa c e s
The MAX1286–MAX1289 feature a serial interface that is
fully compatible with SPI, QSPI, and MICROWIRE. If a
serial interface is available, establish the CPU’s serial
interface as a master, so that the CPU generates the seri-
al clock for the ADCs. Select a clock frequency up to
8MHz.
Tra n s fe r Fu n c t io n
Figure 6 shows the unipolar transfer function for the
MAX1286–MAX1289. Figure 7 shows the bipolar transfer
function for the MAX1288/MAX1289. Code transitions
occur halfway between successive-integer LSB values.
Ho w t o P e rfo rm a Co n ve rs io n
1) Use a general-purpose I/O line on the CPU to hold
CNVST low between conversions.
Ap p lic a t io n s In fo rm a t io n
2) Drive CNVST hig h to a c q uire AIN1(MAX1286/
MAX1287) or unipolar mode (MAX1288/MAX1289).
To acquire AIN2 (MAX1286/MAX1287) or bipolar
mode (MAX1288/MAX1289), drive CNVST low and
high again.
Au t o m a t ic S h u t d o w n Mo d e
With CNVST low, the MAX1286–MAX1289 default to an
AutoShutd own s ta te (< 0.2µA) a fte r p owe r-up a nd
between conversions. After detecting a rising edge on
CNVST, the part powers up, sets DOUT low, and enters
track mode. After detecting a falling edge on CNVST, the
device enters hold mode and begins the conversion. A
maximum of 3.7µs later, the device completes conver-
sion, enters shutdown, and MSB is available at DOUT.
3) Hold CNVST high for 1.4µs.
4) Drive CNVST low and wait approximately 3.7µs for
conversion to complete. After 3.7µs, the MSB is
available at DOUT.
5) Activate SCLK for a minimum of 12 rising clock
OUTPUT CODE
MAX1288/MAX1289
OUTPUT CODE
MAX1286–
MAX1289
V
2
REF
FS
=
011 . . . 111
011 . . . 110
FULL-SCALE
TRANSITION
11 . . . 111
ZS = 0
-FS =
11 . . . 110
11 . . . 101
-V
2
REF
000 . . . 010
000 . . . 001
000 . . . 000
V
4096
REF
1LSB =
FS = V
REF
111 . . . 111
111 . . . 110
111 . . . 101
ZS = GND
V
REF
1LSB =
4096
00 . . . 011
00 . . . 010
100 . . . 001
100 . . . 000
00 . . . 001
00 . . . 000
0
- FS
+FS - 1LSB
0
1
2
3
FS
INPUT VOLTAGE (LSB)
FS - 3/2LSB
INPUT VOLTAGE (LSB)
≤
*V
COM
V
/ 2 *V = (AIN+) - (AIN-)
REF IN
Figure 7. Bipolar Transfer Function
10 ______________________________________________________________________________________
Figure 6. Unipolar Transfer Function
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
edges. DOUT transitions on SCLK’s falling edge
and is available in MSB-first format. Observe the
SCLK to DOUT valid timing characteristic. Clock
data into the µP on SCLK’s rising edge.
SCLK’s ris ing e d g e . The firs t 12 b its a re the d a ta .
DOUT then goes high impedance (Figure 9b).
P IC1 6 a n d S S P Mo d u le a n d
P IC1 7 In t e rfa c e
The MAX1286–MAX1289 a re c omp a tib le with a
PIC16/PIC17 µC, using the synchronous serial port
(SSP) module
S P I a n d MICROWIRE In t e rfa c e
When using an SPI (Figure 8a) or MICROWIRE inter-
face (Figures 8a and 8b), set CPOL = CPHA = 0. Two
8-bit readings are necessary to obtain the entire 12-bit
result from the ADC. DOUT data transitions on the seri-
al clock’s falling edge and is clocked into the µP on
SCLK’s rising edge. The first 8-bit data stream contains
the first 8-bits of DOUT starting with the MSB. The sec-
ond 8-bit data stream contains the remaining four result
bits. DOUT then goes high impedance.
To establish SPI communication, connect the controller
as shown in Figure 10a and configure the PIC16/PIC17
as system master. This is done by initializing its syn-
chronous serial port control register (SSPCON) and
synchronous serial port status register (SSPSTAT) to
the bit patterns shown in Tables 1 and 2.
In SPI mode, the PIC16/PIC17 µCs allow 8 bits of data
to be synchronously transmitted and received simulta-
neously. Two consecutive 8-bit readings (Figure 10b)
are necessary to obtain the entire 12-bit result from the
ADC. DOUT data transitions on the serial clock’s falling
edge and is clocked into the µC on SCLK’s rising edge.
The first 8-bit data stream contains the first 8 data bits
starting with the MSB. The second data stream con-
tains the remaining bits, D3 through D0.
QS P I In t e rfa c e
Using the high-speed QSPI interface (Figure 9a) with
CPOL = 0 and CPHA = 0, the MAX1286–MAX1289
support a maximum f
of 8MHz. One 12- to 16-bit
SCLK
reading is necessary to obtain the entire 12-bit result
from the ADC. DOUT da ta tra nsitions on the se ria l
c loc k’s fa lling e d g e a nd is c loc ke d into the µP on
I/O
SCK
CNVST
SCLK
DOUT
I/O
SK
SI
CNVST
SCLK
DOUT
MISO
V
DD
SPI
MICROWIRE
MAX1286–
MAX1289
MAX1286–
MAX1289
SS
Figure 8a. SPI Connections
Figure 8b. MICROWIRE Connections
Table 1. Detailed SSPCON Register Content
MAX1286–MAX1289
CONTROL BIT
SYNCHRONOUS SERIAL PORT CONTROL REGISTER (SSPCON)
SETTINGS
WCOL
Bit 7
Bit 6
X
X
Write Collision Detection Bit
SSPOV
Receive Overflow Detect Bit
Synchronous Serial Port Enable Bit:
SSPEN
Bit 5
1
0: Disables serial port and configures these pins as I/O port pins.
1: Enables serial port and configures SCK, SDO, and SCI pins as serial port pins.
CKP
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0
0
0
0
1
Clock Polarity Select Bit. CKP = 0 for SPI master mode selection.
SSPM3
SSPM2
SSPM1
SSPM0
Synchronous Serial Port Mode Select Bit. Sets SPI master mode and selects
F
CLK
= f
/ 16.
OSC
______________________________________________________________________________________ 11
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
CNVST
1ST BYTE READ
4
2ND BYTE READ
12
1
8
16
SCLK
DOUT
HIGH-Z
B11
MSB
B0
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
LSB
SAMPLING INSTANT
Figure 8c. SPI/MICROWIRE Interface Timing Sequence (CPOL = CPHA = 0)
one starpoint (Figure 11), connecting the two ground
systems (analog and digital). For lowest-noise opera-
tion, ensure the ground return to the star ground’s
power supply is low impedance and as short as possi-
ble. Route digital signals far away from sensitive analog
and reference inputs.
La yo u t , Gro u n d in g , a n d Byp a s s in g
For best performance, use printed circuit (PC) boards.
Wire-wrap configurations are not recommended since
the layout should ensure proper separation of analog
and digital traces. Do not run analog and digital lines
parallel to each other, and do not lay out digital signal
paths underneath the ADC package. Use separate
analog and digital PC board ground sections with only
High-frequency noise in the power supply (V ) may
DD
degrade the performance of the ADC’s fast comparator.
Bypass V
to the star ground with a 0.1µF capacitor,
DD
located as close as possible to the MAX1286–MAX1289s’
power-supply pin. Minimize capacitor lead length for best
supply-noise rejection. Add an attenuation resistor (5Ω) if
the power supply is extremely noisy.
CS
SCK
CNVST
SCLK
DOUT
MISO
V
DD
QSPI
MAX1286–
MAX1289
SS
Figure 9a. QSPI Connections
Table 2. Detailed SSPSTAT Register Content
MAX1286–MAX1289
CONTROL BIT
SYNCHRONOUS SERIAL STATUS REGISTER (SSPSTAT)
SETTINGS
SPI Data Input Sample Phase. Input data is sampled at the middle of the data
output time.
SMP
CKE
Bit 7
Bit 6
0
SPI Clock Edge Select Bit. Data is transmitted on the rising edge of the serial
clock.
1
D/A
P
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
X
X
X
X
X
X
Data Address Bit
Stop Bit
S
Start Bit
R/W
UA
BF
Read/Write Bit Information
Update Address
Buffer Full Status Bit
12 ______________________________________________________________________________________
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
CNVST
1
4
8
12
16
SCLK
DOUT
HIGH-Z
B11
MSB
B0
LSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
SAMPLING INSTANT
Figure 9b. QSPI Interface Timing Sequence (CPOL = CPHA = 0)
De fin it io n s
V
DD
V
DD
In t e g ra l No n lin e a rit y
Integral nonlinearity (INL) is the deviation of the values
on an actual transfer function from a straight line. This
straight line can be either a best-straight-line fit or a line
drawn between the end points of the transfer function,
once offset and gain errors have been nullified. The sta-
tic linearity parameters for the MAX1286–MAX1289 are
measured using the end-point method.
SCLK
DOUT
SCK
SDI
I/O
CNVST
PIC16/PIC17
MAX1286–
MAX1289
Diffe re n t ia l No n lin e a rit y
Differential nonlinearity (DNL) is the difference between
an actual step width and the ideal value of 1LSB. A
DNL error specification of less than 1LSB guarantees
no missing codes and a monotonic transfer function.
GND
GND
Figure 10a. SPI Interface Connection for a PIC16/PIC17 Controller
CNVST
1ST BYTE READ
2ND BYTE READ
1
4
8
12
16
SCLK
DOUT
HIGH-Z
B11
MSB
B0
LSB
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
SAMPLING INSTANT
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3 - SSPM0 = 0001)
______________________________________________________________________________________ 13
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
S ig n a l-t o -No is e P lu s Dis t o rt io n
Signal-to-noise plus distortion (SINAD) is the ratio of the
fundamental input frequency’s RMS amplitude to RMS
equivalent of all other ADC output signals.
SUPPLIES
SINAD (dB) = 20 ♦ log (Signal
/ Noise
)
RMS
RMS
+5V OR
+3V
V
LOGIC
= +5V
OR +3V
GND
Effe c t ive Nu m b e r o f Bit s
Effective number of bits (ENOB) indicates the global
accuracy of an ADC at a specific input frequency and
sampling rate. An ideal ADC’s error consists of quanti-
zation noise only. With an input range equal to the full-
scale range of the ADC, calculate the effective number
of bits as follows:
R* = 5Ω
0.1µF
ENOB = (SINAD - 1.76) / 6.02
GND
V
DD
+5V OR DGND
+3V
To t a l Ha rm o n ic Dis t o rt io n
Total harmonic distortion (THD) is the ratio of the RMS
sum of the first five harmonics of the input signal to the
fundamental itself. This is expressed as:
DIGITAL
CIRCUITRY
MAX1286–
MAX1289
*OPTIONAL
V22 + V32 + V42 + V52
THD = 20 × log
V
1
Figure 11. Power-Supply and Grounding Connections
where V is the fundamental amplitude, and V through
1
2
Ap e rt u re De fin it io n s
Aperture jitter (t ) is the sample-to-sample variation in
V are the amplitudes of the 2nd- through 5th-order har-
5
AJ
monics.
the time between the samples. Aperture delay (t ) is
AD
S p u rio u s -Fre e Dyn a m ic Ra n g e
Spurious-free dynamic range (SFDR) is the ratio of RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next-largest distortion
component.
the time between the rising edge of the sampling clock
and the instant when an actual sample is taken.
S ig n a l-t o -No is e Ra t io
For a waveform perfectly reconstructed from digital sam-
ples, signal-to-noise ratio (SNR) is the ratio of full-scale
analog input (RMS value) to the RMS quantization error
(residual error). The ideal, theoretical minimum analog-to-
digital noise is caused by quantization error only and
results directly from the ADC’s resolution (N bits):
Ch ip In fo rm a t io n
TRANSISTOR COUNT: 6922
PROCESS: BiCMOS
SNR = (6.02 ♦ N + 1.76)dB
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise, which includes all spectral
components minus the fundamental, the first five har-
monics, and the DC offset.
14 ______________________________________________________________________________________
1 5 0 k s p s , 1 2 -Bit , 2 -Ch a n n e l S in g le -En d e d , a n d
1 -Ch a n n e l Tru e -Diffe re n t ia l ADCs in S OT2 3
P a c k a g e In fo rm a t io n
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Ma x im In t e g ra t e d P ro d u c t s , 1 2 0 S a n Ga b rie l Drive , S u n n yva le , CA 9 4 0 8 6 4 0 8 -7 3 7 -7 6 0 0 ____________________ 15
© 2001 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products.
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