MAX11203 [MAXIM]
16-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with Programmable Gain and GPIO; 16位，单通道，超低功耗， Σ-Δ ADC，具有可编程增益和GPIO
| 型号： | MAX11203 |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 16-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with Programmable Gain and GPIO |
| 文件： | 总27页 (文件大小：1920K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5334; Rev 0; 6/10
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
General Description
Features
S 16-Bit Noise-Free Resolution
The MAX11203/MAX11213 are ultra-low-power (< 300FA
active current), high-resolution, serial-output ADCs.
These devices provide the highest resolution per unit
power in the industry, and are optimized for applications
that require very high dynamic range with low power,
such as sensors on a 4mA to 20mA industrial control
loop. Optional input buffers provide isolation of the sig-
nal inputs from the switched capacitor sampling network
allowing these converters to be used with high-imped-
ance sources without compromising available dynamic
range or linearity. The devices provide a high-accuracy
internal oscillator that requires no external components.
When used with the specified data rates, the internal
digital filter provides more than 100dB rejection of 50Hz
or 60Hz line noise. The devices are configurable using
the SPI™ interface and include four GPIOs that can be
used for external mux control. The MAX11213 includes
digital programmable gain of 1 to 128.
S 570nV Noise at 10sps, ±±36V Input
S ±ppm INL (typ), 20ppm (max)
S No Missing Codes
RMS
FS
S Ultra-Low Power Dissipation
Operating-Mode Current Drain < ±00µA (max)
Sleep-Mode Current Drain < 034µA
S Programmable Gain (1 to 128) (MAX1121±)
S Four SPI-Controlled GPIOs for External Mux
Control
S 237V to ±36V Analog Supply Voltage Range
S 137V to ±36V Digital and I/O Supply Voltage Range
S Fully Differential Signal and Reference Inputs
S High-Impedance Inputs
Optional Input Buffers on Both Signal and
Reference Inputs
S > 100dB (min) 50Hz/60Hz Rejection
The MAX11203/MAX11213 operate over the -40NC to
+85NC temperature range, and are available in a 16-pin
QSOP package.
S SPI-, QSPI™-, MICROWIRE™-Compatible Serial
Interface
S On-Demand Offset and Gain Self-Calibration and
System Calibration
Applications
Sensor Measurement (Temperature and
Pressure)
S User-Programmable Offset and Gain Registers
S -40°C to +85°C Operating Temperature Range
S ±2ꢀV ESD Protection
Portable Instrumentation
Battery Applications
Weigh Scales
S Lead(Pb)-Free and RoHS-Compliant QSOP
Pacꢀage
Ordering Information
PART
TEMP RANGE
-40°C to +85°C
-40°C to +85°C
PIN-PACKAGE
16 QSOP
MAX1120±EEE+
MAX1121±EEE+
16 QSOP
+Denotes a lead(Pb)-free/RoHS-compliant package.
Selector Guide
RESOLUTION
(BITS)
4-WIRE SPI, 16-PIN QSOP,
PROGRAMMABLE GAIN
4-WIRE SPI,
16-PIN QSOP
2-WIRE SERIAL,
10-PIN µMAX
MAX11201 (with buffers)
MAX11202 (without buffers)
24
MAX11210
MAX11200
20
18
16
MAX11206
MAX11209
MAX11213
MAX11207
MAX11211
MAX11203
MAX11208
MAX11212
MAX11205
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
ABSOLUTE MAXIMUM RATINGS
Any Pin to GND....................................................-0.3V to +3.9V
AVDD to GND.......................................................-0.3V to +3.9V
DVDD to GND ......................................................-0.3V to +3.9V
Analog Inputs (AINP, AINN, REFP, REFN)
Continuous Power Dissipation (T = +70NC)
A
16-Pin QSOP (derate 8.3mW/NC above +70NC)..........667mW
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -55NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
to GND ............................................. -0.3V to (V
Digital Inputs and Digital Outputs
to GND ............................................. -0.3V to (V
+ 0.3V)
AVDD
+ 0.3V)
DVDD
ESD
(AVDD, AINP, AINN, REFP, REFN, DVDD, CLK, CS,
HB
SCLK, DIN, RDY/DOUT, GND, GPIO_) ........... Q2kV (Note 1)
Note 1: Human Body Model to specification MIL-STD-883 Method 3015.7.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= +3.6V, V
= +1.7V, V
- V
= V
; internal clock, single-cycle mode (SCYCLE = 1), T = T
to T
,
MAX
DVDD
REFP
REFN
AVDD
A
MIN
unless otherwise noted. Typical values are at T = +25NC under normal conditions, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
STATIC PERFORMANCE
120sps
10sps
16
16
Noise-Free Resolution (Notes 2, 3)
NFR
Bits
120sps
10sps
2.1
0.57
Noise (Notes 2, 3)
Integral Nonlinearity
Zero Error
V
FV
RMS
N
INL
At 10sps (Note 4)
-20
-20
+20
+20
ppmFSR
ppmFSR
nV/NC
After self and system calibration,
V
- V
= 2.5V
REFP
REFN
Zero Drift
50
After self and system calibration,
- V = 2.5V (Note 5)
Full-Scale Error
-45
+45
ppmFSR
V
REFP
REFN
ppmFSR/
Full-Scale Error Drift
0.05
NC
AVDD DC rejection
DVDD DC rejection
70
90
80
Power-Supply Rejection
dB
100
ANALOG INPUTS/REFERENCE INPUTS
DC rejection
90
90
123
Common-Mode Rejection
CMR
50Hz/60Hz rejection at 120sps
50Hz/60Hz rejection at 1sps to 15sps
LINEF = 1, for 1sps to 15sps (Notes 6, 7)
LINEF = 0, for 1sps to 15sps (Notes 6, 7)
AIN buffers disabled
dB
144
100
100
Normal-Mode 50Hz Rejection
Normal-Mode 60Hz Rejection
Common-Mode Voltage Range
NMR
NMR
144
144
dB
dB
V
50
60
V
V
AVDD
GND
2
______________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +3.6V, V
= +1.7V, V
- V
= V
; internal clock, single-cycle mode (SCYCLE = 1), T = T
to T
,
MAX
DVDD
REFP
REFN
AVDD
A
MIN
unless otherwise noted. Typical values are at T = +25NC under normal conditions, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
-
GND
Buffers disabled
30mV
Low input voltage
High input voltage
V
+
GND
Buffers enabled
Buffers disabled
Buffers enabled
100mV
Absolute Input Voltage
V
V
+
AVDD
30mV
V
AVDD
-
100mV
DC Input Leakage
Sleep mode
Buffer disabled
Buffer enabled
Buffer disabled
Buffer enabled
Buffer disabled
Buffer disabled
Unipolar
Q1
FA
FA/V
nA
Q1.4
Q20
Q2.1
Q30
5
AIN Dynamic Input Current
FA/V
nA
REF Dynamic Input Current
AIN Input Capacitance
REF Input Capacitance
pF
7.5
pF
0
V
REF
AIN Voltage Range
Input Sampling Rate
V
Bipolar
-V
+V
REF
REF
LINEF = 0
246
f
S
kHz
LINEF = 1
204.8
Buffers disabled
0
V
V
- 0.1
AVDD
REF Voltage Range
REF Sampling Rate
V
AVDD
Buffers enabled
0.1
LINEF = 0
LINEF = 1
246
kHz
204.8
LOGIC INPUTS (SCLK, CLK, DIN, GPIO1–GPIO4)
Input Current
Input leakage current
Q1
FA
0.3 x
Input Low Voltage
V
V
IL
V
DVDD
0.7 x
Input High Voltage
Input Hysteresis
V
V
IH
V
DVDD
V
200
mV
HYS
60Hz line frequency
55Hz line frequency
50Hz line frequency
2.4576
2.25275
2.048
External Clock
MHz
LOGIC OUTPUTS (RDY/DOUT, GPIO1–GPIO4)
Output Low Level
V
I
= 1mA; also tested for V = 3.6V
DVDD
0.4
V
V
OL
OL
0.9 x
Output High Level
V
I
= 1mA; also tested for V
= 3.6V
OH
OH
DVDD
V
DVDD
Leakage Current
High-impedance state
High-impedance state
Q500
nA
pF
Output Capacitance
9
_______________________________________________________________________________________
±
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +3.6V, V
= +1.7V, V
- V
= V
; internal clock, single-cycle mode (SCYCLE = 1), T = T
to T
,
MAX
DVDD
REFP
REFN
AVDD
A
MIN
unless otherwise noted. Typical values are at T = +25NC under normal conditions, unless otherwise noted.)
A
PARAMETER
POWER REQUIREMENTS
Analog Supply
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
2.7
1.7
3.6
3.6
300
V
V
AVDD
Digital Supply
DVDD
Buffers disabled
Buffers enabled
235
255
0.15
185
205
0.25
50
Total Operating Current
AVDD Sleep Current
AVDD + DVDD
FA
FA
FA
2
Buffers disabled
Buffers enabled
235
AVDD Operating Current
DVDD Sleep Current
2
FA
FA
DVDD Operating Current
SPI TIMING CHARACTERISTICS
SCLK Frequency
65
f
5
MHz
ns
SCLK
SCLK Clock Period
t
200
80
80
40
40
CP
CH
SCLK Pulse-Width High
SCLK Pulse-Width Low
CS Low to 1st SCLK Rise Setup
CS High to 17th SCLK Setup
t
ns
t
60% duty cycle at 5MHz
ns
CL
t
t
ns
CSS0
CSS1
ns
CS High After 16th SCLK
Falling Edge Hold
t
3
ns
CSH1
CS Pulse-Width High
DIN to SCLK Setup
DIN Hold After SCLK
t
40
40
0
ns
ns
ns
CSW
t
DS
DH
t
RDY/DOUT Transition Valid After
SCLK Fall
Output transition time, data changes on fall-
ing edge of SCLK
t
40
ns
ns
DOT
RDY/DOUT Remains Valid After
SCLK Fall
Output hold time allows for negative edge
data read
t
3
DOH
RDY/DOUT Valid Before SCLK Rise
CS Rise to RDY/DOUT Disable
t
t
= t - t
CL DOT
40
ns
ns
DOL
DOL
t
C
= 20pF
25
40
DOD
LOAD
Default value of RDY is 1 for minimum spec-
ification; maximum specification for valid 0
on RDY/DOUT
CS Fall to RDY/DOUT Valid
t
0
0
ns
DOE
Maximum time after RDY asserts to read
DATA register; t
conversion
t
-
CP
CNV
60 x t
DATA Fetch
t
is the time for one
CNV
DF
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note ±: V = V
AINP
AINN.
Note 4: ppmFSR is parts per million of full scale.
Note 5: Positive full-scale error includes zero-scale errors (unipolar offset error or bipolar zero error) and applies to both unipolar
and bipolar input ranges.
Note 6: For data rates (1, 2.5, 5, 10, 15)sps and (0.83, 2.08, 4.17, 8.33, 12.5)sps.
Note 7: Normal-mode rejection of power line frequencies of 60Hz/50Hz apply only for single-cycle data rates at 15sps/10sps and
lower or continuous data rate of 60sps/50sps.
4
______________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Typical Operating Characteristics
(V
AVDD
= 3.6V, V
= 1.8V, V
- V
= 2.5V; internal clock; T = T
to T , unless otherwise noted. Typical values are
MAX
DVDD
REFP
REFN
A
MIN
at T
A =
+25NC.)
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE
(NO BUFFERS ENABLED)
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE
(SIGNAL OR REFERENCE BUFFERS ENABLED)
260
ANALOG ACTIVE CURRENT vs. AVDD VOLTAGE
(SIGNAL AND REFERENCE BUFFERS ENABLED)
280
260
LINEF = 0, LINEF = 1
240
240
220
200
180
160
140
120
260
T = +85°C
A
T
A
= +85°C
220
200
180
160
140
120
240
220
200
180
160
T
= +85°C
A
T = +25°C
A
T
A
= +25°C
T
A
= +25°C
T = -45°C
A
T
A
= -45°C
T
A
= -45°C
SIGNAL BUFFERS
LINEF = 1
2.70 2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
2.70 2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
2.70 2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
ANALOG SLEEP CURRENT
vs. AVDD VOLTAGE
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE (LINEF = 0)
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE (LINEF = 1)
1.0
300
300
T
A
= -45°C, +25°C, +85°C
250
200
150
100
50
250
200
150
100
50
0.8
0.6
0.4
0.2
0
TOTAL
TOTAL
V
= 3.0V
AVDD
V
= 3.0V
AVDD
T
= -45°C
A
V
= 1.8V
DVDD
V
DVDD
= 1.8V
T
= +85°C
A
0
0
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
AVDD VOLTAGE (V)
-45 -25
-5
15
35
55
75
95
-45 -25
-5
15
35
55
75
95
TEMPERATURE (°C)
TEMPERATURE (°C)
DIGITAL ACTIVE CURRENT
vs. DVDD VOLTAGE
DIGITAL SLEEP CURRENT
vs. DVDD VOLTAGE
SLEEP CURRENT vs. TEMPERATURE
1.0
0.8
0.6
0.4
0.2
0
130
120
110
100
90
3.0
2.5
2.0
1.5
1.0
0.5
0
LINEF = 0, LINEF = 1
T = -45°C, +25°C, +85°C
A
T = +85°C
A
T = -45°C
A
LINEF = 0
T = +25°C
A
80
TOTAL
DVDD
T = +85°C
A
T = -45°C
A
70
60
LINEF = 1
50
AVDD
40
-45 -25
-5
15
35
55
75
95
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
DVDD VOLTAGE (V)
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
DVDD VOLTAGE (V)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Typical Operating Characteristics (continued)
(V
AVDD
= 3.6V, V
= 1.8V, V
- V
= 2.5V; internal clock; T = T
to T , unless otherwise noted. Typical values are
MAX
DVDD
REFP
REFN
A
MIN
at T
+25NC.)
A =
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
INTERNAL OSCILLATOR FREQUENCY
vs. AVDD VOLTAGE
INTEGRAL NONLINEARITY
vs. INPUT VOLTAGE
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
1.5
10
V
= 3.0V
VIN(CM) = 1.8V
8
AVDD
6
T = +85°C
A
4
2
LINEF = 0
LINEF = 1
LINEF = 0
LINEF = 1
T = -45°C
A
0
-2
-4
-6
-8
-10
T = +25°C
A
-45 -25
-5
15
35
55
75
95
2.70 2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
TEMPERATURE (°C)
INPUT VOLTAGE (V)
PSRR vs. FREQUENCY
(DATA RATE 120sps)
TUE vs. INPUT VOLTAGE
10
0
-20
VIN(CM) = 1.8V
8
6
T = -45°C
A
4
-40
T = +85°C
A
2
-60
0
-2
-4
-6
-8
-10
-80
AVDD
DVDD
T = +25°C
A
-100
-120
-140
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
1
10
100
1000 10,000 100,000
INPUT VOLTAGE (V)
FREQUENCY (Hz)
PSRR vs. FREQUENCY
(DATA RATE 10sps)
CMRR vs. FREQUENCY
0
-20
0
-20
-40
-40
-60
-60
-80
-80
AVDD
DVDD
120sps
10sps
-100
-120
-140
-100
-120
-140
1
10
100
1000 10,000 100,000
1
10
100
1000 10,000 100,000
FREQUENCY (Hz)
FREQUENCY (Hz)
6
______________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Functional Diagram
CLOCK GENERATOR
CLK
TIMING
AVDD
DVDD
GND
CS
AINP
AINN
DIGITAL LOGIC
AND SERIAL-
INTERFACE
SCLK
DIN
PROGRAMMABLE
GAIN*
DIGITAL FILTER
4
(SINC )
1–128
CONTROLLER
3RD-ORDER
DELTA-SIGMA
MODULATOR
RDY/DOUT
REFP
GPIO1
GPIO2
GPIO3
GPIO4
REFN
MAX11203
MAX11213*
GPIO
*PROGRAMMABLE GAIN ONLY AVAILABLE ON THE MAX11213.
_______________________________________________________________________________________
7
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Pin Configuration
TOP VIEW
+
GPIO1
1
2
3
4
5
6
7
8
16 GPIO4
15 CLK
GPIO2
GPIO3
GND
MAX11203
MAX11213
14 SCLK
13 RDY/DOUT
12 DIN
REFP
REFN
AINN
AINP
11 CS
10 DVDD
9
AVDD
QSOP
Pin Description
PIN
1
NAME
GPIO1
GPIO2
GPIO3
GND
FUNCTION
General-Purpose I/O 1. Register controllable using SPI.
General-Purpose I/O 2. Register controllable using SPI.
General-Purpose I/O 3. Register controllable using SPI.
Ground. Ground reference for analog and digital circuitry.
2
3
4
Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a voltage
between AVDD and GND.
5
6
REFP
REFN
Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a
voltage between AVDD and GND.
7
8
AINN
AINP
AVDD
DVDD
CS
Negative Fully Differential Analog Input
Positive Fully Differential Analog Input
9
Analog Supply Voltage. Connect a supply voltage between +2.7V and +3.6V with respect to GND.
Digital Supply Voltage. Connect a digital supply voltage between +1.7V and +3.6V with respect to GND.
Active-Low, Chip-Select Logic Input
10
11
Serial-Data Input. Data present at DIN is shifted to the device’s internal registers at the rising edge of
the serial clock at SCLK, when the device is accessed for an internal register write or for a command
operation.
12
DIN
Data Ready Output/Serial-Data Output. This output serves a dual function. In addition to the serial-data
output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic-low. RDY/
DOUT changes on the falling edge of SCLK.
13
14
15
16
RDY/DOUT
SCLK
Serial-Clock Input. Apply an external serial clock to SCLK.
External Clock Signal Input. When external clock mode is selected (EXTCLK = 1), provide a 2.4576MHz
or 2.048MHz clock signal at CLK. Other frequencies can be used, but the data rate and digital filter notch
frequencies scale accordingly.
CLK
GPIO4
General-Purpose I/O 4. Register controllable using SPI.
8
______________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
the inputs from the capacitive load presented by the
modulator, allowing for high source-impedance analog
Detailed Description
The MAX11203/MAX11213 are ultra-low-power (< 300FA
transducers. The value of the SIGBUF bit in the CTRL1
active), high-resolution, low-speed, serial-output ADCs.
register determines whether the input buffer is enabled
These ADCs provide the highest resolution per unit power
or disabled. See Table 12.
in the industry, and are optimized for applications that
require very high dynamic range with low power such
as sensors on a 4mA to 20mA industrial control loop.
Optional input buffers provide isolation of the signal inputs
from the switched capacitor sampling network, allow-
ing the devices to be used with very high impedance
sources without compromising available dynamic range.
The devices provide a high-accuracy internal oscillator,
which requires no external components. When used with
the specified data rates, the internal digital filter provides
more than 144dB rejection of 50Hz or 60Hz line noise. The
devices are highly configurable using the SPI interface
and include four GPIOs for external mux control.
Input Voltage Range
The modulator input range is programmable for bipolar
(-V
to +V
) or unipolar (0 to V ) ranges. The
REF
REF
REF
U/B bit in the CTRL1 register configures the MAX11203/
MAX11213 for unipolar or bipolar transfer functions. See
Table 12.
System Clock
The devices incorporate a highly stable internal oscillator
that provides the system clock. The system clock runs
the internal state machine and is trimmed to 2.4576MHz
or 2.048MHz. The internal oscillator clock is divided
down to run the digital and analog timing. The LINEF bit
in the CTRL1 register determines the internal oscillator
frequency. See Tables 10 and 12. Set LINEF = 0 to select
the 2.4576MHz oscillator and LINEF = 1 to select the
Analog Inputs
The devices accept two analog inputs (AINP, AINN) in
buffered or unbuffered mode. The input buffer isolates
Table 13 Continuous Conversion with SCYCLE Bit = 0
BIPOLAR
ENOB
(BITS)
UNIPOLAR
ENOB
(BITS)
OUTPUT
NOISE
DATA RATE* (sps)
BIPOLAR NFR
(BITS)
UNIPOLAR
NFR (BITS)
RATE[2:0]
(µV
)
RMS
LINEF = 0
60
LINEF = 1
50
100
101
110
111
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
0.74
120
240
480
100
200
400
1.03
1.45
2.21
*LINEF = 0 sets the clock frequency to 2.4576MHz and the input sampling frequency to 245.76kHz. LINEF bit = 1 sets the clock
frequency to 2.048MHz and the input sampling frequency to 204.8kHz.
Table 23 Single-Cycle Conversion with SCYCLE Bit = 1
SINGLE-CYCLE DATA RATE*
(sps)
BIPOLAR
ENOB
(BITS)
OUTPUT
NOISE
BIPOLAR
NFR (BITS)
UNIPOLAR
NFR (BITS)
UNIPOLAR
ENOB (BITS)
RATE[2:0]
(µV
)
RMS
LINEF = 0
LINEF = 1
0.833
2.08
4.17
8.33
12.5
25
000
001
010
011
100
101
110
111
1
2.5
5
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
0.21
0.27
0.39
0.57
0.74
1.03
1.45
2.21
10
15
30
60
120
50
100
*LINEF = 0 sets the clock frequency to 2.4576MHz and the input sampling frequency to 245.76kHz. LINEF bit = 1 sets the clock
frequency to 2.048MHz and the input sampling frequency to 204.8kHz.
_______________________________________________________________________________________
9
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
2.048MHz oscillator. The 2.4576MHz oscillator provides
maximum 60Hz rejection, and the 2.048MHz oscillator
provides maximum 50Hz rejection. See Figures 1 and
2. For optimal simultaneous 50Hz and 60Hz rejection,
apply a 2.25275MHz external clock at CLK.
CTRL3 register. The default values for these calibra-
tion control bits are 1, which disables the use of the
internal calibration registers.
The devices power up with the internal calibration regis-
ters disabled, and therefore a full-scale input produces
a result of 60% of the full-scale digital range. To use the
full-scale digital range a calibration must be performed.
Reference
The devices provide differential inputs REFP and REFN
for an external reference voltage. Connect the external
reference directly across the REFP and REFN to obtain
the differential reference voltage. The common-mode
The first level of calibration is the self-calibration where
the part performs the required connections to zero and
full-scale internally. This level of calibration is typically
sufficient for 1FV of offset accuracy and 2ppm of full-
scale accuracy. The self-calibration routine does not
include the source resistance effects from the signal
source driving the input pins, which can change the off-
set and gain of the system.
voltage range for V
and V
is between 0 and
REFP
REFN
V
.
AVDD
The devices accept reference inputs in buffered or
unbuffered mode. The value of the REFBUF bit in the
CTRL1 register determines whether the reference buffer
is enabled or disabled. See Table 12.
A second level of calibration is available where the user
can calibrate a system zero scale and system full scale
by presenting a zero-scale signal or a full-scale signal
to the input pins and initiating a system zero scale or
system gain calibration command.
Buffers
The devices include reference and signal input buffers
capable of reducing the average input current from
2.1FA/V on the reference inputs and from 1.4FA/V on
the analog inputs to a constant 30nA current on the
reference inputs and 20nA current on the analog inputs.
The reference and signal input buffers can be selected
individually by programming the CTRL1 register bits
REFBUF and SIGBUF. When enabled, the reference and
input signal buffers require an additional 20FA from the
AVDD supply pin.
A third level of calibration allows for the user to write to
the internal calibration registers through the SPI interface
to achieve any digital offset or scaling the user requires
with the following restrictions. The range of digital offset
correction is QV
/4. The range of digital gain correc-
REF
tion is from 0.5 to 1.5. The resolution of offset correction
is 0.5 LSB.
The calibration operations are controlled with the CAL1
and CAL0 bits in the command byte. The user requests
a self-calibration by setting the CAL1 bit to 0 and CAL0
bit to 1. A self-calibration requires 200ms to complete,
and both the SCOC and SCGC registers contain the
values that correct the chip output for zero scale and full
scale. The user requests a system zero-scale calibration
by setting the CAL1 bit to 1 and the CAL0 bit to 0 and
presents a system zero-level signal to the input pins. The
SOC register contains the values that correct the chip
zero scale. The system zero calibration requires 100ms
to complete, and the SOC register contains values that
correct the chip zero scale. The user requests a system
full-scale calibration by setting the CAL1 bit to 1 and the
CAL0 bit to 1 and presents a system full-scale signal
level to the input pins. The system full-scale calibration
requires 100ms to complete, and the SGC register con-
tains values that correct for the chip full-scale value. See
Tables 3a and 3b for an example of a self-calibration
sequence and a system calibration sequence.
Power-On Reset (POR)
The devices utilize power-on reset (POR) supply-mon-
itoring circuitry on both the digital supply (DVDD) and
the analog supply (AVDD). The POR circuitry ensures
proper device default conditions after either a digital or
analog power sequencing event. The digital POR trig-
ger threshold is approximately 1.2V and has 100mV of
hysteresis. The analog POR trigger threshold is approxi-
mately 1.25V and has 100mV of hysteresis. Both POR
circuits have lowpass filters that prevent high-frequency
supply glitches from triggering the POR.
Calibration
The devices provide two sets of calibration registers
which offer the user several options for calibrating
their system. The calibration register value defaults
are all zero, which require a user to either perform
a calibration or program the register through the SPI
interface to use them. The on-chip calibration reg-
isters are enabled or disabled by programming the
NOSYSG, NOSYSO, NOSCG, and NOSCO bits in the
10 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Table ±a3 Example of Self-Calibration
REGISTER
BIT
STEP
DESCRIPTION
SCOC
SCGC
SOC
SGC
1
2
3
Initial power-up
0x000000 0x000000 0x000000 0x000000
0x000000 0x000000 0x000000 0x000000
0x00007E 0xBFD345 0x000000 0x000000
1
1
1
1
1
1
1
0
0
1
0
0
Enable self-calibration registers
Self-calibration, DIN = 10010000
Table ±b3 Example of System Calibration
REGISTER
BIT
STEP
DESCRIPTION
SCOC
SCGC
SOC
SGC
1
2
3
4
5
6
7
Initial power-up
0x000000 0x000000 0x000000 0x000000
0x000000 0x000000 0x000000 0x000000
0x00007E 0xBFD345 0x000000 0x000000
0x00007E 0xBFD345 0x000000 0x000000
1
1
1
1
1
0
0
1
1
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
Enable self-calibration registers
Self-calibration, DIN = 10010000
Enable system offset register
System-calibration offset, DIN = 1010000 0x00007E 0xBFD345 0xFFEE1D 0x000000
Enable system gain register
0x00007E 0xBFD345 0xFFEE1D 0x000000
0x00007E 0xBFD345 0xFFEE1D 0x81CB5B
System-calibration gain, DIN = 1011000
line frequency of 60Hz and is guaranteed to attenuate
60Hz normal-mode components by more than 100dB.
Simultaneous 50Hz and 60Hz attenuation can be accom-
plished by using an external clock with a frequency of
2.25275MHz. This guarantees a minimum of 80dB rejec-
tion at 50Hz and 85dB rejection at 60Hz. The SINC4 filter
has a -3dB frequency equal to 24% of the data rate. See
Figures 1 and 2.
Noise vs. Data Rate
The devices offer software-selectable internal oscillator
frequencies as well as software-selectable output data
rates. The LINEF bit in the CTRL1 register (Table 12)
determines the internal oscillator frequency. The RATE
bits in the command byte (Table 8) determine the ADC’s
output data rate. The devices also offer the option of
running in zero latency single-cycle conversion mode
(Table 2) or continuous conversion mode (Table 1). Set
SCYCLE = 0 in the CTRL1 register (Table 12) to run in
continuous conversion mode and SCYCLE = 1 for single-
cycle conversion mode.
GPIOs
The devices provide four GPIO ports. When set as out-
puts, these digital I/Os can be used to drive the digital
inputs to a multiplexer or multichannel switch. Figure 3
details an example where four single-ended signals are
multiplexed in a break-before-make switching sequence,
using the MAX313, a quad SPST analog switch.
Single-cycle conversion mode gives an output result with
no data latency. The devices output data up to 100sps
(2.048MHz internal oscillator) or 120sps (2.4576MHz
internal oscillator) with no data latency. In continuous
conversion mode, the output data rate is four times the
single-cycle conversion mode, for sample rates up to
400sps or 480sps. In continuous conversion mode, the
output data requires three additional 24-bit cycles to
settle from an input step.
The devices’ GPIO ports are configurable through the
CTRL2 register. See Table 13. To select AIN1, write the
command to CTRL2 according to Table 4a. This selects
all GPIOs as outputs, as well as setting all logic signals
to 0 except the selected channel AIN1.
To select channel AIN3 next, it is a good idea to set all
switches to a high-impedance state first (see Table 4b).
Digital Filter
The devices include a SINC4 digital filter that produces
spectral nulls at the multiples of the data rate. For all
data rates less than 30sps, a spectral null occurs at the
Then select channel AIN3 by driving IN3 high (see
Table 4c).
______________________________________________________________________________________ 11
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
NORMAL MODE REJECTION
DATA RATE 10.0sps
NORMAL MODE REJECTION
DATA RATE 120.0sps
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-100
-110
-120
-130
-140
-150
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (Hz)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (Hz)
Figure 1. Normal-Mode Frequency Response (2.4576MHz Oscillator, LINEF = 0)
NORMAL MODE REJECTION
DATA RATE 8.333sps
NORMAL MODE REJECTION
DATA RATE 100.000sps
0
-10
0
-10
-20
-20
-30
-30
-40
-40
-50
-50
-60
-60
-70
-70
-80
-80
-90
-90
-100
-110
-120
-130
-140
-150
-100
-110
-120
-130
-140
-150
0
10 20 30 40 50 60 70 80 90 100
FREQUENCY (Hz)
0
200 400 600 800 1000 1200 1400 1600 1800 2000
FREQUENCY (Hz)
Figure 2. Normal-Mode Frequency Response (2.048MHz Oscillator, LINEF = 1)
Table 4a3 Data Command to Select Channel AIN1 in Figure ±
BIT
B7
DIR4
1
B6
DIR3
1
B5
DIR2
1
B4
DIR1
1
B±
DIO4
0
B2
DIO3
0
B1
DIO2
0
B0
DIO1
1
BIT NAME
VALUE
Table 4b3 Set All Channels High Impedance in Figure ±
BIT
B7
DIR4
1
B6
DIR3
1
B5
DIR2
1
B4
DIR1
1
B±
DIO4
0
B2
DIO3
0
B1
DIO2
0
B0
DIO1
0
BIT NAME
VALUE
12 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
It is not always necessary to transition to a high-imped-
ance state between channel selections, but depends on
MAX313
the source analog signals as well as the control structure
of the multiplexed switches.
LOGIC SWITCH
0
1
OFF
ON
Digital Programmable Gain (MAX11213)
The MAX11213 offers programmable gain settings that
can be digitally set to 1, 2, 4, 8, 16, 32, 64, or 128. The
DGAIN_ bits in the CTRL3 register (see Table 14) config-
ure the digital gain setting and control the input referred
IN1
GPIO1
GPIO2
GPIO3
GPIO4
IN2
IN3
IN4
AIN1
AIN2
AIN3
AIN4
gain. The MAX11213’s input range is 0V to V
/
REF
gain (unipolar) or
V
/gain (bipolar). The MAX11213
REF
always outputs 16 bits of data. But as this is a digital
programmable gain, the noise floor remains constant,
depending on the output rate setting. At an output rate of
10sps, as shown in Figure 4, the noise floor is such that
all gain settings from 1 to 64 provide 16 bits of noise-free
resolution. A gain setting of 128 at 10sps means the LSB
is below the noise floor. The MAX11213 digital gain is
beneficial for low-voltage applications that only require a
MAX313
MAX11203
COM1
COM2
COM3
COM4
AINP
AINN
small portion of the 0V to V
or
V
REF
ranges.
REF
Figure 3. MAX11203 GPIOs Drive an External 4-Channel
Switch (MAX313)
Table 4c3 Data Command to Select Channel AIN± in Figure ±
BIT
B7
DIR4
1
B6
DIR3
1
B5
DIR2
1
B4
DIR1
1
B±
DIO4
0
B2
B1
DIO2
0
B0
BIT NAME
VALUE
DIO3
1
DIO1
0
NOISE FLOOR
REMAINS CONSTANT
AT 0.57µV
RMS
V
= 3V
LSB
REF
16-BIT OUTPUT DATA CYCLE
MSB
SUB-LSBs
BITS USED FOR GAIN = 1
BITS USED FOR GAIN = 2
BITS USED FOR GAIN = 16
BITS USED FOR GAIN = 128
Figure 4. MAX11213 Digital Programmable Gain Example (10sps Output Rate)
______________________________________________________________________________________ 1±
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
is in progress if the RDY/DOUT output reads logic-high
and the conversion is complete if the RDY/DOUT output
reads logic-low. Data at RDY/DOUT changes on the
falling edge of SCLK and is valid on the rising edge of
SCLK. DIN and DOUT are transferred MSB first. Drive
CS high to force DOUT high impedance and cause
the devices to ignore any signals on SCLK and DIN.
Connect CS low for 3-wire operation. Figures 5, 6, and 7
show the SPI timing diagrams.
Serial-Digital Interface
The MAX11203/MAX11213 interface is fully compatible
with SPI-, QSPI-, and MICROWIRE-standard serial inter-
faces. The SPI interface provides access to nine on-chip
registers that are 8 or 24 bits wide.
Drive CS low to transfer data in and out of the devices.
Clock in data at DIN on the rising edge of SCLK. The
RDY/DOUT output serves two functions: conversion sta-
tus and data read. To find the conversion status, assert
CS low and read the RDY/DOUT output; the conversion
t
DS
t
CSH1
t
t
CSW
CP
t
CSH0
t
CSS0
t
CL
t
CH
t
DH
CS
SCLK
DIN
t
CSS1
0
1
8
X
1
0
CAL1
CAL0
IMPD
RATE2
RATE1
RATE0
t
t
DOD
DOE
HIGH-Z
HIGH-Z
RDY/DOUT
Figure 5. SPI Command Byte
SPI REGISTER ACCESS WRITE
t
t
CSW
DS
t
t
CSH0
CP
t
t
CSH1
CSS0
t
CL
t
DH
t
CH
CS
t
CSS1
SCLK
DIN
0
1
8
9
16
X
1
1
X
RS3
RS2
RS1
RS0
W/R
D7
D6
D5
D4
D3
D2
D1
D0
t
t
DOD
HIGH-Z
DOE
HIGH-Z
RDY/DOUT
Figure 6. SPI Register Access Write
14 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
t
DS
t
t
t
DOD
CP
DOT
t
CSS0
t
DOH
t
CL
t
DO1
t
DH
t
CH
CS
t
CSS1
SCLK
1
8
9
16
DIN
X
1
1
X
RS3
RS2
RS1
RS0
W/R
X
X
X
X
X
X
X
X
t
DOE
HIGH-Z
HIGH-Z
D7
D6
D5
D4
D3
D2
D1
D0
RDY/DOUT
Figure 7. SPI Register Access Read
Command Byte
or two’s complement), and single-cycle or continuous
conversion mode. See Table 12.
Communication between the user and the device is con-
ducted through SPI using a command byte. The com-
mand byte consists of two modes differentiated as com-
mand modes and data modes. Command modes and
data modes are further differentiated by decoding the
remaining bits in the command byte. The mode selected
is determined by the MODE bit. If the MODE bit is 0, then
the user is requesting either a conversion, calibration, or
power-down; see Table 5. If the MODE bit is 1, then the
user is selecting a data command and can either read
from or write to a register; see Table 6.
The Control 2 register (CTRL2) is a read/write register,
and the bits configure the GPIOs as inputs or outputs
and their values. See Table 13.
The Control 3 register (CTRL3) is a read/write register,
and the bits determine the MAX11213 programmable
gain setting and the calibration register settings for both
the MAX11213 and MAX11203. See Table 14.
The Data register (DATA) is a read-only register. Data is
output from RDY/DOUT on the next 24 SCLK cycles once
CS is forced low. The data bits transition on the falling
edge of SCLK. Data is output MSB first, and is offset
binary or two’s complement, depending on the setting
of the FORMAT bit in the CTRL1 register. See Table 15.
The Status register (STAT1) is a read-only register and
provides general chip operational status to the user. If
the user attempts to calibrate the system and overranges
the internal signal scaling, then a gain overrange condi-
tion is flagged with the SYSOR bit. The last data rate
programmed for the ADC is available in the RATE bits.
If the input signal has exceeded positive or negative full
scale, this condition is flagged with the OR and UR bits.
If the modulator is busy converting, then the MSTAT bit
is set. If a conversion result is ready for readout, the RDY
bit is set; see Table 11.
The System Offset Calibration register (SOC) is a read/
write register, and the bits contain the digital value that
corrects the data for system zero scale. See Table 17.
The System Gain Calibration register (SGC) is a read/
write register, and the bits contain the digital value that
corrects the data for system full scale. See Table 18.
The Self-Cal Offset Calibration register (SCOC) is a read/
write register, and the bits contain the value that corrects
the data for chip zero scale. See Table 19.
The Control 1 register (CTRL1) is a read/write register,
and the bits determine the internal oscillator frequency,
unipolar or bipolar input range, selection of an internal or
external clock, enabling or disabling the reference and
input signal buffers, the output data format (offset binary
The Self-Cal Gain Calibration register (SCGC) is a read/
write register, and the bits contain the value that corrects
the data for chip full scale. See Table 20.
Table 53 Command Byte (MODE = 0)
BIT
B7
B6
B5
B4
B±
B2
B1
B0
BIT NAME
START = 1
MODE = 0
CAL1
CAL0
IMPD
RATE2
RATE1
RATE0
Table 63 Command Byte (MODE = 1)
BIT
B7
B6
B5
B4
B±
B2
B1
B0
BIT NAME
START = 1
MODE = 1
0
RS3
RS2
RS1
RS0
W/R
Note: The START bit is used to synchronize the data from the host device. The START bit is always 1.
______________________________________________________________________________________ 15
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Table 73 Operating Mode (MODE Bit)
MODE BIT SETTING
OPERATING MODE
0
The command byte initiates a conversion or an immediate power-down. See Tables 5 and 8.
The device interprets the command byte as a register access byte, which is decoded as per
Tables 6 and 9.
1
Table 83 Command Byte (MODE = 0, LINEF = 0)
COMMAND
Self-calibration cycle
System offset calibration cycle
System gain calibration
Immediate power-down
Convert 1sps
START
MODE
CAL1
CAL0
IMPD
RATE2
RATE1
RATE0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
0
0
1
0
1
0
1
0
1
Convert 2.5sps
Convert 5sps
Convert 10sps
Convert 15sps
Convert 30sps
Convert 60sps
Convert 120sps
Table 93 Register Selection (MODE = 1)
RS±
0
RS2
0
RS1
0
RS0
0
REGISTER ACCESS
POWER-ON RESET STATUS
REGISTER SIZE (BITS)
STAT1
CTRL1
CTRL2
CTRL3
DATA
SOC
0x00
0x02
8
8
0
0
0
1
0
0
1
0
0x0F
8
0
0
1
1
0x1E
8
0
1
0
0
0x000000
0x000000
0x000000
0x000000
0x000000
24
24
24
24
24
0
1
0
1
0
1
1
0
SGC
0
1
1
1
SCOC
SCGC
1
0
0
0
16 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Table 103 Register Address Map
REGISTER
NAME
ADDRESS
SEL (RS[±:0])
B7
B6
B5
B4
B±
B2
B1
R/W
B0
STAT1
CTRL1
CTRL2
CTRL3
R
0x0
0x1
0x2
0x3
SYSOR
LINEF
DIR4
RATE2
RATE1
EXTCLK
DIR2
RATE0
REFBUF
DIR1
OR
UR
MSTAT
RDY
SIGBUF
DIO4
FORMAT SCYCLE
R/W
R/W
R/W
U/B
RESERVED
DIO1
DIR3
DIO3
DIO2
DGAIN2* DGAIN1* DGAIN0* NOSYSG NOSYSO
NOSCG
NOSCO
RESERVED
D[15:8]
D[7:0]
DATA
R
0x4
B[23:16]
B[15:8]
B[7:0]
SOC
0x5
R/W
B[23:16]
B[15:8]
B[7:0]
SGC
SCOC
SCGC
0x6
0x7
0x8
R/W
R/W
R/W
B[23:16]
B[15:8]
B[7:0]
B[23:16]
B[15:8]
B[7:0]
*These DGAIN_ bits set the digital gain for the MAX11213. These bits are don’t-care bits for the MAX11203.
______________________________________________________________________________________ 17
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
STAT1: Status Register
Table 113 STAT1 Register (Read Only)
BIT
B7
SYSOR
0
B6
RATE2
0
B5
RATE1
0
B4
RATE0
0
B±
OR
0
B2
UR
0
B1
MSTAT
0
B0
RDY
0
BIT NAME
DEFAULT
SYSOR: The system gain overrange bit, when set to 1, indicates that a system gain calibration was over range. The
SCGC calibration coefficient is maximum value of 1.9999999. This bit, when set to 1, indicates that the full-scale value
out of the converter is likely not available.
RATE[2:0]: The data rate bits indicate the conversion rate that corresponds to the result in the DATA register or the
rate that was used for calibration coefficient calculation. If the previous conversions were done at a different rate, the
RATE[2:0] bits indicate a rate different than the rate of the conversion in progress.
OR: The overrange bit, OR, is set to 1 to indicate the conversion result has exceeded the maximum value of the
converter and that the result has been clipped or limited to the maximum value. The OR bit is set to 0 to indicate the
conversion result is within the full-scale range of the device.
UR: The underrange bit, UR, is set to 1 to indicate the conversion result has exceeded the minimum value of the
converter and that the result has been clipped or limited to the minimum value. The UR bit is set to 0 to indicate the
conversion result is within the full-scale range of the device.
MSTAT: The measurement status bit, MSTAT is set to 1 when a signal measurement is in progress. When MSTAT = 1,
a conversion, self-calibration, or system calibration is in progress and indicates that the modulator is busy. When the
modulator is not converting, the MSTAT bit is set to 0.
RDY: The RDY ready bit is set to 1 to indicate that a conversion result is available. Reading the DATA register resets the
RDY bit to 0 only after another conversion has been initiated. If the DATA has not been read before another conversion
is initiated, the RDY bit remains 1; if the DATA is read before another conversion is initiated, the RDY bit resets to 0. If
the DATA for the previous conversion is read during a following conversion, the RDY bit is reset immediately after the
DATA read operation has completed.
18 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
CTRL1: Control 1 Register
The byte-wide CTRL1 register is a bidirectional read/write register. The byte written to the CTRL1 register indicates if
the part converts continuously or single cycle, if an external or internal clock is used, if the reference and signal buffers
are activated, the format of the data when in bipolar mode, and if the analog signal input range is unipolar or bipolar.
Table 123 CTRL1 Register (Read/Write)
BIT
B7
LINEF
0
B6
B5
EXTCLK
0
B4
REFBUF
0
B±
SIGBUF
0
B2
FORMAT
0
B1
SCYCLE
1
B0
UNUSED
0
BIT NAME
DEFAULT
U/B
0
LINEF: Use the line frequency bit, LINEF, to select if the data rate is centered for 50Hz power mains or 60Hz power
mains. To select data rates for 50Hz power mains, write 1 to LINEF and to select data rates for 60Hz power mains,
write 0 to LINEF.
U/B: The unipolar/bipolar bit, U/B, selects if the input range is unipolar or bipolar. A 1 in this bit location selects a uni-
polar input range and a 0 selects a bipolar input range.
EXTCLK: The external clock bit, EXTCLK, controls the selection of the system clock. A 1 enables an external clock as
system clock, whereas as a 0 enables the internal clock.
REFBUF: The reference buffer bit, REFBUF, enables/disables the reference buffers. A 1 enables the reference buffers.
A 0 powers down the reference buffers and the reference inputs bypass the reference buffers when driving the ADC.
SIGBUF: The signal buffer, SIGBUF, enables/disables the signal buffers. A 1 enables the signal buffer. A 0 powers
down the signal buffers and the analog signal inputs bypass the signal buffers when driving the ADC.
FORMAT: The format bit, FORMAT, controls the digital format of the data. Unipolar data is always in offset binary for-
mat. The bipolar format is two’s complement if the FORMAT bit is set to 0 or offset binary if the FORMAT bit is set to 1.
SCYCLE: The single-cycle bit, SCYCLE, determines if the device runs in “no-latency” single-conversion mode
(SCYCLE = 1) or if the device runs in “latent” continuous-conversion mode (SCYCLE = 0). When in single-cycle conver-
sion mode, the device completes one no-latency conversion and then powers down into a leakage-only state. When
in continuous-conversion mode, the part is continuously converting and the first three data from the part are incorrect
due to the SINC4 filter latency.
Important Note: When operating in continuous-conversion mode (SCYCLE = 0), it is recommended to keep CS low to
properly detect the end of conversion. The end of conversion is signaled by RDY/DOUT changing from 0 to 1. The tran-
sition of RDY/DOUT from 0 to 1 must be used to synchronize the DATA register read back. If the RDY/DOUT output is
not used to synchronize the DATA read back, a timing hazard exists where the DATA register is updated internally after
a conversion has completed simultaneously with the DATA register being read out, causing an incorrect read of DATA.
______________________________________________________________________________________ 19
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
CTRL2: Control 2 Register
The byte-wide CTRL2 register is a bidirectional read/write register. The byte written to the CTRL2 register controls the
direction and values of the digital I/O ports.
Table 1±3 CTRL2 Register (Read/Write)
BIT
B7
DIR4
0
B6
DIR3
0
B5
DIR2
0
B4
DIR1
0
B±
DIO4
1
B2
DIO3
1
B1
DIO2
1
B0
DIO1
1
BIT NAME
DEFAULT
DIR[4:1]: The direction bits configure the direction of the DIO bit. When a DIR bit is set to 0, the associated DIO bit
is configured as an input and the value returned by a read of the DIO bit is the value being driven on the associated
GPIO. When a DIR bit is set to 1, the associated DIO bit is configured as an output and the GPIO port is driven to a
logic value of the associated DIO bit.
DIO[4:1]: The data input/output bits are bits associated with the GPIO ports. When a DIO is configured as an input,
the value read from the DIO bit is the logic value being driven at the GPIO port. When the direction is configured as an
output, the GPIO port is driven to a logic value associated with the DIO bit.
CTRL3: Control 3 Register
The byte-wide CTRL3 register is a bidirectional read/write register. The CTRL3 register controls the operation and
calibration of the device.
Table 143 CTRL± Register (Read/Write)
BIT
B7
DGAIN2*
0
B6
DGAIN1*
0
B5
DGAIN0*
0
B4
NOSYSG
1
B±
NOSYSO
1
B2
NOSCG
1
B1
NOSCO
1
B0
RESERVED
0
BIT NAME
DEFAULT
*These DGAIN_ bits are don’t-care bits for the MAX11203.
DGAIN[2:0] (MAX1121± only): The digital gain bits control the input referred gain. With a gain of 1, the input range is
0 to V (unipolar) or (bipolar). As the gain in increased by 2x, the input range is reduced to 0 to V /gain
V
REF
REF
REF
or
V
/gain. Digital gain is applied to the final offset and gain-calibrated digital data. The DGAIN[2:0] bits decode
REF
to digital gains as follows:
000 = 1
001 = 2
010 = 4
011 = 8
100 = 16
101 = 32
110 = 64
111 = 128
NOSYSG: The no-system gain bit, NOSYSG, controls the system gain calibration coefficient. A 1 in this bit location
disables the use of the system gain value when computing the final offset and gain corrected data value. A 0 in this
location enables the use of the system gain value when computing the final offset and gain corrected data value.
NOSYSO: The no system offset bit, NOSYSO, controls the system offset calibration coefficient. A 1 in this location
disables the use of the system offset value when computing the final offset and gain corrected data value. A 0 in this
location enables the use of the system offset value when computing the final offset and gain corrected data value.
NOSCG: The no self-calibration gain bit, NOSCG, controls the self-calibration gain calibration coefficient. A 1 in this
location disables the use of the self-calibration gain value when computing the final offset and gain corrected data
value. A 0 in this location enables the use of the self-calibration gain value when computing the final offset and gain
corrected data value.
NOSCO: The no self-calibration offset bit, NOSCO, controls the use of the self-calibration offset calibration coefficient.
A 1 in this location disables the use of the self-calibration offset value when computing the final offset and gain cor-
rected data value. A 0 in this location enables the use of the self-calibration offset value when computing the final offset
and gain corrected data value.
20 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
DATA: Data Register
The data register is a 24-bit read-only register. Any attempt to write data to the data register has no effect. The data
read from this register is clocked out MSB first. The data register holds the conversion result. D15 is the MSB, and D0
is the LSB. The result is stored in a format according to the FORMAT bit in the CTRL1 register.
The data format while in unipolar mode is always straight binary. In straight binary format, the most negative value is
0x0000 (V
0xFFFF (V
- V
- V
= 0V), the midscale value is 0x8000 (V
- V
= V
/2), and the most positive value is
REF
AINP
AINP
AINN
AINN
AINP
AINN
= V ).
REF
In bipolar mode, if the FORMAT bit = 1, then the data format is offset binary. If the FORMAT bit = 0, then the data format
is two’s complement. In two’s complement the negative full-scale value is 0x8000 (V - V = -V ), the midscale
AINP
AINN
REF
is 0x0000 (V
- V
= 0V), and the positive full scale is 0x7FFF (V
- V
= V ). Any input exceeding the
REF
AINP
AINN
AINP
AINN
available input range is limited to the minimum or maximum data value.
Table 153 DATA Register (Read Only)
BIT
D15
D14
D1±
D12
D11
D10
D9
D8
DEFAULT
0
0
0
0
0
0
0
0
BIT
D7
D6
D5
D4
D±
D2
D1
D0
DEFAULT
0
0
0
0
0
0
0
0
BIT
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DEFAULT
Table 16a3 Output Data Format for the Unipolar Input Range
DIGITAL OUTPUT CODE FOR UNIPOLAR RANGE
STRAIGHT BINARY FORMAT
0xFFFF
INPUT VOLTAGE
V
- V
AINP
AINN
≥ V
REF
1
24
V
× 1−
0xFFFE
REF
2
−1
V
REF
24
0x0001
0x0000
2
−1
0
______________________________________________________________________________________ 21
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Table 16b3 Output Data Formats for the Bipolar Input Range
DIGITAL OUTPUT CODE FOR BIPOLAR RANGES
OFFSET BINARY FORMAT TWO’S COMPLEMENT FORMAT
0xFFFF 0x7FFF
INPUT VOLTAGE
V
- V
AINP
AINN
≥ V
REF
1
23
V
× 1−
0xFFFE
0x7FFE
REF
2
−1
V
REF
23
0x8001
0x8000
0x7FFF
0x0001
0x0000
0xFFFF
2
−1
0
−V
REF
23
2
−1
1
23
−V
× 1−
0x0001
0x0000
0x8001
0x8000
REF
2
−1
≤ -V
REF
SOC: System Offset Calibration Register
The system offset calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked
in/out MSB (most significant bit) first. This register holds the system offset calibration value. The format is always in
two’s complement binary format. A write to the system-calibration register is allowed. The value written remains valid
until it is either rewritten or until an on-demand system-calibration operation is performed, which overwrites the user-
supplied value.
The system offset calibration value is subtracted from each conversion result provided the NOSYSO bit in the CTRL3
register is set to 0. The system offset calibration value is subtracted from the conversion result after self-calibration
but before system gain correction. The system offset calibration value is also applied prior to the 1x or 2x scale factor
associated with bipolar and unipolar modes.
Table 173 SOC Register (Read/Write)
BIT
B2±
B22
B21
B20
B19
B18
B17
B16
DEFAULT
0
0
0
0
0
0
0
0
BIT
B15
B14
B1±
B12
B11
B10
B9
B8
DEFAULT
0
0
0
0
0
0
0
0
BIT
B7
B6
B5
B4
B±
B2
B1
B0
DEFAULT
0
0
0
0
0
0
0
0
22 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
SGC: System Gain Calibration Register
The system gain calibration register is a 24-bit read/write register. The data written/read to/from this register is clocked
in/out MSB first. This register holds the system gain calibration value. The format is always in two’s complement binary
format. A write to the system-calibration register is allowed. The written value remains valid until it is either rewritten or
until an on-demand system-calibration operation is performed, which overwrites the user-supplied value.
The system gain calibration value is used to scale the offset corrected conversion result, provided the NOSYSG bit
in the CTRL3 register is set to 0. The system gain calibration value scales the offset-corrected result by up to 2x or
corrects a gain error of approximately -50%. The amount of positive gain error that can be corrected is determined by
modulator overload characteristics, which can be as much as +25%. The gain is corrected to within 2 LSB.
Table 183 SGC Register (Read/Write)
BIT
B2±
B22
B21
B20
B19
B18
B17
B16
DEFAULT
0
0
0
0
0
0
0
0
BIT
B15
B14
B1±
B12
B11
B10
B9
B8
DEFAULT
0
0
0
0
0
0
0
0
BIT
B7
B6
B5
B4
B±
B2
B1
B0
DEFAULT
0
0
0
0
0
0
0
0
SCOC: Self-Calibration Offset Register
The self-calibration offset register is a 24-bit read/write register. The data written/read to/from this register is clocked
in/out MSB first. This register holds the self-calibration offset value. The format is always in two’s complement binary
format. A write to the self-calibration offset register is allowed. The written value remains valid until it is either rewritten
or until an on-demand self-calibration operation is performed, which overwrites the user-supplied value.
The self-calibration offset value is subtracted from each conversion result provided the NOSCO bit in the CTRL3 reg-
ister is set to 0. The self-calibration offset value is subtracted from the conversion result before the self-calibration gain
correction and before the system offset and gain correction. The self-calibration offset value is also applied prior to the
2x scale factor associated with unipolar mode.
Table 193 SCOC Register (Read/Write)
BIT
B2±
B22
B21
B20
B19
B18
B17
B16
DEFAULT
0
0
0
0
0
0
0
0
BIT
B15
B14
B1±
B12
B11
B10
B9
B8
DEFAULT
0
0
0
0
0
0
0
0
BIT
B7
B6
B5
B4
B±
B2
B1
B0
DEFAULT
0
0
0
0
0
0
0
0
______________________________________________________________________________________ 2±
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
SCGC: Self-Calibration Gain Register
The self-calibration gain register is a 24-bit read/write register. The data written/read to/from this register is clocked
in/out MSB first. This register holds the self-calibration gain calibration value. The format is always in two’s complement
binary format. A write to the self-calibration register is allowed. The written value remains valid until it is either rewritten
or until an on-demand self-calibration operation is performed, which overwrites the user-supplied value. Any attempt
to write to this register during an active calibration operation is ignored.
The self-calibration gain value is used to scale the self-calibration offset corrected conversion result before the system
offset and gain calibration values have been applied, provided the NOSCG bit in the CTRL3 register is set to 0. The
self-calibration gain value scales the self-calibration offset corrected conversion result by up to 2x or can correct a gain
error of approximately -50%. The gain is corrected to within 2 LSB.
Table 203 SCGC Register (Read/Write)
BIT
B2±
B22
B21
B20
B19
B18
B17
B16
DEFAULT
0
0
0
0
0
0
0
0
BIT
B15
B14
B1±
B12
B11
B10
B9
B8
DEFAULT
0
0
0
0
0
0
0
0
BIT
B7
B6
B5
B4
B±
B2
B1
B0
DEFAULT
0
0
0
0
0
0
0
0
Table 213 Data Rates for All Combinations of RATE[2:0] (LINEF = 0)
RATE[2:0]
000
SINGLE-CYCLE DATA RATE (sps)
CONTINUOUS DATA RATE (sps)
1
2.5
5
—
—
001
010
—
011
10
15
30
60
120
—
100
60
101
120
240
480
110
111
Table 223 Data Rates for All Combinations of RATE[2:0] (LINEF = 1)
RATE[2:0]
000
SINGLE-CYCLE DATA RATE (sps)
CONTINUOUS DATA RATE (sps)
0.833
2.08
4.17
8.33
12.5
25
—
—
001
010
—
011
—
100
50
101
100
200
400
110
50
111
100
24 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Applications Information
See Figure 8 for the RTD temperature measurement circuit
and Figure 9 for a resistive bridge measurement circuit.
I
= K x I
REF2
REF1
I
REF2
Adding more active circuitry to the analog input signal
path is not always the best solution to a small-signal
problem. Sometimes, increasing the dynamic range of
an active device can lead to a simpler solution that also
helps power consumption and linearity.
REFP
R
REF
MAX11203
MAX11213
I
REF1
REFN
AINP
Often, circuit designers immediately look for an exter-
nal op amp or programmable gain amplifier (PGA)
when confronted with coupling low-amplitude signals
to sampled digital systems. In many cases, choosing
an ADC with more dynamic range and better low-noise
performance yields a solution that works better, simpler,
and with less power.
R
RTD
AINN
GND
One such example is measurements from a strain gauge
in a Wheatstone bridge configuration. Assuming a dif-
ferential output signal from the bridge in Figure 10, the
bridge’s output voltage varies from 5mV to 105mV,
while the noise of the bridge itself limits the sensitivity
to approximately 1FV. This gives approximately 100,000
discrete levels that are available for quantization, a feat
accomplished quite well with any ADC having 17 bits or
more of usable resolution. However, as it is not likely that
a 17-bit ADC will have an input range of 105mV, a gain
stage is needed to boost the signal to span the input
range of the ADC (typically between 3V and 5V).
Figure 8. RTD Temperature Measurement Circuit
AVDD
REFP
REFN
MAX11203
MAX11213
AINP
AINN
This solution requires finding an amplifier and associated
passives that meet the overall system noise and linearity
needs. Also, the power consumed in the gain stage may
equal or surpass that of the ADC itself, a fact that is sig-
nificant in systems where power consumption is severely
constrained, such as portable sensors or 4–20mA loops.
Figure 9. Resistive Bridge Measurement Circuit
The low-noise floor of the MAX11213 family of 16-/18-/20-
bit devices gives the designer the ability to use simple
binary shifting (digital gain) of the data word to align the
sample range with the available code space. Digital gain
is internally available in the MAX11213.
______________________________________________________________________________________ 25
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Chip Information
AVDD
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns,
go to www3maxim-ic3com/pacꢀages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
16-BIT ADC
R
STRAIN
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO3
16 QSOP
E16+4
21-0055
AVDD
AINP
AINN
R
STRAIN
MAX11213
Figure 10. The MAX11213 ADC Eliminates an External Gain
Stage.
26 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low-Power, Delta-
Sigma ADCs with Programmable Gain and GPIO
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
6/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
27
©
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.
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