MAX11205AEUB+T [MAXIM]
暂无描述;
| 型号： | MAX11205AEUB+T |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | 暂无描述 |
| 文件： | 总14页 (文件大小：1371K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-5238; Rev 0; 4/10
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
General Description
Features
S 16-Bit Full-Scale Resolution
S 720nV Noise (MAX11205B)
S 3ppm INL
S No Missing Codes
S Ultra-Low-Power Dissipation
The MAX11205 is an ultra-low-power (< 300FA max
active current), high-resolution, serial-output ADC. This
device provides the highest resolution per unit power
in the industry, and is optimized for applications that
require very high dynamic range with low power such as
sensors on a 4mA to 20mA industrial control loop. The
MAX11205 provides a high-accuracy internal oscillator
that requires no external components.
RMS
Operating-Mode Current Drain < 300µA (max)
Sleep-Mode Current Drain < 0.1µA
S 2.7V to 3.6V Analog Supply Voltage Range
S 1.7V to 3.6V Digital and I/O Supply Voltage Range
S Fully Differential Signal Inputs
When used with the specified data rates, the internal
digital filter provides more than 80dB rejection of 50Hz or
60Hz line noise. The MAX11205 provides a simple 2-wire
S Fully Differential Reference Inputs
M
serial interface in the space-saving, 10-pin FMAX pack-
S Internal System Clock
2.4576MHz (MAX11205A)
2.2528MHz (MAX11205B)
age. The MAX11205 operates over the -40NC to +85NC
temperature range.
S External Clock
Applications
S Serial 2-Wire Interface (Clock Input and Data Input)
S On-Demand Offset and Gain Self-Calibration
S -40°C to +85°C Operating Temperature Range
Sensor Measurement (Temperature and
Pressure)
Portable Instrumentation
Battery Applications
Weigh Scales
S
2kV ESD Protection
S Lead(Pb)-Free and RoHS-Compliant µMAX
Package
Ordering Information
OUTPUT RATE
(sps)
PART
PIN-PACKAGE
MAX11205AEUB+*
MAX11205BEUB+
10 FMAX
10 FMAX
120
13.75
Note: All devices are specified over the -40NC to +85NC oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*Future product—contact factory for availability.
Selector Guide
RESOLUTION
(BITS)
4-WIRE SPI, 16-PIN QSOP,
PROGRAMMABLE GAIN
4-WIRE SPI,
16-PIN QSOP
2-WIRE SERIAL,
10-PIN µMAX
MAX11201 (with buffers)
MAX11202 (without buffers)
24
MAX11210
MAX11200
20
18
16
MAX11206
MAX11209
MAX11213
MAX11207
MAX11211
MAX11203
MAX11208
MAX11212
MAX11205
µMAX is a registered trademark of Maxim Integrated Products, Inc.
_______________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
ABSOLUTE MAXIMUM RATINGS
Any Pin to GND....................................................-0.3V to +3.9V
AVDD to GND.......................................................-0.3V to +3.9V
DVDD to GND ......................................................-0.3V to +3.9V
Analog Inputs (AINP, AINN, REFP, REFN)
Continuous Power Dissipation (T = +70NC)
A
10-Pin FMAX (derate 5.6mW/NC above +70NC)..........444mW
Operating Temperature Range.......................... -40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range............................ -55NC to +150NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
to GND.............................................. -0.3V to (V
Digital Inputs and Digital Outputs
to GND.............................................. -0.3V to (V
+ 0.3V)
AVDD
+ 0.3V)
DVDD
ESD
(AVDD, AINP, AINN, REFP, REFN, DVDD, CLK, SCLK,
HB
RDY/DOUT, GND) ............................................ Q2kV (Note 1)
Note 1: Human Body Model to specification MIL-STD-883 Method 3015.7.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
AVDD
= +3.6V, V
= +1.8V, V
- V
= V
; internal clock, T = T
to T
, unless otherwise noted. Typical values
MAX
DVDD
REFP
REFN
AVDD
A
MIN
are at T = +25NC under normal conditions, unless otherwise noted.)
A
PARAMETER
ADC PERFORMANCE
Noise-Free Resolution
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NFR
(Notes 2, 3)
MAX11205A
MAX11205B
(Note 4)
16
2.1
Bits
Thermal Noise (Notes 2, 3)
V
N
FV
RMS
0.72
Integral Nonlinearity
Zero Error
INL
-20
-20
+20
+20
ppmFSR
ppmFSR
nV/NC
V
OFF
After calibration, V
- V
- V
= 2.5V
=2.5V
1
REFP
REFN
Zero Drift
50
After calibration, V
(Note 5)
REFP
REFN
Full-Scale Error
-45
3
+45
ppmFSR
ppmFSR/
Full-Scale Error Drift
Power-Supply Rejection
0.05
NC
AVDD DC rejection
70
86
80
dB
DVDD DC rejection (Note 6)
100
ANALOG INPUTS/REFERENCE INPUTS
DC rejection
90
90
123
Common-Mode Rejection (Note 6)
CMR
50Hz/60Hz rejection, MAX11205A
50Hz/60Hz rejection, MAX11205B
MAX11205B (Note 7)
dB
144
65
Normal Mode 50Hz Rejection
Normal Mode 60Hz Rejection
Common-Mode Voltage Range
NMR
NMR
80.5
87
dB
dB
V
50
MAX11205B (Note 7)
73
60
GND
V
AVDD
GND -
30mV
Low input voltage
Absolute Input Voltage
V
V
AVDD
High input voltage
+ 30mV
DC Input Leakage
Sleep mode (Note 2)
1
5
FA
FA
AIN Dynamic Input Current
2
______________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +3.6V, V
= +1.8V, V
- V
= V
; internal clock, T = T
to T
, unless otherwise noted. Typical values
MAX
DVDD
REFP
REFN
AVDD
A
MIN
are at T = +25NC under normal conditions, unless otherwise noted.)
A
PARAMETER
REF Dynamic Input Current
AIN Input Capacitance
REF Input Capacitance
AIN Voltage Range
SYMBOL
CONDITIONS
MIN
TYP
7.5
10
MAX
UNITS
FA
pF
15
pF
V
- V
AINN
-V
REF
+V
V
AINP
REF
REF Voltage Range
V
V
AVDD
MAX11205A
MAX11205B
MAX11205A
MAX11205B
246
225
246
225
Input Sampling Rate
REF Sampling Rate
f
kHz
kHz
S
LOGIC INPUTS (SCLK, CLK)
Input Current
Input leakage current
1
FA
0.3 x
Input Low Voltage
V
V
IL
V
DVDD
0.7 x
Input High Voltage
Input Hysteresis
External Clock
V
V
IH
V
DVDD
V
200
mV
HYS
MAX11205A
MAX11205B
2.4576
2.2528
MHz
LOGIC OUTPUTS (RDY/DOUT)
Output Low Level
V
I
I
= 1mA; also tested for V
= 3.6V
= 3.6V
0.4
V
V
OL
OL
DVDD
0.9 x
Output High Level
V
OH
= 1mA; also tested for V
DVDD
OH
V
DVDD
Floating State Leakage Current
Output leakage current
Q10
FA
pF
Floating State Output
Capacitance
9
POWER REQUIREMENTS
Analog Supply Voltage
Digital Supply Voltage
Total Operating Current
DVDD Operating Current
AVDD Operating Current
AVDD Sleep Current
AVDD
DVDD
2.7
1.7
3.6
3.6
300
60
245
2
V
V
(AVDD + DVDD)
230
45
FA
FA
FA
FA
FA
185
0.4
DVDD Sleep Current
0.35
2
2-WIRE SERIAL-INTERFACE TIMING CHARACTERISTICS
SCLK Frequency
f
5
MHz
ns
SCLK
SCLK Pulse Width Low
SCLK Pulse Width High
t
t
60/40 duty cycle 5MHz clock
40/60 duty cycle 5MHz clock
80
80
1
2
ns
SCLK Rising Edge to Data Valid
Transition Time
t
40
ns
3
_______________________________________________________________________________________
3
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
ELECTRICAL CHARACTERISTICS (continued)
(V
AVDD
= +3.6V, V
= +1.8V, V
- V
= V
; internal clock, T = T
to T
, unless otherwise noted. Typical values
MAX
DVDD
REFP
REFN
AVDD
A
MIN
are at T = +25NC under normal conditions, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCLK Rising Edge Data Hold
Time
t
t
t
t
t
t
Allows for positive edge data read
3
ns
4
5
6
7
8
9
RDY/DOUT Fall to SCLK Rising
Edge
0
ns
Fs
MAX11205A
MAX11205B
MAX11205A
MAX11205B
MAX11205A
MAX11205B
MAX11205A
MAX11205B
155
169
Next Data Update Time;
No Read Allowed
8.6
Data Conversion Time
ms
ms
ms
73
208.3
256.1
Data Ready Time After
Calibration Starts (CAL + CNV)
0
0
8.6
73
SCLK High After RDY/DOUT Goes
Low to Activate Sleep Mode
Time from RDY/DOUT Low to
SCLK High for Sleep Mode
Activation
MAX11205A
MAX11205B
0
0
8.6
73
t
10
t
11
t
12
ms
ms
ms
MAX11205A
MAX11205B
8.6
73
Data Ready Time After Wake-Up
from Sleep Mode
Data Ready Time After
Calibration from Sleep Mode
Wake-Up (CAL + CNV)
MAX11205A
MAX11205B
208.4
256.2
Note 2: These specifications are not fully tested and are guaranteed by design and/or characterization.
Note 3: V = V
AINP
AINN.
Note 4: ppmFSR is parts per million of full-scale range.
Note 5: Positive full-scale error includes zero-scale errors.
Note 6: Tested with V
= 1.8V.
REF
Note 7: The MAX11205A has no normal-mode rejection at 50Hz or 60Hz.
4
______________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Typical Operating Characteristics
(V
AVDD
= 3.6V, V
= 1.8V, V
- V
= V
; internal clock; T = T
to T , unless otherwise noted. Typical values
MAX
DVDD
REFP
REFN
AVDD
A
MIN
are at T
+25NC.)
A =
ANALOG ACTIVE CURRENT
vs. AVDD VOLTAGE (MAX11205A)
ANALOG ACTIVE CURRENT
vs. AVDD VOLTAGE (MAX11205B)
ANALOG SLEEP CURRENT vs. AVDD
VOLTAGE (MAX11205A/MAX11205B)
1.0
240
220
200
180
160
140
120
100
240
220
200
180
160
140
120
100
V
= 1.8V
V
= 1.8V
V = 1.8V
DVDD
DVDD
DVDD
0.8
0.6
0.4
0.2
0
T
T
T
= +85°C
= +25°C
= -45°C
T
T
T
= +85°C
= +25°C
= -45°C
A
A
A
A
A
A
T
A
= -45°C
T
A
= +85°C
T
A
= +25°C
2.70 2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
2.70 2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
2.7 2.8 2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6
AVDD VOLTAGE (V)
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE (MAX11205A)
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE (MAX11205B)
SLEEP CURRENT vs. TEMPERATURE
(MAX11205A/MAX11205B)
300
250
200
150
100
50
300
250
200
150
100
50
1.0
0.8
0.6
0.4
0.2
0
V
V
= 3.6V
= 1.8V
AVDD
DVDD
TOTAL
TOTAL
V
= 3.6V
AVDD
V
= 3.6V
AVDD
V
= 1.8V
DVDD
V
= 1.8V
DVDD
TOTAL
55
V
DVDD
V
AVDD
0
0
-45 -25
-5
15
35
55
75
95
-45 -25
-5
15
35
55
75
95
-45 -25
-5
15
35
75
95
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
INTERNAL OSCILLATOR FREQUENCY
vs. TEMPERATURE
DIGITAL ACTIVE CURRENT
vs. DVDD VOLTAGE
DIGITAL SLEEP CURRENT vs. DVDD
VOLTAGE (MAX11205A/MAX11205B)
2.6
2.5
2.4
2.3
2.2
2.1
2.0
130
120
110
100
90
3.0
2.5
2.0
1.5
1.0
0.5
0
V
T
= 3.6V
= +85°C, +25°C, -45°C
V
DVDD
V
AVDD
= 1.8V
= 3.0V
AVDD
A
V
= 3.6V
AVDD
MAX11205A
MAX11205B
T
A
= -45°C
T
A
= +25°C
MAX11205A
80
70
MAX11205B
T
A
= +85°C
60
50
40
-45 -25
-5
15
35
55
75
95
1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6
DVDD VOLTAGE (V)
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5
DVDD VOLTAGE (V)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Typical Operating Characteristics (continued)
(V
AVDD
= 3.6V, V
= 1.8V, V
- V
= V
; internal clock; T = T
to T , unless otherwise noted. Typical values
MAX
DVDD
REFP
REFN
AVDD
A
MIN
are at T
+25NC.)
A =
OFFSET ERROR vs. V
(MAX11205A/MAX11205B)
INTERNAL OSCILLATOR FREQUENCY
vs. AVDD VOLTAGE
REF
OFFSET ERROR vs. TEMPERATURE
(MAX11205A/MAX11205B)
2.0
1.5
1.0
0.5
0
2.6
2.5
2.4
2.3
2.2
2.1
2.5
V
= V
- V
REFP REFN
REF
CALIBRATED AT +25°C
V
= 1.8V
DVDD
2.0
1.5
1.0
0.5
0
T
A
= +25°C
MAX11205A
MAX11205B
T
A
= +85°C
T
A
= -45°C
-0.5
-1.0
1.0
1.5
2.0
2.5
3.0
3.5
4.0
2.70 2.85 3.00 3.15 3.30 3.45 3.60
AVDD VOLTAGE (V)
-45 -25
-5
15
35
55
75
95
V
REF
VOLTAGE (V)
TEMPERATURE (°C)
INTEGRAL NONLINEARITY vs. INPUT
VOLTAGE (MAX11205A/MAX11205B)
FULL-SCALE ERROR vs. TEMPERATURE
(MAX11205A/MAX11205B)
PSRR vs. FREQUENCY
(MAX11205A)
10
8
10
8
0
-20
V
V
V
V
= 3.0V
= 1.8V
= 2.5V
V
= 2.5V
REF
AVDD
DVDD
REF
+FS ERROR
6
6
= 1.5V
IN(CM)
-40
4
4
T
A
= +85°C
2
2
T
T
= +25°C
= -45°C
A
A
-60
0
0
-80
-2
-4
-6
-8
-10
-2
-4
-6
-8
-10
V
V
AVDD
-100
-120
-140
DVDD
10
-FS ERROR
-2.5 -2.0 -1.5 -1.0 -0.5
0
0.5 1.0 1.5 2.0 2.5
-45
-25
-5
15
35
55
75
1
100
1k
10k
100k
INPUT VOLTAGE (V)
TEMPERATURE (°C)
FREQUENCY (Hz)
PSRR vs. FREQUENCY
(MAX11205B)
CMRR vs. FREQUENCY
(MAX11205A/MAX11205B)
NORMAL-MODE FREQUENCY RESPONSE
(MAX11205A)
0
0
-20
0
-20
-20
-40
-40
-40
-60
-60
-60
-80
-80
-80
V
AVDD
MAX11205A
MAX11205B
-100
-120
-140
-100
-120
-140
-100
-120
-140
V
DVDD
1
10
100
1k
10k
100k
1
10
100
1k
10k
100k
1
10
100
1k
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
6
______________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Typical Operating Characteristics (continued)
(V
AVDD
= 3.6V, V
= 1.8V, V
- V
= V
; internal clock; T = T
to T
, unless otherwise noted. Typical values
DVDD
REFP
REFN
AVDD
A
MIN
MAX
are at T
A =
+25NC.)
NORMAL-MODE FREQUENCY RESPONSE
(MAX11205B)
NORMAL-MODE REJECTION OF 50Hz TO 60Hz
(MAX11205B)
0
0
-20
-40
-20
-40
-60
-60
-80
-80
-100
-120
-140
-100
-120
-140
1
10
100
1k
40
45
50
55
60
65
70
FREQUENCY (Hz)
FREQUENCY (Hz)
Functional Diagram
CLOCK GENERATOR
CLK
TIMING
AVDD
DVDD
GND
AINP
AINN
REFP
REFN
SCLK
DIGITAL LOGIC
AND SERIAL-
INTERFACE
DIGITAL FILTER
4
(SINC )
3RD-ORDER
DELTA-SIGMA
MODULATOR
CONTROLLER
RDY/DOUT
MAX11205
_______________________________________________________________________________________
7
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Pin Configuration
TOP VIEW
GND
REFP
REFN
AINN
AINP
1
2
3
4
5
10 CLK
9
8
7
6
SCLK
MAX11205
RDY/DOUT
DVDD
AVDD
µMAX
Pin Description
PIN
NAME
FUNCTION
Ground. Ground reference for analog and digital circuitry.
1
GND
Differential Reference Positive Input. REFP must be more positive than REFN. Connect REFP to a
voltage between AVDD and GND.
2
3
REFP
REFN
Differential Reference Negative Input. REFN must be more negative than REFP. Connect REFN to a
voltage between AVDD and GND.
4
5
6
AINN
AINP
Negative Fully Differential Analog Input
Positive Fully Differential Analog Input
AVDD
Analog Supply Voltage. Connect a supply voltage between +2.7V and +3.6V with respect to GND.
Digital Supply Voltage. Connect a digital supply voltage between +1.7V and +3.6V with respect to
GND.
7
DVDD
Data Ready Output/Serial Data Output. This output serves a dual function. In addition to the serial
data output function, the RDY/DOUT also indicates that the data is ready when the RDY is logic low.
RDY/DOUT changes on the falling edge of SCLK.
RDY/
DOUT
8
9
SCLK
CLK
Serial-Clock Input. Apply an external serial clock to SCLK.
External Clock Signal Input. The internal clock shuts down when CLK is driven by an external clock.
Use a 2.4576MHz oscillator (MAX11205A) or a 2.2528MHz oscillator (MAX11205B).
10
8
______________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
The internal oscillator clock is divided down to run the
digital and analog timing.
Detailed Description
The MAX11205 is an ultra-low power (< 240FA active),
Reference
The MAX11205 provides differential inputs REFP and
REFN for an external reference voltage. Connect the
external reference directly across REFP and REFN to
obtain the differential reference voltage. The common-
high-resolution, low-speed, serial-output ADC. This device
provides the highest resolution per unit power in the
industry, and is optimized for applications that require
very high dynamic range with low power such as sensors
on a 4mA to 20mA industrial control loop.
mode voltage range for V
and V
is between 0
REFP
REFN
The MAX11205 provides a high-accuracy internal oscilla-
tor, which requires no external components. When used
with the specified data rates, the internal digital filter pro-
vides more than 80dB rejection of 50Hz or 60Hz line noise.
The MAX11205 provides a simple, system-friendly, 2-wire
serial interface in the space-saving, 10-pin FMAX package.
and V . The differential voltage range for REFP and
AVDD
REFN is 1V to V
.
AVDD
Digital Filter
The MAX11205 contains an on-chip, digital lowpass filter
that processes the 1-bit data stream from the modulator
using a SINC4 (sinx/x)4 response. When the device is
operating in single-cycle conversion mode, the filter is
reset at the end of the conversion cycle. When operat-
ing in continuous conversion latent mode, the filter is not
reset. The SINC4 filter has a -3dB frequency equal to
24% of the data rate.
Power-On Reset (POR)
The MAX11205 utilizes power-on reset (POR) supply-
monitoring circuitry on both the digital supply (DVDD)
and the analog supply (AVDD). The POR circuitry
ensures proper device default conditions after either a
digital or analog power-sequencing event.
Serial-Digital Interface
The MAX11205 communicates through a 2-wire serial
interface with a clock input and data output. The output
rate is predetermined based on the package option
(MAX11205A at 120sps and MAX11205B at 13.75sps).
The MAX11205 performs a self-calibration operation as
part of the startup initialization sequence whenever a
digital POR is triggered. It is important to have a stable
reference voltage available at the REFP and REFN pins
to ensure an accurate calibration cycle. If the reference
voltage is not stable during a POR event, the part should
be calibrated once the reference has stabilized. The part
can be programmed for calibration by using 26 SCLKs
as shown in Figure 3.
2-Wire Interface
The MAX11205 is compatible with the 2-wire interface
and uses SCLK and RDY/DOUT for serial communica-
tions. In this mode, all controls are implemented by tim-
ing the high or low phase of the SCLK. The 2-wire serial
interface only allows for data to be read out through the
RDY/DOUT output.
The digital POR trigger threshold is approximately 1.2V
and has 100mV of hysteresis. The analog POR trigger
threshold is approximately 1.25V and has 100mV of hys-
teresis. Both POR circuits have lowpass filters that pre-
vent high-frequency supply glitches from triggering the
POR. The analog supply (AVDD) and the digital supply
(DVDD) pins should be bypassed using 0.1FF capaci-
tors placed as close as possible to the package pin.
Supply the serial clock to SCLK to shift the conversion
data out.
The RDY/DOUT is used to signal data ready, as well as
reading the data out when SCLK pulses are applied.
RDY/DOUT is high by default. The MAX11205 pulls
RDY/DOUT low when data is available at the end of con-
version, and stays low until clock pulses are applied at
SCLK input; on applying the clock pulses at SCLK, the
RDY/DOUT outputs the conversion data on every SCLK
positive edge. To monitor data availability, pull RDY/
DOUT high after reading the 16 bits of data by supplying
a 25th SCLK pulse.
Analog Inputs
The MAX11205 accepts two analog inputs (AINP and
AINN). The modulator input range is bipolar (-V
to
REF
+V ).
REF
Internal Oscillator
The MAX11205 incorporates a highly stable internal
oscillator that provides the system clock. The system
clock runs the internal state machine and is trimmed to
2.4576MHz (MAX11205A) or 2.2528MHz (MAX11205B).
The different operational modes using this 2-wire inter-
face are described in the following sections.
_______________________________________________________________________________________
9
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Data Read Following Every Conversion
The MAX11205 indicates conversion data availability, as
well as allows the retrieval of data through the RDY/DOUT
output. The RDY/DOUT output idles at the value of the
last bit read unless a 25th SCLK pulse is provided, caus-
ing RDY/DOUT to idle high. RDY/DOUT is pulled low
when the conversion data is available.
not required to read out all 16 bits before putting the part
in sleep mode. Sleep mode is activated after the SCLK is
held high (see Figure 4). The RDY/DOUT output is pulled
high once the device enters sleep mode. To come out
of the sleep mode, pull SCLK low. After the sleep mode
is deactivated (when the device wakes up), conversion
starts again and RDY/DOUT goes low, indicating the
next conversion data is available. See Figure 4.
Figure 1 shows the timing diagram for the data read.
Once a low is detected on RDY/DOUT, clock pulses at
SCLK clock out the data. Data is shifted out MSB first
and is in binary two’s complement format. Once all the
data has been shifted out, a 25th SCLK is required to
pull the RDY/DOUT output back to the idle high state.
See Figure 2.
Single-Conversion Mode
For operating the MAX11205 in single-conversion mode,
activate and deactivate sleep mode between conver-
sions as described in the Data Read Followed by Sleep
Mode section). Single-conversion mode reduces power
consumption by shutting down the device when idle
between conversions. See Figure 4.
If the data is not read before the next conversion data is
updated, the old data is lost, as the new data overwrites
the old value.
Single-Conversion Mode
with Self-Calibration at Wake-Up
The MAX11205 can be put in self-calibration mode imme-
diately after wake-up from sleep mode. Self-calibration at
wake-up helps to compensate for temperature or supply
changes if the device is shut down for extensive periods.
To automatically start self-calibration at the end of sleep
mode, all the data bits must be shifted out followed by
the 25th SCLK edge to pull RDY/DOUT high. On the 26th
SCLK, keep it high for as long as shutdown is desired.
Once SCLK is pulled back low, the device automatically
performs a self-calibration, and when the data is ready,
the RDY/DOUT output goes low. See Figure 5. This also
achieves the purpose of single conversions with self-
calibration.
Data Read Followed by Self-Calibration
To initiate self-calibration at the end of a data read,
provide a 26th SCLK pulse. After reading the 16 bits of
conversion data, a 25th positive edge on SCLK pulls the
RDY/DOUT output back high, indicating the end of data
read. Provide a 26th SCLK pulse to initiate a self-calibra-
tion routine starting on the falling edge of the 26th SCLK.
A subsequent falling edge of RDY/DOUT indicates data
availability at the end of calibration. The timing is illus-
trated in Figure 3.
Data Read Followed by Sleep Mode
The MAX11205 can be put into sleep mode to save
power between conversions. To activate the sleep mode,
idle the SCLK high any time after the RDY/DOUT output
goes low (that is, after conversion data is available). It is
10 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
t
5
t
1
t
2
SCLK
1
2
3
24
t
3
t
4
RDY/DOUT
D15
D14
0
t
6
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE
t
7
Figure 1. Timing Diagram for Data Read After Conversion
SCLK
1
2
3
24
25
25TH SLK RISING EDGE
PULLS RDY/DOUT
HIGH
RDY/DOUT
D15
D14
0
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE
Figure 2. Timing Diagram for Data Read Followed by RDY/DOUT Being Asserted High Using 25th SCLK
CALIBRATION STARTS ON 26TH SCLK
SCLK
1
2
3
24
25
26
1
2
25TH SCLK PULLS
RDY/DOUT HIGH
RDY/DOUT
D15
D14
0
D15
D14
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE AFTER CALIBRATION
t
8
Figure 3. Timing Diagram for Data Read Followed by Two Extra Clock Cycles for Self-Calibration
______________________________________________________________________________________ 11
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
DEVICE ENTERS
SLEEP MODE
DEVICE EXITS OUT
SLEEP MODE
1
2
3
1
2
24
SCLK
SLEEP
MODE
t
9
t
10
RDY/DOUT
D14
0
D15
D15
D14
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE
t
11
Figure 4. Timing Diagram for Data Read Followed by Sleep Mode Activation; Single-Conversion Timing
25TH SCLK PULLS RDY/DOUT HIGH
DEVICE ENTERS
SLEEP MODE
DEVICE EXITS OUT SLEEP MODE
AND STARTS CALIBRATION
1
2
3
1
2
24
25
26
SCLK
SLEEP
MODE
t
10
RDY/DOUT
D14
0
D15
D15
D14
CONVERSION IS DONE
DATA IS AVAILABLE
CONVERSION IS DONE
DATA IS AVAILABLE AFTER CALIBRATION
t
12
Figure 5. Timing Diagram for Sleep Mode Activation Followed by Self-Calibration at Wake-Up
12 _____________________________________________________________________________________
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Applications Information
See Figure 6 for the RTD temperature measurement circuit
and Figure 7 for a resistive bridge measurement circuit.
Chip Information
PROCESS: BiCMOS
Package Information
I
REF2
For the latest package outline information and land pat-
terns, go to www.maxim-ic.com/packages. Note that
a “+”, “#”, or “-” in the package code indicates RoHS
status only. Package drawings may show a different suf-
fix character, but the drawing pertains to the package
regardless of RoHS status.
REFP
R
REF
I
REF1
REFN
AINP
I
= K x I
REF2
REF1
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
10 µMAX
U10+2
21-0061
MAX11205
R
RTD
AINN
GND
Figure 6. RTD Temperature Measurement Circuit
AVDD
REFP
REFN
MAX11205
AINP
AINN
Figure 7. Resistive Bridge Measurement Circuit
______________________________________________________________________________________ 13
16-Bit, Single-Channel, Ultra-Low Power,
Delta-Sigma ADC with 2-Wire Serial Interface
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
4/10
Initial release
—
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
14
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
©
相关型号：
MAX11205BEUB+
16-Bit, Single-Channel, Ultra-Low Power, Delta-Sigma ADC with 2-Wire Serial Interface
MAXIM
MAX11206
20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with Programmable Gain and GPIO
MAXIM
MAX11206EEE
The MAX11200, MAX11206, MAX11209, MAX11210, and MAX11213 evaluation kits (EV kits) consist of one MAX11200, MAX11206, MAX11209, MAX11210, or MAX11213 evaluation board and software.
MAXIM
MAX11206EEE+
20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with Programmable Gain and GPIO
MAXIM
MAX11206EEE+T
A/D Converter, 20-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO16, ROHS COMPLIANT, QSOP-16
MAXIM
MAX11207
20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with Programmable Gain and GPIO
MAXIM
MAX11207EEE+
20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADCs with Programmable Gain and GPIO
MAXIM
MAX11207EEE+T
A/D Converter, 20-Bit, 1 Func, 1 Channel, Serial Access, BICMOS, PDSO16, ROHS COMPLIANT, QSOP-16
MAXIM
MAX11208
20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADC with 2-Wire Serial Interface
MAXIM
MAX11208AEUB+
20-Bit, Single-Channel, Ultra-Low-Power, Delta-Sigma ADC with 2-Wire Serial Interface
MAXIM
©2020 ICPDF网 联系我们和版权申明