DS3508E+T&R/C [MAXIM]
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| 型号： | DS3508E+T&R/C |
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MAXIM INTEGRATED PRODUCTS |
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Rev 1; 3/08
2
I C, 8-Channel Gamma Buffer with EEPROM
General Description
Features
The DS3508 is a programmable 8-channel gamma volt-
age generator with one byte of on-chip EEPROM and
one byte of SRAM memory per channel. Each channel
is composed of an independent 8-bit DAC with an asso-
ciated EEPROM/SRAM pair. At power-up, nonvolatile
(NV) EEPROM gamma data is loaded into its corre-
sponding SRAM register that drives the associated 8-bit
DAC. An on-chip control register allows selectable con-
trol of writing to SRAM/EEPROM or SRAM only.
o 8-Bit Gamma DACs, 8 Channels
o 1 Byte EEPROM and 1 Byte SRAM per Channel
o Ultra-Low Power (2mA I , typ)
DD
2
o 400kbps I C Interface
o 9.0V to 15.5V Analog Supply
o 2.7V to 5.5V Digital Supply
The DS3508 is designed for low-power operation and
o 20-Pin TSSOP Package
draws less than 2mA (typ) from the V
supply.
DD
o Address Pin Allows Two DS3508s to Reside on
2
Programming occurs through an I C-compatible serial
interface with support for speeds up to 400kHz.
2
the Same I C Bus
Ordering Information
Applications
TFT-LCD Gamma Buffer
Industrial Controls
PART
TEMP RANGE
-45°C to +95°C
-45°C to +95°C
PIN-PACKAGE
20 TSSOP
DS3508E+
DS3508E+T&R
20 TSSOP
+Denotes a lead-free package.
T&R = Tape and reel.
Typical Operating Circuit
Pin Configuration
TOP VIEW
SCL
SDA
GND
A0
1
2
3
4
5
6
7
8
9
20
V
CC
15.0V
14.8V 8.0V
VHH VHM
19 GM1
18 GM2
17 GM3
16 GM4
15 GM5
14 GM6
13 GM7
12 GM8
11 N.C.
5.0V
8
SOURCE DRIVER
V
DD
V
GM1
GM2
GM3
GM4
CC
DS3508
VHH
VHM
VLM
VLL
2
SDA
SCL
LIQUID-CRYSTAL
DISPLAY
I C
DS3508
GM5
GM6
GM7
GM8
MASTER
A0
GND
VLL VLM
0.2V 7.0V
V
DD
N.C. 10
TSSOP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
I C, 8-Channel Gamma Buffer with EEPROM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
and
Junction Temperature......................................................+125°C
Operating Temperature Range ...........................-45°C to +95°C
Programming Temperature Range .........................0°C to +70°C
Storage Temperature..........................................55°C to +125°C
Soldering Temperature..............................................Refer to the
IPC/JEDEC J-STD-020 Specification.
DD
VHH Relative to GND ..........................................-0.5V to +16V
Voltage Range on VHM, VLM, and
VLL Relative to GND............................................-0.5V to +12V
Voltage Range on V , SDA, SCL, and
CC
A0 Relative to GND ............................................-0.5V to +6.0V
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -45°C to +95°C)
A
PARAMETER
Analog Supply Voltage
VHH, VHM
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
V
DD
(Note 1)
+9.0
+15.5
V
V
V
V
V
V
V
Applies to GM1–GM4
Applies to GM5–GM8
V
/2 - 1
DD
V
- 0.2
DD
VLM, VLL
0.2
3.0
2.7
V
/2 + 1
5.5
DD
VHH–VHM and VLM–VLL
Digital Voltage Supply
Input Logic 0 (A0, SDA, SCL)
Input Logic 1 (A0, SDA, SCL)
V
REF
ꢀ
V
CC
(Note 1)
V
0.3 x V
CC
IL
V
0.7 x V
IH
CC
INPUT ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -45°C to +95°C.)
A
PARAMETER
SYMBOL
CONDITIONS
= 15.5V (Note 2)
MIN
TYP
MAX
UNITS
Analog Supply Current
I
V
DD
2
4
mA
DD
Digital Supply Current, NV Read
or Write
I
f
= 400kHz
= 5.5V (Note 3)
= 5.5V
0.2
2
1.0
10
mA
µA
µA
CC
SCL
Digital Supply Standby Current
I
V
V
STBY
CC
Input Leakage
(SDA, SCL, A0)
I
-1
1
+1
IL
CC
Input Resistance at VHH, VHM,
VLM, VLL
R
Mꢀ
IN
2
_______________________________________________________________________________________
2
I C, 8-Channel Gamma Buffer with EEPROM
OUTPUT ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V; V = 15.5V, T = -45°C to +95°C, unless otherwise noted.)
DD A
PARAMETER
SYMBOL
CONDITIONS
MIN
8
TYP
MAX
UNITS
Bits
Gamma DAC Resolution
Integral Nonlinearity Error
T
T
= +25°C (Note 4)
-1.25
-0.5
+1.25
+0.5
LSB
A
Differential Nonlinearity Error
= +25°C (Note 5)
LSB
A
Output Voltage Range:
GM1–GM4
VHM
VLL
VHH
VLM
V
V
Output Voltage Range:
GM5–GM8
R
(GM1–GM8)
R
OUT
(Notes 6, 7)
= +25°C (Note 8)
20
kꢀ
OUT
Amplifier Offset
T
-35
+35
mV
A
2
I C ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +5.5V, T = -45°C to +95°C, timing referenced to V
and V .) (Figure 4)
IH(MIN)
CC
A
IL(MAX)
PARAMETER
SYMBOL
CONDITIONS
MIN
0
TYP
MAX
UNITS
kHz
µs
SCL Clock Frequency
Low Period of SCL
High Period of SCL
f
(Note 9)
400
SCL
t
Measured at V
Measured at V
1.3
0.6
LOW
IL
IH
t
µs
HIGH
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
0.6
µs
µs
µs
BUF
SCL rising through V to SDA falling
IH
START Setup Time
t
t
SU:STA
through V
IH
Hold Time (Repeated) START
Condition
SDA falling through V to SCL falling
IL
HD:STA
through V
IH
Data Hold Time
t
t
0
0.9
µs
ns
µs
µs
ns
ns
µs
HD:DAT
Data Setup Time
A0 Setup Time
100
0.6
0.6
SU:DAT
t
t
Before START
After STOP
(Note 10)
SU:A
A0 Hold Time
HD:A
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Setup Time
t
R
20 + (0.1 x C )
300
300
B
t
F
(Note 10)
20 + (0.1 x C )
B
t
0.6
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 10)
(Note 11)
400
20
pF
ms
ns
B
EEPROM Write Time
t
W
SCL Falling Edge to SDA Output
Data Valid
SCL falling through V to SDA exit
IL
0.3–0.7 x V window
CC
t
900
AA
DH
SCL falling through V until SDA in
IL
0.3–0.7 x V window
CC
Output Data Hold
t
0
ns
_______________________________________________________________________________________
3
2
I C, 8-Channel Gamma Buffer with EEPROM
2
I C ELECTRICAL CHARACTERISTICS (continued)
(V
= +2.7V to +5.5V, T = -45°C to +95°C, timing referenced to V
and V
.) (Figure 4)
CC
A
IL(MAX)
CONDITIONS
4mA sink current
6mA sink current
IH(MIN)
PARAMETER
SYMBOL
MIN
TYP
MAX
0.4
UNITS
SDA Output Low Voltage
V
V
OL
0.6
Input Capacitance on
A0, SDA, or SCL
C
5
10
pF
I
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= +2.7V to +5.5V)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
EEPROM Write Cycles
T
A
= +70°C
50,000
Writes
Note 1: All voltages referenced to ground.
Note 2: Analog supply current specified with no load on GMx outputs.
Note 3: ISTBY specified for the inactive state measured with SDA = SCL = V
.
CC
Note 4: INL = [V(GMx) - (V(GMx) ]/LSB(ideal) - i, for i = 0 to 254.
i
0
Note 5: DNL = [V(GMx)
- (V(GMx) ]/LSB(ideal) - 1, for i = 0 to 255.
i+1
i
Note 6: DAC code = 80h.
Note 7: Outputs unloaded.
Note 8: VHH = 12.0V, VHM = 8.75V, VLM = 6.75V, VLL = 0.5V.
Note 9: Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I C standard mode.
2
Note 10: C —Total capacitance of one bus line in picofarads.
B
Note 11: EEPROM write begins after a STOP condition occurs.
Typical Operating Characteristics
(V
DD
= 15.0V, V = 5.0V, T = +25°C, unless otherwise noted.)
CC A
DIGITAL SUPPLY STANDBY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
DIGITAL SUPPLY STANDBY CURRENT
vs. TEMPERATURE
10
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10
9
8
7
6
5
4
3
2
1
0
SDA = SCL = V
CC
V
= 5.5V
CC
SDA = SCL = V
9
8
7
6
5
4
3
2
1
0
CC
2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
8
10
12
(V)
14
16
-45 -25
-5
15
35
55
75
95
V
CC
(V)
V
TEMPERATURE (°C)
DD
4
_______________________________________________________________________________________
2
I C, 8-Channel Gamma Buffer with EEPROM
Typical Operating Characteristics (continued)
(V
DD
= 15.0V, V = 5.0V, T = +25°C, unless otherwise noted.)
CC A
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
GAMMA OUTPUT vs. SETTING
GAMMA OFFSET vs. TEMPERATURE
4.0
15
12
9
10
8
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
GM1 = VHH = 14.5V
GM1 = VHH = 12.0V
GM1–GM4
= 15.0V
VHH = 14.8V
VHM = 8.0V
VLM = 7.0V
VLL = 0.2V
6
V
DD
4
2
0
6
-2
-4
-6
-8
-10
GM8 = VLM = 8.5V
GM8 = VLL = 0.5V
3
GM5–GM8
GM1 = VHM = 6.5V
0
-45 -25
-5
15
35
55
75
95
0
32 64 96 128 160 192 224 256
GAMMA SETTING (DEC)
-45 -25
-5
15
35
55
75
95
TEMPERATURE (°C)
TEMPERATURE (°C)
GM1 DNL
GM1 INL
GM8 DNL
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
1.00
0.75
0.50
0.25
0
V
= 15.0V
V
= 15.0V
V
= 15.0V
DD
DD
DD
VHH = 14.8V
VHM = 8.0V
VHH = 14.8V
VHM = 8.0V
VLM = 7.0V
VLL = 0.2V
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
-0.25
-0.50
-0.75
-1.00
0
32 64 96 128 160 192 224 256
GAMMA SETTING (DEC)
0
32 64 96 128 160 192 224 256
0
32 64 96 128 160 192 224 256
GAMMA SETTING (DEC)
GAMMA SETTING (DEC)
GM8 INL
1.00
0.75
0.50
0.25
0
V
= 15.0V
DD
VLM = 7.0V
VHM = 0.2V
-0.25
-0.50
-0.75
-1.00
0
32 64 96 128 160 192 224 256
GAMMA SETTING (DEC)
_______________________________________________________________________________________
5
2
I C, 8-Channel Gamma Buffer with EEPROM
Functional Diagram
V
DD
V
DD
VHH
8-BIT
DAC
SRAM 1
GM1
GM2
GM3
GM4
V
CC
EEPROM 1
SRAM 2
V
CC
8-BIT
DAC
SDA
SCL
A0
2
I C
INTERFACE
EEPROM 2
SRAM 3
8-BIT
DAC
CONTROL
LOGIC
EEPROM 3
SRAM 4
8-BIT
DAC
CONTROL
REGISTERS
VHM
VLM
EEPROM 4
8-BIT
DAC
SRAM 5
GM5
GM6
GM7
GM8
EEPROM 5
SRAM 6
8-BIT
DAC
EEPROM 6
SRAM 7
8-BIT
DAC
EEPROM 7
SRAM 8
8-BIT
DAC
VLL
EEPROM 8
GND
DS3508
6
_______________________________________________________________________________________
2
I C, 8-Channel Gamma Buffer with EEPROM
Pin Description
PIN
NAME
TYPE
FUNCTION
2
1
SCL
Input
Serial Clock Input. I C clock input.
2
Input/
Output
Serial Data Input/Output (Open Drain). I C bidirectional data pin that requires a pullup
resistor to realize high logic levels.
2
SDA
3
4
GND
A0
Ground
Input
Ground
2
Address Input. Determines I C slave address.
Reference
Input
5
6
7
8
VHH
VHM
VLM
VLL
High-Voltage DAC, Upper Reference
High-Voltage DAC, Lower Reference
Low-Voltage DAC, Upper Reference
Low-Voltage DAC, Lower Reference
Reference
Input
Reference
Input
Reference
Input
9
10, 11
12
V
Power
—
Analog Supply
No Connection
DD
N.C.
GM8
GM7
GM6
GM5
GM4
GM3
GM2
GM1
13
Gamma Analog Outputs 5–8. These pins are the low-voltage gamma outputs
referenced to VLL and VLM.
Output
14
15
16
17
Gamma Analog Outputs 1–4. These pins are the high-voltage gamma outputs
referenced to VHH and VHM.
Output
Power
18
19
20
V
CC
Digital Supply
2
MODE = 0: I C writes to memory addresses
Detailed Description
00h–07h write to both SRAM 1–8 and
EEPROM 1–8.
The DS3508 provides eight independent DACs that
allow precise and repeatable setting of gamma curves.
The DS3508 provides four high-voltage DACs
(GM1–GM4) that operate between VHH and VHM and
four low-voltage DACs (GM5–GM8) that operate
between VLM and VLL. Each of the DACs provides 8
bits of resolution.
2
I C reads from addresses 00h–07h
read from SRAM 1–8.
2
MODE = 1: I C writes to addresses 00h–07h write
to SRAM 1–8.
2
I C reads from addresses 00h–07h
The DS3508 DAC output voltages are independently
controlled by the data stored in that channel’s SRAM
register. The MODE bit in the volatile control register
read from SRAM 1–8.
2
Regardless of the MODE bit setting, all I C reads of
address 00–07h return the contents of the SRAM regis-
ters. Setting MODE = 1 allows for quick writing of SRAM
without the added delay of writing to the associated
EEPROM register. The data that is stored in EEPROM and
SRAM remains unchanged if the MODE bit is toggled.
2
(CR bit 7) determines how I C data is written to the
SRAM and EEPROM gamma data registers. Reading
and writing to the SRAM/EEPROM gamma data regis-
ters is based on the state of the MODE bit as follows:
_______________________________________________________________________________________
7
2
I C, 8-Channel Gamma Buffer with EEPROM
On power-up, the gamma data that is stored in each
channel’s EEPROM register is loaded into the corre-
sponding SRAM registers. The volatile CR register pow-
ers up as 00h, setting the device into mode 0.
with end points VHH and VHM controls outputs
GM1–GM4, and a low-voltage array with end points
VLM and VLL controls outputs GM5–GM8. The resistor
string arrays are composed of 255 identical resistors.
The switching networks can select any tap point
between adjacent resistors as well as either end point
(VHH/VHM or VLM/VLL pins). Table 1 shows the rela-
tionship between the 8-bit data and the DAC voltage.
DAC Description
The DACs are composed of a resistor string array and
a switching network per channel. A high-voltage array
SDA
SCL
A0
2
I C
8-BIT
DAC
SRAM
GMx
INTERFACE
EEPROM
Figure 1. Single-Channel Block Diagram
VHH
VLL
CODE 0
CODE 0
CODE 1
CODE 2
R
H1
R
H2
R
H3
R
R
R
L1
CODE 1
CODE 2
L2
L3
R
H253
R
H254
R
H255
R
L253
R
L254
R
L255
CODE 253
CODE 254
CODE 255
CODE 253
CODE 254
CODE 255
VHM
VLM
Figure 2. DAC Block Diagram
8
_______________________________________________________________________________________
2
I C, 8-Channel Gamma Buffer with EEPROM
Table 1. DAC Voltage/Data Relationship for Selected Codes
OUTPUT VOLTAGE
DATA (BINARY)
GM1–GM4
GM5–GM8
0000 0000
0000 0001
0000 0010
0000 0011
0000 1111
0011 1111
0111 1111
1111 1101
1111 1110
1111 1111
VHH
VLL
VHH + 1 x (VHM - VHH)/255
VHH + 2 x (VHM - VHH)/255
VHH + 3 x (VHM - VHH)/255
VHH + 15 x (VHM - VHH)/255
VHH + 63 x (VHM - VHH)/255
VHH + 127 x (VHM - VHH)/255
VHH + 253 x (VHM - VHH)/255
VHH + 254 x (VHM - VHH)/255
VHM
VLL+ 1 x (VLM - VLL)/255
VLL + 2 x (VLM - VLL)/255
VLL + 3 x (VLM - VLL)/255
VLL + 15 x (VLM - VLL)/255
VLL + 63 x (VLM - VLL)/255
VLL + 127 x (VLM - VLL)/255
VLL + 253 x (VLM - VLL)/255
VLL + 254 x (VLM - VLL)/255
VLM
Slave Address Byte and Address Pin
The slave address byte consists of a 7-bit slave
address plus a R/W bit (see Figure 3). The DS3508’s
slave address is determined by the state of the A0 pin.
This pin allows up to two devices to reside on the same
LSB
MSB
1
1
1
0
1
0
A0
R/W
2
I C bus. Connecting A0 to GND results in a 0 in the
SLAVE ADDRESS*
READ/WRITE BIT
corresponding bit position in the slave address.
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
Conversely, connecting A0 to V
results in a 1 in the
CC
corresponding bit position. For example, the DS3508’s
2
slave address byte is E8h when A0 is grounded. I C
Figure 3. DS3508 Slave Address Byte
2
communication is described in detail in the I C Serial
Interface Description section.
_______________________________________________________________________________________
9
2
I C, 8-Channel Gamma Buffer with EEPROM
registers also has a corresponding NV EEPROM regis-
Memory Organization
Memory Description
The list of registers/memory contained in the DS3508 is
shown in the memory map (Table 2). Each of the GMx
ter. Additional information regarding reading and writ-
2
ing the memory is located in the I C Serial Interface
Description section.
Table 2. Memory Map
ADDRESS
NAME
(HEX)
SRAM
EEPROM
GM1
GM2
00
01
SRAM1 (8 bits)
SRAM2 (8 bits)
SRAM3 (8 bits)
SRAM4 (8 bits)
SRAM5 (8 bits)
SRAM6 (8 bits)
SRAM7 (8 bits)
SRAM8 (8 bits)
Volatile Control Register
Reserved
EEPROM1 (8 bits)
EEPROM2 (8 bits)
EEPROM3 (8 bits)
EEPROM4 (8 bits)
EEPROM5 (8 bits)
EEPROM6 (8 bits)
EEPROM7 (8 bits)
EEPROM8 (8 bits)
N/A
GM3
02
GM4
03
GM5
04
GM6
05
GM7
06
GM8
07
Control Register
Reserved
08
09–FF
Reserved
*All EEPROM1–8 is factory-programmed to 80h.
Detailed Register Description
Register 08h: Control Register (CR)
POWER-UP DEFAULT
00h
MEMORY TYPE
Volatile
08h
MODE
Bit 7
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Bit 0
2
MODE 0 = (Default) I C writes to both SRAM and EEPROM.
Bit 7
Bits 6 to 0
2
MODE 1 = I C writes to SRAM only.
Reserved.
This bit determines if data is written to EEPROM and SRAM or only SRAM.
10 ______________________________________________________________________________________
2
I C, 8-Channel Gamma Buffer with EEPROM
2
Bit write: Transitions of SDA must occur during the low
I C Serial Interface Description
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into the
device during the rising edge of the SCL.
2
I C Definitions
The following terminology is commonly used to describe
I C data transfers. (See Figure 4 and the I C Electrical
Characteristics table for additional information.)
2
2
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA at
the falling edge of the previous SCL pulse and the data
bit is valid at the rising edge of the current SCL pulse.
Remember that the master generates all SCL clock puls-
es, including when it is reading bits from the slave.
Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states.
Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a
write operation) performs an ACK by transmitting a 0
during the 9th bit. A device performs a NACK by trans-
mitting a 1 during the 9th bit. Timing for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
data. A NACK is used to terminate a read sequence or
indicates that the device is not receiving data.
START condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated STARTS are
commonly used during read operations to identify a spe-
cific memory address to begin a data transfer. A repeat-
ed START condition is issued identically to a normal
START condition.
Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgment from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
R
t
F
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 4. I C Timing Diagram
______________________________________________________________________________________ 11
2
I C, 8-Channel Gamma Buffer with EEPROM
Byte read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition, and the master transmits an ACK using
the bit write definition to receive additional data bytes.
The master must NACK the last byte read to terminate
communication so the slave returns control of SDA to
the master.
Writing multiple bytes to a slave: To write multiple
bytes to a slave in one transaction, the master gener-
ates a START condition, writes the slave address byte
(R/W = 0), writes the starting memory address, writes
up to 4 data bytes, and generates a STOP condition.
The DS3508 can write 1 to 4 bytes (1 page or row) in a
single write transaction. This is internally controlled by
an address counter that allows data to be written to
consecutive addresses without transmitting a memory
address before each data byte is sent. The address
counter limits the write to one 4-byte page. The first
page begins at address 00h and the second page
begins at 04h. Attempts to write to additional pages of
memory without sending a STOP condition between
pages results in the address counter wrapping around
to the beginning of the present row. To prevent address
wrapping from occurring, the master must send a
STOP condition at the end of the page, then wait for the
bus-free or EEPROM-write time to elapse. Then the
master can generate a new START condition, and write
the slave address byte (R/W = 0) and the first memory
address of the next memory row before continuing to
write data.
2
Slave address byte: Each slave on the I C bus
responds to a slave address byte sent immediately fol-
lowing a START condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
The DS3508’s slave address is determined by the state
of the A0 address pin as shown in Figure 3. An address
pin connected to GND results in a 0 in the correspond-
ing bit position in the slave address. Conversely, an
address pin connected to V
responding bit positions.
results in a 1 in the cor-
CC
When the R/W bit is 0 (such as in E8h), the master is
indicating that it will write data to the slave. If R/W = 1
(E9h in this case), the master is indicating that it wants
to read from the slave.
Acknowledge polling: Any time a EEPROM byte is
written, the DS3508 requires the EEPROM write time
(t ) after the STOP condition to write the contents of
W
If an incorrect slave address is written, the DS3508
the byte to EEPROM. During the EEPROM write time,
the device does not acknowledge its slave address
because it is busy. It is possible to take advantage of
this phenomenon by repeatedly addressing the
DS3508, which allows communication to continue as
soon as the DS3508 is ready. The alternative to
acknowledge polling is to wait for a maximum period of
2
assumes the master is communicating with another I C
device and ignores the communication until the next
START condition is sent.
2
Memory address: During an I C write operation, the
master must transmit a memory address to identify the
memory location where the slave is to store the data.
The memory address is always the second byte trans-
mitted during a write operation following the slave
address byte.
t
W
to elapse before attempting to access the device.
Reading a single byte from a slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read opera-
tion occurs at the present value of the memory address
counter. To read a single byte from the slave, the master
generates a START condition, writes the slave address
byte with R/W = 1, reads the data byte with a NACK to
indicate the end of the transfer, and generates a STOP
condition. However, since requiring the master to keep
track of the memory address counter is impractical, the
following method should be used to perform reads from
a specified memory location.
2
I C Communication
2
See Figure 5 for I C communication examples.
Writing a single byte to a slave: The master must gen-
erate a START condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a STOP condition. Remember the
master must read the slave’s acknowledgment during
all byte write operations.
When writing to the DS3508, the DAC adjusts to the new
setting following a STOP. The EEPROM (used to make
the setting NV) is written following the STOP condition at
the end of the write command if the MODE bit is set to 0.
Reading multiple bytes from a slave: The read opera-
tion can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
12 ______________________________________________________________________________________
2
I C, 8-Channel Gamma Buffer with EEPROM
2
TYPICAL I C WRITE TRANSACTION
MSB
LSB
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
1
1
1
0
1
0
A0 R/W
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
REGISTER ADDRESS
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
SLAVE
ADDRESS*
DATA
2
EXAMPLE I C TRANSACTIONS (WHEN A0 IS CONNECTED TO GND)
E8h
08h
80h
A) SINGLE-BYTE WRITE
-WRITE CR REGISTER TO 80h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
STOP
START 1 1 1 0 1 0 0 0
0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 0
E8h
02h
E9h
DATA
GM3
B) SINGLE-BYTE READ
MASTER
NACK
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
START 1 1 1 0 1 0 0 0
-READ GM3
0 0 0 0 0 0 1 0
1 1 1 0 1 0 0 1
STOP
E8h
00h
80h
80h
C) TWO-BYTE WRITE
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START 1 1 1 0 1 0 0 0
- WRITE GM1 AND GM2 TO 80h
0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
STOP
DATA
GM1
DATA
GM2
E8h
00h
E9h
1 1 1 0 1 0 0 1
SLAVE
ACK
MASTER
ACK
MASTER
NACK
D) TWO-BYTE READ
SLAVE
ACK
SLAVE
ACK
REPEATED
START
START 1 1 1 0 1 0 0 0
- READ GM1 AND GM2
0 0 0 0 0 0 0 0
STOP
2
Figure 5. I C Communication Examples
byte before terminating the transaction. After the master
reads the last byte it must NACK to indicate the end of
the transfer and generates a STOP condition.
components minimize lead inductance, which improves
performance, and ceramic capacitors tend to have
adequate high-frequency response for decoupling
applications.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
desires to read, generates a repeated START condi-
tion, writes the slave address byte (R/W = 1), reads
data with ACK or NACK as applicable, and generates a
STOP condition. The master must NACK the last byte to
inform the slave that no additional bytes are to be read.
SDA and SCL Pullup Resistors
SDA is an I/O with an open-collector output that
requires a pullup resistor to realize high-logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be used
for SCL. Pullup resistor values should be chosen to
ensure that the rise and fall times listed in the electrical
characteristics are within specification. A typical value
for the pullup resistors is 4.7kΩ.
Applications Information
Package Information
Power-Supply Decoupling
(For the latest package outline information, go to
To achieve the best results when using the DS3508,
www.maxim-ic.com/DallasPackInfo.)
decouple both power-supply pins (V
and V ) with a
DD
CC
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
0.01µF or 0.1µF capacitor. Use a high-quality ceramic
surface-mount capacitor if possible. Surface-mount
20 TSSOP
—
56-G2010-000
______________________________________________________________________________________ 13
2
I C, 8-Channel Gamma Buffer with EEPROM
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
1/08
Initial release.
—
4
In the Nonvolatile Memory Characteristics table, removed T = +25°C 200,000
write cycle specification for EEPROM write cycles.
A
1
3/08
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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