DS3514T+ [MAXIM]
I2C Gamma and VCOM Buffer with EEPROM; I2C Gamma和VCOM缓冲器，带有EEPROM
| 型号： | DS3514T+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | I2C Gamma and VCOM Buffer with EEPROM |
| 文件： | 总21页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 1; 10/08
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
General Description
Features
The DS3514 is a programmable gamma and V
volt-
COM
♦ 10-Bit Gamma Buffers, 14 Channels
♦ 8-Bit V Buffer, 1 Channel
age generator that supports both real-time updating as
well as multibyte storage of gamma/V data in on-
COM
COM
chip EEPROM memory. An independent 10-bit DAC, two
10-bit data registers, and four words of EEPROM memo-
ry are provided for each individually addressable
♦ Four 10-Bit EEPROM Words per Channel
♦ Low-Power 400µA/ch Gamma Buffers
gamma or V
channel. High-performance buffer
2
COM
♦ I C-Compatible Serial Interface
amplifiers are integrated on-chip, providing rail-to-rail,
low-power (400µA/gamma channel) operation. The
2
♦ Flexible Control from I C or Pins
V
channel features a high current drive (> 250mA
COM
♦ 9.0V to 15.0V Analog Supply
♦ 2.7V to 5.5V Digital Supply
peak) and a fast-settling buffer amplifier optimized to
drive the V
node of a wide range of TFT-LCD panels.
2
COM
Programming occurs through an I C-compatible serial
interface. Interface performance and flexibility are
enhanced by a pair of independently loaded data latch-
♦ 48-Pin TQFN Package (7mm x 7mm)
2
es per channel, as well as support for I C speeds up to
Ordering Information
400kHz. The multitable EEPROM memory enables a
rich variety of display system enhancements, including
support for temperature or light-level dependent
gamma tables, enabling of factory or field automated
display adjustment, and support for backlight dimming
algorithms to reduce system power. Upon power-up
and depending on mode, DAC data is selected from
EEPROM by the S0/S1 pins or from a fixed memory
address.
PART
TEMP RANGE
-45°C to +95°C
-45°C to +95°C
PIN-PACKAGE
48 TQFN-EP*
48 TQFN-EP*
DS3514T+
DS3514T+T&R
+Denotes a lead-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
Applications
TFT-LCD Gamma and V
Buffer
COM
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
Adaptive Gamma and V
2
Adjustment (Real
2
COM
Time by I C, Select EEPROM Through I C or
S0/S1 Pins)
Industrial Process Control
Gamma or V
Channel Functional Diagram
COM
SDA, SCL
2
I C
LATCH A
8-/
10-BIT*
DAC
INTERFACE
A0
MUX
LATCH B
V
OUT
IN
OUT
EEPROM
ADDRESS
S1/ S0
LD
LOGIC
* 10 BITS FOR GAMMA CHANNELS, 8 BITS FOR THE V
CHANNEL.
COM
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
I C Gamma and V
Buffer with EEPROM
COM
ABSOLUTE MAXIMUM RATINGS
Voltage Range on V
Relative to GND ................-0.5V to +16V
Junction Temperature......................................................+125°C
Operating Temperature Range ...........................-45°C to +95°C
Programming Temperature Range.........................0°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
DD
Voltage Range on VRL, VRH, GHH, GHM, GLM, GLL
Relative to GND.........-0.5V to (V + 0.5V), not to exceed 16V
DD
Voltage Range on V
Relative to GND ..................-0.5V to +6V
CC
Voltage Range on SDA, SCL, A0, LD, S0,
S1 Relative to GND .....-0.5V to (V + 0.5V), not to exceed 6V
CC
DS3514
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -45°C to +95°C.)
A
PARAMETER
Digital Supply Voltage
Analog Supply Voltage
SYMBOL
CONDITIONS
MIN
2.7
9.0
TYP
MAX
5.5
UNITS
V
CC
V
DD
(Notes 1, 2)
(Note 1)
V
V
15.0
VRH, VRL Voltage
V
Applies to V
output
2.0
V
V
- 2.0
V
V
V
V
VCOM
COM
DD
GND +
0.2
GHH, GHM, GLM, GLL Voltage
V
Applies to GM1–GM14
- 0.2
GM1–14
DD
Input Logic 1
(SCL, SDA, A0, S0, S1, LD)
0.7 x
V
CC
+ 0.3
V
IH
V
CC
Input Logic 0
(SCL, SDA, A0, S0, S1, LD)
V
-0.3
0.3 x V
IL
CC
V
Load Capacitor
C
1
μF
μF
COM
D
VCAP Compensation Capacitor
C
0.1
COMP
INPUT ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -45°C to +95°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
μA
Input Leakage (SDA, SCL, A0,
S0, S1, LD)
I
L
-1
+1
10
V
Supply Current
I
I
(Note 3)
(Note 4)
5
mA
DD
DD
CC
V
CC
Supply Current, Nonvolatile
Read or Write
0.25
0.6
mA
V
V
Standby Supply Current
Standby Supply Current
I
I
(Note 5)
(Note 6)
10
30
μA
μA
CC
CCQ
450
850
DD
DDQ
I/O Capacitance (SDA, SCL, LD,
S0, S1, A0)
C
Guaranteed by design
5
10
pF
I/O
End-to-End Resistance
(VRH to VRL)
R
16
kꢀ
TOTAL
R
Tolerance
T = +25°C°
A
-20
+20
%
TOTAL
2
_______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
INPUT ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.7V to +5.5V, T = -45°C to +95°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Resistance (GHH, GHM,
GLM, GLL)
75
kꢀ
Input Resistance Tolerance
Power-On Recall Voltage
Power-Up Time
T = +25°C
A
-20
1.6
+20
2.6
%
V
V
(Note 7)
(Note 8)
POR
t
D
25
ms
OUTPUT ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, VRL = +2.0V, GLL = +0.2V, GLM = +4.8V, GHM = +10.2V, VRH = +13.0V, GHH = +14.8V, T = -45°C to
A
+95°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
10
TYP
MAX
UNITS
Bits
GM1–GM14 DAC Resolution
V
V
V
DAC Resolution
8
Bits
COM
COM
Integral Nonlinearity Error
Differential Nonlinearity
INL
T = +25°C (Note 9)
-0.5
+0.5
+0.5
LSB
A
COM
DNL
T = +25°C (Note 10)
A
-0.5
-1.0
LSB
LSB
LSB
Error
GM1–GM14 Integral
Nonlinearity Error
INL
T = +25°C (Note 9)
A
+1.0
GM1–GM14 Differential
Nonlinearity Error
DNL
T = +25°C (Note 10)
A
-0.35
+0.35
Output Voltage Range (V
)
2.0
0.2
-20
V
V
- 2.0
V
COM
DD
Output Voltage Range (GM1–G14)
Output Accuracy
- 0.2
V
DD
V
COM
T = +25°C
+20
mV
mV
mV
V/V
A
GM1–GM14 Offset
GM outputs = V /2, T = +25°C
37
DD
A
GM1–GM14 Output Accuracy
Voltage Gain (GM1–GM14)
GM outputs = V /2, T = +25°C
-35
+35
DD
A
0.995
Load Regulation
1.0
mV/mA
(V
COM
, GM1–GM14)
Short-Circuit Current (V
)
To V or GND
DD
250
mA
ns
COM
S0/S1 to LD Setup Time
S0/S1 to LD Hold Time
t
t
Figure 2
Figure 2
37.5
37.5
SU
ns
HD
V
Settling Time from LD Low
Settling to 0.1% of final V
(Figure 1) (Note 11)
level
COM
COM
t
2.0
μs
μs
ns
SET-V
to High (S0/S1 Meet t
)
SU
GM1–GM14 Settling Time from
LD Low to High
4t
AU
settled with I =
LOAD
20mA
t
5.0
SET-G
(Figure 2) (Notes 11, 12, 13)
S0, S1 to GM1–GM14 Output
10% Settled
10% settling (Figure 3), LD = V
(asynchronous) (Notes 11, 13)
CC
t
600
SEL
_______________________________________________________________________________________
3
2
I C Gamma and V
Buffer with EEPROM
COM
2
I C ELECTRICAL CHARACTERISTICS
(V
= +2.7V to +5.5V, T = -45°C to +95°C, timing referenced to V
and V . See Figure 4.)
IH(MIN)
CC
A
IL(MAX)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 14)
0
400
kHz
SCL
Bus-Free Time between STOP
and START Conditions
t
1.3
0.6
μs
μs
BUF
DS3514
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
0
μs
μs
μs
ns
μs
LOW
t
HIGH
t
t
t
0.9
HD:DAT
SU:DAT
SU:STA
Data Setup Time
START Setup Time
100
0.6
20 +
SDA and SCL Rise Time
t
(Note 15)
(Note 15)
300
300
ns
R
0.1C
B
20 +
SDA and SCL Fall Time
STOP Setup Time
t
ns
μs
F
0.1C
B
t
0.6
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 15)
(Note 16)
(Note 17)
400
20
pF
ms
ns
B
W
EEPROM Write Time
t
Pulse-Width Suppression Time
at SDA and SCL Inputs
t
50
IN
A0 Setup Time
A0 Hold Time
t
t
Before START
After STOP
0.6
0.6
μs
μs
SU:A
HD:A
SDA and SCL Input Buffer
Hysteresis
0.05 x
V
V
CC
Input Capacitance on
A0, SDA, or SCL
C
5
10
0.4
900
pF
V
I
Low-Level Output Voltage (SDA)
V
4mA sink current
SCL falling through 0.3 x V to SDA exit
OL
AA
SCL Falling Edge to SDA Output
Data Valid
CC
t
t
ns
0.3 x V to 0.7 x V window
CC
CC
SCL falling through 0.3x V until SDA in
CC
Output Data Hold
0
ns
DH
0.3 x V to 0.7 x V window
CC
CC
4
_______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
NONVOLATILE MEMORY CHARACTERISTICS
(V
= +2.7V to +5.5V.)
CC
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
T
T
= +85°C (Guaranteed by design)
= +25°C (Guaranteed by design)
50,000
200,000
A
EEPROM Write Cycles
Writes
A
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are
negative.
Note 2: If V
2
is less than +2.7V or is left unconnected, the DS3514 pulls the I C bus to V , preventing communication with other
CC
CC
2
devices on the I C bus.
Note 3:
Note 4:
Note 5:
Note 6:
I
I
I
I
supply current is specified with V
is specified with the following conditions: SCL = 400kHz, SDA = V
= 15.0V and no load on V
or GM1–GM14 outputs.
DD
CC
DD
COM
= 5.5V, and V
and GM1–GM14 floating.
CC
COM
is specified with the following conditions: SCL = SDA = V
is specified with the following conditions: SCL = SDA = V
= 5.5V, and V
and GM1–GM14 floating.
COM
and GM1–GM14 floating.
COM
CCQ
DDQ
CC
= 5.5V and V
CC
Note 7: This is the minimum V
voltage that causes EEPROM to be recalled.
CC
Note 8: This is the time from V
> V
and V
> V
until the device is powered up.
CC
POR
DD
DD(MIN)
Note 9: Integral nonlinearity is the deviation of a measured value from the expected values at each particular setting. Expected
value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting.
INL = [V(RW) - (V(RW) ]/LSB(measured) - i, for i = 0...N (N = 255 for V , 1023 for GM1–GM14).
i
0
COM
Note 10: Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size. The
expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position.
DNL = [V(RW)
- (V(RW) ]/LSB(measured) - 1, for i = 0...(N - 1) (N = 255 for V
, 1023 for GM1–GM14).
COM
i+1
i
Note 11: Specified with the V
and gamma bias currents set to 100% (CR.5 = 1, CR.4 = 0).
COM
Note 12: EEPROM data is assumed already settled at input of Latch B. LD transitions after EEPROM byte has been selected.
Note 13: Rising transition from 5V to 10V; falling transition from 10V to 5V.
2
2
Note 14: I C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I C
standard-mode timing.
Note 15: C —total capacitance of one bus line in picofarads.
B
Note 16: EEPROM write time begins after a STOP condition occurs.
Note 17: Pulses narrower than max are suppressed.
VRH
V
DD
DS3514
V
COM
8-BIT
DAC
80h
0.1μF
2.2Ω
= 1μF
V
COM
C
D
0 TO 1.5V
50kHz
VRL
Figure 1. V
Settling Timing Diagram
COM
_______________________________________________________________________________________
5
2
I C Gamma and V
Buffer with EEPROM
COM
V
V
IH
S0/S1
IL
t
t
SU
HD
t
SET-G
GM1–GM14
DS3514
V
IH
100pF
LD
I
LOAD
V
IL
4t SETTLED
AU
GM1–G14
Figure 2. GM1–GM14 Settling Timing Diagram
V
V
IH
S0/S1
(LD = V
)
CC
IL
GM1–GM14
t
SEL
100pF
OUTPUT 10% SETTLED
GM1–GM14
Figure 3. Input Pin to Output Change Timing Diagram
SDA
t
BUF
t
t
F
SP
t
HD:STA
t
LOW
SCL
t
HIGH
t
SU:STA
t
t
R
t
HD:STA
SU:STO
t
t
SU:DAT
HD:DAT
STOP
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 4. I C Timing Diagram
6
_______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
Typical Operating Characteristics
(V
CC
= +5.0V, V = +15V, T = +25°C, unless otherwise noted.)
DD A
DIGITAL SUPPLY STANDBY CURRENT
ANALOG SUPPLY STANDBY CURRENT
DIGITAL SUPPLY STANDBY CURRENT
vs. TEMPERATURE
vs. V
vs. V
CC
DD
30
450
400
350
300
250
200
150
100
50
30
25
20
15
10
5
SDA = SCL = V
CC
SDA = SCL = V
CC
25
20
15
10
5
V
CC
= 5.0V
V
= 3.3V
35
CC
0
0
0
2
3
4
5
6
9
11
V
13
VOLTAGE (V)
15
-45 -25
-5
15
55
75
95
V
VOLTAGE (V)
TEMPERATURE (°C)
CC
DD
ANALOG SUPPLY CURRENT
ANALOG SUPPLY STANDBY CURRENT
vs. TEMPERATURE
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
vs. V
DD
10
9
8
7
6
5
4
3
2
1
0
450
400
350
300
250
200
150
100
50
10
9
8
7
6
5
4
3
2
1
0
BIAS = 150%
BIAS = 100%
BIAS = 150%
BIAS = 100%
BIAS = 80%
BIAS = 60%
BIAS = 80%
BIAS = 60%
0
9
11
V
13
VOLTAGE (V)
15
-45 -25
-5
15
35
55
75
95
-45 -25
-5
15
35
55
75
95
TEMPERATURE (°C)
TEMPERATURE (°C)
DD
GAMMA SETTLING
GAMMA OUTPUT vs. SETTING
GM DNL
10
9
15
12
9
0.25
0.20
0.15
0.10
0.05
0
V
= 15.0V, GHH = 14.8V,
DD
BIAS = 150%
GHM = 10.2V, GLM = 4.8V,
GLL = 0.2V
8
BIAS = 80%
BIAS = 100%
GM8 TO GM14
7
6
-0.05
-0.10
-0.15
-0.20
-0.25
BIAS = 60%
GM1 TO GM7
6
3
5
4
0
-1
0
1
2
3
4
5
0
128 256 384 512 640 768 896 1024
GAMMA SETTING (DEC)
0
128 256 384 512 640 768 896 1024
GAMMA SETTING (DEC)
TIME (μs)
_______________________________________________________________________________________
7
2
I C Gamma and V
Buffer with EEPROM
COM
Typical Operating Characteristics (continued)
(V
CC
= +5.0V, V = +15V, T = +25°C, unless otherwise noted.)
DD A
V
COM
DNL
V
COM
INL
GM INL
0.50
0.40
0.30
0.20
0.10
0
0.50
0.40
0.30
0.20
0.10
0
0.50
DS3514
0.25
0
-0.10
-0.20
-0.30
-0.40
-0.50
-0.10
-0.20
-0.30
-0.40
-0.50
-0.25
-0.50
0
32 64 96 128 160 192 224 256
SETTING (DEC)
0
32 64 96 128 160 192 224 256
SETTING (DEC)
0
128 256 384 512 640 768 896 1024
GAMMA SETTING (DEC)
V
V
COM
COM
V
PHASE MARGIN
V
COM
UNITY GAIN BANDWIDTH
vs. LOAD CAPACITANCE
COM
vs. LOAD CAPACITANCE
180
150
120
90
500
400
300
200
100
0
60
30
0
100.0E-9
1.0E-6
10.0E-6
100.0E-9
1.0E-6
10.0E-6
LOAD CAPACITANCE (F)
LOAD CAPACITANCE (F)
8
_______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
Pin Description
PIN
NAME
TYPE
FUNCTION
1–5, 9, 10,
46, 48
N.C.
—
No Connection
Analog Supply (9.0V to 15.5V)
6, 23, 43
V
DD
Power
7
8
VRH
VRL
Ref Input
Ref Input
High-Voltage Reference for V
DAC
DAC
COM
COM
Low-Voltage Reference for V
11, 18, 19,
21, 22, 42
GND
Power
Ground
12
13
S1
S0
Input
Input
Select Inputs. When the Control register [1,0] = 00, S0 and S1 are used to select
DAC input data from EEPROM.
Latch Data Input. When LD is low, Latch B retains existing data (acts as a latch).
When LD is high, the input to Latch B data flows through to the output and updates
the DACs asynchronously.
14
LD
Input
2
15
16
SDA
SCL
Input/Output I C Serial Data Input/Output
2
Input
Power
I C Serial Clock Input
17, 47
20
V
CC
Digital Supply (2.7V to 5.5V)
VCAP
GM1–GM7
GM8–GM14
GLM
Input
Compensation Capacitor Input. Connect VCAP to GND through a 0.1μF capacitor.
Low-Voltage Gamma Analog Outputs
24–30
31–37
38
Output
Output
Ref Input
Ref Input
Ref Input
Ref Input
Output
Input
High-Voltage Gamma Analog Outputs
Reference for Low-Voltage Gamma DAC
Reference for Low-Voltage Gamma DAC
Reference for High-Voltage Gamma DAC
Reference for High-Voltage Gamma DAC
39
GLL
40
GHM
41
GHH
44
V
COM
V
COM
Analog Output. This output requires a 1μF capacitor to GND.
2
45
A0
Address Input. This pin determines the DS3514’s I C slave address.
Ground. Exposed Pad. Connect to GND.
EP
GND
—
_______________________________________________________________________________________
9
2
I C Gamma and V
Buffer with EEPROM
COM
Block Diagram
GHH
GHH
BANKS
GHH
GM14 BANK A
GM14 BANK B
GM14 BANK C
GM14 BANK D
DS3514
MUX
0
1
10 BITS
10-BIT
DAC
LATCH B
LD
DS3514
0
1
S0/S1 PINS
S0/S1 BITS
GM14
LATCH A
GHM
GHH
2
I C
COMP
MODE0 BIT
MODE1 BIT
BANKS
GM8 BANK A
GM8 BANK B
GM8 BANK C
GM8 BANK D
MUX
MUX
MUX
0
10 BITS
10-BIT
DAC
LATCH B
LD
0
1
1
S0/S1 PINS
S0/S1 BITS
GM8
LATCH A
LATCH A
LATCH A
GHM
2
I C
SDA
SCL
A0
2
COMP
MODE0 BIT
MODE1 BIT
I C
2
I C
INTERFACE
GHM
GHM
VRH
BANKS
VCOM BANK A
VCOM BANK B
VCOM BANK C
VCOM BANK D
MODE0 BIT (CR.0)
MODE1 BIT (CR.1)
S0/S1 PINS
0
8 BITS
8-BIT
DAC
S0
S1
LD
LOGIC
AND
CONTROL
LATCH B
LD
0
1
1
S0/S1 PINS
S0/S1 BITS
V
COM
S0/S1 BITS (SOFT S0/S1)
LD
2
VRL
I C
COMP
MODE0 BIT
MODE1 BIT
GLM
GLM
VCAP
COMPENSATION
COMP
BANKS
GLM
GM7 BANK A
GM7 BANK B
GM7 BANK C
GM7 BANK D
0
10 BITS
10-BIT
DAC
LATCH B
LD
0
1
1
S0/S1 PINS
S0/S1 BITS
GM7
GLL
V
DD
CC
2
I C
V
V
DD
CC
COMP
MODE0 BIT
MODE1 BIT
V
BANKS
GLM
GM1 BANK A
GM1 BANK B
GM1 BANK C
GM1 BANK D
GND
MUX
0
10 BITS
10-BIT
DAC
LATCH B
LD
0
1
1
S0/S1 PINS
S0/S1 BITS
GM1
GLL
LATCH A
GLL
2
I C
COMP
MODE0 BIT
MODE1 BIT
GLL
10 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
the state of S0/S1 to meet the t
specification.
SEL
Detailed Description
Conversely, when LD is low, Latch B functions as a
latch, holding its previous data. A low-to-high transition
on LD allows the Latch B input data to flow through and
update the DACs with the EEPROM bank selected by
S0/S1. A high-to-low transition on LD latches the select-
ed DAC data into Latch B.
The DS3514 operates in one of three modes that deter-
mine how the V
and gamma DACs are
COM
controlled/updated. The first two modes allow “banked”
control of the 14 gamma channels and one V chan-
COM
nel. Depending on the mode, one of four banks (in
EEPROM) can be selected using either the S0/S1 pins
or using the SOFT S0/S1 bits in the Soft S0/S1 register.
Once a bank is selected, the LD pin can then be used
to simultaneously update each channel’s DAC output.
SOFT S0/S1 Bit-Controlled Bank-Updating
Mode
This mode also features banked operation with the only
difference being how the desired bank is selected. In
particular, the bank is selected using the SOFT S0 (bit
0) and SOFT S1 (bit 1) bits contained in the Soft S0/S1
register (40h). The S0 and S1 pins are ignored in this
mode. Table 2 illustrates the relationship between the
bit settings and the selected bank. For example, if
SOFT S0 and SOFT S1 are written to zero, the first bank
(Bank A) is selected. Once a bank is selected, the tim-
ing of the DAC update depends on the state of the LD
pin. When LD is high, Latch B functions as a flow-
through latch, so the amplifier responds asynchronous-
ly to changes in the state of the SOFT S0/S1 bits. These
2
The third and final mode is not banked. It allows I C
control of each channel’s Latch A register that is SRAM
(volatile), allowing quick and unlimited updates. In this
mode, the LD pin can also be used to simultaneously
update each channel’s DAC output. A detailed descrip-
tion of the three modes as well as additional features of
the DS3514 follows.
Mode Selection
The DS3514 mode of operation is determined by two
bits located in Control register (CR, register 48h), which
is nonvolatile (NV) (EEPROM). In particular, the mode is
determined by the MODE0 bit (CR.0) and the MODE1
bit (CR.1). Table 1 illustrates how the two control bits
are used to select the operating mode. When shipped
from the factory, the DS3514 is programmed with both
MODE bits set to zero.
2
are changed by an I C write. Conversely, when LD is
low, Latch B functions as a latch, holding its previous
data. A low-to-high transition on LD allows the Latch B
input data to flow through and update the DACs with
the EEPROM bank selected by the SOFT S0/S1 bits. A
high-to-low transition on LD latches the selected DAC
data into Latch B.
S0/S1 Pin-Controlled Bank-Updating Mode
As shown in the Block Diagram, each channel contains
four words of EEPROM that are used to implement the
“banking” functionality. Each bank contains unique
DAC settings for each channel. When the DS3514 is
configured in this operating mode, the desired bank is
selected using the S0 and S1 pins as shown in Table 2
Because the Soft S0/S1 register is SRAM, subsequent
power ups result in the SOFT S0 and SOFT S1 bits
being cleared to 0 and, hence, powering up to Bank A.
2
I C Individual Channel-Control Mode
2
In this mode the I C master writes directly to individual
where 0 is ground and 1 is V . For example, if S0 and
CC
channel Latch A registers to update a single DAC (i.e.,
not banked). The Latch A registers are SRAM and not
EEPROM. This allows an unlimited number of write
cycles as well as quicker write times since t only
W
applies to EEPROM writes. As shown in the Memory
S1 are both connected to ground, the first bank (Bank
A) is selected. Once a bank is selected, the timing of
the DAC update depends on the state of LD pin. When
LD is high, Latch B functions as a flow-through latch, so
the amplifier responds asynchronously to changes in
Table 1. Operating Modes
Table 2. Bank Selection Table
BIT OR PIN
MODE1 BIT
(CR.1)
MODE0 BIT
(CR.0)
V
GAMMA
CHANNELS
COM
MODE
CHANNEL
S1
0
S0
0
V
V
V
V
Bank A
Bank B
Bank C
Bank D
GM1–GM14 Bank A
GM1–GM14 Bank B
GM1–GM14 Bank C
GM1–GM14 Bank D
S0/S1 Pin-Controlled Bank
Updating (Factory Default)
COM
COM
COM
COM
0
0
1
0
1
X
0
1
1
0
S0/S1 Bit-Controlled Bank
Updating
1
1
2
I C Individual Channel
Control
______________________________________________________________________________________ 11
2
I C Gamma and V
Buffer with EEPROM
COM
Map, the Latch A registers for each channel are
accessed through memory addresses 00–1Ch. Then,
like the other modes, the LD pin determines when the
DACs are updated. If the LD signal is high, Latch B is
flow-through and the DAC is updated immediately. If
LD is low, Latch B is loaded from Latch A after a low-to-
high transition on the LD pin. This latter method allows
the timing of the DAC update to be controlled by an
external signal pulse.
buffered output. The V
channel’s digital poten-
COM
tiometer is composed of 255 equal resistive elements.
The relationship between output voltage and DAC set-
ting is illustrated in Table 3a. Unlike the gamma chan-
nels, the V
channel is capable of outputting a
COM
range of voltages including both references (VRH and
VRL). Each of the gamma channel digital potentiome-
ters, on the other hand, are composed of 1024 equal
resistive elements. The extra resistive element prohibits
one of the rails from being reached. In particular,
gamma channel outputs GM1–GM7 can span from
(and including) GLL to 1 LSB away from GLM.
Likewise, gamma channel outputs GM8–GM14 span
from (and including) GHM to 1 LSB away from GHH.
The relationship between output voltage and DAC set-
ting for the gamma channels are also illustrated in
Table 3b.
DS3514
V
/Gamma Channel Outputs
COM
As illustrated in the Block Diagram, the gamma channel
outputs are equivalent to a 10-bit digital potentiometer
(DAC) with a buffered output. The V
equivalent to an 8-bit digital potentiometer (DAC) with a
channel is
COM
Table 3a. V
DAC Voltage/Data
COM
Relationship for Selected Codes
Standby Mode
Standby mode (not to be confused with the three
DS3514 operating modes) can be used to minimize
current consumption. Standby mode is entered by set-
ting the STANDBY bit, which is the MSB of register 41h.
SETTING
(HEX)
V
OUTPUT VOLTAGE
COM
00h
01h
02h
03h
0Fh
3Fh
7Fh
FDh
FEh
FFh
VRL
VRL + (1/255) x (VRH - VRL)
VRL + (2/255) x (VRH - VRL)
VRL + (3/255) x (VRH - VRL)
VRL + (15/255) x (VRH - VRL)
VRL + (63/255) x (VRH - VRL)
VRL + (127/255) x (VRH - VRL)
VRL + (253/255) x (VRH - VRL)
VRL + (254/255) x (VRH - VRL)
VRH
The V
and gamma outputs are placed in a high-
COM
impedance state. Current drawn from the V
supply in
DD
this state is specified as I
.
DDQ
2
The DS3514 continues to respond to I C commands,
2
and thus draws some current from V
2
when I C activi-
CC
ty is occurring. When the I C interface is inactive, cur-
rent drawn from the V
supply is specified as I
.
CC
CCQ
Thermal Shutdown
As a safety feature, the DS3514 goes into a thermal
shutdown state if the junction temperature ever reaches
Table 3b. Gamma DAC Voltage/Data Relationship for Selected Codes
SETTING
(HEX)
GM1–GM7 OUTPUT VOLTAGE
GM8–GM14 OUTPUT VOLTAGE
000h
001h
002h
003h
00Fh
03Fh
07Fh
0FFh
3FDh
3FEh
3FFh
GLM + (0 + 1) x ((GLL - GLM)/1024)
GLM + (1 + 1) x ((GLL - GLM)/1024)
GLM + (2 + 1) x ((GLL - GLM)/1024)
GLM + (3 + 1) x ((GLL - GLM)/1024)
GLM + (15 + 1) x ((GLL - GLM)/1024)
GLM + (63 + 1) x ((GLL - GLM)/1024)
GLM + (127 + 1) x ((GLL - GLM)/1024)
GLM + (255 + 1) x ((GLL - GLM)/1024)
GLM + (1021 + 1) x ((GLL - GLM)/1024)
GLM + (1022 + 1) x ((GLL - GLM)/1024)
GLL
GHM + (0 + 1) x ((GHH - GHM)/1024)
GHM + (1 + 1) x ((GHH - GHM)/1024)
GHM + (2 + 1) x ((GHH - GHM)/1024)
GHM + (3 + 1) x ((GHH - GHM)/1024)
GHM + (15 + 1) x ((GHH - GHM)/1024)
GHM + (63 + 1) x ((GHH - GHM)/1024)
GHM + (127 + 1) x ((GHH - GHM)/1024)
GHM + (255 + 1) x ((GHH - GHM)/1024)
GHM + (1021 + 1) x ((GHH - GHM)/1024)
GHM + (1022 + 1) x ((GHH - GHM)/1024)
GHH
12 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
or exceeds +150°C. In this state, the V
buffer is
COM
disabled (output goes high impedance) until the junc-
tion temperature falls below +150°C.
LSB
R/W
MSB
1
Slave Address Byte and Address Pin
The slave address byte consists of a 7-bit slave
address plus a R/W bit (see Figure 5). The DS3514’s
slave address is determined by the state of the A0 pin.
This pin allows up to two devices to reside on the same
1
0
0
0
A0
0
SLAVE ADDRESS*
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
2
I C bus. Connecting A0 to GND results in a 0 in the
corresponding bit position in the slave address.
Conversely, connecting A0 to V
results in a 1 in the
CC
corresponding bit position. For example, the DS3514’s
2
slave address byte is C0h when A0 is grounded. I C
Figure 5. DS3514 Slave Address Byte
2
communication is described in detail in the I C Serial
Interface Description section.
as well as the power-up default values for volatile loca-
tions and factory-programmed defaults for the non-
volatile locations. Additional information regarding
Memory Organization
Memory Description
The list of registers/memory contained in the DS3514 is
shown in the Memory Map section. Also shown for
each of the registers is the memory type, accessibility,
2
reading and writing the memory is located in the I C
Serial Interface Description section.
Memory Map
TYPE
MEMORY
OR COMMAND
ADDRESS
NAME
2
I C
DESCRIPTION
ACCESS
(HEX)
(DEC)
2
Latch A for V
Ch
0h
0
8-Bit I C Data for V
DAC
COM
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
COM
2
Latch A for GM1 Ch
Latch A for GM2 Ch
Latch A for GM3 Ch
Latch A for GM4 Ch
Latch A for GM5 Ch
Latch A for GM6 Ch
Latch A for GM7 Ch
Latch A for GM8 Ch
Latch A for GM9 Ch
Latch A for GM10 Ch
Latch A for GM11 Ch
Latch A for GM12 Ch
2h, 3h
2, 3
10-Bit I C Data for GM1 DAC
2
4h, 5h
4, 5
10-Bit I C Data for GM2 DAC
2
6h, 7h
6, 7
10-Bit I C Data for GM3 DAC
2
8h, 9h
8, 9
10-Bit I C Data for GM4 DAC
2
Ah, Bh
Ch, Dh
Eh, Fh
10, 11
12, 13
14, 15
16, 17
18, 19
20, 21
22, 23
24, 25
10-Bit I C Data for GM5 DAC
2
10-Bit I C Data for GM6 DAC
2
10-Bit I C Data for GM7 DAC
2
10h, 11h
12h, 13h
14h, 15h
16h, 17h
18h, 19h
10-Bit I C Data for GM8 DAC
2
10-Bit I C Data for GM9 DAC
2
10-Bit I C Data for GM10 DAC
2
10-Bit I C Data for GM11 DAC
2
10-Bit I C Data for GM12 DAC
______________________________________________________________________________________ 13
2
I C Gamma and V
Buffer with EEPROM
COM
Memory Map (continued)
TYPE
MEMORY
OR COMMAND
ADDRESS
NAME
2
I C
DESCRIPTION
ACCESS
(HEX)
(DEC)
2
Latch A for GM13 Ch
Latch A for GM14 Ch
Reserved
1Ah, 1Bh
1Ch, 1Dh
1Eh–3Fh
40h
26, 27
28, 29
30–63
64
10-Bit I C Data for GM13 DAC
Volatile
Volatile
—
R/W
R/W
—
2
10-Bit I C Data for GM14 DAC
DS3514
—
Soft S1/S0
Software Bank Select Byte (Bits 1:0)
Volatile
Volatile
—
R/W
R/W
—
Standby
41h
65
Shutdown Byte
Reserved
42h–47h
48h
66–71
72
—
Control
Control Register (see Table 1)
NV
R/W
—
Reserved
49h
73
—
—
Status Bits
Reserved
4Ah
74
Status Bits
—
Status
—
R
4Bh–4Fh
75–79
—
50h, 52h, 80, 82, 84,
VCOM1–VCOM4
V
COM
EEPROM Data (Four 8-Bit Words)
NV
R/W
54h, 56h
86
GM1 GDAT1–GDAT4
GM2 GDAT1–GDAT4
GM3 GDAT1–GDAT4
GM4 GDAT1–GDAT4
GM5 GDAT1–GDAT4
GM6 GDAT1–GDAT4
GM7 GDAT1–GDAT4
GM8 GDAT1–GDAT4
GM9 GDAT1–GDAT4
GM10 GDAT1–GDAT4
GM11 GDAT1–GDAT4
GM12 GDAT1–GDAT4
GM13 GDAT1–GDAT4
GM14 GDAT1–GDAT4
Reserved
58h–5Fh
60h–67h
68h–6Fh
70h–77h
78h–7Fh
80h–87h
88h–8Fh
90h–97h
98h–9Fh
A0h–A7h
A8h–AFh
B0h–B7h
B8h–BFh
C0h–C7h
C8h–FFh
88–95
GM1 EEPROM Data (Four 10-Bit Words)
GM2 EEPROM Data (Four 10-Bit Words)
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
96–103
104–111 GM3 EEPROM Data (Four 10-Bit Words)
112–119 GM4 EEPROM Data (Four 10-Bit Words)
120–127 GM5 EEPROM Data (Four 10-Bit Words)
128–135 GM6 EEPROM Data (Four 10-Bit Words)
136–143 GM7 EEPROM Data (Four 10-Bit Words)
144–151 GM8 EEPROM Data (Four 10-Bit Words)
152–159 GM9 EEPROM Data (Four 10-Bit Words)
160–167 GM10 EEPROM Data (Four 10-Bit Words)
168–175 GM11 EEPROM Data (Four 10-Bit Words)
176–183 GM12 EEPROM Data (Four 10-Bit Words)
184–191 GM13 EEPROM Data (Four 10-Bit Words)
192–198 GM14 EEPROM Data (Four 10-Bit Words)
200–255
—
14 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
Detailed Register Descriptions
Soft S0/S1 Register 40h: SOFT S1/S0 Bits
FACTORY DEFAULT
MEMORY TYPE
00h
Volatile
40h
x
x
x
x
x
x
SOFT S1
SOFT S0
BIT 0
BIT 7
Bits 7:2
Bits 1:0
Reserved
These bits are used when in SOFT S0/S1 Bit-Controlled Bank-Updating mode (MODE1 = 0, MODE0 = 1)
SOFT S1, SOFT S0:
00 = Selects V
01 = Selects V
10 = Selects V
and GM1–GM14 Bank A
and GM1–GM14 Bank B
and GM1–GM14 Bank C
COM
COM
COM
11 = Selects V
and GM1–GM14 Bank D
COM
Standby Register 41h: Standby Mode Enable
FACTORY DEFAULT
MEMORY TYPE
00h
Volatile
41h STANDBY
x
x
x
x
x
x
x
BIT 7
BIT 0
STANDBY:
Bit 7
0 = Standby mode disabled
1 = Standby mode enabled
Bits 6:1
Reserved
______________________________________________________________________________________ 15
2
I C Gamma and V
Buffer with EEPROM
COM
Control Register 48h: Control Register (CR)
FACTORY DEFAULT
MEMORY TYPE
20h
NV
48h
x
x
BIAS1
BIAS0
x
x
MODE1
MODE0
BIT 0
BIT 7
DS3514
Bits 7:6
Bits 5:4
Reserved
and Gamma Bias Current Control Bits (BIAS[1:0]):
00 = 60%
01 = 80%
V
COM
10 = 100% (default)
11 = 150%
Bits 3:2
Bits 1:0
Reserved
DS3514 Mode (MODE[1:0]):
00 = S0/S1 pins are used to select the desired bank (A–D) (default).
01 = SOFT S0/S1 (bits) are used to select the desired bank (A–D).
1X = Latch A is used to control the DACs.
Status Bits Register 4Ah: Real-Time Indicator of Logic State on LD, S1, and S0 Pins
FACTORY DEFAULT
MEMORY TYPE
—
Read Only
4Ah
LD
x
x
x
x
x
S1
S0
BIT 7
BIT 0
GDATx Register: EEPROM Data for the Gamma Channels
This is an example of how the bits are arranged for a typical GDATx memory location. GDATx has 10 bits that are
arranged in two consecutive bytes. The following example shows the arrangement for GM1 GDAT1 (58h–59h). This
arrangement is applicable for all the EEPROM data for all gamma channels.
FACTORY DEFAULT
MEMORY TYPE
8000h
NV
58h
59h
GDAT[9]
GDAT[8]
GDAT[0]
GDAT[7]
x
GDAT[6]
x
GDAT[5]
x
GDAT[4]
x
GDAT[3]
x
GDAT[2]
x
GDAT[1]
BIT 7
BIT 0
16 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
2
during a write operation) performs an ACK by trans-
mitting a 0 during the 9th bit. A device performs a
NACK by transmitting a 1 during the 9th bit. Timing
for the ACK and NACK is identical to all other bit
writes. An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or indicates that the
device is not receiving data.
I C Serial Interface Description
2
I C Definitions
The following terminology is commonly used to
describe I C data transfers. (See Figure 4 and the I C
Electrical Characteristics for additional information.)
2
2
Master device: The master device controls the
slave devices on the bus. The master device gener-
ates SCL clock pulses and START and STOP condi-
tions.
Byte write: A byte write consists of 8 bits of informa-
tion transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgment
from the slave to the master. The 8 bits transmitted
by the master are done according to the bit-write
definition and the acknowledgment is read using the
bit-read definition.
Slave devices: Slave devices send and receive
data at the master’s request.
Bus idle or not busy: Time between STOP and
START conditions when both SDA and SCL are inac-
tive and in their logic-high states.
Byte read: A byte read is an 8-bit information trans-
fer from the slave to the master plus a 1-bit ACK or
NACK from the master to the slave. The 8 bits of
information that are transferred (most significant bit
first) from the slave to the master are read by the
master using the bit read definition, and the master
transmits an ACK using the bit write definition to
receive additional data bytes. The master must
NACK the last byte read to terminate communication
so the slave will return control of SDA to the master.
START condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL
remains high generates a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data
transfer to indicate that it will immediately initiate a
new data transfer following the current one.
Repeated STARTs are commonly used during read
operations to identify a specific memory address to
begin a data transfer. A repeated START condition
is issued identically to a normal START condition.
2
Slave address byte: Each slave on the I C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit.
The DS3514’s slave address is determined by the
state of the A0 address pin as shown in Figure 5. An
address pin connected to GND results in a 0 in the
corresponding bit position in the slave address.
Bit write: Transitions of SDA must occur during the
low state of SCL. The data on SDA must remain valid
and unchanged during the entire high pulse of SCL
plus the setup and hold time requirements. Data is
shifted into the device during the rising edge of the
SCL.
Conversely, an address pin connected to V
results in a 1 in the corresponding bit position.
CC
When the R/W bit is 0 (such as in C0h), the master is
indicating it will write data to the slave. If R/W is set
to a 1 (C1h in this case), the master is indicating that
it wants to read from the slave.
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time before the next rising edge of SCL dur-
ing a bit read. The device shifts out each bit of data
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the cur-
rent SCL pulse. Remember that the master gener-
ates all SCL clock pulses, including when it is
reading bits from the slave.
If an incorrect (nonmatching) slave address is writ-
ten, the DS3514 assumes the master is communicat-
2
ing with another I C device and ignores the
communication until the next START condition is
sent.
2
Memory address: During an I C write operation to
the DS3514, the master must transmit a memory
address to identify the memory location where the
slave is to store the data. The memory address is
always the second byte transmitted during a write
operation following the slave address byte.
Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th
bit transmitted during a byte transfer. The device
receiving data (the master during a read or the slave
______________________________________________________________________________________ 17
2
I C Gamma and V
Buffer with EEPROM
COM
2
this phenomenon by repeatedly addressing the
DS3514, which allows communication to continue as
soon as the DS3514 is ready. The alternative to
acknowledge polling is to wait for a maximum period of
I C Communication
Writing a single byte to a slave: The master must gen-
erate a START condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a STOP condition. Remember the
master must read the slave’s acknowledgment during
all byte-write operations.
t
to elapse before attempting to access the device.
W
EEPROM write cycles: The DS3514’s EEPROM write
cycles are specified in the Nonvolatile Memory
Characteristics table. The specification shown is at
the worst-case temperature (hot) as well as at room
temperature.
DS3514
When writing to the DS3514 (and if LD = 1), the DAC
adjusts to the new setting once it has acknowledged the
new data that is being written, and the EEPROM (used to
make the setting nonvolatile) is written following the
STOP condition at the end of the write command.
Reading a single byte from a slave: Unlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
slave address byte with R/W = 1, reads the data byte
with a NACK to indicate the end of the transfer, and
generates a STOP condition. However, because
requiring the master to keep track of the memory
address counter is impractical, the following method
should be used to perform reads from a specified
memory location.
Writing multiple bytes to a slave: To write multiple
bytes to a slave in one transaction, the master gener-
ates a START condition, writes the slave address byte
(R/W = 0), writes the memory address, writes up to 8
data bytes, and generates a STOP condition. The
DS3514 can write 1 to 8 bytes (one page or row) in a
single write transaction. This is internally controlled by
an address counter that allows data to be written to
consecutive addresses without transmitting a memory
address before each data byte is sent. The address
counter limits the write to one 8-byte page (one row of
the memory map). The first page begins at address
00h and subsequent pages begin at multiples of 8
(08h, 10h, 18h, etc). Attempts to write to additional
pages of memory without sending a STOP condition
between pages results in the address counter wrap-
ping around to the beginning of the present row. To
prevent address wrapping from occurring, the master
must send a STOP condition at the end of the page,
then wait for the bus-free or EEPROM write time to
elapse. Then the master can generate a new START
condition and write the slave address byte (R/W = 0)
and the first memory address of the next memory row
before continuing to write data.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
desires to read, generates a repeated START condi-
tion, writes the slave address byte (R/W = 1), reads
data with ACK or NACK as applicable, and generates a
STOP condition. Recall that the master must NACK the
last byte to inform the slave that no additional bytes will
be read.
2
See Figure 6 for I C communication examples.
Reading multiple bytes from a slave: The read opera-
tion can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the mas-
ter reads the last byte it must NACK to indicate the end
of the transfer and generates a STOP condition.
Acknowledge polling: Any time a EEPROM byte is
written, the DS3514 requires the EEPROM write time
(t ) after the STOP condition to write the contents of
W
the byte to EEPROM. During the EEPROM write time,
the device does not acknowledge its slave address
because it is busy. It is possible to take advantage of
18 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
2
TYPICAL I C WRITE TRANSACTION
MSB
LSB
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
1
1
0
0
0
0
A0 R/W
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
REGISTER ADDRESS
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
SLAVE
ADDRESS*
DATA
2
EXAMPLE I C TRANSACTIONS (WHEN A0 IS CONNECTED TO GND).
C0h
08h
OOh
A) SINGLE-BYTE WRITE
-WRITE LATCH A
GM8 TO 00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 1 0 0 0 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0
START
STOP
C0h
02h
C1h
DATA
B) SINGLE-BYTE READ
-READ LATCH A GM2
MASTER
NACK
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
1 1 0 0 0 0 0 1
START 1 1 0 0 0 0 0 0
I/O STATUS
STOP
0 0 0 0 0 0 1 0
C0h
41h
80h
C) SINGLE-BYTE WRITE
-ENTER STANDBY MODE
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 1 0 0 0 0 0 0
0 1 0 0 0 0 0 1
1 0 0 0 0 0 0 0
START
START
START
STOP
C0h
10h
80h
80h
D) TWO-BYTE WRITE
- WRITE 10h AND 11h TO 80h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 1 0 0 0 0 0 0
0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
STOP
C0h
10h
C1h
DATA
DATA
MASTER
NACK
SLAVE
ACK
MASTER
ACK
E) TWO-BYTE READ
- READ 10h AND 11h
SLAVE
ACK
SLAVE
ACK
REPEATED
START
STOP
1 1 0 0 0 0 0 0
0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 1
2
Figure 6. I C Communication Examples
SDA and SCL Pullup Resistors
Applications Information
SDA is an I/O with an open-collector output that
requires a pullup resistor to realize high-logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be used
for SCL. Pullup resistor values should be chosen to
Power-Supply Decoupling
To achieve the best results when using the DS3514,
decouple all the power-supply pins (V
and V ) with
DD
CC
a 0.01µF or 0.1µF capacitor. Use a high-quality ceramic
surface-mount capacitor if possible. Surface-mount
components minimize lead inductance, which improves
performance, and ceramic capacitors tend to have
adequate high-frequency response for decoupling
applications.
2
ensure that the rise and fall times listed in the I C
Electrical Characteristics are within specification. A typ-
ical value for the pullup resistors is 4.7kΩ.
______________________________________________________________________________________ 19
2
I C Gamma and V
Buffer with EEPROM
COM
Typical Operating Circuit
15V 14.8V 8V
7V
0.2V
14
5V
SOURCE DRIVER
V
DD
GHH GHM GLM GLL
V
GM1
GM2
GM3
GM4
GM5
GM6
GM7
CC
DS3514
SCL
SDA
2
I C MASTER
DS3514
LCD
S0
S1
LD
GM8
GM9
GM10
GM11
GM12
GM13
GM14
A0
GND
VRH VRL
V
COM
13V
2V
Pin Configuration
Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
TOP VIEW
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
35 34 33 32 31 30 29 28 27
36
26
25
48 TQFN-EP
T4877M+6
21-0144
GM14
GLM
37
38
24 GM1
V
23
DD
22 GND
21 GND
20 VCAP
19 GND
18 GND
GLL 39
GHM 40
GHH 41
GND
42
43
44
DS3514
V
DD
17
16 SCL
SDA
14 LD
13
V
CC
V
COM
A0 45
N.C.
15
46
47
48
*EP
+
V
CC
S0
N.C.
2
3
4
5
6
7
8
9
10
1
11
12
THIN QFN
(7mm × 7mm)
*EXPOSED PAD.
20 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
DS3514
Revision History
REVISION REVISION
PAGES
CHANGED
DESCRIPTION
NUMBER
DATE
0
9/08
Initial release.
Changed the maximum V supply current (l ) specification from 0.5mA to
—
CC
CC
1
10/08
2
0.6mA.
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 21
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
相关型号：
©2020 ICPDF网 联系我们和版权申明