DS3510T+ [MAXIM]
I2C Gamma and VCOM Buffer with EEPROM; I2C Gamma和VCOM缓冲器，带有EEPROM
| 型号： | DS3510T+ |
| 厂家： | 
MAXIM INTEGRATED PRODUCTS |
| 描述： | I2C Gamma and VCOM Buffer with EEPROM |
| 文件： | 总17页 (文件大小：224K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Rev 0; 2/08
2
I C Gamma and V
Buffer with EEPROM
COM
General Description
Features
The DS3510 is a programmable gamma and V
volt-
COM
o 8-Bit Gamma Buffers, 10 Channels
o 8-Bit V Buffer, 1 Channel
age generator which supports both real-time updating
as well as multibyte storage of gamma/V data in on-
COM
COM
chip EEPROM memory. An independent 8-bit DAC, two
8-bit data registers, and 4 bytes of EEPROM memory
are provided for each individually addressable gamma
o 4 EEPROM Bytes per Channel
o Low-Power 400µA/ch Gamma Buffers
or V
channel. High-performance buffer amplifiers
2
COM
o I C-Compatible Serial Interface
are integrated on-chip, providing rail-to-rail, low-power
(400µA/gamma channel) operation. The V channel
2
o Flexible Control from I C or Pins
COM
features a high-current drive (> 250mA peak) and a fast-
o 9.0V to 15.0V Analog Supply
o 2.7V to 5.5V Digital Supply
settling buffer amplifier optimized to drive the V
node of a wide range of TFT-LCD panels.
COM
Programming occurs through an I2C-compatible serial
interface. Interface performance and flexibility are
enhanced by a pair of independently loaded data reg-
isters per channel, as well as support for I2C speeds up
to 400kHz. The multitable EEPROM memory enables a
rich variety of display system enhancements, including
support for temperature or light-level-dependent
gamma tables, enabling of factory or field automated
display adjustment, and support for backlight dimming
algorithms to reduce system power. Upon power-up
and depending on mode, DAC data is selected from
EEPROM by the S0/S1 pads or from a fixed memory
address.
o 48-Pin Package (TQFN 7mm x 7mm)
Ordering Information
PART
DS3510T+
TEMP RANGE
-45°C to +95°C
-45°C to +95°C
PIN-PACKAGE
48 TQFN-EP*
48 TQFN-EP*
DS3510T+T&R
+Denotes a lead-free package.
T&R = Tape and reel.
*EP = Exposed pad.
Applications
TFT-LCD Gamma and V
Buffer
COM
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
Adaptive Gamma and V
2
Adjustment (Real-
2
COM
Time by I C, Select EEPROM Through I C or
S0/S1 Pads)
Industrial Process Control
Gamma or V
Channel Functional Diagram
COM
SDA, SCL
2
I C
LATCH A
8-BIT
DAC
INTERFACE
A0
MUX
LATCH B
V
OUT
IN
OUT
EEPROM
ADDRESS
S1/ S0
LD
LOGIC
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
2
I C Gamma and V
Buffer with EEPROM
COM
ABSOLUTE MAXIMUM RATINGS
Voltage on V
Relative to GND............................-0.5V to +16V
Junction Temperature......................................................+125°C
Operating Temperature Range ...........................-45°C to +95°C
Programming Temperature Range .........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...............Refer to IPC/JEDEC J-STD-020
Specification.
DD
Voltage on VRL, VRH, GHH, GHM, GLM, GLL
Relative to GND........-0.5V to (V + 0.5V), not to exceed 16V
DD
Voltage on V
Relative to GND..............................-0.5V to +6V
CC
Voltage on SDA, SCL, A0, LD, S0,
S1 Relative to GND ....-0.5V to (V
+ 0.5V), not to exceed 6V
CC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
(T = -45°C to +95°C.)
A
PARAMETER
Digital Supply Voltage
Analog Supply Voltage
SYMBOL
CONDITIONS
MIN
+2.7
+9.0
TYP
MAX
+5.5
UNITS
V
CC
V
DD
(Note 1)
(Note 1)
V
V
+15.0
VRH, VRL Voltage
V
Applies to V
output
+2.0
V
V
- 2.0
V
V
V
V
VCOM
COM
DD
GND +
0.2
GHH, GHM, GLM, GLL Voltage
V
Applies to GM1–GM10
- 0.2
GM1–10
DD
Input Logic 1
(SCL, SDA, A0, S0, S1, LD)
0.7 x
V
CC
V
CC
+ 0.3
V
IH
Input Logic 0
(SCL, SDA, A0, S0, S1, LD)
V
-0.3
0.3 x V
CC
IL
V
V
Load Capacitor
C
1
µF
µF
COM
D
Compensation Capacitor
C
0.1
CAP
COMP
INPUT ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, T = -45°C to +95°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input Leakage (SDA, SCL, S0,
S1, LD)
I
L
-1
+1
µA
Input Leakage (A0)
I
2
mA
mA
L:A0
V
DD
Supply Current
I
(Notes 2, 3)
(Note 4)
6.7
0.2
15.0
DD
V
CC
Supply Current, Nonvolatile
I
1.0
mA
CC
Read or Write
V
V
Standby Supply Current
Standby Supply Current
I
I
(Note 5)
(Note 6)
(Note 7)
1.8
2
10.0
4
µA
mA
pF
CC
CCQ
DD
DDQ
I/O Capacitance (SDA, SCL, A0)
C
5
10
I/O
End-to-End Resistance
(VRH to VRL)
R
16
kꢀ
TOTAL
2
_______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
INPUT ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +2.7V to +5.5V, T = -45°C to +95°C, unless otherwise noted.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
R
Tolerance
T
= +25°C
= +25°C
-20
+20
%
TOTAL
A
A
Input Resistance (GHH, GHM,
GLM, GLL)
75
kꢀ
Input Resistance Tolerance
T
-20
+20
%
OUTPUT ELECTRICAL CHARACTERISTICS
(V
CC
= +2.7V to +5.5V, VRL = GLL = +0.2V, GLM = +4.8V, GHM = +10.2V, VRH = GHH = +14.8V, T = -45°C to +95°C, unless
A
otherwise noted.)
PARAMETER
/GM1–10 DAC resolution
SYMBOL
CONDITIONS
MIN
8
TYP
MAX
UNITS
V
COM
Bits
V
-0.75
-0.4
-0.3
2.0
+0.75
+0.4
+0.3
COM
Integral Nonlinearity Error
INL
(Note 8)
LSB
Gamma
Differential Nonlinearity Error
DNL
V
COM
/gamma (Note 9)
LSB
V
Output Voltage Range (V
COM
)
V
V
- 2.0
DD
DD
Output Voltage Range (GM1–10)
0.2
- 0.2
V
V
-25
-50
+25
Output Accuracy
COM
T
= +25°C
mV
V/V
A
(V
COM
, GM1–10)
Gamma
+50
Voltage Gain (GM1–10)
Load Regulation
(Note 10)
0.995
0.5
mV/mA
(V
COM
, GM1–10)
Short-Circuit Current (V
COM
)
To V or GND
DD
250
200
200
mA
ns
S0/S1 to LD Setup Time
S0/S1 to LD Hold Time
t
t
Figure 1 or 2
Figure 1 or 2
SU
ns
HD
V
Settling Time from LD Low
Settling to 0.1% (see Figure 1)
(Notes 3, 11)
COM
to High (S0/S1 Meet t
t
2
µs
µs
ns
SET-V
)
SU
GM1–10 Settling Time from LD
Low to High
4 tau settled with I =
LOAD
20mA
t
6.7
SET-G
(see Figure 2) (Notes 3, 11, 12)
S0, S1 to V or GM1–10
Output 10% Settled
10% settling (see Figure 3), LD = V
(asynchronous) (Note 12)
COM
CC
t
450
SEL
_______________________________________________________________________________________
3
2
I C Gamma and V
Buffer with EEPROM
COM
2
I C ELECTRICAL CHARACTERISTICS (See Figure 4)
(V
= +2.7V to +5.5V, T = -45°C to +95°C, timing referenced to V
and V
.)
CC
A
IL(MAX)
IH(MIN)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SCL Clock Frequency
f
(Note 13)
0
400
kHz
SCL
Bus Free Time Between STOP
and START Conditions
t
1.3
0.6
µs
µs
BUF
Hold Time (Repeated) START
Condition
t
HD:STA
Low Period of SCL
High Period of SCL
Data Hold Time
t
1.3
0.6
0
µs
µs
µs
ns
µs
LOW
t
HIGH
t
t
t
0.9
HD:DAT
SU:DAT
SU:STA
Data Setup Time
START Setup Time
100
0.6
20 +
SDA and SCL Rise Time
t
(Note 14)
(Note 14)
300
300
ns
R
0.1C
B
20 +
SDA and SCL Fall Time
STOP Setup Time
t
ns
µs
F
0.1C
B
t
0.6
SU:STO
SDA and SCL Capacitive
Loading
C
(Note 14)
(Note 15)
(Note 16)
400
20
pF
ms
ns
B
W
EEPROM Write Time
t
Pulse-Width Suppression Time
at SDA and SCL Inputs
t
50
IN
A0 Setup Time
A0 Hold Time
t
t
Before START
After STOP
0.6
0.6
µs
µs
SU:A
HD:A
SDA and SCL Input Buffer
Hysteresis
0.05 x
V
V
V
CC
Low-Level Output Voltage (SDA)
V
4mA sink current
SCL falling through 0.3V to SDA exit
0.4
OL
SCL Falling Edge to SDA Output
Data Valid
CC
t
t
900
ns
AA
0.3V ~0.7V window
CC CC
SCL falling through 0.3V until SDA in
CC
0.3V ~0.7V window
CC CC
Output Data Hold
0
ns
DH
4
_______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
NONVOLATILE MEMORY CHARACTERISTICS
(V
CC
= +2.7V to +5.5V.)
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
UNITS
Writes
Writes
EEPROM Write Cycles
EEPROM Write Cycles
T
T
= +70°C
= +25°C
50,000
200,000
A
A
Note 1: All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are
negative.
Note 2:
I
supply current is specified with V
= 15.0V and no load on V
or GM1–10 outputs.
DD
DD
COM
Note 3: Specified with the V
and gamma bias currents set to 100%.
COM
Note 4:
Note 5:
Note 6:
I
I
I
is specified with the following conditions: SCL = 400kHz, SDA = V
= 5.5V, and VCOM and GM1–10 floating.
CC
CC
is specified with the following conditions: SCL = SDA = V
is specified with the following conditions: SCL = SDA = V
= 5.5V, and V
= 5.5V and V
and GM1–10 floating.
COM
and GM1–10 floating.
COM
CCQ
DDQ
CC
CC
Note 7: Guaranteed by design.
Note 8: Integral nonlinearity is the deviation of a measured value from the expected values at each particular setting. Expected
value is calculated by connecting a straight line from the measured minimum setting to the measured maximum setting.
INL = [V(RW) - (V(RW) ]/LSB(measured) - i, for i = 0...255.
i
0
Note 9: Differential nonlinearity is the deviation of the step size change between two LSB settings from the expected step size. The
expected LSB step size is the slope of the straight line from measured minimum position to measured maximum position.
DNL = [V(RW)
- (V(RW) ]/LSB(measured) - 1, for i = 0...254.
i+1
i
Note 10: Tested at VRL = VRH = 6.5V/7.5V/8.5V, GLL = GLM = 0.5V/6.5V/8.5V/14.5V, GHM = GHH = 0.5V/6.5V/8.5V/14.5V.
Note 11: EEPROM data is assumed already settled at input of Latch B. LD transitions after EEPROM byte has been selected.
Note 12: Rising transition from 5V to 10V; falling transition from 10V to 5V.
2
2
Note 13: I C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I C
standard mode timing.
Note 14: C —total capacitance of one bus line in picofarads.
B
Note 15: EEPROM write time begins after a STOP condition occurs.
Note 16: Pulses narrower than max are suppressed.
V
V
IH
S0/S1
IL
t
t
HD
SU
V
t
SET-V
2Ω
V
COM
IH
LD
100nF
V
IL
0.1% SETTLED
V
COM
Figure 1. V
Settling Timing Diagram
COM
_______________________________________________________________________________________
5
2
I C Gamma and V
Buffer with EEPROM
COM
V
V
IH
S0/S1
IL
t
t
SU
HD
t
SET-G
GM1–GM10
V
IH
100pF
LD
I
LOAD
V
IL
4 TAU SETTLED
GM1–10
Figure 2. GM1–10 Settling Timing Diagram
V
V
IH
S0/S1
(LD = V
)
CC
IL
GM1–GM10
t
SEL
100pF
OUTPUT 10% SETTLED
GM1–GM10
Figure 3. Input Pin to Output Change Timing Diagram
SDA
t
BUF
t
SP
t
HD:STA
t
LOW
t
t
F
R
SCL
t
SU:STA
t
HD:STA
t
HIGH
t
REPEATED
START
t
SU:STO
SU:DAT
STOP
START
t
HD:DAT
NOTE: TIMING IS REFERENCED TO V
AND V
.
IH(MIN)
IL(MAX)
2
Figure 4. I C Timing Diagram
6
_______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
Typical Operating Characteristics
(T = +25°C, unless otherwise noted.)
A
I
vs. V
I
vs. V
DD DD
I
vs. TEMPERATURE
CC
CC
CC
180
160
140
120
100
80
7.0
6.5
6.0
5.5
5.0
4.5
4.0
180
160
140
120
100
80
+95°C
+25°C
+25°C
+95°C
5.5V
-40°C
-40°C
3.6V
2.7V
60
60
2.7
-45
0
3.2
3.7
4.2
(V)
4.7
5.2
9
10
11
12
(V)
13
14
15
-45
0
45
90
V
V
TEMPERATURE (°C)
CC
DD
I
vs. V
V INL vs. SETTING
COM
I
vs. BIAS CURRENT SETTING
DD
DD
DD
7.0
6.5
6.0
5.5
5.0
4.5
4.0
9
8
7
6
5
4
3
V
= 4V, V = 15V
DD
0.65
0.45
CC
+95°C
0.25
0.05
+25°C
-40°C
-0.15
-0.35
-0.55
-0.75
0
45
90
0
50
100
V SETTING (DEC)
COM
150
200
250
0
1
2
3
V
(V)
DD
BIAS CURRENT SETTING (DEC)
V
DNL vs. SETTING
GM1–GM10 INL vs. SETTING
GM1–GM10 DHL vs. SETTING
COM
0.3
0.2
0.1
0
0.4
0.3
0.3
0.2
0.1
0
0.2
0.1
0
-0.1
-0.2
-0.3
-0.4
-0.1
-0.2
-0.3
-0.1
-0.2
-0.3
50
100
150
200
250
0
50
100
150
200
250
0
50
100
150
200
250
V
SETTING (DEC)
GM1–GM10 SETTING (DEC)
GM1–GM10 SETTING (DEC)
COM
_______________________________________________________________________________________
7
2
I C Gamma and V
Buffer with EEPROM
COM
Pin Description
NAME
PIN
TYPE
FUNCTION
V
1, 19, 20, 24
Power
Analog Supply (9.0V to 15.5V)
Ground
DD
2, 38, 40,
42, 43
GND
Power
Latch Data Input. When LD is low, Latch B retains existing data (acts as a latch).
When LD is high, the input to Latch B data flows through to the output and updates
the DACs asynchronously.
LD
3
Input
S1
S0
4
5
6
7
8
9
Select Inputs. When Control register [1,0] = 00, S0 and S1 pins are used to select
DAC input data from EEPROM.
Input
Input
2
SCL
SDA
A0
I C Serial Clock Input
2
Input/Output I C Serial Data Input/Output
2
Input
Address Input. This pin determines I C slave address of the DS3510.
Digital Supply (2.7V to 5.5V)
V
CC
Power
Reference
Input
VRH, VRL
N.C.
10, 11
V
Reference Inputs. High-voltage reference for V DAC.
COM
COM
12–17, 23,
36, 37,
—
No Connection
44–48
V
18
Input
Compensation Capacitor Input. Connect VCAP to GND through a 0.1µF capacitor.
References for Low-Voltage Gamma DAC
CAP
Reference
Input
GLL, GLM
GM1–GM5
21, 22
25–29
30
Output
Output
Output
Low-Voltage Gamma Analog Outputs
V
COM
V
COM
Analog Output. This output requires a 1µF capacitor to GND.
GM6–GM10
GHM, GHH
GND
31–35
High-Voltage Gamma Analog Outputs
References for High-Voltage Gamma DAC
Ground. Exposed pad. Connect to GND.
Reference
Input
41, 39
EP
—
8
_______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
Block Diagram
GHH
GHH
BANKS
GM10 BANK A
GHH
DS3510
GM10 BANK B
GM10 BANK C
GM10 BANK D
MUX
0
1
8 BITS
8-BIT
DAC
LATCH B
LD
0
S0/S1 PINS
GM10
S0/S1 BITS
1
LATCH A
GHM
GHH
2
I C
COMP
MODE0 BIT
MODE1 BIT
BANKS
GM6 BANK A
GM6 BANK B
GM6 BANK C
GM6 BANK D
MUX
0
8 BITS
8-BIT
DAC
LATCH B
LD
0
1
1
S0/S1 PINS
S0/S1 BITS
GM6
LATCH A
GHM
2
I C
COMP
SDA
SCL
A0
2
MODE0 BIT
MODE1 BIT
I C
2
I C
INTERFACE
GHM
GHM
VRH
BANKS
VCOM BANK A
VCOM BANK B
VCOM BANK C
VCOM BANK D
MUX
MODE0 BIT (CR.0)
MODE1 BIT (CR.1)
S0/S1 PINS
0
8 BITS
8-BIT
DAC
S0
S1
LD
LOGIC
AND
CONTROL
LATCH B
LD
0
1
1
S0/S1 PINS
S0/S1 BITS
V
COM
S0/S1 BITS (SOFT S0/S1)
LD
LATCH A
2
VRL
I C
COMP
MODE0 BIT
MODE1 BIT
GLM
GLM
V
CAP
COMPENSATION
COMP
BANKS
GLM
GM5 BANK A
GM5 BANK B
GM5 BANK C
GM5 BANK D
MUX
0
8 BITS
8-BIT
DAC
LATCH B
LD
0
1
1
S0/S1 PINS
S0/S1 BITS
GM5
LATCH A
GLL
V
DD
CC
2
I C
V
DD
CC
COMP
MODE0 BIT
MODE1 BIT
V
V
BANKS
GLM
GM1 BANK A
GM1 BANK B
GM1 BANK C
GM1 BANK D
GND
MUX
0
8 BITS
8-BIT
DAC
LATCH B
LD
0
1
1
S0/S1 PINS
S0/S1 BITS
GM1
GLL
LATCH A
GLL
2
I C
COMP
MODE0 BIT
MODE1 BIT
GLL
_______________________________________________________________________________________
9
2
I C Gamma and V
Buffer with EEPROM
COM
changes in the state of S0/S1 to meet the t
specifi-
SEL
Detailed Description
cation. Conversely, when LD is low, Latch B functions
as a latch, holding its previous data. A low-to-high tran-
sition on LD allows the Latch B input data to flow
through and update the DACs with the EEPROM bank
selected by S0/S1. A high-to-low transition on LD latch-
es the selected DAC data into Latch B.
The DS3510 operates in one of three modes which
determine how the V
and gamma DACs are con-
COM
trolled/updated. The first two modes allow “banked”
control of the 10 gamma channels and 1 V chan-
COM
nel. Depending on the mode, one of four banks (in
EEPROM) can be selected using either the S0/S1 pins
or using the SOFT S0/S1 bits in the Soft S0/S1 register.
Once a bank is selected, the LD pin can then be used
to simultaneously update each channel’s DAC output.
The third and final mode is not banked. It allows I2C
control of each channel’s Latch A register which is
SRAM (volatile), allowing quick and unlimited updates.
In this mode, the LD pin can also be used to simultane-
ously update each channel’s DAC output. A detailed
description of the three modes as well as additional
features of the DS3510 follows.
Table 2. DS3510 Bank Selection Table
V
GAMMA
CHANNELS
COM
CHANNEL
S1
S0
0
0
1
1
0
1
0
1
V
COM
V
COM
V
COM
V
COM
Bank A
Bank B
Bank C
Bank D
GM1–10 Bank A
GM1–10 Bank B
GM1–10 Bank C
GM1–10 Bank D
Mode Selection
The DS3510 mode of operation is determined by 2 bits
located in the Control register (60h), which is non-
volatile (NV) (EEPROM). In particular, the mode is
determined by the MODE0 bit (CR.0) and the MODE1
bit (CR.1). Table 1 illustrates how the 2 control bits are
used to select the operating mode. When shipped from
the factory, the DS3510 is programmed with both
MODE bits set to zero.
SOFT S0/S1 (Bit) Controlled Bank
Updating Mode
This mode also features “banked” operation with the
only difference being how the desired bank is selected.
In particular, the bank is selected using the SOFT S0
(bit 0) and SOFT S1 (bit 1) bits contained in the Soft
S0/S1 register (50h). The S0 and S1 pins are ignored in
this mode. Table 2 illustrates the relationship between
the bit settings and the selected bank. For example, if
both bits, S0 and S1, are written to zero, then the first
bank (Bank A) is selected. Once a bank is selected, the
timing of the DAC update depends on the state of the
LD pin. When LD is high, Latch B functions as a flow-
through latch, so the amplifier will respond asynchro-
nously to changes in the state of the S0/S1 bits. These
are changed by an I2C write. Conversely, when LD is
low, Latch B functions as a latch, holding its previous
data. A low-to-high transition on LD allows the Latch B
input data to flow through and update the DACs with
the EEPROM bank selected by the S0/S1 bits. A high-
to-low transition on LD latches the selected DAC data
into Latch B.
Table 1. DS3510 Operating Modes
MODE1 BIT
(CR.1)
MODE0 BIT
(CR.0)
MODE
S0/S1 Pin-Controlled Bank
Updating (Factory Default)
0
0
1
0
1
X
S0/S1 Bit-Controlled Bank
Updating
2
I C Individual Channel
Control
S0/S1 Pin-Controlled Bank Updating Mode
As shown in the block diagram, each channel contains
4 bytes of EEPROM, which are used to implement the
“banking” functionality. Each “bank” contains unique
DAC settings for each channel. When the DS3510 is
configured in this operating mode, the desired bank is
selected using the S0 and S1 pins as shown in Table 2
Since the Soft S0/S1 register is SRAM, subsequent
power-ups result in the SOFT S0 and SOFT S1 bits
being cleared to 0 and, hence, powering up to Bank A.
I2C Individual Channel Control Mode
In this mode the I2C master writes directly to individual
channel Latch A registers to update a single DAC (i.e.,
not banked). The Latch A registers are SRAM and not
EEPROM. This allows an unlimited number of write
where 0 is ground and 1 is V . For example, if S0 and
CC
S1 are both connected to ground, then the first bank
(Bank A) is selected. Once a bank is selected, the tim-
ing of the DAC update depends on the state of LD pin.
When LD is high, Latch B functions as a flow-through
latch, so the amplifier will respond asynchronously to
cycles as well as quicker write times since t only
W
applies to EEPROM writes. As shown in the Memory
Map, the Latch A registers for each channel are
accessed through memory addresses 00–0Ah. Then,
10 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
Table 3. DAC Voltage/Data Relationship for Selected Codes
SETTING
(HEX)
V
OUTPUT VOLTAGE
GM1–GM5 OUTPUT VOLTAGE
GM6–GM10 OUTPUT VOLTAGE
COM
00h
01h
02h
03h
0Fh
3Fh
7Fh
FDh
FEh
FFh
VRL
GLL
GHM + (255/256) x (GHH - GHM)
GHM + (254/256) x (GHH - GHM)
GHM + (253/256) x (GHH - GHM)
GHM + (252/256) x (GHH - GHM)
GHM + (240/256) x (GHH - GHM)
GHM + (192/256) x (GHH - GHM)
GHM + (128/256) x (GHH - GHM)
GHM + (2/256) x (GHH - GHM)
GHM + (1/256) x (GHH - GHM)
GHM
VRL + (1/255) x (VRH - VRL)
VRL + (2/255) x (VRH - VRL)
VRL + (3/255) x (VRH - VRL)
VRL + (15/255) x (VRH - VRL)
VRL + (63/255) x (VRH - VRL)
VRL + (127/255) x (VRH - VRL)
VRL + (253/255) x (VRH - VRL)
VRL + (254/255) x (VRH - VRL)
VRH
GLL + (1/256) x (GLM - GLL)
GLL + (2/256) x (GLM - GLL)
GLL + (3/256) x (GLM - GLL)
GLL + (15/256) x (GLM - GLL)
GLL + (63/256) x (GLM - GLL)
GLL + (127/256) x (GLM - GLL)
GLL + (253/256) x (GLM - GLL)
GLL + (254/256) x (GLM - GLL)
GLL + (255/256) x (GLM - GLL)
like the other modes, the LD pin determines when the
DACs get updated. If the LD signal is high, Latch B is
flow-through and the DAC is updated immediately. If
LD is low, Latch B will be loaded from Latch A after a
low-to-high transition on the LD pin. This latter method
allows the timing of the DAC update to be controlled by
an external signal pulse.
impedance state. Current drawn from the V
supply in
DD
this state is specified as I
.
DDQ
The DS3510 continues to respond to I2C commands,
and thus draws some current from V
when I2C activi-
CC
ty is occurring. When the I2C interface is inactive, cur-
rent drawn from the V supply is specified as I
.
CCQ
CC
Thermal Shutdown
V
/Gamma Channel Outputs
COM
As a safety feature, the DS3510 goes into a thermal
shutdown state if the junction temperature ever reaches
As illustrated in the Block Diagram, the V
and
COM
gamma channel outputs are equivalent to an 8-bit digi-
tal potentiometer (DAC) with a buffered output. The
or exceeds +150°C. In this state, the V
buffer is
COM
disabled (output goes high impedance) until the junc-
tion temperature falls below +150°C.
V
channel’s digital potentiometer is comprised of
COM
255 equal resistive elements. The relationship between
output voltage and DAC setting is illustrated in Table 3.
Slave Address Byte and Address Pin
The slave address byte consists of a 7-bit slave
address plus a R/W bit (see Figure 5). The DS3510’s
slave address is determined by the state of the A0 pin.
This pin allows up to two devices to reside on the same
I2C bus. Connecting A0 to GND results in a 0 in the cor-
responding bit position in the slave address.
Unlike the gamma channels, the V
channel is
COM
capable of outputting a range of voltages including
both references (VRH and VRL). Each of the gamma
channel digital potentiometers, on the other hand, are
comprised of 256 equal resistive elements. The extra
resistive element prohibits one of the rails from being
reached. In particular, gamma channel outputs
GM1–GM5 can span from (and including) GLL to 1 LSB
away from GLM. Likewise, gamma channel outputs
GM6–GM10 span from (and including) GHM to 1 LSB
away from GHH. The relationship between output volt-
age and DAC setting for the gamma channels is also
illustrated in Table 3.
Conversely, connecting A0 to V
results in a 1 in the
CC
corresponding bit position. For example, the DS3510’s
slave address byte is C0h when A0 is grounded. I2C
communication is described in detail in the I2C Serial
Interface Description section.
LSB
R/W
MSB
1
Standby Mode
Standby mode (not to be confused with the three
DS3510 operating modes) can be used to minimize
current consumption. Standby mode is entered by set-
ting the standby bit, which is the LSB of register 51h.
1
0
0
0
A0
0
SLAVE ADDRESS*
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
The V
and gamma outputs are placed in a high-
COM
Figure 5. DS3510 Slave Address Byte
______________________________________________________________________________________ 11
2
I C Gamma and V
Buffer with EEPROM
COM
factory-programmed defaults for the NV locations.
Detailed register descriptions for the registers shown in
bold follow in the Detailed Register Descriptions sec-
tion. Furthermore, additional information regarding
reading and writing the memory is located in the I2C
Serial Interface Description section.
Memory Organization
Memory Description
The list of registers/memory contained in the DS3510 is
shown in the Memory Map. Also shown for each of the
registers is the memory type and accessibility, as well
as the power-up default values for volatile locations and
Memory Map
2
ADDR
(HEX)
I C
NAME
Latch A
DESCRIPTION
MEMORY TYPE
DEFAULT (HEX)
ACCESS
2
V
00
01
02
03
04
05
06
07
08
09
0A
Data for I C Control of V
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
Volatile
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
00
00
00
00
00
00
00
00
00
00
00
—
COM
COM
2
GM1 Latch A
GM2 Latch A
GM3 Latch A
GM4 Latch A
GM5 Latch A
GM6 Latch A
GM7 Latch A
GM8 Latch A
GM9 Latch A
GM10 Latch A
Reserved
Data for I C Control of GM1
2
Data for I C Control of GM2
2
Data for I C Control of GM3
2
Data for I C Control of GM4
2
Data for I C Control of GM5
2
Data for I C Control of GM6
2
Data for I C Control of GM7
2
Data for I C Control of GM8
2
Data for I C Control of GM9
2
Data for I C Control of GM10
0B–0F Reserved
10–13 EEPROM Data (4 Bytes)
V
Bank A–D
V
COM
NV
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
80
80
80
80
80
80
80
80
80
80
80
—
COM
GM1 Bank A–D
GM2 Bank A–D
GM3 Bank A–D
GM4 Bank A–D
GM5 Bank A–D
GM6 Bank A–D
GM7 Bank A–D
GM8 Bank A–D
GM9 Bank A–D
GM10 Bank A–D
Reserved
14–17 GM1 EEPROM Data (4 Bytes)
18–1B GM2 EEPROM Data (4 Bytes)
1C–1F GM3 EEPROM Data (4 Bytes)
20–23 GM4 EEPROM Data (4 Bytes)
24–27 GM5 EEPROM Data (4 Bytes)
28–2B GM6 EEPROM Data (4 Bytes)
2C–2F GM7 EEPROM Data (4 Bytes)
30–33 GM8 EEPROM Data (4 Bytes)
34–37 GM9 EEPROM Data (4 Bytes)
38–3B GM10 EEPROM Data (4 Bytes)
3C–4F Reserved
NV
NV
NV
NV
NV
NV
NV
NV
NV
NV
—
Soft S0/S1
50
51
Software Bank Select Bits
Standby (xxxxxxx, Standby)
Volatile
Volatile
—
R/W
R/W
—
00
00
—
Standby
Reserved
52–56 Reserved
Status
57
Status Bits (LD, xxxxx, S1, S0)
Status
—
R
N/A
—
Reserved
58–5F Reserved
—
Control Register (CR)
Reserved
60
Control Register
NV
R/W
—
10
—
61–FF Reserved
—
12 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
Detailed Register Descriptions
SOFT S0/S1 50h: SOFT S1/S0 Bits
FACTORY DEFAULT
MEMORY TYPE
00h
Volatile
50h
x
x
x
x
x
x
SOFT S1
SOFT S0
bit0
bit7
bit7:2
Reserved
These bits are used when in SOFT S0/S1 (bit) Controlled Bank Updating Mode (MODE1 = 0, MODE0 = 1)
SOFT S1, SOFT S0:
00 = Selects V
01 = Selects V
10 = Selects V
11 = Selects V
and GM1–GM10 Bank A
and GM1–GM10 Bank B
and GM1–GM10 Bank C
and GM1–GM10 Bank D
COM
COM
COM
COM
bit1, bit0
STANDBY 51h: Standby Mode Enable
FACTORY DEFAULT
00h
MEMORY TYPE
Volatile
51h
x
x
x
x
x
x
x
Standby
bit0
bit7
bit7:1
bit0
Reserved
Standby:
0 = Standby Mode Disabled
1 = Standby Mode Enabled
STATUS 57h: Real-Time Indicator of Logic State on LD, S1, and S0 Pins
FACTORY DEFAULT
MEMORY TYPE
—
Read Only
57h
LD
x
x
x
x
x
S1
S0
bit7
bit0
______________________________________________________________________________________ 13
2
I C Gamma and V
Buffer with EEPROM
COM
CONTROL REGISTER 60h: Control Register (CR)
FACTORY DEFAULT
MEMORY TYPE
10h
NV
60h
x
x
BIAS1
BIAS0
x
x
MODE1
MODE0
bit0
bit7
bit7:6
bit5:4
Reserved
and Gamma Bias Current Control Bits:
00 = 150%
01 = 100% (default)
10 = 80%
V
COM
11 = 60%
bits3:2
bits1:0
Reserved
DS3510 Mode:
00 = S0/S1 Pins are Used to Select the Desired Bank (A–D) (Default)
01 = Soft S0/S1 (Bits) Are Used to Select the Desired Bank (A–D)
1X = Latch A Is Used to Control the DACs
2
specific memory address to begin a data transfer. A
repeated START condition is issued identically to a nor-
mal START condition.
I C Serial Interface Description
I2C Definitions
The following terminology is commonly used to describe
Bit write: Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements. Data is shifted into the
device during the rising edge of the SCL.
2
I C data transfers. (See Figure 4 and I2C Electrical
Characteristics for additional information.)
Master device: The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses and START and STOP conditions.
Bit read: At the end of a write operation, the master
must release the SDA bus line for the proper amount of
setup time before the next rising edge of SCL during a
bit read. The device shifts out each bit of data on SDA
at the falling edge of the previous SCL pulse and the
data bit is valid at the rising edge of the current SCL
pulse. Remember that the master generates all SCL
clock pulses, including when it is reading bits from the
slave.
Slave devices: Slave devices send and receive data at
the master’s request.
Bus idle or not busy: Time between STOP and START
conditions when both SDA and SCL are inactive and in
their logic-high states.
START condition: A START condition is generated by
the master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a START condition.
Acknowledge (ACK and NACK): An Acknowledge
(ACK) or Not Acknowledge (NACK) is always the 9th bit
transmitted during a byte transfer. The device receiving
data (the master during a read or the slave during a
write operation) performs an ACK by transmitting a 0
during the 9th bit. A device performs a NACK by trans-
mitting a 1 during the 9th bit. Timing for the ACK and
NACK is identical to all other bit writes. An ACK is the
acknowledgment that the device is properly receiving
data. A NACK is used to terminate a read sequence or
indicates that the device is not receiving data.
STOP condition: A STOP condition is generated by
the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition.
Repeated START condition: The master can use a
repeated START condition at the end of one data trans-
fer to indicate that it will immediately initiate a new data
transfer following the current one. Repeated starts are
commonly used during read operations to identify a
14 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
2
Byte write: A byte write consists of 8 bits of information
transferred from the master to the slave (most signifi-
cant bit first) plus a 1-bit acknowledgment from the
slave to the master. The 8 bits transmitted by the mas-
ter are done according to the bit write definition and the
acknowledgment is read using the bit read definition.
I C Communication
Writing a single byte to a slave: The master must gen-
erate a START condition, write the slave address byte
(R/W = 0), write the memory address, write the byte of
data, and generate a STOP condition. Remember the
master must read the slave’s acknowledgment during
all byte write operations.
Byte read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the bit
read definition above, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to ter-
minate communication so the slave will return control of
SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately fol-
lowing a start condition. The slave address byte con-
tains the slave address in the most significant 7 bits
and the R/W bit in the least significant bit.
When writing to the DS3510 (and if LD = 1), the DAC will
adjust to the new setting once it has acknowledged the
new data that is being written, and the EEPROM (used to
make the setting nonvolatile) will be written following the
STOP condition at the end of the write command.
Writing multiple bytes to a slave: To write multiple
bytes to a slave in one transaction, the master gener-
ates a START condition, writes the slave address byte
(R/W = 0), writes the memory address, writes up to 8
data bytes, and generates a STOP condition. The
DS3510 is capable of writing 1 to 8 bytes (1 page or
row) in a single write transaction. This is internally con-
trolled by an address counter that allows data to be
written to consecutive addresses without transmitting a
memory address before each data byte is sent. The
address counter limits the write to one 8-byte page
(one row of the memory map). The first page begins at
address 00h and subsequent pages begin at multiples
of 8 (08h, 10h, 18h, etc). Attempts to write to additional
pages of memory without sending a STOP condition
between pages results in the address counter wrap-
ping around to the beginning of the present row. To
prevent address wrapping from occurring, the master
must send a STOP condition at the end of the page,
then wait for the bus-free or EEPROM-write time to
elapse. Then the master can generate a new START
condition and write the slave address byte (R/W = 0)
and the first memory address of the next memory row
before continuing to write data.
The DS3510’s slave address is determined by the state
of the A0 address pin as shown in Figure 5. An address
pin connected to GND results in a 0 in the correspond-
ing bit position in the slave address. Conversely, an
address pin connected to V
responding bit position.
results in a 1 in the cor-
CC
When the R/W bit is 0 (such as in C0h), the master is
indicating it will write data to the slave. If R/W is set to a
1, (C1h in this case), the master is indicating it wants to
read from the slave.
If an incorrect (non-matching) slave address is written,
the DS3510 will assume the master is communicating
with another I2C device and ignore the communication
until the next start condition is sent.
2
Memory address: During an I C write operation to the
Acknowledge polling: Any time a EEPROM byte is
DS3510, the master must transmit a memory address to
identify the memory location where the slave is to store
the data. The memory address is always the second
byte transmitted during a write operation following the
slave address byte.
written, the DS3510 requires the EEPROM write time
(t ) after the STOP condition to write the contents of
W
the byte to EEPROM. During the EEPROM write time,
the device will not acknowledge its slave address
because it is busy. It is possible to take advantage of
this phenomenon by repeatedly addressing the
DS3510, which allows communication to continue as
soon as the DS3510 is ready. The alternative to
acknowledge polling is to wait for a maximum period of
t
W
to elapse before attempting to access the device.
______________________________________________________________________________________ 15
2
I C Gamma and V
Buffer with EEPROM
COM
2
TYPICAL I C WRITE TRANSACTION
MSB
1
LSB
MSB
LSB
MSB
LSB
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
START
1
0
0
0
0
A0 R/W
b7 b6 b5 b4 b3 b2 b1 b0
b7 b6 b5 b4 b3 b2 b1 b0
STOP
READ/
WRITE
REGISTER ADDRESS
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PIN A0.
SLAVE
ADDRESS*
DATA
2
EXAMPLE I C TRANSACTIONS (WHEN A0 IS CONNECTED TO GND)
C0h
08h
OOh
A) SINGLE-BYTE WRITE
-WRITE LATCH A
GM8 TO 00h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 1 0 0 0 0 0 0
0 0 0 0 1 0 0 0
0 0 0 0 0 0 0 0
START
STOP
C0h
02h
C1h
DATA
B) SINGLE-BYTE READ
-READ LATCH A GM2
MASTER
NACK
SLAVE
ACK
SLAVE
ACK
REPEATED
START
SLAVE
ACK
1 1 0 0 0 0 0 1
START 1 1 0 0 0 0 0 0
I/O STATUS
STOP
0 0 0 0 0 0 1 0
C0h
51h
01h
C) SINGLE-BYTE WRITE
-ENTER STANDBY MODE
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 1 0 0 0 0 0 0
0 1 0 1 0 0 0 1
0 0 0 0 0 0 0 1
START
START
START
STOP
C0h
10h
80h
80h
D) TWO-BYTE WRITE
- WRITE 10h AND 11h TO 80h
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
SLAVE
ACK
1 1 0 0 0 0 0 0
0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0
STOP
C0h
10h
C1h
DATA
DATA
MASTER
NACK
SLAVE
ACK
MASTER
ACK
E) TWO-BYTE READ
- READ 10h AND 11h
SLAVE
ACK
SLAVE
ACK
REPEATED
START
STOP
1 1 0 0 0 0 0 0
0 0 0 1 0 0 0 0
1 1 0 0 0 0 0 1
2
Figure 6. I C Communication Examples
EEPROM write cycles: The DS3510’s EEPROM write
cycles are specified in the Nonvolatile Memory
Characteristics table. The specification shown is at the
worst-case temperature (hot) as well as at room tem-
perature.
Manipulating the address counter for reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master gen-
erates a START condition, writes the slave address
byte (R/W = 0), writes the memory address where it
desires to read, generates a repeated START condi-
tion, writes the slave address byte (R/W = 1), reads
data with ACK or NACK as applicable, and generates a
STOP condition. Recall that the master must NACK the
last byte to inform the slave that no additional bytes will
be read.
Reading a single byte from a slave: Unlike the write
operation that uses the specified memory address byte
to define where the data is to be written, the read opera-
tion occurs at the present value of the memory address
counter. To read a single byte from the slave, the master
generates a START condition, writes the slave address
byte with R/W = 1, reads the data byte with a NACK to
indicate the end of the transfer, and generates a STOP
condition. However, since requiring the master to keep
track of the memory address counter is impractical, the
following method should be used to perform reads from
a specified memory location.
2
See Figure 6 for I C communication examples.
Reading multiple bytes from a slave: The read opera-
tion can be used to read multiple bytes with a single
transfer. When reading bytes from the slave, the master
simply ACKs the data byte if it desires to read another
byte before terminating the transaction. After the mas-
ter reads the last byte, it must NACK to indicate the end
of the transfer and generates a STOP condition.
16 ______________________________________________________________________________________
2
I C Gamma and V
Buffer with EEPROM
COM
SDA and SCL Pullup Resistors
Applications Information
SDA is an I/O with an open-collector output that
requires a pullup resistor to realize high-logic levels. A
master using either an open-collector output with a
pullup resistor or a push-pull output driver can be used
for SCL. Pullup resistor values should be chosen to
ensure that the rise and fall times listed in the I2C
Electrical Characteristics are within specification. A typ-
ical value for the pullup resistors is 4.7kΩ.
Power-Supply Decoupling
To achieve the best results when using the DS3510,
decouple all the power-supply pins (V
and V ) with a
DD
CC
0.01µF or 0.1µF capacitor. Use a high-quality ceramic
surface-mount capacitor if possible. Surface-mount com-
ponents minimize lead inductance, which improves per-
formance, and ceramic capacitors tend to have adequate
high-frequency response for decoupling applications.
Typical Operating Circuit
15V 14.8V 8V
7V
0.2V
8
5V
SOURCE DRIVER
V
DD
GHH GHM GLM GLL
GM1
GM2
GM3
GM4
GM5
V
CC
SCL
SDA
DS3510
GM6
GM7
2
LCD
I C MASTER
GM8
GM9
GM10
A0
GND
VRH VRL
V
COM
8
7.5V
2V
Pin Configuration
Package Information
(For the latest package outline information, go to
TOP VIEW
www.maxim-ic.com/packages.)
48 47 46 45 44 43 42 41 40 39 38 37
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
V
1
2
3
4
5
6
7
8
9
36 N.C.
35 GM10
34 GM9
33 GM8
32 GM7
31 GM6
DD
48 TQFN-EP
T4877+6
21-0144
GND
LD
S1
S0
SCL
SDA
A0
DS3510
30
V
COM
29 GM5
28 GM4
27 GM3
26 GM2
25 GM1
V
CC
VRH 10
VRL 11
N.C. 12
*EP
13 14 15 16 17 18 19 20 21 22 23 24
TQFN
(7mm × 7mm × 0.8mm)
*EXPOSED PAD
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 17
© 2008 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
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