LTM4616 [Linear]
Dual 8A per Channel Low VIN DC/DC μModule; 每通道低输入电压的DC / DC微型模块双通道8A型号: | LTM4616 |
厂家: | Linear |
描述: | Dual 8A per Channel Low VIN DC/DC μModule |
文件: | 总24页 (文件大小:309K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM4616
Dual 8A per Channel Low
V DC/DC µModule
IN
FEATURES
DESCRIPTION
The LTM®4616 is a complete dual 2-phase 8A per channel
switch mode DC/DC power regulator system in a 15mm ×
15mmsurfacemountLGApackage.Includedinthepackage
are the switching controller, power FETs, inductor and all
support components. Operating from an input voltage
range of 2.7V to 5.5V, the LTM4616 supports two outputs
within a voltage range of 0.6V to 5V, each set by a single
external resistor. This high efficiency design delivers up
to 8A continuous current (10A peak) for each output. Only
bulk input and output capacitors are needed, depending
on ripple requirement. The part can also be configured for
a 2-phase single output at up to 16A.
■
Complete Dual DC/DC Regulator System
■
Input Voltage Range: 2.7V to 5.5V
■
Dual 8A Outputs, or Single 16A Output with a 0.6V
to 5V Range
Output Voltage Tracking and Margining
■
■
1.75ꢀ Total DC Output Error (–40°C to 125°C)
■
Current Mode Control/Fast Transient Response
■
Power-Good Tracking and Margining
■
Overcurrent/Thermal Shutdown Protection
■
Onboard Frequency Synchronization
■
Spread Spectrum Frequency Modulation
■
Multiphase Operation
Selectable Burst Mode® Operation
■
The low profile package (2.82mm) enables utilization
of unused space on the back side of PC boards for high
density point-of-load regulation.
■
Output Overvoltage Protection
■
Gold-Pad Finish Allows Soldering with Pb and Pb-
Free Solder Paste
■
Fault protection features include overvoltage protection,
overcurrent protection and thermal shutdown. The power
moduleisofferedinaspacesavingandthermallyenhanced
15mm × 15mm × 2.82mm LGA package. The LTM4616 is
Pb-free and RoHS compliant.
Small Surface Mount Footprint, Low Profile
(15mm × 15mm × 2.82mm) LGA Package
APPLICATIONS
■
Telecom, Networking and Industrial Equipment
Different Combinations of Input and Output
■
Storage and ATCA, PCI Express Cards
Number of Inputs
Number of Outputs
I
(MAX)
OUT
■
Battery Operated Equipment
2
2
1
1
2
1
2
1
8A, 8A
L, LT, LTC, LTM and Burst Mode are registered trademarks of Linear Technology Corporation.
μModule is a trademark of Linear Technology Corporation. All other trademarks are the property
of their respective owners. Protected by U.S. Patents, including 5481178, 6580258, 6304066,
6127815, 6498466, 6611131, 6724174.
16A
8A, 8A
16A
TYPICAL APPLICATION
Efficiency vs Load Current
95
90
85
80
75
Dual Output DC/DC μModule™ Regulator
5V 3.3V
IN
OUT
V
5V
IN1
V
OUT1
V
V
IN1
OUT1
FB1
3.3V/8A
5V 2.5V
IN
OUT
100μF
10μF
LTM4616
ITHM1
2.21k
3.09k
V
3.3V TO 5V
10μF
IN2
V
OUT2
V
V
IN2
OUT2
FB2
2.5V/8A
100μF
ITHM2
GND2
70
0
GND1
2
4
6
8
4616 TA01a
LOAD CURRENT (A)
4616 TA01b
4616fa
1
LTM4616
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
V
, SV , V , SV ................................–0.3V to 6V
TOP VIEW
IN1
IN1 IN2 IN2
V
SGND2 & CONTROL
V
IN2
OUT2
CLKOUT1, CLKOUT2....................................–0.3V to 2V
PGOOD1, PLLLPF1, CLKIN1, PHMODE1,
M
L
MODE1, PGOOD2, PLLLPF2, CLKIN2,
K
J
PHMODE2, MODE2................................. –0.3V to V
IN
I
, I
, RUN1, FB1, TRACK1, MGN1,
GND2
TH1 THM1
H
G
F
SW2,
I/O & CONTROL
BSEL1, I , I
, RUN2, FB2, TRACK2,
TH2 THM2
MGN2, BSEL2......................................... –0.3V to V
IN
IN
SGND1 & CONTROL
V
, V
, SW1, SW2............................ –0.3V to V
OUT1 OUT2
V
E
OUT1
V
IN1
Internal Operating Temperature Range
D
C
B
A
(Note 2) .............................................–40°C to 125°C
Junction Temperature ........................................... 125°C
Storage Temperature Range...................–55°C to 125°C
GND1
1
2
3
4
5
6
7
8
9
10
11
12
SW1, I/O & CONTROL
LGA PACKAGE
144-LEAD (15mm × 15mm × 2.8mm)
T
= 125°C, θ = 2°C/W, θ = 16°C/W
JP JC
JMAX
ORDER INFORMATION
LEAD FREE FINISH
LTM4616EV#PBF
LTM4616IV#PBF
TRAY
PART MARKING*
PACKAGE DESCRIPTION
INTERNAL TEMPERATURE RANGE
–40°C to 125°C
LTM4616EV#PBF
LTM4616IV#PBF
LTM4616V
144-Lead (15mm × 15mm × 2.82mm) LGA
144-Lead (15mm × 15mm × 2.82mm) LGA
LTM4616V
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
The ● denotes the specifications which apply over the –40°C to 125°C
ELECTRICAL CHARACTERISTICS
internal operating temperature range. TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specified
as each channel (Note 3).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
●
●
V
V
Input DC Voltage
2.7
5.5
V
IN1(DC), IN2(DC)
V
, V
Output Voltage, Total Variation
with Line and Load
C
V
= 10μF × 1, C
= 100μF Ceramic,
OUT
OUT1(DC) OUT2(DC)
IN
100μF POSCAP, R = 6.65k
1.472
1.464
1.49
1.49
1.508
1.516
V
V
FB
= 2.7V to 5.5V,
IN
I
= I
to I
(Note 4)
OUT(DC)MAX
OUT
OUT(DC)MIN
Input Specifications
V
V
,
Undervoltage Lockout Threshold SV Rising
2.05
1.85
2.2
2.0
2.35
2.15
V
V
IN1(UVLO)
IN2(UVLO)
IN
SV Falling
IN
4616fa
2
LTM4616
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the –40°C to 125°C
internal operating temperature range. TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specified
as each channel (Note 3).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input Supply Bias Current
V
IN
V
IN
V
IN
= 3.3V, V
= 3.3V, V
= 3.3V, V
= 1.5V, No Switching, Mode = V
IN
= 1.5V, No Switching, Mode = 0V
= 1.5V, Switching Continuous
400
1.15
55
μA
mA
mA
Q(VIN1, VIN2)
OUT
OUT
OUT
V
V
V
= 5V, V
= 5V, V
= 5V, V
= 1.5V, No Switching, Mode = V
IN
= 1.5V, No Switching, Mode = 0V
= 1.5V, Switching Continuous
450
1.3
75
μA
mA
mA
IN
IN
IN
OUT
OUT
OUT
Shutdown, RUN = 0, V = 5V
1
μA
IN
I
Input Supply Current
V
IN
V
IN
= 3.3V, V
= 1.5V, I = 8A
OUT
4.5
2.93
A
A
S(VIN1, VIN2)
OUT
= 5V, V
= 1.5V, I
= 8A
OUT
OUT
Output Specifications
I
I
Output Continuous Current Range V
(Note 4)
= 1.5V
OUT1(DC), OUT2(DC)
OUT
V
= 3.3V, 5.5V
0
0
8
5
A
A
IN
IN
V
= 2.7V
●
ΔV
ΔV
/V
Line Regulation Accuracy
Load Regulation Accuracy
V
= 1.5V, V from 2.7V to 5.5V, I
= 0A
0.1
0.25
%/V
OUT1(LINE) OUT1
OUT
IN
OUT
/V
OUT2(LINE) OUT2
ΔV
ΔV
/V
/V
V
OUT
= 1.5V (Note 4)
OUT1(LOAD) OUT1
OUT2(LOAD) OUT2
●
●
V
V
= 3.3V, 5.5V, I = 0A to 8A
LOAD
0.3
0.3
0.5
0.5
%
%
IN
IN
= 2.7V, I
= 0A to 5A
LOAD
V
, V
Output Ripple Voltage
I
= 0A, C
OUT
= 100μF X5R Ceramic, V = 5V,
OUT IN
OUT1(AC) OUT2(AC)
OUT
V
= 1.5V
10
mV
P-P
f
f
f
Switching Frequency
SYNC Capture Range
Turn-On Overshoot
I
= 8A, V = 5V, V = 1.5V
OUT
1.25
0.75
1.5
1.75
2.25
MHz
MHz
S1, S2
OUT
IN
f
SYNC1, SYNC2
ΔV
ΔV
C
= 100μF, V
= 1.5V, I
= 0A
OUT
OUT1(START),
OUT2(START)
OUT
V
OUT
= 3.3V
= 5V
10
10
mV
mV
IN
IN
V
t
t
Turn-On Time
C
= 100μF, V
= 1.5V, V = 5V,
IN
START1, START2
OUT
OUT
OUT
I
= 1A Resistive Load, Track = V
100
20
μs
IN
ΔV
ΔV
Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load,
mV
OUT1(LS),
OUT2(LS)
C
V
= 100μF Ceramic x2, 470μF POSCAP,
OUT
IN
= 5V, V
= 1.5V
OUT
t
I
t
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load, V = 5V,
OUT
10
μs
SETTLE1, SETTLE2
IN
V
= 1.5V, C
= 100μF
OUT
I
Output Current Limit
C
= 100μF
OUT1(PK), OUT2(PK)
OUT
V
= 2.7V, V
= 3.3V, V
= 1.5V
= 1.5V
8
11
13
A
A
A
IN
IN
IN
OUT
OUT
V
V
= 5V, V
= 1.5V
OUT
Control Section
FB1, FB2
Voltage at FB Pin
I
= 0A, V
= 1.5V, V = 2.7V to 5.5V
0.590
0.587
0.596
0.596
0.602
0.606
V
V
OUT
OUT
IN
●
SS Delay
Internal Soft-Start Delay
90
μs
I
FB
0.2
μA
V
V
RUN Pin On/Off Threshold
RUN Rising
RUN Falling
1.4
1.3
1.55
1.4
1.7
1.5
V
V
RUN1, RUN2
TRACK1, TRACK2
Tracking Threshold (Rising)
Tracking Threshold (Falling)
Tracking Disable Threshold
RUN = V
0.57
0.18
IN
V
V
V
IN
RUN = 0V
V
– 0.5
4616fa
3
LTM4616
ELECTRICAL CHARACTERISTICS The ● denotes the specifications which apply over the –40°C to 125°C
internal operating temperature range. TA = 25°C, VIN = 5V unless otherwise noted. Per the typical application in Figure 18. Specified
as each channel (Note 3).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
R
R
Resistor Between V
and FB
OUT
9.95
10
10.05
kΩ
FBHI1, FBHI2
Pins
ΔV
ΔV
PGOOD2
PGOOD Range
10
%
PGOOD1,
%Margining
Output Voltage Margining
Percentage
MGN = V , BSEL = 0V
4
9
14
–4
–9
–14
5
6
%
%
%
%
%
%
IN
MGN = V , BSEL = V
10
11
IN
IN
MGN = V , BSEL = Float
15
–5
–10
–15
16
–6
–11
–16
IN
MGN = 0V, BSEL = 0V
MGN = 0V, BSEL = V
IN
MGN = 0V, BSEL = Float
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4616E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4616I is guaranteed to meet specifications over the full
internal operating temperature range. Note that the maximum ambient
temperature is determined by specific operating conditions in conjunction
with board layout, the rated package thermal resistance and other
environmental factors.
Note 3: Two channels are tested separately and the same testing
conditions are applied to each channel.
Note 4: See Output Current Derating curves for different V , V
and T .
A
IN OUT
Specified as Each Channel
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current
Efficiency vs Load Current
Efficiency vs Load Current
100
95
90
85
80
75
70
100
95
100
95
CONTINUOUS MODE
CONTINUOUS MODE
CONTINUOUS MODE
90
85
90
85
80
75
70
80
75
70
5V 1.2V
IN
OUT
OUT
OUT
OUT
OUT
3.3V 1.2V
IN
OUT
OUT
OUT
OUT
5V 1.5V
IN
2.7V 1.0V
3.3V 1.5V
IN
IN
OUT
OUT
OUT
5V 1.8V
IN
2.7V 1.5V
IN
3.3V 1.8V
IN
3.3V 2.5V
IN
5V 2.5V
IN
2.7V 1.8V
IN
5V 3.3V
IN
0
2
3
4
5
6
7
0
2
4
6
8
1
0
2
4
6
8
LOAD CURRENT (A)
LOAD CURRENT
LOAD CURRENT
4616 G03
4616 G02
4616 G01
4616fa
4
LTM4616
TYPICAL PERFORMANCE CHARACTERISTICS Specified as Each Channel
Burst Mode Efficiency with
5V Input
VIN to VOUT Step-Down Ratio
VIN to VOUT Step-Down Ratio
100
90
80
70
60
50
40
4.0
3.5
3.0
2.5
4.0
3.5
3.0
2.5
I
= 5A
I
= 8A
OUT
OUT
V
V
V
V
V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
V
V
V
V
V
= 1.2V
= 1.5V
= 1.8V
= 2.5V
= 3.3V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
2.0
1.5
2.0
1.5
1.0
0.5
0
1.0
0.5
0
V
V
V
= 1.5V
= 2.5V
= 3.3V
OUT
OUT
OUT
1
2
4
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1
LOAD CURRENT (A)
1
2
4
0
5
6
0
5
6
3
3
V
(V)
V
(V)
IN
IN
4616 G04
4616 G06
4616 G05
Supply Current vs VIN
Load Transient Response
Load Transient Response
1.6
1.4
1.2
1
V
= 1.2V PULSE-SKIPPING MODE
I
I
O
V
LOAD
LOAD
1A/DIV
1A/DIV
V
V
OUT
OUT
0.8
0.6
0.4
0.2
0
50mV/DIV
50mV/DIV
= 1.2V BURST MODE
O
4616 G08
4616 G09
V
V
= 5V
20μs/DIV
V
V
= 5V
20μs/DIV
IN
OUT
IN
OUT
= 3.3V
= 2.5V
2A/μs STEP
= 2 × 100μF X5R, 470μF 4V POSCAP
2A/μs STEP
= 2 × 100μF X5R, 470μF 4V POSCAP
C
C
OUT
OUT
2.5
3
3.5
4
4.5
5
5.5
INPUT VOLTAGE (V)
4616 G07
Load Transient Response
Load Transient Response
Load Transient Response
I
I
LOAD
LOAD
I
LOAD
1A/DIV
1A/DIV
1A/DIV
V
V
V
OUT
OUT
OUT
50mV/DIV
50mV/DIV
50mV/DIV
4616 G10
4616 G11
4616 G12
V
V
= 5V
20μs/DIV
V
V
= 5V
20μs/DIV
V
V
= 5V
20μs/DIV
IN
OUT
IN
OUT
IN
OUT
= 1.8V
= 1.5V
= 1.2V
2.5A/μs STEP
= 2 × 100μF X5R, 470μF 4V POSCAP
2.5A/μs STEP
= 2 × 100μF X5R, 470μF 4V POSCAP
2.5A/μs STEP
= 2 × 100μF X5R, 470μF POSCAP
C
C
C
OUT
OUT
OUT
4616fa
5
LTM4616
TYPICAL PERFORMANCE CHARACTERISTICS Specified as Each Channel
Start-Up
VFB vs Temperature
Load Regulation vs Current
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
602
600
598
596
594
592
590
V
OUT
0.5V/DIV
V
V
= 5.5V
= 3.3V
IN
IN
V
IN
2V/DIV
V
= 2.7V
IN
4616 G13
V
V
C
= 5V
50μs/DIV
IN
FC MODE
= 1.5V
OUT
OUT
V
V
= 3.3V
IN
OUT
= 100μF NO LOAD AND 8A LOAD
= 1.5V
(DEFAULT 100μs SOFT-START)
–25
0
50
–50
75 100 125
25
0
2
4
6
8
LOAD CURRENT (A)
TEMPERATURE (°C)
4616 G14
4616 G15
Short-Circuit Protection
(2.5V Short, No Load)
Short-Circuit Protection
(2.5V Short, 4A Load)
2.5V Output Current
3.0
2.5
V
IN
5V/DIV
5V/DIV
2V/DIV
2V/DIV
V
V
IN
OUT
V
OUT
OUT
2.0
1.5
I
LOAD
OUT
5A/DIV
5A/DIV
5A/DIV
I
I
SHORT
OUT
1.0
0.5
0
4616 G17
4616 G18
V
V
= 5V
50μs/DIV
V
V
= 5V
50μs/DIV
IN
OUT
IN
OUT
= 2.5V
= 2.5V
0
5
10
15
20
OUTPUT CURRENT (A)
4616 G16
PIN FUNCTIONS
IN1 IN2
GND1 and GND2 (BANK2 and BANK5); (A1-A5, A12, B1-
B5, B7-B12, C3-C12, D3-D7) and (G1-G5, G12, H1-H5,
H7-H12, J3-J12, K3-K7): Power Ground Pins for Both
Input and Output Returns.
V
, V , (BANK1 and BANK2); (F1-F4, E1-E4, C1-C2,
D1-D2) and (J1-J2, K1-K2, L1-L4, M1-M4): Power Input
Pins. Apply input voltage between these pins and GND
pins. Recommend placing input decoupling capacitance
directly between V pins and GND pins.
IN
SV andSV (E5andL5):SignalInputVoltageforEach
IN1
IN2
Channel. This pin is internally connected to V through
V , V
OUT1 OUT2
(BANK3 and BANK6); (D9-D12, E9-E12,
IN
a lowpass filter.
F9-F12) and (K9-K12, L9-L12, M9-M12): Power Output
Pins. Apply output load between these pins and GND
pins. Recommend placing output decoupling capacitance
directly between these pins and GND pins. See Table 1.
SGND1 and SGND2 (F5 and M5): Signal Ground Pin for
Each Channel. Return ground path for all analog and low
power circuitry. Tie a single connection to the output
capacitor GND in the application. See layout guidelines
in Figure 17.
4616fa
6
LTM4616
PIN FUNCTIONS
MODE1 and MODE2 (A8 and G8): Mode Select Input for
Each Channel. Tying this pin high enables Burst Mode
operation. Tying this pin low enables forced continuous
operation. Floating this pin or tying it to V /2 enables
pulse-skipping operation.
Pin for Each Channel. Voltage tracking is enabled when
the TRACK voltage is below 0.57V. If tracking is not
desired, then connect the TRACK pin to SV . If TRACK
IN
is not tied to SV , then the TRACK pin’s voltage needs to
IN
IN
be below 0.18V before the chip shuts down even though
RUN is already low. Do not float this pin. A resistor and
capacitor can be applied to the TRACK pin to increase the
soft-start time of the regulator. TRACK1 and TRACK2 can
be tied together for parallel operation and tracking. See
the Applications section.
CLKIN1andCLKIN2(A7andG7):ExternalSynchronization
Input to Phase Detector for Each Channel. This pin is
internally terminated to SGND with a 50k resistor. The
phase-locked loop will force the internal top power PMOS
turn on to be synchronized with the rising edge of the
CLKIN signal. Connect this pin to SV to enable spread
FB1 and FB2 (D8 and K8): The Negative Input of the Error
IN
spectrum modulation. During external synchronization,
AmplifierforEachChannel.Internally,thispinisconnected
make sure the PLLLPF pin is not tied to V or GND.
to V
with a 10k precision resistor. Different output
IN
OUT
voltages can be programmed with an additional resistor
between FB and GND pins. In PolyPhase® operation, tying
the FB pins together allows for parallel operation. See
Applications section for details.
PLLLPF1 and PLLLPF2 (E6 and L6): Phase-Locked Loop
Lowpass Filter for Each Channel. An internal lowpass filter
is tied to this pin. In spread spectrum mode, placing a
capacitor here to SGND controls the slew rate from one
frequencytothenext. Alternatively, floatingthispinallows
I
and I (F8 and M8): Current Control Threshold and
TH2
TH1
normalrunningfrequencyat1.5MHz,tyingthispintoSV
ErrorAmplifierCompensationPointforEachChannel. The
current comparator threshold increases with this control
voltage. Tie together in parallel operation.
IN
forces the part to run at 1.33 times its normal frequency
(2MHz), tying it to ground forces the frequency to run at
0.67 times its normal frequency (1MHz).
I
andI
(E7andL7):NegativeInputtotheInternal
THM1
THM2
PHMODE1 and PHMODE2 (A9 and G9): Phase Selector
Input for Each Channel. This pin determines the phase
relationshipbetweentheinternaloscillatorandCLKOUT.Tie
ithighfor2-phaseoperation,tieitlowfor3-phaseoperation,
I
Differential Amplifier for Each Channel. Tie this pin to
TH
SGND for single phase operation on each channel. For
PolyPhase operation, tie the master’s I
connecting all of the I
to SGND while
THM
pins together at the master.
THM
and float or tie it to V /2 for 4-phase operation.
IN
PGOOD1 and PGOOD2 (A11 and G11): Output Voltage
Power Good Indicator for Each Channel. Open-drain logic
output that is pulled to ground when the output voltage
is not within 10% of the regulation point. Power good
is disabled during margining.
MGN1 and MGN2 (A10 and G10): Voltage Margining Pin
forEachChannel.TiethispintoV
todisablemargining.
OUT
For margining, connect a voltage divider from V to GND
IN
with the center point connected to the MGN pin for the
specific channel. Each resistor should be close to 50k.
RUN1 and RUN2 (F6 and M6): Run Control Pin. A voltage
above 1.5V will turn on the module.
Margin High is within 0.3V of V , and Margin Low is
IN
within 0.3V of GND. See the Applications section and
Figure 18 for margining control. The specified tri-state
drivers are capable of the high and low requirements for
margining.
SW1 and SW2 (B6 and H6): Switching Node of Each
Channel That is Used for Testing Purposes. This can be
connected to copper on the board for improved thermal
performance.
BSEL1 and BSEL2 (A6 and G6): Margining Bit Select Pin
for Each Channel. Tying BSEL low selects 5% margin
value, tying it high selects 10% margin value. Floating it
CLKOUT1 and CLKOUT2 (F7 and M7): Output Clock
Signal for PolyPhase Operation. The phase of CLKOUT is
determined by the state of the PHMODE pin.
or tying it to V /2 selects 15% margin value.
IN
TRACK1andTRACK2(E8andL8):OutputVoltageTracking
PolyPhase is a registered trademark of Linear Technology Corporation.
4616fa
7
LTM4616
SIMPLIFIED BLOCK DIAGRAM
V
SGND2 & CONTROL
V
IN2
OUT2
M
L
K
J
GND2
H
G
F
SW2,
I/O & CONTROL
SGND1 & CONTROL
V
E
OUT1
V
IN1
D
C
B
A
GND1
1
2
3
4
5
6
7
8
9
10
11
12
SW1, I/O & CONTROL
4616 F01
TOP VIEW OF LGA PINOUT
LOOKING THROUGH COMPONENT
SV
IN1
V
INTERNAL
FILTER
IN1
3V TO 5.5V
+
+
TRACK1
10μF
10μF
10μF
C
IN1
PGND1
MGN1
BSEL1
V
OUT1
M1
M2
SW1
PGOOD1
MODE1
L
V
1.5V
8A
OUT1
POWER
CONTROL
RUN1
CLKIN1
CLKOUT1
PHMODE1
10μF
C
OUT1
PGND1
I
TH1
INTERNAL
COMP
50k
10k
PLLLPF1
FB1
INTERNAL
FILTER
R
SET1
6.65k
I
THM1
PGND1
SGND1
SV
IN2
V
INTERNAL
FILTER
IN2
3V TO 5.5V
+
+
TRACK2
10μF
10μF
10μF
C
IN2
PGND2
MGN2
BSEL2
V
OUT2
M3
M4
SW2
PGOOD2
MODE2
L
V
1.2V
8A
OUT2
POWER
CONTROL
RUN2
CLKIN2
CLKOUT2
PHMODE2
10μF
C
OUT2
PGND2
I
TH2
INTERNAL
COMP
50k
10k
PLLLPF2
FB2
INTERNAL
FILTER
R
SET2
10k
I
THM2
PGND2
SGND2
4616 BD
Figure 1. Simplified LTM4616 Block Diagram
4616fa
8
LTM4616
SIMPLIFIED BLOCK DIAGRAM
Table 1. Decoupling Requirements. TA = 25°C, Block Diagram Configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
C
External Input Capacitor Requirement
IN1
IN2
(V = 2.7V to 5.5V, V
= 1.5V)
= 2.5V)
I
I
= 8A
= 8A
22
22
μF
μF
IN1
OUT1
OUT2
OUT1
OUT2
(V = 2.7V to 5.5V, V
IN2
C
OUT1
C
OUT2
External Output Capacitor Requirement
(V = 2.7V to 5.5V, V
= 1.5V)
= 2.5V)
I
I
= 8A
= 8A
100
100
μF
μF
IN1
OUT1
OUT2
OUT1
OUT2
(V = 2.7V to 5.5V, V
IN2
OPERATION
Pulling the RUN pins below 1.3V forces the regulators
into a shutdown state, by turning off both MOSFETs. The
TRACK pin is used for programming the output voltage
ramp and voltage tracking during start-up. See Applica-
tions Information section.
The LTM4616 is a dual-output standalone nonisolated
switching mode DC/DC power supply. It can provide two
8A outputs with few external input and output capacitors.
This module provides precisely regulated output voltages
programmable via external resistors from 0.6V to 5V
DC
DC
over 2.7V to 5.5V input voltages. The typical application
The LTM4616 is internally compensated to be stable over
all operating conditions. Table 3 provides a guideline for
inputandoutputcapacitancesforseveraloperatingcondi-
tions. The Linear Technology μModule Power Design Tool
will be provided for transient and stability analysis. The
FB pin is used to program the output voltage with a single
external resistor to ground.
schematic is shown in Figure 18.
The LTM4616 has integrated constant frequency current
mode regulators and built-in power MOSFET devices with
fast switching speed. The typical switching frequency is
1.5MHz. For switching noise sensitive applications, it can
be externally synchronized from 0.75MHz to 2.25MHz.
Even spread spectrum switching can be implemented in
the design to reduce noise.
Multiphase operation can be easily employed with the
synchronizationandphasemodecontrols.Upto12phases
canbecascadedtorunsimultaneouslywithrespecttoeach
otherbyprogrammingthePHMODEpintodifferentlevels.
The LTM4616 has clock in and clock out for poly phasing
multiple devices or frequency synchronization.
With current mode control and internal feedback loop
compensation, the LTM4616 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
High efficiency at light loads can be accomplished with
selectableBurstModeoperationusingtheMODEpin.These
light load features will accommodate battery operation.
Efficiency graphs are provided for light load operation in
the Typical Performance Characteristics section.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limit and thermal shutdown in an overcurrent condition.
Internal overvoltage and undervoltage comparators pull
the open-drain PGOOD output low if the output feedback
voltage exits a 10% window around the regulation point.
The power good pins are disabled during margining.
Output voltage margining is supported, and can be pro-
gramed from 5% to 15% using the MGN and BSEL
pins.
4616fa
9
LTM4616
APPLICATIONS INFORMATION
The typical LTM4616 application circuit is shown in
Figure 18. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 3 for specific external capacitor
requirements for a particular application.
step is required up to the 4A level. A 47μF to 100μF
surface mount aluminum electrolytic bulk capacitor can
be used for more input bulk capacitance. This bulk input
capacitor is only needed if the input source impedance is
compromisedbylonginductiveleads,tracesornotenough
source capacitance. If low impedance power planes are
used, then this 47μF capacitor is not needed.
V to V
Step-Down Ratios
IN
OUT
There are restrictions in the maximum V to V
step-
For a buck converter, the switching duty-cycle can be
estimated as:
IN
OUT
down ratio that can be achieved for a given input voltage.
Each output of the LTM4616 is 100% duty cycle, but the
VOUT
V to V
IN
minimum drop out is still shown as a function
OUT
D =
V
of its load current. For 5V input, all outputs can deliver 8A.
For 3.3V input, all outputs can deliver 8A, except 2.5V
IN
OUT
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
which is limited to 6A. All outputs derived from 2.7V input
are limited to 5A.
IOUT(MAX)
ICIN(RMS)
=
• D • 1– D
Output Voltage Programming
(
)
η%
The PWM controller has an internal 0.596V reference
voltage. As shown in the Block Diagram, a 10k 0.5%
Intheaboveequation,η%istheestimatedefficiencyofthe
power module so the RMS input current at the worst case
for 8A maximum current is about 4A. The bulk capacitor
can be a switcher-rated electrolytic aluminum capacitor,
polymercapacitorforbulkinputcapacitance.Eachinternal
10μF ceramic input capacitor is typically rated for 2 amps
of RMS ripple current.
internal feedback resistor connects V
and FB pins
OUT
together. The output voltage will default to 0.596V with
no feedback resistor. Adding a resistor R from FB pin
FB
to GND programs the output voltage:
10k + RFB
VOUT = 0.596V •
RFB
Output Capacitors
Table 2. FB Resistor vs Various Output Voltages
The LTM4616 is designed for low output voltage ripple
V
0.596V
Open
1.2V
10k
1.5V
1.8V
2.5V
3.3V
OUT
noise. The bulk output capacitors defined as C
are
OUT
R
6.65k
4.87k
3.09k
2.21k
FB
chosenwithlowenougheffectiveseriesresistance(ESR)to
meettheoutputvoltagerippleandtransientrequirements.
For parallel operation of N the below equation can be
C
can be a low ESR tantalum capacitor, low ESR
used to solve for R . Tying the FB pins together for each
OUT
FB
polymercapacitororceramiccapacitor.Thetypicaloutput
capacitancerangeisfrom47μFto220μF.Additionaloutput
filtering may be required by the system designer, if further
reduction of output ripples or dynamic transient spikes is
required.Table3showsamatrixofdifferentoutputvoltages
and output capacitors to minimize the voltage droop and
overshoot during a 3A/μs transient. The table optimizes
totalequivalentESRandtotalbulkcapacitancetooptimize
thetransientperformance.Stabilitycriteriaareconsidered
in the Table 3 matrix, and the Linear Technology μModule
Power Design Tool will be provided for stability analysis.
parallel output:
10k /N
RFB =
VOUT
0.596
−1
Input Capacitors
The LTM4616 module should be connected to a low AC
impedance DC source. For each regulator, three 10μF
ceramic capacitors are included inside the module.
Additional input capacitors are only needed if a large load
4616fa
10
LTM4616
APPLICATIONS INFORMATION
Table 3. Output Voltage Response Versus Component Matrix (Refer to Figure 18) 0A to 3A Load Step
TYPICAL MEASURED VALUES
C
OUT1
VENDORS
VALUE
PART NUMBER
C
OUT2
VENDORS
VALUE
PART NUMBER
TDK
22μF, 6.3V
22μF, 16V
100μF, 6.3V
100μF, 6.3V
C3216X7S0J226M
GRM31CR61C226KE15L
C4532X5R0J107MZ
GRM32ER60J107M
Sanyo POSCAP
470μF, 4V
4TPE470M
Murata
TDK
C
IN
(BULK) VENDORS VALUE
PART NUMBER
10CE100FH
Sanyo
100μF, 10V
Murata
V
C
C
C
C
V
(V)
DROOP PEAK-TO- PEAK
RECOVERY
TIME (μs)
LOAD STEP
R
FB
OUT
IN
IN
OUT1
OUT2
IN
(V)
1.0
1.0
1.0
1.0
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
3.3
3.3
(CERAMIC) (BULK)* (CERAMIC)
(BULK)
I
C1
C3
(mV)
20
30
30
25
20
20
30
30
32
25
22
25
30
25
42
25
35
25
35
35
35
32
50
32
65
40
DEVIATION (mV)
(A/μs)
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
(kΩ)
14.7
14.7
14.7
14.7
10
TH
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
10μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF
100μF × 2
100μF × 2
100μF × 2
22μF × 1
100μF × 2
22μF × 1
100μF × 2
22μF × 1
100μF × 2
22μF × 1
100μF × 1
22μF × 1
100μF × 2
22μF × 1
100μF × 1
22μF × 1
100μF × 2
22μF × 1
100μF × 2
22μF × 1
100μF × 1
22μF × 1
100μF × 1
22μF × 1
100μF × 1
22μF × 1
470μF
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
5
40
60
60
50
40
41
60
60
64
50
42
50
60
50
80
50
70
50
70
20
40
65
100
65
135
87
40
25
25
25
25
25
20
25
20
25
25
25
25
25
25
30
30
30
30
30
30
40
30
40
30
40
5
2.7
2.7
5
470μF
470μF
470μF
470μF
470μF
470μF
470μF
470μF
470μF
470μF
470μF
470μF
5
10
2.7
2.7
5
10
10
6.65
6.65
6.65
6.65
6.65
6.65
4.87
4.87
4.87
4.87
4.87
4.87
3.09
3.09
3.09
3.09
2.21
2.21
5
3.3
3.3
2.7
2.7
5
5
3.3
3.3
2.7
2.7
5
5
3.3
3.3
5
5
*Bulk capacitance is optional if V has very low input impedance.
IN
Multiphase operation will reduce effective output ripple as
a function of the number of phases. Application Note 77
discusses this noise reduction versus output ripple cur-
rent cancellation, but the output capacitance will be more
a function of stability and transient response. The Linear
Technology μModule Power Design Tool will calculate the
output ripple reduction as the phase number increases
by N times.
Burst Mode Operation
The LTM4616 is capable of Burst Mode operation on
each regulator in which the power MOSFETs operate
intermittentlybasedonloaddemand,thussavingquiescent
current. For applications where maximizing the efficiency
at very light loads is a high priority, Burst Mode operation
shouldbeapplied.ToenableBurstModeoperation,simply
tie the MODE pin to V . During this operation, the peak
IN
current of the inductor is set to approximately 20% of
4616fa
11
LTM4616
APPLICATIONS INFORMATION
the maximum peak current value in normal operation
mode is disabled and inductor current is prevented
from reversing until the LTM4616’s output voltage is in
regulation. Each regulator can be configured for Forced
Continuous mode.
even though the voltage at the I pin indicates a lower
TH
value. The voltage at the I pin drops when the inductor’s
TH
average current is greater than the load requirement. As
the I voltage drops below 0.2V, the BURST comparator
TH
Multiphase Operation
trips, causing the internal sleep line to go high and turn
off both power MOSFETs.
For output loads that demand more than 8A of current,
two outputs in LTM4616 or even multiple LTM4616s can
be cascaded to run out-of-phase to provide more output
currentwithoutincreasinginputandoutputvoltageripple.
The CLKIN pin allows the LTC4616 to synchronize to an
external clock (between 0.75MHz and 2.25MHz) and the
internal phase-locked loop allows the LTM4616 to lock
onto CLKIN’s phase as well. The CLKOUT signal can be
connectedtotheCLKINpinofthefollowingLTM4616stage
to line up both the frequency and the phase of the entire
In Burst Mode operation, the internal circuitry is partially
turned off, reducing the quiescent current to about 450μA
for each output. The load current is now being supplied
fromtheoutputcapacitors.Whentheoutputvoltagedrops,
causingI toriseabove0.25V,theinternalsleeplinegoes
TH
low,andtheLTM4616resumesnormaloperation.Thenext
oscillator cycle will turn on the top power MOSFET and the
switching cycle repeats. Each regulator can be configured
for BurstModeoperation.
system. Tying the PHMODE pin to SV , SGND or SV /2
IN
IN
Pulse-Skipping Mode Operation
(floating) generates a phase difference (between CLKIN
and CLKOUT) of 180°, 120° or 90° respectively, which
correspondstoa2-phase,3-phaseor4-phaseoperation.A
total of 12 phases can be cascaded to run simultaneously
with respect to each other by programming the PHMODE
pin of each LTM4616 to different levels. For a 6-phase
example in Figure 2, the 2nd stage that is 120° out-of-
phase from the 1st stage can generate a 240° (PHMODE
= 0) CLKOUT signal for the 3rd stage, which then can
generate a CLKOUT signal that’s 420°, or 60° (PHMODE
Inapplicationswherelowoutputrippleandhighefficiency
atintermediatecurrentsaredesired, pulse-skippingmode
should be used. Pulse-skipping operation allows the
LTM4616toskipcyclesatlowoutputloads,thusincreasing
efficiencybyreducingswitchingloss.FloatingtheMODEpin
or tying it to V /2 enables pulse-skipping operation. This
IN
allows discontinuous conduction mode (DCM) operation
down to near the limit defined by the chip’s minimum
on-time (about 100ns). Below this output current level,
the converter will begin to skip cycles in order to maintain
output regulation. Increasing the output load current
slightly, above the minimum required for discontinuous
conduction mode, allows constant frequency PWM. Each
regulator can be configured for Pulse-Skipping mode.
= SV ) for the 4th stage. With the 60° CLKIN input, the
IN
next two stages can shift 120° (PHMODE = 0) for each
to generate a 300° signal for the 6th stage. Finally, the
signal with a 60° phase shift on the 6th stage (PHMODE
is floating) goes back to the 1st stage. Figure 3 shows the
configuration for 12-phase operation.
Forced Continuous Operation
A multiphase power supply significantly reduces the
amount of ripple current in both the input and output
capacitors. The RMS input ripple current is reduced by,
and the effective ripple frequency is multiplied by, the
number of phases used (assuming that the input voltage
isgreaterthanthenumberofphasesusedtimestheoutput
voltage). The output ripple amplitude is also reduced by
the number of phases used.
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
outputrippleisdesired,forcedcontinuousoperationshould
be used. Forced continuous operation can be enabled by
tying the MODE pin to GND. In this mode, inductor current
is allowed to reverse during low output loads, the I
TH
voltage is in control of the current comparator threshold
throughout, and the top MOSFET always turns on with
each oscillator pulse. During start-up, forced continuous
The LTM4616 device is an inherently current mode con-
trolled device, so parallel modules will have very good
4616fa
12
LTM4616
APPLICATIONS INFORMATION
(420)
60
0
120
240
180
300
+120
+120
+180
+120
+120
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
PHMODE
PHASE 1
PHMODE
PHASE 3
S
PHMODE
PHASE 5
PHMODE
PHASE 2
PHMODE
PHASE 4
PHMODE
VIN
4616 F02
PHASE 6
Figure 2. 6-Phase Operation
(390)
30
0
90
180
270
+90
+90
+90
+120
+90
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
PHMODE
PHASE 1
PHMODE
PHASE 4
PHMODE
PHASE 7
PHMODE
PHASE 10
PHMODE
PHASE 2
(420)
60
120
210
300
150
+90
+90
+120
+90
+90
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
CLKIN CLKOUT
PHMODE
PHASE 5
PHMODE
PHASE 8
PHMODE
PHASE 11
PHMODE
PHASE 3
PHMODE
PHASE 6
4616 F03
240
330
+90
CLKIN CLKOUT
CLKIN CLKOUT
PHMODE
PHASE 9
PHMODE
PHASE 12
Figure 3. 12-Phase Operation
current sharing. This will balance the thermals on the
Spread Spectrum Operation
design. Tie the I pins of each LTM4616 together to share
TH
Switchingregulatorscanbeparticularlytroublesomewhere
electromagnetic interference (EMI) is concerned.
the current evenly. To reduce ground potential noise, tie
the I
pins of all LTM4616s together and then connect
THM
Switching regulators operate on a cycle-by-cycle basis to
transfer power to an output. In most cases, the frequency
ofoperationisfixedbasedontheoutputload.Thismethod
of conversion creates large components of noise at the
frequency of operation (fundamental) and multiples of the
operating frequency (harmonics).
to the SGND of the master at the point it connects to the
output capacitor GND. See layout guideline in Figure 17.
Figure 19 shows a schematic of the parallel design. The
FB pins of the parallel module are tied together.
Input RMS Ripple Current Cancellation
Application Note 77 provides a detailed explanation of
multiphase operation. The input RMS ripple current can-
cellation mathematical derivations are presented, and a
graph is displayed representing the RMS ripple current
reductionasafunctionofthenumberofinterleavedphases.
Figure 4 shows this graph.
To reduce this noise, the LTM4616 can run in spread
spectrum operation by tying the CLKIN pin to SV .
IN
In spread spectrum operation, the LTM4616’s internal
oscillator is designed to produce a clock pulse whose
period is random on a cycle-by-cycle basis but fixed
4616fa
13
LTM4616
APPLICATIONS INFORMATION
0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY FACTOR (V /V
)
O
IN
4616 F04
Figure 4. Normalized Input RMS Ripple Current vs Duty Factor for One to Six Channels (Phases)
between 70% and 130% of the nominal frequency. This
has the benefit of spreading the switching noise over
a range of frequencies, thus significantly reducing the
peak noise. Spread spectrum operation is disabled if
CLKIN is tied to ground or if it’s driven by an external
frequency synchronization signal. A capacitor value
of 0.01μF to 0.1μF be placed from the PLLLPF pin to
ground to control the slew rate of the spread spectrum
frequency change.
V
TRACK
is the track ramp applied to the slave’s track pin.
has a control range of 0V to 0.596V, or the internal
TRACK
V
reference voltage. When the master’s output is divided
down with the same resistor values used to set the slave’s
output, then the slave will coincident track with the master
until it reaches its final value. The master will continue to
its final value from the slave’s regulation point. Voltage
trackingisdisabledwhenV
Figure 5 will be equal to R for coincident tracking.
ismorethan0.596V.R in
TRACK
TA
FB
Thetrackpinofthemastercanbecontrolledbyanexternal
Output Voltage Tracking
ramp or by R and C in Figure 5 referenced to V . The
SR
SR
IN
Output voltage tracking can be programmed externally
using the TRACK pin. The output can be tracked up and
downwithanotherregulator.Themasterregulator’soutput
is divided down with an external resistor divider that is the
sameastheslaveregulator’sfeedbackdividertoimplement
coincident tracking. The LTM4616 uses an accurate 10k
resistor internally for the top feedback resistor. Figure 5
shows an example of coincident tracking:
RC ramp time can be programmed using equation:
ꢀ
ꢃ
ꢀ
ꢃ
0.596V
t = – ln 1–
•RSR • CSR
ꢂ
ꢅ
ꢂ
ꢅ
V
ꢁ
ꢄ
ꢁ
ꢄ
IN
Ratiometric tracking can be achieved by a few simple
calculationsandtheslewratevalueappliedtothemaster’s
trackpin.Asmentionedabove,theTRACKpinhasacontrol
range from 0V to 0.596V. The master’s TRACK pin slew
ꢀ
ꢂ
ꢁ
ꢃ
10k
R
Slave = 1+
• VTRACK
ꢅ
TA ꢄ
4616fa
14
LTM4616
APPLICATIONS INFORMATION
rate is directly equal to the master’s output slew rate in
Volts/Time:
Inratiometrictracking, adifferentslewratemaybedesired
for the slave regulator. R can be solved for when SR is
TB
slower than MR. Make sure that the slave supply slew rate
ischosentobefastenoughsothattheslaveoutputvoltage
will reach it final value before the master output.
MR
• 10k = RTB
SR
where MR is the master’s output slew rate and SR is the
slave’s output slew rate in Volts/Time. When coincident
tracking is desired, then MR and SR are equal, thus R
is equal to 10k. R is derived from equation:
For example: MR = 3.3V/ms and SR = 1.5V/ms. Then
R
TB
= 22.1k. Solve for R to equal to 4.87k.
TA
TB
TA
0.596V
MASTER OUTPUT
SLAVE OUTPUT
RTA
=
VTRACK
V
V
FB
FB
+
–
10k RFB
RTB
whereV isthefeedbackvoltagereferenceoftheregulator
FB
TRACK
and V
is 0.596V. Since R is equal to the 10k top
TB
feedback resistor of the slave regulator in equal slew rate
or coincident tracking, then R is equal to R with V
TA
TB
FB
= V
. Therefore R = 10k and R = 6.65k in Figure
TRACK
TB TA
TIME
4616 F06
5. Figure 6 shows the output voltage for coincident
tracking.
Figure 6. Output Voltage Coincident Tracking
CLKIN1
V
4V TO 5.5V
SW1
CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
IN
MASTER
3.3V/7A
V
V
OUT1
IN1
SV
FB1
IN1
R
RUN
10μF
FB1
RUN1
ITH1
2.21k
100μF
PLLLPF1
MODE1
ITHM1
PGOOD1
BSEL1
RSR
PHMODE1
TRACK1
MGN1
LTM4616
SLAVE
1.5V/8A
V
V
IN2
OUT2
FB2
CSR
SV
IN2
R
RUN
10μF
FB2
RUN2
ITH2
6.65k
100μF
100μF
PLLLPF2
MODE2
PHMODE2
TRACK2
ITHM2
PGOOD2
BSEL2
MASTER
3.3V
PGOOD
BSEL
R
TB
10k
MGN2
R
TA
SW2
SGND1
GND1
SGND2
GND2
6.65k
4616 F05
FOR TRACK1:
1. TIE TO VIN TO DISABLE TRACK WITH DEFAULT 100μs SOFT START
2. APPLY A CONTROL RAMP WITH RSR AND CSR TIED TO V WITH t = –(ln(1–0.596/V ) • RSR • CSR))
IN
IN
3. APPLY AN EXTERNAL TRACKING RAMP DIRECTLY
Figure 5. Dual Outputs (3.3V and 1.5V) with Tracking
4616fa
15
LTM4616
APPLICATIONS INFORMATION
Forapplicationsthatdonotrequiretrackingorsequencing,
MGN pin is low, it forces negative margining, in which the
output voltage is below the regulation point. When MGN is
high, the output voltage is forced to above the regulation
point. The MGN pin with a voltage divider is driven with a
small tri-state gate as shown in Figure 18 for three margin
states, (High, Low, and No Margin). The amount of output
voltage margining is determined by the BSEL pin. When
BSEL is low, it’s 5%. When BSEL is high, it’s 10%. When
BSEL is floating, it’s 15%. When margining is active, the
internaloutputovervoltageandundervoltagecomparators
are disabled and PGOOD remains high.
simply tie the TRACK pin to SV to let RUN control the
IN
turn on/off. Connecting TRACK to SV also enables the
IN
~100μs of internal soft-start during start-up.
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a 10% window around the regulation point. As shown
in Figure 20, the sequencing function can be realized in a
dualoutputapplicationbycontrollingtheRUNpinsandthe
PGOOD signals from each other. The 1.5V output begins
its soft starting after the PGOOD signal of 3.3V output
becomes high, and 3.3V output starts its shutdown after
the PGOOD signal of 1.5V output becomes low. This can
be applied to systems that require voltage sequencing
between the core and sub-power supplies.
Thermal Considerations and Output Current Derating
The power loss curves in Figures 7 and 8 can be used
in coordination with the load current derating curves in
Figures 9 to16 for calculating an approximate θ thermal
JA
resistance for the LTM4616 with various heatsinking and
airflow conditions. Both LTM4616 outputs are placed in
parallel for a total output current of 16A, and the power
loss curves are plotted for specific output voltages up to
16A.Thederatingcurvesareplottedwitheachoutputat8A
combined for a total of 16A. The output voltages are 1.2V,
2.5V and 3.3V. These are chosen to include the lower and
higher output voltage ranges for correlating the thermal
resistance. Thermal models are derived from several
temperature measurements in a controlled temperature
chamber along with thermal modeling analysis. The
junction temperatures are monitored while ambient
temperature increased with and without airflow. The
junctions are maintained at ~115°C while lowering output
Stability Compensation
The module has already been internally compensated
for all output voltages. Table 2 is provided for most ap-
plication requirements. The Linear Technology μModule
Power Design Tool will be provided for other control loop
optimization.
Output Margining
For a convenient system stress test on the LTM4616’s
output, the user can program each output to 5%, 10%
or 15% of its normal operational voltage. The MGN pin is
tied to the output voltage to disable margining. When the
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
1
5V 1.2V
3.3V 1.2V
IN
OUT
OUT
IN
OUT
OUT
5V 3.3V
IN
3.3V 2.5V
IN
0
0
8
0
4
12
16
8
0
4
12
16
LOAD CURRENT (A)
LOAD CURRENT (A)
4616 F08
4616 F07
Figure 7. 1.2V, 2.5V Power Loss
Figure 8. 1.2V, 3.3V Power Loss
4616fa
16
LTM4616
APPLICATIONS INFORMATION
16
14
12
10
8
16
14
12
10
8
16
14
12
10
8
400 LFM
400 LFM
400 LFM
0 LFM
200 LFM
0 LFM
0 LFM
200 LFM
6
6
200 LFM
6
4
4
4
2
2
2
0
0
0
55
70
85
55
70
85
25
40
100
115
25
115
40
100
60
70
80
40
50
90 100 110
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4616 F09
4616 F11
4616 F10
Figure 9. 5VIN to 3.3VOUT
with No Heatsink
Figure 10. 5VIN to 1.2VOUT
with No Heatsink
Figure 11. 5VIN to 3.3VOUT
with BGA Heatsink
16
14
12
10
8
16
14
12
10
8
16
14
12
10
8
400 LFM
400 LFM
0 LFM
400 LFM
0 LFM
0 LFM
200 LFM
200 LFM
6
6
6
200 LFM
4
4
4
2
2
2
0
0
0
60
80
40
100
120
50
70
90
30
110
60
70
80
40
50
90 100 110
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4616 F13
4616 F14
4616 F12
Figure 12. 5VIN to 1.2VOUT
with BGA Heatsink
Figure 13. 3.3VIN to 1.2VOUT
with No Heatsink
Figure 14. 3.3VIN to 2.5VOUT
with No Heatsink
current or power while increasing ambient temperature.
The 115°C is chosen to allow for a 10°C margin window
relative to the maximum 125°C. The decreased output
current will decrease the internal module loss as ambient
temperatureisincreased.ThepowerlosscurvesinFigures7
and 8 show this amount of power loss as a function of
load current that is specified with both channels in paral-
lel. The monitored junction temperature of 115°C minus
the ambient operating temperature specifies how much
moduletemperaturerisecanbeallowed.Asanexample,in
Figure 10 the load current is derated to 10A at ~ 80°C and
the power loss for the 5V to 1.2V at 10A output is ~3W.
If the 80°C ambient temperature is subtracted from the
115°C maximum junction temperature, then difference of
35°C divided by 3.2W equals a 10.9°C/W. Table 4 specifies
a 10.5°C/W value which is very close. Table 4 and Table 5
provide equivalent thermal resistances for 1.2V and 3.3V
outputs, with and without airflow and heatsinking. The
printed circuit board is a 1.6mm thick four layer board
with two ounce copper for the two outer layers and one
ouncecopperforthetwoinnerlayers.ThePCBdimensions
are 95mm × 76mm. The BGA heatsinks are listed below
Table 5. At load currents on each channel from 3A to 8A
(6A to16A in parallel on the derate curves); the thermal
resistance values in Tables 4 and 5 are closely accurate.
As the load currents go below the 3A level on each channel
thethermalresistancestartstoincreaseduetothereduced
power loss on the board. The approximate thermal
resistance values for these lower currents is 15°C/W.
4616fa
17
LTM4616
APPLICATIONS INFORMATION
16
16
14
12
10
8
14
12
400 LFM
400 LFM
10
8
0 LFM
0 LFM
200 LFM
6
6
200 LFM
4
2
0
4
2
0
50 60 70 80 90 100 110
AMBIENT TEMPERATURE (°C)
40
120
50
70
90
30
110
AMBIENT TEMPERATURE (°C)
4616 F15
4616 F16
Figure 15. 3.3VIN 1.2VOUT with BGA Heatsink
Table 4. 1.2V Output
Figure 16. 3.3VIN 2.5VOUT with BGA Heatsink
DERATING CURVE
Figures 10, 13
Figures 10, 13
Figures 10, 13
Figures 12, 15
Figures 12, 15
Figures 12, 15
V
(V)
POWER LOSS CURVE
Figures 7, 8
AIR FLOW (LFM)
HEAT SINK
None
θ
JA
(°C/W)
IN
3.3, 5
3.3, 5
3.3, 5
3.3, 5
3.3, 5
3.3, 5
0
10.5
8.0
7.0
9.5
6.3
5.2
Figures 7, 8
200
400
0
None
Figures 7, 8
None
Figures 7, 8
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figures 7, 8
200
400
Figures 7, 8
Table 5. 3.3V Output
DERATING CURVE
Figure 9
V
IN
(V)
POWER LOSS CURVE
Figure 8
AIR FLOW (LFM)
HEAT SINK
None
θ
(°C/W)
JA
5
0
10.5
8.0
7.0
9.8
7.0
5.5
Figure 9
5
5
5
5
5
Figure 8
200
400
0
None
Figure 9
Figure 8
None
Figure 11
Figure 8
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 11
Figure 8
200
400
Figure 11
Figure 8
Heatsink Manufacturer
Wakefield Engineering
AAVID Thermalloy
Part No: LTN20069
Phone Number: 603-635-2800
Phone Number: 603-224-9988
Part No: 375424B000346
Layout Checklist/Example
Safety Considerations
The high integration of LTM4616 makes the PCB board
layout very simple and easy. However, to optimize
its electrical and thermal performance, some layout
considerations are still necessary.
The LTM4616 modules do not provide isolation from V
IN
to V . There is no internal fuse. If required, a slow blow
OUT
fuse with a rating twice the maximum input current needs
to be provided to protect each unit from catastrophic
failure. The device does support thermal shutdown and
overcurrent protection.
• Use large PCB copper areas for high current paths,
including V , V , PGND1 and PGND2, V
OUT2
and thermal stress.
and
IN1 IN2
OUT1
V
. It helps to minimize the PCB conduction loss
4616fa
18
LTM4616
APPLICATIONS INFORMATION
• Place high frequency ceramic input and output capaci-
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to GND underneath the unit.
tors next to the V , GND and V
pins to minimize
IN
OUT
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• For parallel modules, tie the I , FB and I
pins to-
TH
THM
gether. Use an internal layer to closely connect these
pins together. All of the I pins connect to the SGND
THM
• Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
ofthemasterregulator,thenthemasterSGNDconnects
to GND.
Figure 17 gives a good example of the recommended
layout.
• Do not put vias directly on the pads, unless they are
capped or plated over.
V
V
OUT1
IN1
VIA TO GND 2X
CONTROL1
M
L
C
OUT2
V
OUT1
C
IN1
V
IN1
K
J
H
G
F
GND1
GND1
CONTROL1 & 2
C
OUT2
E
V
OUT2
V
IN2
C
IN2
D
C
B
A
GND2
GND2
1
2
3
4
5
6
7
8
9
10
11
12
4616 F17
GND2
CONTROL2
LTM4616 TOP VIEW
GND2
Figure 17. Recommended PCB Layout
CLKIN1
V
3V TO 5.5V
SW1
CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
IN1
V
OUT1
1.8V/8A
V
V
IN1
OUT1
FB1
SV
IN1
RUN1
100μF
10μF
4.87k
ITH1
PLLLPF1
MODE1
ITHM1
PGOOD1
BSEL1
V
IN
A2
PGOOD
BSEL
+
R4
V
PHMODE1
TRACK1
–
+
50k
OUT
I
I
OE
IN
MGN1
LTM4616
V
IN2
3V TO 5.5V
V
OUT2
V
IN2
V
OUT2
1.5V/8A
GND
R3
50k
SV
FB2
IN2
10μF
5 PIN SC70 PACKAGE
6.65k
RUN2
ITH2
100μF
s2
PLLLPF2
MODE2
PHMODE2
TRACK2
ITHM2
PGOOD2
BSEL2
V
IN
BSEL: HIGH = 10%
FLOAT = 15%
LOW = 5%
A1
PGOOD
BSEL
+
V
A1, A2 PERICOM P174ST1G126CEX
TOSHIBA TC75Z126AFE
R2
50k
–
+
OUT
I
I
OE
MGN2
OE
IN
OUT
MGN MARGIN VALUE
IN
SW2
SGND1
GND1
SGND2
GND2
R1
50k
H
H
L
H
L
X
H
L
Z
H
L
+ Value of BSEL Selection
– Value of BSEL Selection
4616 F18
GND
5 PIN SC70 PACKAGE
VIN/2 No Margin
Figure 18. Typical 3.2V to 5VIN, to 1.8V, 1.5V Outputs
4616fa
19
LTM4616
APPLICATIONS INFORMATION
V
3V TO 5.5V
SW1
CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
IN
V
OUT
1.5V/16A
V
V
IN1
OUT1
10μF
SV
IN1
RUN1
FB1
100μF
RUN
ENABLE
ITH1
3.32k
PLLLPF1
MODE1
ITHM1
PGOOD1
BSEL1
PHMODE1
TRACK1
MGN1
LTM4616
V
IN2
V
OUT2
10μF
SV
FB2
IN2
100μF
100μF
RUN2
ITH2
PLLLPF2
MODE2
PHMODE2
TRACK2
ITHM2
PGOOD2
BSEL2
MGN2
SW2
SGND1
GND1
SGND2
GND2
4616 F19
Figure 19. LTM4616 Two Outputs Parallel, 1.5V at 16A Design
CLKIN
V
5V
SW1
CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
IN
V
OUT1
3.3V/7A
V
IN1
V
OUT1
22μF
SHDNB
SV
IN1
RUN1
FB1
2.21k
ITH1
100μF
PLLLPF1
MODE1
ITHM1
PGOOD1
BSEL1
100k
100k
PHMODE1
TRACK1
PGOOD2
SV
IN1
MGN1
LTM4616
V
OUT2
1.5V/8A
V
IN2
V
OUT2
SV
FB2
IN2
100μF
RUN2
ITH2
6.65k
100μF
PLLLPF2
MODE2
PHMODE2
TRACK2
ITHM2
PGOOD2
BSEL2
100k
SHDNB
3.3V
1.5V
100k
PGOOD1
MGN2
SV
IN2
SW2
SGND1
GND1
SGND2
GND2
4616 F20
Figure 20. LTM4616 Output Sequencing Application
4616fa
20
LTM4616
APPLICATIONS INFORMATION
SW1
CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
V
IN
V
V
V
OUT
1.2V AT 32A
IN1
OUT1
3V TO 6.5V
+
C1
470μF
6.3V
10μF
6.3V
SV
IN1
RUN1
FB1
2.47k
ITH1
PLLLPF1
MODE1
ITHM1
PGOOD1
BSEL1
SANYO POSCAP
10mꢀ
PHMODE1
TRACK1
TRACK INPUT
MGN1
OR 3V
IN
LTM4616
V
V
OUT2
IN2
+
C2
470μF
6.3V
10μF
6.3V
SV
FB2
IN2
RUN2
ITH2
PLLLPF2
MODE2
PHMODE2
TRACK2
ITHM2
PGOOD2
BSEL2
MGN2
SW2
SGND1
GND1
SGND2
GND2
SW1
CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
V
V
OUT1
IN1
+
C3
470μF
6.3V
10μF
6.3V
SV
IN1
RUN1
FB1
ITH1
PLLLPF1
MODE1
ITHM1
PGOOD1
BSEL1
PHMODE1
TRACK1
MGN1
LTM4616
V
V
OUT2
IN2
+
+
C5
22μF
6.3V
C4
22μF
6.3V
10μF
6.3V
SV
FB2
IN2
RUN2
ITH2
PLLLPF2
MODE2
PHMODE2
TRACK2
ITHM2
PGOOD2
BSEL2
V
IN
3V TO 6.6V
MGN2
A1
+
R1
SW2
SGND1
GND1
SGND2
GND2
V
–
+
50k
4616 F21
I
I
OE
OUT
IN
R2
50k
GND
BSEL: HIGH = 10%
A1, A2 PERICOM P174ST1G126CEX
TOSHIBA TC75Z126AFE
6 PIN SC70 PACKAGE
FLOAT = 15%
LOW = 5%
OPTIONAL MARGINING CIRCUIT,
IF NOT USED TIE THE MGN PINS TO V
OUT
OE
IN
OUT
MGN MARGIN VALUE
H
H
L
H
L
X
H
L
Z
H
L
+ Value of BSEL Selection
– Value of BSEL Selection
VIN/2 No Margin
Figure 21. Four Phase in Parallel, 1.2V at 32A
4616fa
21
LTM4616
APPLICATIONS INFORMATION
SW1
CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
V
V
OUT1
IN
V
V
IN1
OUT1
3.3V/7A
4V TO 5.5V
10μF
RUN
ENABLE
SV
FB1
100μF
IN1
2.21k
RUN1
ITH1
PLLLPF1
MODE1
ITHM1
PGOOD1
BSEL1
PHMODE1
TRACK1
MGN1
LTM4616
V
OUT2
V
V
IN2
OUT2
FB2
2.5V/8A
SV
10μF
100μF
IN2
RUN2
ITH2
3.16k
PLLLPF2
MODE2
PHMODE2
TRACK2
ITHM2
PGOOD2
BSEL2
3.3V
10k
MGN2
SW2
SGND1
GND1
SGND2
GND2
3.16k
SW1
CLKIN1 CLKOUT1 CLKIN2 CLKOUT2
V
OUT3
V
V
IN1
OUT1
1.8V/8A
100μF
SV
FB1
IN1
10μF
RUN1
ITH1
4.99k
100μF
PLLLPF1
MODE1
ITHM1
PGOOD1
BSEL1
3.3V
10k
PHMODE1
TRACK1
MGN1
LTM4616
V
OUT4
4.99k
V
V
IN2
OUT2
FB2
1.5V/8A
100μF
SV
IN2
10μF
6.65k
RUN2
ITH2
100μF
PLLLPF2
MODE2
PHMODE2
TRACK2
ITHM2
PGOOD2
BSEL2
3.3V
10k
MGN2
SW2
SGND1
GND1
SGND2
GND2
6.65k
4616 F22
Figure 22. 4-Phase, Four Outputs (3.3V, 2.5V, 1.8V and 1.5V) with Tracking
4616fa
22
LTM4616
PACKAGE DESCRIPTION
LGA Package
144-Lead (15mm × 15mm × 2.82mm)
(Reference LTC DWG # 05-08-1816 Rev A)
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
4616fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTM4616
PACKAGE DESCRIPTION
Pin Assignment Table
(Arranged by Pin Number)
PIN NAME
A1 GND1
A2 GND1
A3 GND1
A4 GND1
A5 GND1
A6 BSEL1
A7 CLKIN1
A8 MODE1
PIN NAME
PIN NAME
PIN NAME
PIN NAME
PIN NAME
B1 GND1
B2 GND1
B3 GND1
B4 GND1
B5 GND1
B6 SW1
B7 GND1
B8 GND1
C1
C2
V
V
D1
D2
V
IN1
V
IN1
E1
E2
E3
E4
V
IN1
V
IN1
V
IN1
V
IN1
F1
F2
F3
F4
V
IN1
V
IN1
V
IN1
V
IN1
IN1
IN1
C3 GND1
C4 GND1
C5 GND1
C6 GND1
C7 GND1
C8 GND1
C9 GND1
C10 GND1
C11 GND1
C12 GND1
D3 GND1
D4 GND1
D5 GND1
D6 GND1
D7 GND1
D8 FB1
E5 SV
F5 SGND1
E6 PLLFLTR1 F6 RUN1
IN1
E7 ITHM1
E8 TRACK1
E9 VOUT1
E10 VOUT1
E11 VOUT1
E12 VOUT1
F7 CLKOUT1
F8 ITH1
A9 PHMODE1 B9 GND1
D9 VOUT1
D10 VOUT1
D11 VOUT1
D12 VOUT1
F9 VOUT1
F10 VOUT1
F11 VOUT1
F12 VOUT1
A10 MGN1
A11 PGOOD1
A12 GND1
B10 GND1
B11 GND1
B12 GND1
PIN NAME
G1 GND2
G2 GND2
G3 GND2
G4 GND2
G5 GND2
G6 BSEL2
G7 CLKIN2
G8 MODE2
PIN NAME
H1 GND2
H2 GND2
H3 GND2
H4 GND2
H5 GND2
H6 SW2
PIN NAME
PIN NAME
PIN NAME
PIN NAME
J1
J2
V
V
K1
K2
V
L1
L2
L3
L4
V
V
V
V
M1
M2
M3
M4
V
IN2
V
IN2
V
IN2
V
IN2
IN2
IN2
IN2
IN2
IN2
IN2
IN2
IN2
V
J3 GND2
J4 GND2
J5 GND2
J6 GND2
J7 GND2
J8 GND2
J9 GND2
J10 GND2
J11 GND2
J12 GND2
K3 GND2
K4 GND2
K5 GND2
K6 GND2
K7 GND2
K8 FB2
L5 SV
M5 SGND2
L6 PLLFLTR2 M6 RUN2
IN2
H7 GND2
H8 GND2
L7 ITHM2
L8 TRACK2
L9 VOUT2
L10 VOUT2
L11 VOUT2
L12 VOUT2
M7 CLKOUT2
M8 ITH2
G9 PHMODE2 H9 GND2
K9 VOUT2
K10 VOUT2
K11 VOUT2
K12 VOUT2
M9 VOUT2
M10 VOUT2
M11 VOUT2
M12 VOUT2
G10 MGN2
G11 PGOOD2
G12 GND2
H10 GND2
H11 GND2
H12 GND2
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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LTM4600
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Guaranteed Operation from –55°C to 125°C Ambient, LGA Package
LTM4601/
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LTM4602
LTM4603
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Pin Compatible with the LTM4600, LGA Package
6A DC/DC μModule with PLL and Outpupt Tracking/ Synchronizable, PolyPhase Operation, LTM4603-1 Version has no Remote
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LTM4604A
LTM4608A
Low V 4A DC/DC μModule
2.375V ≤ V ≤ 5.5V, 0.8V ≤ V
≤ 5V, 9mm × 15mm × 2.3mm LGA Package
IN
IN
OUT
Low V 8A DC/DC μModule
2.7V ≤ V ≤ 5.5V; 0.6V ≤ V
≤ 5V; 9mm × 15mm × 2.8mm LGA Package
OUT
IN
IN
LTM8022/LTM8023 36V , 1A and 2A DC/DC μModule
Pin Compatible; 4.5V ≤ V ≤ 36V; 9mm × 11.25mm × 2.8mm LGA Package
IN
IN
4616fa
LT 1108 REV A • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
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