LTM4618IVPBF [Linear]
6A DC/DC μModule Regulator with Tracking and Frequency Synchronization; 6A DC / DC微型模块稳压器，带有跟踪和频率同步
| 型号： | LTM4618IVPBF |
| 厂家： | 
Linear |
| 描述： | 6A DC/DC μModule Regulator with Tracking and Frequency Synchronization |
| 文件： | 总24页 (文件大小：339K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTM4618
6A DC/DC µModule
Regulator with Tracking and
Frequency Synchronization
FEATURES
DESCRIPTION
The LTM®4618 is a complete 6A output switching mode
DC/DC power supply in a 9mm × 15mm × 4.32mm LGA
package. Included in the package are the switching con-
troller, power FETs, inductor and all support components.
Operating over an input voltage range of 4.5V to 26.5V,
the LTM4618 supports an output voltage range of 0.8V
to 5V set by a single external resistor. Its high efficiency
design delivers 6A continuous current (8A peak). Only a
few input and output capacitors are needed.
n
Complete Standalone Power Supply
n
Wide Input Voltage Range: 4.5V to 26.5V
n
6A DC Typical, 8A Peak Output Current
n
0.8V to 5V Output
Output Voltage Tracking
±±.ꢀ5ꢁ Maꢂimum Total DC Error
n
n
n
Current Mode Control/Fast Transient Response
n
Phase-Lockable Fiꢂed Frequency 250kHz to ꢀ80kHz
n
On-Board Frequency Synchronization
Selectable Burst Mode® Operation
n
Highswitchingfrequencyandacurrentmodearchitecture
enable a very fast transient response to line and load
changes without sacrificing stability. The device supports
frequencysynchronizationandoutputvoltagetrackingfor
supply rail sequencing. Burst Mode operation or pulse-
skipping mode can be selected for light load operations.
n
Power Good Voltage Indicator
n
Output Overvoltage Protection
n
Output Current Foldback Limiting
n
9mm × 15mm × 4.32mm LGA Package
APPLICATIONS
Fault protection features include overvoltage protection,
overcurrent protection and foldback current limit for
short-circuit protection.
n
Telecom and Networking Equipment
n
Servers
n
Storage Cards
The LTM4618 is Pb-free and RoHS compliant.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and μModule are registered
trademarks of Linear Technology Corporation. All other trademarks are the property of their
respective owners.
n
ATCA Cards
Industrial Equipment
Point of Load Regulation
n
n
n
Medical Systems
TYPICAL APPLICATION
2.5V/6A DC/DC Power μModule® with 6V to 26.5V Input
Efficiency and Power Loss vs Load Current
95
90
85
80
75
70
3.0
2.5
2.0
1.5
1.0
0.5
0
EFFICIENCY
MODE/PLLIN INTV
CC
EXTV
CC
FREQ
V
IN
6V to 26.5V
V
IN
C
IN
V
OUT
2.5V/6A
COMP
TK/SS
RUN
V
OUT
LTM4618
C
OUT
V
FB
0.1μF
28.7k
PGOOD
SGND
PGND
POWER LOSS
4618 TA01
12V TO 2.5V
IN
OUT
OUT
24V TO 2.5V
IN
0
1
2
3
4
5
6
LOAD CURRENT (A)
4618 TA01b
4618f
1
LTM4618
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note ±)
TOP VIEW
SW
V , SW...................................................... –0.3V to 28V
IN
7
INTV , RUN, EXTV , PGOOD .................... –0.3V to 6V
CC
CC
V
IN
COMP, V ................................................. –0.3V to 2.7V
6
5
4
3
2
1
PGND
FB
MODE/PLLIN, TK/SS,
EXTV
CC
FREQ..................................................... –0.3V to INTV
CC
SGND/PGND
V
............................................................... 0.8V to 5V
OUT
MODE/
PLLIN
FREQ
RUN
V
OUT
Operating Junction Temperature Range
(Note 2)..................................................–40°C to 125°C
Storage Temperature Range...................–55°C to 125°C
Peak Package Body Temperature .......................... 250°C
A
B
C
D
E
F
G
H
J
K
L
M
TK/SS COMP V PGOOD INTV
FB CC
LGA PACKAGE
84-LEAD (15mm s 9mm s 4.32mm)
= 16°C/W, Θ = 15°C/W, Θ = 4°C/W, WEIGHT = 2.3g,
JCtop
Θ
JA
θ
JCbottom
+ θ = 16°C/W, θ = BOARD-TO-AMBIENT RESISTANCE,
JB
BA
BA
θ VALUES DEFINED PER JESD51-12
ORDER INFORMATION
LEAD FREE FINISH
LTM4618EV#PBF
LTM4618IV#PBF
PART MARKING*
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTM4618V
–40°C to 125°C
–40°C to 125°C
84-Lead (15mm × 9mm × 4.32mm) LGA
84-Lead (15mm × 9mm × 4.32mm) LGA
LTM4618V
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = ±2V, per typical application in Figure 2±.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
l
l
V
V
Input DC Voltage
(Note 5)
4.5
26.5
V
IN(DC)
Output Voltage Total Variation with
Line and Load
C
C
= 10μF ×2, R = 28.0kΩ
OUT(DC)
IN
FB
= 100μF ×3 X7R Ceramic
OUT
2.476
2.52
2.557
V
MODE/PLLIN = 0V, V
= 2.4V
FREQ
OUT
V
= 6V to 26.5V, I
= 0A to 6A (Note 4)
IN
Input Specifications
V
Undervoltage Lockout Thresholds
Input Inrush Current at Start-Up
V
V
Rising
Falling
2.00
1.85
2.20
2.00
2.35
2.15
V
V
IN(UVLO)
INTVCC
INTVCC
I
I
= 0A, C = 10μF ×2, C
= 100μF ×3
INRUSH(VIN)
OUT
IN
OUT
V
= 2.5V
OUT
0.3
0.2
A
A
V
IN
V
IN
= 12V
= 26.5V
4618f
2
LTM4618
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = ±2V, per typical application in Figure 2±.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX UNITS
I
Input Supply Bias Current
V
V
= 12V, V
= 2.5V, I = 0A
OUT
OUT
26
20
80
mA
mA
μA
Q(VIN)
S(VIN)
IN
IN
OUT
= 26.5V, V
= 2.5V, I
= 0A
OUT
Shutdown, RUN = 0, V = 26.5V
IN
I
Input Supply Current
V
IN
V
IN
= 12V, V
= 26.5V, V
= 2.5V, I = 6A
OUT
1.430
0.675
A
A
OUT
= 2.5V, I
= 6A
OUT
OUT
INTV
Internal V Voltage
V
= 12V, V > 2V, No Load
RUN
4.8
4.5
5
5.2
V
V
CC
CC
IN
l
V
EXTV Switchover Voltage
EXTV Ramping Positive
4.7
50
EXTVCC
CC
CC
VLDO External
EXTV Voltage Drop
INTV = 20mA, V = 5V
EXTVCC
100
mV
mV
CC
CC
CC
V
Hysteresis EXTV Hysteresis
200
EXTVCC
Output Specifications
I
Output Continuous Current Range
Line Regulation Accuracy
V
V
= 12V, V = 2.5V (Note 4)
OUT
0
6
A
OUT(DC)
IN
= 2.5V, V from 6V to 26.5V
ΔV
ΔV
V
OUT
IN
OUT(LINE)
l
l
I
= 0A
0.02
0.3
0.04
0.6
%/V
%
OUT
V
OUT
Load Regulation Accuracy
Output Ripple Voltage
V
IN
= 12V, V
= 2.5V, 0 to 6A (Note 4)
OUT
OUT(LOAD)
V
OUT
I
= 0A, C
= 100μF ×3 X5R Ceramic
OUT(AC)
OUT
OUT
10
12
mV
mV
V
= 12V, V
= 2.5V
OUT
IN
IN
V
= 26.5V, V
= 2.5V
OUT
f
Output Ripple Voltage Frequency
Turn-On Overshoot
I
= 2A, V = 12V, V
= 2.5V, V
= INTV
CC
780
kHz
S
OUT
IN
OUT
FREQ
ΔV
C
V
= 100μF ×3 X5R Ceramic
OUT
OUT(START)
= 2.5V, I
= 0A
OUT
OUT
20
20
mV
mV
V
= 12V
IN
IN
V
= 26.5V
t
Turn-On Time
C
V
= 100μF ×3 X5R Ceramic,
START
OUT
OUT
V
V
= 2.5V, I
= 0A, TK/SS Capacitor = 0.01μF
OUT
0.75
0.70
ms
ms
= 12V
IN
IN
= 26.5V
Peak Deviation for Dynamic Load
Settling Time for Dynamic Load Step
Output Current Limit
Load: 0% to 50% of Full Load
ΔV
OUTLS
C
= 100μF ×3 X5R Ceramic, V
= 2.5V
= 2.5V
OUT
V
OUT
OUT
= 12V
15
10
mV
μs
IN
t
Load: 0% to 50% of Full Load
SETTLE
C
OUT
V
= 100μF ×3 X5R Ceramic, V
IN
= 12V
I
C
= 100μF ×3 X5R Ceramic
OUT(PK)
OUT
11
11
A
A
V
= 6V, V
= 2.5V
IN
OUT
V
= 26.5V, V
= 2.5V
OUT
IN
Control Section
V
Error Amplifier Feedback Voltage
I
= 0A, V = 2.5V
OUT
0.792
0.788
0.8
0.8
0.808
0.808
V
V
FB
OUT
l
I
Error Amplifier Feedback Current
Feedback Voltage Lockout
Soft-Start Charge Current
Maximum Duty Factor
Minimum On-Time
(Note 3)
Measured at V
–10
0.86
1.3
–50
0.88
1.7
nA
V
FB
V
0.84
0.9
OVL
FB
I
V
TK/SS
= 0V
μA
%
TK/SS
DF
In Dropout (Note 3)
(Note 3)
97
MAX
ON(MIN)
NOM
t
f
f
90
ns
Nominal Frequency
V
= 1.2V
= 0V
450
210
500
250
550
290
kHz
kHz
FREQ
FREQ
Lowest Frequency
V
LOW
4618f
3
LTM4618
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C (Note 2), VIN = ±2V, per typical application in Figure 2±.
SYMBOL
PARAMETER
CONDITIONS
MIN
700
2.0
TYP
MAX UNITS
f
Highest Frequency
V
FREQ
≥ 2.4V, INTV
CC
780
860
kHz
V
HIGH
V
V
Synchronous Clock High Level
Synchronous Clock Low Level
MODE/PLLIN Input Resistance
IH(MODE/PLLIN)
IL(MODE/PLLIN)
0.8
V
R
250
kΩ
MODE/PLLIN
FREQ
I
FREQ Pin
Sinking Current
Sourcing Current
f
f
> f
< f
–13
13
μA
μA
MODE/PLLIN
MODE/PLLIN
OSC
OSC
V
V
RUN Pin On Threshold
RUN Pin Hysteresis
RUN Rising
1.1
1.22
120
1.35
60.7
V
mV
kꢀ
RUN
Hysteresis
RUN
R
Resistor Between V
and V Pins
60.1
60.4
FBHI
OUT
FB
PGOOD Output
V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
0.3
2
V
PGL
PGOOD
I
PGOOD Leakage Current
PGOOD Trip Level
V
μA
PGOOD
PGOOD
V
PG
V
with Respect to Set Regulated Voltage
FB
V
V
Ramping Negative
Ramping Positive
–5
5
–7.5
7.5
–10
10
%
%
FB
FB
Note ±: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
operating junction temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal resistance and other environmental factors.
Note 2: The LTM4618 is tested under pulsed load conditions such that
Note 3: 100% tested at wafer level only.
T ≈ T . The LTM4618E is guaranteed to meet performance specifications
J
A
Note 4: See Output Current Derating curves for different V , V
and T .
A
IN OUT
over the 0°C to 125°C operating junction temperature range. Specifications
over the full –40°C to 125°C operating junction temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4618I is guaranteed to meet specifications over the full
Note 5: For input voltages less than 6V, tie the V , INTV and EXTV
CC
IN
CC
together. The LTM4618 will operate from 5V inputs, but V , INTV and
IN
CC
EXTV need to be tied together.
CC
4618f
4
LTM4618
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency vs Load Current with
5VIN (CCM)
Efficiency vs Load Current with
±2VIN (CCM)
Efficiency vs Load Current with
24VIN (CCM)
100
95
90
85
80
75
70
100
95
90
85
80
75
70
95
90
85
80
75
70
12V TO 1.2V
12V TO 1.5V
12V TO 2.5V
12V TO 3.3V
12V TO 5V
5V TO 0.8V
OUT
OUT
OUT
OUT
OUT
5V TO 1.2V
OUT
5V TO 1.5V
OUT
24V TO 2.5V
24V TO 3.3V
24V TO 5V
OUT
OUT
5V TO 2.5V
OUT
5V TO 3.3V
OUT
OUT
OUT
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4618 G01
4618 G02
4618 G03
Efficiency vs Load Current with
Different Mode Settings
(±2V to 3.3V)
±.2V Transient Response
±.5V Transient Response
100
90
80
70
60
50
40
30
20
10
0
V
V
= 12V
IN
OUT
= 3.3V
I
I
OUT
OUT
1A/DIV
1A/DIV
V
V
OUT
50mV/DIV
OUT
50mV/DIV
4618 G05
4618 G06
50μs/DIV
50μs/DIV
V
C
= 12V AND V
OUT
= 1.2V AT 3A/μs LOAD STEP
V
C
= 12V AND V
OUT
= 1.5V AT 3A/μs LOAD STEP
OUT
IN
OUT
IN
= 2s 22μF 6.3V CERAMIC CAPACITOR
= 2s 22μF 6.3V CERAMIC CAPACITOR
BURST
PULSE SKIP
CCM
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
0.01
0.1
1
LOAD CURRENT (A)
4618 G04
2.5V Transient Response
3.3V Transient Response
5V Transient Response
I
I
I
OUT
OUT
OUT
1A/DIV
1A/DIV
1A/DIV
V
V
OUT
V
OUT
OUT
100mV/DIV
50mV/DIV
50mV/DIV
4618 G07
4618 G08
4618 G09
50μs/DIV
50μs/DIV
50μs/DIV
V
C
= 12V AND V
OUT
= 2.5V AT 3A/μs LOAD STEP
V
C
= 12V AND V
OUT
= 3.3V AT 3A/μs LOAD STEP
V
C
= 12V AND V
OUT
= 5V AT 3A/μs LOAD STEP
OUT
IN
OUT
IN
OUT
IN
= 2s 22μF 6.3V CERAMIC CAPACITOR
= 2s 22μF 6.3V CERAMIC CAPACITOR
= 2s 22μF 6.3V CERAMIC CAPACITOR
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
1s 100μF 6.3V CERAMIC CAPACITOR
1s 220μF SANYO POSCAP
4618f
5
LTM4618
TYPICAL PERFORMANCE CHARACTERISTICS
Start-Up, IOUT = 0A
Start-Up, IOUT = 6A
V
V
OUT
OUT
1V/DIV
1V/DIV
I
I
IN
IN
0.5A/DIV
0.2A/DIV
4618 G11
4618 G10
20ms/DIV
= 12V AND V = 2.5V
OUT
20ms/DIV
= 12V AND V = 2.5V
OUT
V
C
V
C
IN
IN
= 2s 22μF 6.3V CERAMIC,
= 2s 22μF 6.3V CERAMIC,
OUT
OUT
1s 100μF 6.3V CERAMIC AND
1s 220μF SANYO POSCAP
1s 100μF 6.3V CERAMIC AND
1s 220μF SANYO POSCAP
C
= 0.1μF
C
= 0.1μF
SOFT-START
SOFT-START
Short-Circuit Protection,
IOUT = 0A
Short-Circuit Protection,
IOUT = 6A
V
V
OUT
1V/DIV
OUT
1V/DIV
I
I
IN
1A/DIV
IN
1A/DIV
4618 G12
4618 G13
100μs/DIV
100μs/DIV
V
C
= 12V AND V
OUT
= 2.5V
V
C
= 12V AND V
OUT
= 2.5V
IN
OUT
IN
OUT
= 2s 22μF 6.3V CERAMIC,
= 2s 22μF 6.3V CERAMIC,
1s 100μF 6.3V CERAMIC AND
1s 220μF SANYO POSCAP
1s 100μF 6.3V CERAMIC AND
1s 220μF SANYO POSCAP
4618f
6
LTM4618
PIN FUNCTIONS
NC (A±): No Connect. Leave floating.
SGND (B3, C2 and C3): Signal Ground Pin. Return ground
path for all analog and low power circuitry. Tie a single
connection to PGND. See applications for details.
FREQ (A2): Frequency Selection Pin. An internal low pass
filter is tied to this pin. The frequency can be selected from
250kHz to 780kHz by setting a voltage from this pin to
SGND. A programming resistor divider can be used to set
the operating frequency. See the Applications Information
section.
COMP (C±): Current control threshold and error ampli-
fier compensation point. The module has been internally
compensated for most I/O ranges.
EXTV (C4):ExternalVoltageInput.Bypassestheinternal
CC
MODE/PLLIN(A3):ModeSelectionorExternalSynchroni-
zationPin. TyingthispintoINTV enablespulse-skipping
INTV LDOandpowerstheinternalcircuitryandMOSFET
CC
drivers. If a 5V source is available, the internal LDO is
disabled, and the power dissipation is lower, especially at
higher input voltages. See the Applications Information
section.
CC
operation. Tying this pin low enables forced continuous
modeoperation. BurstModeoperationisenabledbyfloat-
ing the pin. A clock on the pin will force the controller into
forced continuous mode of operation and synchronize to
the internal oscillator. The programming DC voltage has
to be removed for clock synchronization.
V
(D±): The negative input of the error amplifier. Inter-
FB
nally,thispinisconnectedtoV
witha60.4kΩprecision
OUT
resistor. Different output voltages can be programmed
PGND (BANK 2: A4, B4, D4-Dꢀ, E±-Eꢀ, F±-Fꢀ, G±-Gꢀ,
H±-Hꢀ, J5-Jꢀ, K5, Kꢀ, L5-Lꢀ, M5-Mꢀ): Power ground
pins for both input and output returns.
with an additional resistor between V and SGND pins.
FB
See applications for details.
PGOOD(D2):OutputVoltagePowerGoodIndicator.Open-
drain logic output that is pulled to ground when the output
voltage is not within 7.5% of the regulation point.
V
IN
(BANK ±: A5-Aꢀ, B5-Bꢀ, C5-Cꢀ): Power Input Pins.
Apply input voltage between these pins and PGND pins.
Recommendplacinginputdecouplingcapacitancedirectly
INTV (D3): Internal 5V Regulator Output. This pin is for
CC
between V pins and PGND pins.
IN
additional decoupling of the 5V internal regulator.
TK/SS(B±):OutputVoltageTrackingandSoft-StartPin.An
internal soft-start current of 1.3μA charges the soft-start
capacitor. See the Applications Information section.
V
(BANK3:J±-J4,K±-K4,L±-L4,M±-M4):PowerOut-
OUT
put Pins. Apply output load between these pins and PGND
pins. Recommend placing output decoupling capacitance
directly between these pins and PGND pins.
RUN (B2): Run Control Pin. A voltage above 1.35V on
this pin turns on the module. Forcing this pin below 1.1V
will shut down the output. The RUN pin has a 1μA pull-
up current source that increases to 10μA as the RUN pin
voltage reaches 1.5V and up to compliance. Therefore the
pin can be left floating for normal operation. A maximum
of 6V can be applied to the pin. A voltage divider can be
used for a UVLO function. See the Applications Informa-
tion section.
SW (K6): Switching Node of the Circuit. This pin is used
to check the switching frequency. Leave pin floating. A
resistor-capacitor snubber can be placed from SW to
PGND to eliminate high frequency switch node ringing.
See the Applications Information section.
7
BANK 2
PGND
BANK 1
6
V
IN
SW
5
4
3
2
1
SGND/PGND
CNTRL
BANK 3
V
OUT
A
B
C
D
E
F
G
H
J
K
L
M
4618f
7
LTM4618
SIMPLIFIED BLOCK DIAGRAM
≤6V V
IN
TIE V , INTV AND
IN
CC
EXTV TOGETHER
CC
V
INTERNAL
FILTER
IN
4.5V TO 26.5V
+
+
1.5μF
C
C
EXTV
INTV
MODE/PLLIN
IN
CC
CC
M1
M2
SW
1.5μH
TK/SS
V
OUT
C
SS
2.5V/6A
10μF
POWER
CONTROL
OUT
RUN
PGOOD
COMP
PGND
INTERNAL
COMP
60.4k
INTV
CC
FREQ
V
FB
R
FB
INTERNAL
FILTER
28k
SGND
4618 F01
Figure ±. Simplified LTM46±8 Block Diagram
TA = 25°C. Use Figure ± configuration.
DECOUPLING REQUIREMENTS
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
C
External Input Capacitor Requirement
I
I
= 6A
10
μF
IN
OUT
(V = 4.5V to 26.5V, V
= 2.5V)
IN
OUT
External Output Capacitor Requirement
(V = 4.5V to 26.5V, V = 2.5V)
= 6A
200
μF
OUT
OUT
IN
OUT
4618f
8
LTM4618
OPERATION
Power Module Description
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limitandcurrentfoldbackinashort-circuitcondition.Pull-
ing the RUN pin below 1.1V forces the controller into its
shutdown state, by turning off both MOSFETs. The TK/SS
pin can be used for programming the output voltage ramp
and voltage tracking during start-up. See the Applications
Information section.
TheLTM4618isastandalonenon-isolatedswitchingmode
DC/DC power supply. It can deliver up to 6A (DC current)
output with few external input and output capacitors. This
module provides precisely regulated output voltages pro-
grammable via external resistors from 0.8VDC to 5.0VDC
over 4.5V to 26.5V input voltages. The typical application
schematic is shown in Figure 21. For ≤6V inputs, connect
V , INTV and EXTV together.
IN
CC
CC
The LTM4618 is internally compensated to be stable over
all operating conditions. The Linear Technology μModule
Power Design Tool will be provided for transient and
TheLTM4618hasanintegratedconstantfrequencycurrent
mode regulator and built-in power MOSFET devices with
fast switching speed. The typical switching frequency is
750kHz.
stability analysis. The V pin is used to program the
FB
output voltage with a single external resistor to ground.
Multiphase operation can be easily employed with the
synchronization control.
With current mode control and internal feedback loop
compensation, the LTM4618 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
High efficiency at light loads can be accomplished with
selectableBurstModeorpulse-skippingmodeoperations
usingtheMODE/PLLINpin.Efficiencygraphsareprovided
for light load operation in the Typical Performance Char-
acteristics section.
4618f
9
LTM4618
APPLICATIONS INFORMATION
The typical LTM4618 application circuit is shown in
Figure 21. External component selection is primarily
determined by the maximum load current and output
voltage.
Input Capacitors
The LTM4618 module should be connected to a low AC-
impedance DC source. One 1.5μF input ceramic capacitor
is included inside the module. Additional input capacitors
are only needed if a large load step is required up to
the 6A level. A 47μF to 100μF surface mount aluminum
electrolytic bulk capacitor can be used for more input bulk
capacitance. This bulk input capacitor is only needed if
the input source impedance is compromised by long in-
ductive leads, traces or not enough source capacitance.
If low impedance power planes are used, then this 47μF
capacitor is not needed.
V to V
Step-Down Ratios
IN
OUT
There are restrictions in the maximum V to V
step-
IN
OUT
down ratio that can be achieved for a given input voltage.
One of the restrictions is the minimum on-time t
,
ON(MIN)
which is the smallest time duration that the LTM4618 can
operate.Makesurethattheoperatingon-timeislargerthan
theminimumon-timeasshownintheequationbelow. See
the Thermal Considerations and Output Current Derating
sections in this data sheet for the current restrictions.
For a buck converter, the switching duty-cycle can be
estimated as:
t
is approximately 90ns, guardband to 110ns.
ON(MIN)
VOUT
VOUT
D=
tON(MIN)
<
V
IN
V • ƒ
IN
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
Output Voltage Programming
ThePWMcontrollerhasaninternal0.8Vreferencevoltage.
As shown in the Block Diagram, a 60.4k internal feedback
IOUT(MAX)
ICIN(RMS)
=
• D•(1–D)
η
resistorconnectsV totheV pin.AddingaresistorR
OUT
FB
FB
from the V pin to SGND programs the output voltage:
In the above equation, η is the estimated efficiency of
the power module. One 10μF ceramic input capacitor is
typically rated for 2A of RMS ripple current, so the RMS
input current at the worst case 6A maximum current is
about 3A. If a low inductance plane is used to power the
device, then two 10μF ceramic capacitors are enough for
the output at 6A load and no external input bulk capacitor
is required. The input RMS ripple current can be cancelled
by paralleling multiple LTM4618 power modules out of
phase, allowing the use of fewer input capacitors. Ap-
plication Note 77 explains the details.
FB
60.4k +RFB
VOUT = 0.8V •
RFB
Table ±. VFB Resistor Table vs Various Output Voltages
V
(V)
0.8
1
1.2
1.5
1.8
2.5
3.3
5
OUT
R
(kΩ)
Open
243
121
69.8 48.7 28.7 19.1 11.5
FB
4618f
10
LTM4618
APPLICATIONS INFORMATION
Output Capacitors
Frequency Selection
The LTM4618 is designed for low output voltage ripple
The switching frequency of the LTM4618’s controller can
be selected using a DC voltage. If the MODE/PLLIN pin
is not being driven by an external clock source, the FREQ
pin can program the controller’s operating frequency
from 250kHz to 780kHz by connecting a resistor divider
as shown in Figure 21. The typical frequency is 750kHz.
But if the minimum on-time is reached, a lower frequency
needs to be set to increase the turn-on time. Otherwise, a
significant amount of cycle skipping can occur with cor-
respondingly larger ripple current and voltage ripple.
noise. The bulk output capacitors defined as C
are
OUT
chosenwithlowenougheffectiveseriesresistance(ESR)to
meettheoutputvoltagerippleandtransientrequirements.
C
can be a low ESR tantalum capacitor, a low ESR
OUT
polymer capacitor or ceramic capacitor. The typical output
capacitancerangeisfrom100μFto300μF.Additionaloutput
filtering may be required by the system designer if further
reduction of output ripple or dynamic transient spikes is
required.Table4showsamatrixofdifferentoutputvoltages
and output capacitors to minimize the voltage droop and
overshootduringa3A/μstransient.Thetableoptimizesthe
totalequivalentESRandtotalbulkcapacitancetooptimize
thetransientperformance.Stabilitycriteriaareconsidered
in the Table 4 matrix, and the Linear Technology μModule
Power Design Tool is available for stability analysis. Mul-
tiphase operation will reduce effective output ripple as a
function of the number of phases. Application Note 77
discusses this noise reduction versus output ripple cur-
rent cancellation, but the output capacitance should be
consideredcarefullyasafunctionofstabilityandtransient
response. The Linear Technology μModule Power Design
Toolcancalculatetheoutputripplereductionasthenumber
of implemented phases increases by N times.
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
2.5
FREQ PIN VOLTAGE (V)
4618 F03
Figure 3. Relationship Between Switching
Frequency and Voltage at the FREQ Pin
Mode Selections and Phase-Locked Loop
Frequency Synchronization
The LTM4618 can be enabled to enter high efficiency
BurstModeoperation,constant-frequency,pulse-skipping
mode, or forced continuous conduction mode. To select
the forced continuous operation, tie the MODE/PLLIN pin
to ground. To select pulse-skipping mode of operation,
The MODE/PLLIN pin allows the LTM4618 to be synchro-
nized to an external clock (between 400kHz to 780kHz)
and the internal phase-locked loop allows the LTM4618
to lock onto input clock phase as well. The FREQ pin has
the onboard loop filter for the PLL. The incoming clock
must be applied before the RUN pin is enabled. For ap-
plications powering the clock source from the LTM4618’s
tie the MODE/PLLIN pin to INTV . To select Burst Mode
CC
operation, float the pin.
A phase-locked loop (PLL) is available on the LTM4618
to synchronize the internal oscillator to an external clock
source that is connected to the MODE/PLLIN pin. The
incoming clock should be applied before the regulator’s
RUN pin is enabled.
INTV , the RUN pin has to be enabled in order to acti-
CC
vate INTV for the clock source. In this situation (see
CC
Figure 22) the TK/SS pin can be used to soft-start the
regulator for 100ms using a ≈ 0.22μF capacitor. This will
allow the regulator to synchronize to the right frequency
before the regulator’s inductor ripple current peaks.
4618f
11
LTM4618
APPLICATIONS INFORMATION
TheLTM4618canbesynchronizedfrom400kHzto780kHz
with an input clock that has a high level above 2.0V and a
low level below 0.8V. The 400kHz low end operation limit
is put in place to limit inductor ripple current. See the
TypicalApplicationssectionforsynchronizationexamples.
The LTM4618 minimum on-time is limited to about 90ns.
Guardband the on-time to 110ns. The on-time can be
calculated as:
V
is the track ramp applied to the slave’s TK/SS
TRACK
TRACK
pin. V
has a control range of 0V to 0.8V. When the
master’s output is divided down with the same resistor
values used to set the slave’s output, then the slave will
coincident track with the master until it reaches its final
value. The master will continue to its final value from the
slave’s regulation point.
Ratiometric modes of tracking can be achieved by select-
ing different divider resistor values to change the output
tracking ratio. The master output must be greater than the
slave output for the tracking to work. Master and slave
data inputs can be used to implement the correct resistor
values for coincident or ratio tracking.
⎛
⎜
⎝
⎞
⎟
⎠
VOUT
1
tON(MIN)
=
•
FREQ
V
IN
Soft-Start and Tracking
LTM4618 has the ability to either soft-start by itself with a
capacitor or track the output of an external supply. When
the module is configured to soft-start by itself, a capacitor
should be connected to its TK/SS pin. When the module
is in the shutdown state, the TK/SS pin is actively pulled
to ground.
MODE/PLLIN INTV
EXTV
CC
CC
V
IN
V
FREQ
IN
5V
C
IN
V
OUT(SLAVE)
COMP
V
OUT
2.5V/6A
22pF
MASTER
OUTPUT
R1
60.4k
LTM4618
C
OncetheRUNpinvoltageisabove1.22V, themodulepow-
ers up. Then a soft-start current of 1.3μA starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined as the voltage range from 0V to 0.8V on the TK/SS
pin. The total soft-start time can be calculated as:
OUT
TK/SS
RUN
V
FB
PGOOD
R2
28.7k
28.7k
SGND
PGND
4618 F04
Figure 4. Output Voltage Coincident Tracking
MASTER OUTPUT
SLAVE OUTPUT
0.8V •CSS
tSOFT-START
=
1.3µA
OUTPUT
VOLTAGE
Output voltage tracking can be programmed externally
using the TK/SS pin. The master voltage is divided down
with an external resistor divider that is the same as the
slave’s feedback divider to implement coincident tracking.
The LTM4618 uses an accurate 60.4k resistor internally
for the top feedback resistor. Figure 4 shows an example
of coincident tracking.
4618 F05
TIME
Figure 5. Coincident Tracking Characteristics
R1
R2
⎛
⎞
VOUT(SLAVE) = 1+
• V
TRACK
⎜
⎟
⎠
⎝
4618f
12
LTM4618
APPLICATIONS INFORMATION
Slope Compensation
figuration section are in-and-of themselves not relevant to
providing guidance of thermal performance; instead, the
derating curves provided in the data sheet can be used in
a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
The module has already been internally compensated
for all output voltages. The Linear Technology μModule
Power Design Tool will be provided for other control loop
optimization.
RUN Pin
The Pin Configuration section shows four thermal coef-
ficientsexplicitlydefinedinJESD51-12;thesecoefficients
are quoted or paraphrased below:
The RUN pin has a 1μA pull-up current source that will
enable the device in a float condition. A voltage divider
can be used to enable a UVLO function using the RUN
pin. See Figure 21.
• θ , the thermal resistance from junction to ambi-
JA
ent, is the natural convection junction-to-ambient
air thermal resistance measured in a one cubic foot
sealed enclosure. This environment is sometimes
referred to as “still air” although natural convection
causes the air to move. This value is determined with
the part mounted to a JESD 51-9 defined test board,
which does not reflect an actual application or viable
operating condition.
Fault Conditions: Current Limit and Overcurrent
Foldback
The LTM4618 has a current mode controller, which inher-
ently limits the cycle-by-cycle inductor current not only in
steady-state operation, but also in transient.
To further limit current in the event of an overload condi-
tion,theLTM4618providesfoldbackcurrentlimiting.Ifthe
output voltage falls by more than 40%, then the maximum
output current is progressively lowered to about 25% of
its full current limit value.
• θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is the junction-to-board
thermal resistance with all of the component power
dissipation flowing through the bottom of the pack-
age. In the typical μModule, the bulk of the heat flows
out the bottom of the package, but there is always
heat flow out into the ambient environment. As a
result, this thermal resistance value may be useful
for comparing packages but the test conditions don’t
generally match the user’s application.
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-9 and are intended for use with
finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
μModulepackagemountedtoahardwaretestboard—also
defined by JESD51-9 (“Test Boards for Area Array Surface
MountPackageThermalMeasurements”).Themotivation
for providing these thermal coefficients in found in JESD
51-12 (“Guidelines for Reporting and Using Electronic
Package Thermal Information”).
• θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
component power dissipation flowing through the
top of the package. As the electrical connections of
the typical μModule are on the bottom of the pack-
age, it is rare for an application to operate such that
most of the heat flows from the junction to the top of
the part. As in the case of θ
, this value may
JCbottom
be useful for comparing packages but the test condi-
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to anticipate
the μModule regulator’s thermal performance in their ap-
plicationatvariouselectricalandenvironmentaloperating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
tions don’t generally match the user’s application.
• θ , the thermal resistance from junction to the
JB
printed circuit board, is the junction-to-board thermal
resistance where almost all of the heat flows through
the bottom of the μModule and into the board, and
4618f
13
LTM4618
APPLICATIONS INFORMATION
simplicity—but also, not ignoring practical realities—an
approach has been taken using FEA software modeling
along with laboratory testing in a controlled-environment
chamber to reasonably define and correlate the thermal
resistance values supplied in this data sheet: (1) Initially,
FEA software is used to accurately build the mechanical
geometry of the μModule and the specified PCB with all
of the correct material coefficients along with accurate
power loss source definitions; (2) this model simulates
a software-defined JEDEC environment consistent with
JSED51-9topredictpowerlossheatflowandtemperature
readings at different interfaces that enable the calculation
of the JEDEC-defined thermal resistance values; (3) the
model and FEA software is used to evaluate the μModule
with heat sinks and airflow; (4) having solved for and
analyzed these thermal resistance values and simulated
various operating conditions in the software model, a
thorough laboratory evaluation replicates the simulated
conditions with thermocouples within a controlled-envi-
ronment chamber while operating the device at the same
power loss as that which was simulated. An outcome of
this process and due-diligence yields a set of derating
curves provided in other sections of this data sheet. After
theselaboratorytestshavebeenperformedandcorrelated
is really the sum of the θ
and the thermal re-
JCbottom
sistance of the bottom of the part through the solder
joints and through a portion of the board. The board
temperature is measured at specified distance from
the package, using a two sided, two layer board.
This board is described in JESD 51-9.
A graphical representation of the forementioned thermal
resistances is given in Figure 6; blue resistances are con-
tained within the μModule, whereas green resistances are
external to the μModule.
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD 51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a μModule. For example, in actual
board-mounted applications, never does 100% of the
device’s total power loss (heat) thermally conduct exclu-
sivelythroughthetoporexclusivelythroughbottomofthe
μModule—asthestandarddefinesforθ
andθ
,
JCtop
JCbottom
respectively.Inpractice,powerlossisthermallydissipated
inbothdirectionsawayfromthepackage—granted, inthe
absence of a heat sink and airflow, a majority of the heat
flow is into the board.
to the μModule model, then the θ and θ are summed
JB
BA
together to correlate quite well with the μModule model
with no air flow or heat sinking in a properly define cham-
WithinaSIP(System-In-Package)module,beawarethere
are multiple power devices and components dissipating
power, with a consequence that the thermal resistances
relative to different junctions of components or die are not
exactly linear with respect to total package power loss. To
reconcile this complication without sacrificing modeling
ber. This θ + θ value is shown in the Pin Configuration
JB
BA
section and should accurately equal the θ value because
JA
approximately 100% of power loss flows from the junc-
tion through the board into ambient with no airflow or top
mounted heat sink.
JUNCTION-TO-AMBIENT RESISTANCE (JESD 51-9 DEFINED BOARD)
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
A
t
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4618 F06
μMODULE DEVICE
Figure 6. Graphical Representation of JESD5±-±2 Thermal Coefficients
4618f
14
LTM4618
APPLICATIONS INFORMATION
The 1.5V and 3.3V power loss curves in Figures 7 and 8
can be used in coordination with the load current derating
curves in Figures 9 to 16 for calculating an approximate
no air flow or heat sink and the power loss for the 12V to
1.5V at 5A output is about 1.7W. The 1.7W loss is calcu-
lated with the ~1.4W room temperature loss from the 12V
to 1.5V power loss curve at 5A, and the 1.2 multiplying
factor at 85°C ambient. If the 85°C ambient temperature
is subtracted from the 115°C junction temperature, then
θ thermal resistance for the LTM4618 with various heat
JA
sinking and air flow conditions. The power loss curves
are taken at room temperature, and are increased with
multiplicative factors according to the ambient tempera-
ture. These approximate factors are: 1 for 40°C; 1.05 for
50°C; 1.1 for 60°C; 1.15 for 70°C; 1.2 for 80°C; 1.25 for
90°C; 1.3 for 100°C; 1.35 for 110°C and 1.4 for 125°C.
The derating curves are plotted with the output current
starting at 6A and the ambient temperature at 40°C. The
output voltages are 1.5V, and 3.3V. These are chosen to
include the lower and higher output voltage ranges for
correlating the thermal resistance. Thermal models are
derivedfromseveraltemperaturemeasurementsinacon-
trolledtemperaturechamberalongwiththermalmodeling
analysis. The junction temperatures are monitored while
ambient temperature is increased with and without air
flow. The power loss increase with ambient temperature
change is factored into the derating curves. The junctions
are maintained at 120°C maximum while lowering output
current or power with increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased. The
monitored junction temperature of 120°C minus the
ambient operating temperature specifies how much mod-
ule temperature rise can be allowed. As an example, in
Figure 11 the load current is derated to ~5A at ~85°C with
the difference of 30°C divided 1.7W equals a 17°C/W θ
JA
thermalresistance.Table2specifiesa16°C/Wvaluewhich
isveryclose.Table2andTable3provideequivalentthermal
resistances for 1.5V and 3.3V outputs with and without air
flow and heat sinking. The derived thermal resistances in
Tables 2 and 3 for the various conditions can be multiplied
by the calculated power loss as a function of ambient
temperature to derive temperature rise above ambient,
thus maximum junction temperature. Room temperature
power loss can be derived from the efficiency curves
in the Typical Performance Characteristics section and
adjusted with the above ambient temperature multiplica-
tive factors. The printed circuit board is a 1.6mm thick
four layer board with two ounce copper for the two outer
layers and one ounce copper for the two inner layers. The
PCB dimensions are 95mm × 76mm. The BGA heat sink
is listed in Table 3.
Safety Considerations
TheLTM4618modulesdonotprovideisolationfromV to
IN
V
OUT
.Thereisnointernalfuse.Ifrequired,aslowblowfuse
with a rating twice the maximum input current needs to be
provided to protect each unit from catastrophic failure.
2.0
3.0
5V
IN
12V
IN
12V
IN
24V
IN
2.5
2.0
1.5
1.0
0.5
0
1.5
1.0
0.5
0
0
1
2
3
4
5
6
0
1
2
3
4
5
6
LOAD CURRENT (A)
LOAD CURRENT (A)
4618 F07
4618 F08
Figure ꢀ. Power Loss at ±.5VOUT
Figure 8. Power Loss at 3.3VOUT
4618f
15
LTM4618
APPLICATIONS INFORMATION
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
0LFM
200LFM
400LFM
0LFM
200LFM
400LFM
0LFM
200LFM
400LFM
70 75 80 85 90 95 100 105 110 115
70 75 80 85 90 95 100 105 110 115
70 75 80 85 90 95 100 105 110 115
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4618 F09
4618 F11
4618 F10
Figure 9. 5VIN to ±.5VOUT without
Heat Sink
Figure ±0. 5VIN to ±.5VOUT with
Heat Sink
Figure ±±. ±2VIN to ±.5VOUT
without Heat Sink
6
6
5
4
3
2
1
0
6
5
4
3
2
1
0
5
4
3
2
1
0
0LFM
200LFM
400LFM
0LFM
200LFM
400LFM
0LFM
200LFM
400LFM
60 65 70 75 80 85 90 95 100 105 110
60 65 70 75 80 85 90 95 100 105 110
70 75 80 85 90 95 100 105 110 115
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4618 F13
4618 F14
4618 F12
Figure ±3. ±2VIN to 3.3VOUT without
Heat Sink
Figure ±2. ±2VIN to ±.5VOUT with
Heat Sink
Figure ±4. ±2VIN to 3.3VOUT with
Heat Sink
6
5
4
3
2
6
5
4
3
2
1
0
0LFM
200LFM
400LFM
1
0
0LFM
200LFM
400LFM
60 65 70 75 80 85 90 95 100 105
60 65 70 75 80 85 90 95 100 105
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4618 F16
4618 F15
Figure ±6. 24VIN to 3.3VOUT with
Heat Sink
Figure ±5. 24VIN to 3.3VOUT
without Heat Sink
4618f
16
LTM4618
APPLICATIONS INFORMATION
Table 2. ±.5V Output
DERATING CURVE
Figures 9, 11
Figures 9, 11
Figures 9, 11
Figures 10, 12
Figures 10, 12
Figures 10, 12
V
(V)
POWER LOSS CURVE
Figure 7
AIRFLOW (LFM)
HEAT SINK
None
Θ
(°C/W)
IN
JA
5, 12
5, 12
5, 12
5, 12
5, 12
5, 12
0
16
Figure 7
200
400
0
None
12.2
11.2
15.2
11.6
10.7
Figure 7
None
Figure 7
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figure 7
200
400
Figure 7
Table 3. 3.3V Output
DERATING CURVE
Figures 13, 15
V
(V)
POWER LOSS CURVE
Figure 8
AIRFLOW (LFM)
HEAT SINK
None
Θ
(°C/W)
IN
JA
12, 24
12, 24
12, 24
12, 24
12, 24
12, 24
0
15
Figures 13, 15
Figure 8
200
400
0
None
11.2
10.2
14.2
10.6
9.7
Figures 13, 15
Figure 8
None
Figures 14, 16
Figure 8
BGA Heat Sink
BGA Heat Sink
BGA Heat Sink
Figures 14, 16
Figure 8
200
400
Figures 14, 16
Figure 8
Heat Sink Used: 15 × 9 Version of Aavid #375424B000346
Table 4. Output Voltage Response vs Component Matriꢂ (Refer to Figure 2±) 0A to 3A Load Step
C
C
C
C
C2
FREQ DROOP P-P DEVIATION RECOVERY LOAD STEP
R
FB
IN
IN
OUT±
OUT2
V
(V) (CERAMIC) (BULK) (CERAMIC) (BULK) COMP
(pF)
(kHz)
400
400
400
400
400
400
500
500
500
500
500
500
500
600
600
600
600
600
(mV)
38
35
30
40
37
27
48
40
30
52
45
50
65
75
60
90
80
150
(mV)
TIME (μs)
(A/μs)
(kΩ)
242
242
242
121
121
121
68.1
68.1
68.1
48.7
48.7
48.7
28
OUT
1
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
68μF
None
220μF
470μF
None
220μF
470μF
None
220μF
470μF
None
220μF
None
None
None
220μF
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
100
None
None
47
76
35
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
22μF × 2
100μF × 4
100μF × 2
100μF
1
1
70
35
60
35
1.2
80
30
100μF × 4
100μF × 2
100μF
1.2
1.2
1.5
1.5
1.5
1.8
1.8
1.8
2.5
2.5
2.5
3.3
3.3
5
None
None
47
74
35
54
35
96
36
100μF × 3
100μF
None
None
47
80
36
100μF
60
40
104
90
36
100μF × 3
100μF
None
47
35
100
130
150
120
180
160
300
35
100μF × 4
100μF × 3
100μF × 4
100μF
47
38
None
None
22
35
28
45
28
36
19.1
19.1
11.5
100μF × 2
100μF × 2
100μF
47
40
47
40
4618f
17
LTM4618
APPLICATIONS INFORMATION
VISHAY INLP1616BZERR22M01
0.22μH
IN
INTV
MODE/PLLIN EXTV
CC
CC
π FILTER
V
FREQ
V
IN
6V TO 26.5V
C
IN
10μF
s2
V
OUT
10μF
V
COMP
TK/SS
RUN
OUT
3.3V/6A
s2
C2
47pF
C
OUT
LTM4618
100μF
V
FB
s3
V
IN
C1
0.1μF
19.1k
PGOOD
R1
R2
SGND PGND
SW
¥
´
R2
R1ꢀR2
4618 F17
V
•
r1.22V
IN
¦
µ
R
§
¶
SNUB
1.2ꢀ 0805
C
SNUB
470pF
0805, 50V
Figure ±ꢀ. 6V to 26.5V Input, 3.3V at 6A Design,
Meeting CISPR25 Conducted and CISPR22 Radiated EMI Solution
10dB/μV
PER DIV
150kHz
100MHz
VIDEO BANDWIDTH
4618 F18
Figure ±8. VIN 26.5V, VOUT 3.3V, IOUT 5A,
π Filter 20μF to 0.22μH Vishay (±6±6BZ) to 20μF
CISPR25 Conducted Emissions
55
45
35
25
15
5
55
CISPR22
CLASS A
45
35
25
15
5
CISPR22
CLASS B
0
100 200 300 400 500 600 700 800 900 1000
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz)
FREQUENCY (MHz)
4618 F19a
4618 F19b
Figure ±9. VIN 26.5V, VOUT 3.3V, IOUT 5A,
π Filter 20μF to 0.22μH Vishay (±6±6BZ) to 20μF
CISPR22 Radiated EMI Plots
4618f
18
LTM4618
APPLICATIONS INFORMATION
EMI Section
• Use large PCB copper areas for high current path,
including V , PGND and V . It helps to minimize
IN
OUT
The LTM4618 has been evaluated for CISPR22 A and B
Radiated EMI and CISPR25 Conducted EMI. The CISPR25
Conducted EMI test was performed with an input π filter
as shown in Figure 17. An RC snubber circuit is optionally
usedfromtheSWpintothePGNDpintoimprovethehigher
frequencyattenuationandEMIlimitguardband. Figure18
shows the CISPR25 conducted emissions plot for 26.5V
input to 3.3V output at 5A load. Several conditions were
evaluated, and Figure 18 results are from the worst-case
condition.Theinputπfilterisusedtoattenuatethereflected
noise from the regulator input, and is primarily utilized
when the power regulators are closed to the input power
feed to a board, like the input power connectors. If the
regulator design is placed out on the center of the system
board, then the input π filter may not be needed because
all of the extra board capacitance and the inductive planes
will provide filtering for reflected emissions. If the system
board has noise sensitive circuitry that is powered from
the same voltage rail as the regulators are, then an input
π filter is a good idea to keep regulator noise from cor-
rupting the noise sensitive circuitry on the system board.
Figure 19 shows the CISPR22 B Radiated EMI plots. The
input π filter is used to attenuate the reflected noise from
propagating out onto the input power cables, thus pos-
sibly causing radiated EMI issues. An RC snubber circuit
is optionally used from the SW pin to the PGND pin to
improve the higher frequency attenuation and EMI limit
the PCB conduction loss and thermal stress.
• Test points can be placed on signal pin for monitor-
ing during testing.
• Place high frequency ceramic input and output
capacitors next to the V , PGND and V
pins to
IN
OUT
minimize high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce mod-
ule thermal stress, use multiple vias for interconnec-
tion between top layer and other power layers.
• Do not put vias directly on the pad, unless they are
capped.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
Figure 20 gives a good example of the recommended
layout.
V
PGND
IN
guard band. A placeholder can accommodate the R
7
SNUB
and C
components with 1.2Ω and 470pF. These
6
5
4
3
2
1
SNUB
components are probably not necessary, but can be used
or adjusted to improve the radiated limit guard bands at
the higher frequencies by attenuating any switch node
ringing due to parasitic values in the high speed switching
paths. It is important to follow the recommended layout
guidelines and use good X5R or X7R ceramic capacitors
to get good results.
CNTRL
A
B
C
D
E
F
G
H
J
K
L
M
CNTRL
C
C
OUT
Layout Checklist/Eꢂample
OUT
ThehighintegrationofLTM4618makesthePCboardlayout
very simple and easy. However, to optimize its electrical
and thermal performance, some layout considerations
are still necessary.
PGND
V
OUT
4618 F20
Figure 20. Recommended PCB Layout Eꢂample
4618f
19
LTM4618
TYPICAL APPLICATIONS
31.6k
10k
INTV
MODE/PLLIN EXTV
CC
CC
V
IN
FREQ
V
IN
6V TO 26.5V
C
IN
10μF
V
OUT
V
COMP
TK/SS
RUN
OUT
s2
2.5V/6A
C2
47pF
C
OUT
LTM4618
100μF
V
FB
s3
V
C1
0.1μF
IN
28.7k
PGOOD
R1
SGND
PGND
¥
´
R2
R1ꢀR2
V
•
r1.22V
4618 F21
IN
¦
µ
§
¶
UVLO FUNCTION
R2
Figure 2±. Typical 6V to 26.5V Input, 2.5V at 6A Design, 500kHz Operation
CLOCK SYNC
0° PHASE
PGOOD MODE/PLLIN
V
IN
FREQ
V
IN
6V TO 26.5V
C
IN1
V
OUT
10μF
V
COMP
TK/SS
RUN
OUT
2.5V/12A
C4
LTM4618
C
OUT
47pF
100μF
V
FB
s4
ON/OFF
0.47μF
R4
14.3k
C3
INTV
CC
CC
SGND
PGND EXTV
+
V
OUT1
LTC6908-1
C5
0.1μF
R5
165k
CLOCK SYNC
180° PHASE
GND
OUT2
MODE/PLLIN
PGOOD
SET
MOD
FREQ
V
IN
C
IN2
10μF
2-PHASE OSCILLATOR
V
OUT
COMP
TK/SS
RUN
LTM4618
V
FB
WITH CLOCK SYNC,
SOFT-START THE REGULATOR FOR APPROXIMATELY 100ms
INTV
CC
CC
100ms • 2 • 1.3μA
SGND
PGND EXTV
C3 ꢁ
0.8V
4618 F22
Figure 22. Two LTM46±8 Parallel, 2.5V at ±2A Design
4618f
20
LTM4618
TYPICAL APPLICATIONS
4618f
21
LTM4618
PACKAGE PHOTOGRAPH
PACKAGE DESCRIPTION
Pin Assignment Tables
(Arranged by Pin Function)
PIN NAME
PIN NAME
PIN NAME
PGND
PIN NAME
A1
A2
A3
A4
A5
A6
A7
N/C
FREQ
MODE/PLLIN
PGND
D1
D2
D3
D4
D5
D6
D7
V
G1
G2
G3
G4
G5
G6
G7
K1
K2
K3
K4
K5
K6
K7
V
V
V
V
FB
OUT
OUT
OUT
OUT
PGOOD
PGND
PGND
PGND
PGND
PGND
PGND
INTV
CC
PGND
PGND
PGND
PGND
V
V
V
PGND
SW
PGND
IN
IN
IN
B1
B2
B3
B4
B5
B6
B7
TK/SS
RUN
E1
E2
E3
E4
E5
E6
E7
PGND
PGND
PGND
PGND
PGND
PGND
PGND
H1
H2
H3
H4
H5
H6
H7
PGND
PGND
PGND
PGND
PGND
PGND
PGND
L1
L2
L3
L4
L5
L6
L7
V
V
V
V
OUT
OUT
OUT
OUT
SGND
PGND
V
V
V
PGND
PGND
PGND
IN
IN
IN
C1
C2
C3
C4
C5
C6
C7
COMP
SGND
SGND
F1
F2
F3
F4
F5
F6
F7
PGND
PGND
PGND
PGND
PGND
PGND
PGND
J1
J2
J3
J4
J5
J6
J7
V
V
V
V
M1
M2
M3
M4
M5
M6
M7
V
V
V
V
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
EXTV
CC
V
V
V
PGND
PGND
PGND
PGND
PGND
PGND
IN
IN
IN
4618f
22
LTM4618
PACKAGE DESCRIPTION
Z
b b b
Z
3 . 8 1 0
2 . 5 4 0
1 . 2 7 0
0 . 0 0 0
1 . 2 7 0
2 . 5 4 0
3 . 8 1 0
0 . 3 1 5
0 . 3 1 5
a a a
Z
4618f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LTM4618
TYPICAL APPLICATION
5V Input, 2.5V at 6A Design, 500kHz Operation
31.6k
10k
INTV
MODE/PLLIN EXTV
CC
CC
V
5V
IN
FREQ
V
IN
4.5V ≤ V ≤ 6V
IN
C
IN
10μF
V
OUT
V
COMP
TK/SS
RUN
OUT
s2
2.5V/6A
C2
47pF
C
OUT
LTM4618
100μF
V
FB
s3
V
C1
0.1μF
IN
28.7k
PGOOD
R1
SGND
PGND
¥
´
R2
R1ꢀR2
V
•
r1.22V
µ
4618 TA02
IN
¦
§
¶
UVLO FUNCTION
R2
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTM4603
6A DC/DC μModule Regulator with PLL
and Output Tracking/Margining
4.5V to 20V Input, 0.6V to 5V Output, 15mm × 15mm × 2.8mm LGA Package
LTM4604A
LTM4608A
LTM4612
LTM4619
LTM8025
4A DC/DC μModule Regulator
8A DC/DC μModule Regulator
2.375V to 5.5V Input, 0.8V to 5V Output, Tracking
2.7V to 5.5V Input, 0.6V to 5V Output, PLL, Tracking
4.5V to 36V Input, 3.3V to 15V Output, PLL, Tracking, Margining
4.5V to 26.5V Input, Dual 0.8V to 5V Output, PLL, Tracking
36V DC/DC μModule Regulator
IN
Dual 4A DC/DC μModule Regulator
36V , 3A DC/DC μModule Regulator
3.6V ≤ V ≤ 36V; 0.8V ≤ V
≤ 24V; 9mm × 15mm × 4.32mm LGA Package
OUT
IN
IN
4618f
LT 0710 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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LTM4619 - Dual, 26VIN, 4A DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C
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LTM4619IV#PBF
LTM4619 - Dual, 26VIN, 4A DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C
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