LTM4619EV#PBF [Linear]
LTM4619 - Dual, 26VIN, 4A DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C;![LTM4619EV#PBF](http://pdffile.icpdf.com/pdf2/p00274/img/icpdf/LTM4619EV-PB_1639553_icpdf.jpg)
型号: | LTM4619EV#PBF |
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描述: | LTM4619 - Dual, 26VIN, 4A DC/DC µModule (Power Module) Regulator; Package: LGA; Pins: 144; Temperature Range: -40°C to 85°C 开关 |
文件: | 总26页 (文件大小:551K) |
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LTM4619
Dual, 26V , 4A DC/DC
IN
µModule Regulator
FeaTures
DescripTion
The LTM®4619 is a complete dual 4A or single 8A step-
downDC/DCµModule® (micromodule)regulator.Included
in the package are the switching controller, power FETs,
inductor, and all support components. Operating over
input voltage ranges of 4.5V to 26.5V, the LTM4619 sup-
ports two outputs with voltage ranges of 0.8V to 5V, each
set by a single external resistor. Its high efficiency design
delivers 4A continuous current (5A peak) for each output.
n
Complete Standalone Power Supply
n
Wide Input Voltage Range: 4.5V to 26.5V
(EXTV Available for V ≤ 5.5V)
CC
IN
n
Dual 180° Out-of-Phase Outputs with 4A DC
Typical, 5A Peak Output Current for Each
Dual Outputs with 0.8V to 5V Range
Output Voltage Tracking
n
n
n
n
n
n
n
n
n
n
n
1.5ꢀ Maꢁimum Total DC Output Error
Current Mode Control/Fast Transient Response
Power Good
Highswitchingfrequencyandacurrentmodearchitecture
enable a very fast transient response to line and load
changes without sacrificing stability. The two outputs
are interleaved with 180° phase to minimize the ripple
noise and reduce the I/O capacitors. The device supports
frequencysynchronizationandoutputvoltagetrackingfor
supply rail sequencing. Burst Mode operation or pulse-
skipping mode can be selected for light load operations.
Phase-Lockable Fiꢁed Frequency 250kHz to 780kHz
On Board Frequency Synchronization
Parallel Current Sharing
Selectable Burst Mode® Operation
Output Overvoltage Protection
15mm × 15mm × 2.82mm LGA Package
Fault protection features include overvoltage protection,
overcurrent protection and foldback current limit for
short-circuit protection.
applicaTions
n
Telecom and Networking Equipment
n
Servers
The low profile package (2.82mm) enables utilization of
unused space on the bottom of PC boards for high density
point of load regulation. The power module is offered in
a 15mm × 15mm × 2.82mm LGA package. The LTM4619
is RoHS compliant with Pb-free finish.
n
Storage Cards
n
ATCA Cards
Industrial Equipment
Point of Load Regulation
n
n
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and µModule are registered
trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.
Typical applicaTion
Dual 4A 3.3V/2.5V DC/DC µModule Regulator
Efficiency and Power Loss at 12V input
95
90
85
80
75
70
65
60
55
2.0
1.5
1.0
0.5
0
EFFICIENCY
MODE/PLLIN INTV
CC
FREQ/PLLFLTR
5.5V TO 26.5V
V
V
IN
10µF
28k
19.1k
22pF
×2
V
FB1
FB2
22pF
COMP1
COMP2
V
V
OUT2
3.3V/4A
OUT1
LTM4619
V
V
OUT2
OUT1
2.5V/4A
100µF
100µF
TK/SS1
RUN1
TK/SS2
RUN2
POWER LOSS
0.1µF
0.1µF
PGOOD
EXTV
CC
2.5V
3.3V
OUT
OUT
SGND
PGND
4619 TA01a
0
0.5
1
1.5
2
2.5
3
3.5
4
LOAD CURRENT (A)
4619 TA01b
4619fc
1
For more information www.linear.com/LTM4619
LTM4619
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V ............................................................. –0.3V to 28V
IN
TK/SS2
V
COMP2 COMP1
V
TK/SS1
FB2
FB1
INTV , PGOOD, RUN1, RUN2, EXTV ....... –0.3V to 6V
CC
CC
M
L
V
, V ................................................. –0.3V to 2.7V
V
IN
FB1 FB2
COMP1, COMP2 (Note 4).......................... –0.3V to 2.7V
MODE/PLLIN, TK/SS1, TK/SS2,
K
J
RUN2
FREQ/PLLFLTR
RUN1
EXTV
CC
SGND
FREQ/PLLFLTR .....................................–0.3V to INTV
CC
H
G
F
SW2
SW1
V
, V
.................................................. 0.8V to 5V
OUT1 OUT2
Internal Operating Temperature Range
PGOOD
MODE/PLLIN
INTV
CC
(Note 2).................................................. –40°C to 125°C
Maximum Reflow Body Temperature.................... 245°C
Storage Temperature Range .................. –55°C to 125°C
E
D
C
B
A
GND
V
V
OUT1
OUT2
2
1
3
4
5
6
7
8
9
10
11
12
LGA PACKAGE
144-LEAD (15mm × 15mm × 2.82mm)
T
= 125°C, θ = 13.4°C/W, θ = 6°C/W, θ = 16°C/W, θ ≈ θ
,
JMAX
JA
JCbottom
JCtop
JB
JCbottom
θ
JB
+ θ = 13.4° C/W, θ DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g
BA
JA
orDer inForMaTion
PART NUMBER
PAD OR BALL FINISH
PART MARKING*
PACKAGE
TYPE
MSL
TEMPERATURE RANGE
RATING (SEE NOTE 2)
DEVICE
FINISH CODE
LTM4619EV#PBF
LTM4619IV#PBF
Au (RoHS)
Au (RoHS)
LTM4619V
LTM4619V
e4
e4
LGA
LGA
3
3
–40°C to 125°C
–40°C to 125°C
Consult Marketing for parts specified with wider operating temperature
ranges. *Device temperature grade is indicated by a label on the shipping
container. Pad or ball finish code is per IPC/JEDEC J-STD-609.
• Recommended LGA and BGA PCB Assembly and Manufacturing
Procedures:
www.linear.com/umodule/pcbassembly
• LGA and BGA Package and Tray Drawings:
http://www.linear.com/packaging
• Terminal Finish Part Markings:
www.linear.com/leadfree
elecTrical characTerisTics
The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 19.
Specified as each channel. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
4.5
TYP
MAX
26.5
5.0
UNITS
l
l
V
V
V
Input DC Voltage
Output Voltage Range
Output Voltage
V
V
C
≤ 5.5V, Connect V and INTV Together
V
V
IN(DC)
IN
IN
IN
IN
CC
= 5.5V to 26.5V
0.8
OUT1, 2(RANGE)
OUT1, 2(DC)
= 10µF ×1, C
= 100µF Ceramic, 100µF POSCAP,
OUT
R
= 28.0kΩ
= 12V, V
= 12V, V
SET
V
2.483
2.470
2.52 2.557
2.52 2.570
V
V
= 2.5V, I
= 2.5V, I
= 0A
= 4A
IN
IN
OUT
OUT
OUT
OUT
l
V
Input Specifications
V
Undervoltage Lockout Thresholds
V
V
Rising
Falling
2.00
1.85
2.2
2.0
2.35
2.15
V
V
IN(UVLO)
INTVCC
INTVCC
4619fc
2
For more information www.linear.com/LTM4619
LTM4619
elecTrical characTerisTics The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 19.
Specified as each channel. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
Input Inrush Current at Start-Up
I
= 0A, C = 10µF, C
= 100µF, V
= 2.5V
INRUSH(VIN)
OUT
IN
IN
OUT
OUT
V
= 12V
0.25
A
I
Input Supply Bias Current
Input Supply Current
V
V
V
V
= 12V, V
= 12V, V
= 2.5V, Switching Continuous
= 2.5V, Switching Continuous
OUT1
OUT2
30
30
40
40
40
mA
mA
mA
mA
µA
Q(VIN)
IN
IN
IN
IN
OUT1
OUT2
= 26.5V, V
= 26.5V, V
= 2.5V, Switching Continuous
= 2.5V, Switching Continuous
Shutdown, RUN = 0, V = 20V
IN
I
V
V
= 12V, V
= 2.5V, I = 4A
OUT
0.97
0.480
A
A
S(VIN)
IN
IN
OUT
= 26.5V, V
= 2.5V, I
= 4A
OUT
OUT
INTV
Internal V Voltage
V
= 12V, V > 2V, No Load
RUN
4.8
4.5
5
5.2
4
V
V
CC
CC
IN
l
EXTV
EXTV Switchover Voltage
EXTV Ramping Positive
4.7
CC
CC
CC
Output Specifications
I
Output Continuous Current Range
Line Regulation Accuracy
V
V
= 12V, V = 2.5V (Note 5)
OUT
0
A
OUT1, 2(DC)
IN
= 2.5V, V from 6V to 26.5V
0.15
0.25
0.3
0.5
%
%
ΔV
OUT1(LINE)
OUT
OUT
IN
l
I
= 0A For Each Output
V
OUT(NOM)
Line Regulation Accuracy
Load Regulation Accuracy
Load Regulation Accuracy
Output Ripple Voltage
V
= 2.5V, V from 6V to 26.5V
0.15
0.25
0.3
0.5
%
%
ΔV
V
OUT
OUT
IN
OUT2(LINE)
l
l
I
= 0A For Each Output
OUT(NOM)
For Each Output, V
V
= 2.5V, 0A to 4A (Note 5)
= 2.5V, 0A to 4A (Note 5)
0.6
0.8
%
ΔV
V
OUT
OUT
OUT1(LOAD)
= 12V
IN
OUT1(NOM)
l
For Each Output, V
V
0.6
0.8
%
ΔV
OUT2(LOAD)
= 12V
IN
V
OUT2(NOM)
V
I
= 0A, C
= 100µF X5R Ceramic
OUT
OUT1, 2(AC)
OUT
V
V
= 12V, V
= 2.5V
OUT
20
25
mV
mV
IN
IN
= 26.5V, V
= 2.5V
OUT
f
Output Ripple Voltage Frequency
Turn-On Overshoot
I
= 2A, V = 12V, V
= 2.5V
780
kHz
S
OUT
IN
OUT
CC
FREQ/PLLFLTR = INTV
C
= 100µF X5R Ceramic, V
= 2.5V, I
= 2.5V, I
= 0A
= 0A
ΔV
OUT
OUT
OUT
OUT
OUTSTART
V
= 12V
10
10
mV
mV
IN
IN
V
= 26.5V
t
Turn-On Time
C
= 100µF X5R Ceramic, V
OUT
START
OUT
Resistive Load,
V
IN
V
IN
= 12V
= 26.5V
0.250
0.130
ms
ms
Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load
= 100µF X5R Ceramic,V = 2.5V, V = 12V
ΔV
OUTLS
C
15
10
mV
µs
OUT
OUT
IN
t
I
Settling Time for Dynamic Load
Step
Load: 0% to 50% to 0% of Full Load
OUT
SETTLE
C
= 100µF X5R Ceramic,V
= 2.5V, V = 12V
OUT IN
Output Current Limit
C
= 100µF X5R Ceramic,
OUTPK
OUT
V
= 6V, V
= 2.5V
OUT
12
11
A
A
IN
IN
V
= 26.5V, V
= 2.5V
OUT
Control Section
V
, V
FB1 FB2
Voltage at V Pin
I
= 0A, V = 2.5V
OUT
0.792
0.788
0.8
0.8
0.808
0.810
V
FB
OUT
l
I
Soft-Start Charge Current
Maximum Duty Factor
Minimum On-Time
V
= 0V, V = 2.5V
OUT
0.9
1.3
97
90
1.7
µA
%
TK/SS1, 2
TK/SS
DF
In Dropout (Note 4)
(Note 4)
MAX
t
ns
ON(MIN)
4619fc
3
For more information www.linear.com/LTM4619
LTM4619
elecTrical characTerisTics
The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 19.
Specified as each channel. (Note 3)
SYMBOL
PARAMETER
CONDITIONS
MIN
450
210
700
TYP
500
250
780
250
MAX
550
290
860
UNITS
kHz
f
f
f
Nominal Frequency
Lowest Frequency
Highest Frequency
MODE/PLLIN Input Resistance
V
V
V
= 1.2V
= 0V
NOM
LOW
HIGH
FREQ
FREQ
FREQ
kHz
≥ 2.4V
kHz
R
kΩ
MODE/PLLIN
FREQ
I
Frequency Setting
Sinking Current
Sourcing Current
f
f
> f
< f
–13
13
µA
µA
MODE
MODE
OSC
OSC
V
RUN Pin ON/OFF Threshold
RUN Rising
RUN Falling
1.1
1.02
1.22
1.14
1.35
1.27
V
V
RUN1, 2
R
, R
FB1 FB2
Resistor Between V
and V
FB
60.1
60.4
60.7
kΩ
OUT
Pins for Each Channel
V
PGOOD Voltage Low
I
= 2mA
= 5V
0.1
0.3
2
V
PGL
PGOOD
I
PGOOD Leakage Current
PGOOD Range
V
µA
PGOOD
PGOOD
V
V
Ramping Negative
Ramping Positive
–5
5
–7.5
7.5
–10
10
%
%
ΔV
FB
FB
PGOOD
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
internal operating temperature range. Note that the maximum ambient
temperature consistent with these specifications is determined by specific
operating conditions in conjunction with board layout, the rated package
thermal resistance and other environmental factors.
Note 2: The LTM4619E is guaranteed to meet performance specifications
over the 0°C to 125°C internal operating temperature range. Specifications
over the full –40°C to 125°C internal operating temperature range are
assured by design, characterization and correlation with statistical process
controls. The LTM4619I is guaranteed to meet specifications over the full
Note 3: The two outputs are tested separately and the same testing
condition is applied to each output.
Note 4: 100% tested at wafer level only.
Note 5: See Output Current Derating curves for different V , V
and T .
A
IN OUT
Typical perForMance characTerisTics
(Refer to Figures 19 and 20)
Efficiency vs Load Current with
Efficiency vs Load Current with
12VIN (f = 500kHz for 1.2VOUT and
5VIN (f = 500kHz for 0.8VOUT
,
Efficiency vs Load Current with
24VIN (f = 500kHz for 1.5VOUT
1.2VOUT and 1.5VOUT
)
1.5VOUT
)
)
95
90
85
80
75
70
65
60
55
50
45
95
90
85
80
75
70
65
60
55
95
90
85
80
75
70
65
60
55
5V
3.3V
OUT
OUT
5V
OUT
2.5V
OUT
3.3V
OUT
3.3V
OUT
2.5V
OUT
1.2V
OUT
1.5V
OUT
1.5V
1.2V
OUT
2.5V
OUT
OUT
1.5V
OUT
0.8V
OUT
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
0
0.5
1
1.5
2
2.5
3
3.5
4
LOAD CURRENT (A)
LOAD CURRENT (A)
LOAD CURRENT (A)
4619 G03
4619 G01
4619 G02
4619fc
4
For more information www.linear.com/LTM4619
LTM4619
(Refer to Figures 19 and 20)
Typical perForMance characTerisTics
1.2V Output Transient Response
1.5V Output Transient Response
2.5V Output Transient Response
I
I
I
OUT
1A/DIV
OUT
OUT
1A/DIV
1A/DIV
V
V
V
OUT
OUT
OUT
50mV/DIV
50mV/DIV
50mV/DIV
4619 G04
4619 G05
4619 G06
100µs/DIV
100µs/DIV
100µs/DIV
6V 1.2V
AT 2A/µs LOAD STEP
6V 1.5V
AT 2A/µs LOAD STEP
6V 2.5V AT 2A/µs LOAD STEP
IN
OUT
IN
OUT
IN
OUT
f = 780kHz
f = 780kHz
f = 780kHz
C
C
2× 22µF, 6.3V X5R CERAMIC
1× 330µF, 6.3V SANYO POSCAP
C
OUT
C
OUT
2× 22µF, 6.3V X5R CERAMIC
1× 330µF, 6.3V SANYO POSCAP
C
C
2× 22µF, 6.3V X5R CERAMIC
1× 330µF, 6.3V SANYO POSCAP
OUT
OUT
OUT
OUT
3.3V Output Transient Response
Start-Up, IOUT = 0A
Start-Up, IOUT = 4A
I
V
V
OUT
IN
IN
1A/DIV
1V/DIV
1V/DIV
V
OUT
50mV/DIV
I
I
IN
IN
0.5A/DIV
0.5A/DIV
4619 G09
4619 G07
4619 G08
20ms/DIV
100µs/DIV
20ms/DIV
V
I
= 12V, V
= 2.5V,
6V 3.3V
AT 2A/µs LOAD STEP
V
C
= 12V, V
OUT
AND 1× 100µF 6.3V CERAMIC CAPs
= 2.5V, I
= 0A
IN
OUT
IN
OUT
IN
OUT
OUT
= 4A RESISTIVE LOAD
f = 780kHz
= 2× 22µF 10V
OUT
OUT
C
= 2× 22µF 10V,
C
C
2× 22µF, 6.3V X5R CERAMIC
1× 330µF, 6.3V SANYO POSCAP
OUT
OUT
AND 1× 100µF 6.3V CERAMIC CAPs
C
= 0.1µF
SOFTSTART
C
= 0.1µF
USE RUN PIN TO CONTROL START-UP
SOFTSTART
USE RUN PIN TO CONTROL START-UP
Short Circuit, IOUT = 0A
Short Circuit, IOUT = 4A
V
V
OUT
1V/DIV
OUT
1V/DIV
I
IN
0.5A/DIV
I
IN
0.5A/DIV
4619 G10
4619 G11
50µs/DIV
= 2.5V, I
50µs/DIV
V
C
= 12V, V
OUT
= 0A
V
C
= 12V, V
OUT
= 2.5V, I
= 4A
IN
OUT
OUT
IN
OUT
OUT
= 2× 22µF 10V,
= 2× 22µF 10V,
AND 1× 100µF 6.3V CERAMIC CAPs
AND 1× 100µF 6.3V CERAMIC CAPs
4619fc
5
For more information www.linear.com/LTM4619
LTM4619
pin FuncTions
PACKAGE ROW AND COLUMN LABELING MAY VARY
FREQ/PLLFLTR (J8): Frequency Selection Pin. An internal
lowpass filter is tied to this pin. The frequency can be
selected from 250kHz to 780kHz by varying the DC volt-
age on this pin from 0V to 2.4V. The nominal frequency
setting is 500kHz. Frequency selection can be modified as
long as the inductor ripple current is less ≈40% to 50%
at the output current
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
V (J1 to J3, J10 to J12, K1 to K4, K9 to K12, L1 to L5,
IN
L8 to L12, M1 to M12): Power Input Pins. Apply input
voltage between these pins and PGND pins. Recommend
placinginput decouplingcapacitance directlybetween V
IN
CC
pins and PGND pins. For V < 5.5, tie V and INTV
IN
IN
1
VOUT
together.
1–
VOUT
FREQ
V
IN
IRIPPLE
=
V
, V
(A10 to D10, A11 to D11, A12 to D12, A1 to
OUT1 OUT2
L
D1, A2 to D2, A3 to D3): Power Output Pins. Apply output
load between these pins and PGND pins. Recommend
placing output decoupling capacitance directly between
these pins and PGND pins.
Where FREQ is selected operating frequency and L is
the inductor value. Leave this pin floating when external
synchronization is used.
PGND (H1, H2, H4, H9, H11, H12, G1 to G12, F1 to F5,
F7 to F12, E1 to E12, D4 to D9, C4 to C9, B4 to B9, A4 to
A9): Power ground pins for both input and output returns.
TK/SS1, TK/SS2 (K8, K5): Output Voltage Tracking and
Soft-StartPins.Internalsoft-startcurrentsof1.3µAcharge
thesoft-startcapacitors. SeetheApplicationsInformation
section to use the tracking function.
INTV (F6): Internal 5V Regulator Output. This pin is for
CC
additional decoupling of the 5V internal regulator.
V
, V
(K7, K6): The negative input of the error
FB1
FB2
amplifier. Internally, this pin is connected to V
with
OUT
EXTV (J4): External Power Input to Controller. When
CC
a 60.4k precision resistor. Different output voltages can
be programmed with an additional resistor between V
EXTV is higher than 4.7V, the internal 5V regulator is
CC
FB
disabled and external power supplies current to reduce
the power dissipation in the module. This will improve the
efficiency more at high input voltages.
and SGND pins. See the Applications Information section
for details.
COMP1, COMP2 (L7, L6): Current Control Threshold and
ErrorAmplifierCompensationPoint.Themodulehasbeen
internally compensated for most I/O ranges.
SGND(J6, J7, H6, H7):SignalGroundPin. Returnground
path for all analog and low power circuitry. Tie a single
connection to PGND in the application.
PGOOD (H5): Output Voltage Power Good Indicator. Open
drain logic output that is pulled to ground when the output
voltage is not within 7.5% of the regulation point.
MODE/PLLIN(H8):Modeselectionorexternalsynchroniza-
tion pin. Tying this pin high enables pulse-skipping mode.
Tying this pin low enables force continuous operation.
Floating this pin enables Burst Mode operation. A clock
on the pin will force the controller into the continuous
mode of operation and synchronize the internal oscillator.
The suitable synchronizable frequency range is 250kHz to
780kHz subject to inductor ripple current limits described
in the FREQ/PLLFLTR pin section. The external clock input
high threshold is 1.6V, while the input low threshold is 1V.
RUN1, RUN2 (J9, J5): Run Control Pins. 0.5µA pull-up
currents on these pins turn on the module if these pins
are floating. Forcing either of these pins below 1.2V will
shutdownthecorrespondingoutputs.Anadditional4.5µA
pull-up current is added to this pin, once the RUN pin rises
above 1.2V. Also, active control or pull-up resistors can
be used to enable the RUN pin. The maximum voltage is
6V on these pins.
SW1, SW2 (H10, H3): Switching Test Pins. These pins
are provided externally to check the operation frequency.
4619fc
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LTM4619
siMpliFieD block DiagraM
V
INTERNAL
FILTER
IN
4.5V TO 26.5V*
+
+
1.5µF
C
C
IN
INTV
CC
M1
M2
PGND
SW1
PGOOD
MODE/PLLIN
V
OUT1
2.5V/4A
L1
1.5µH
EXTV
CC
10µF
V
IN
OUT1
TK/SS1
PGND
C
SS1
R1
R2
RUN1
60.4k
COMP1
V
FB1
R
28k
INTERNAL
COMP
SET1
POWER
CONTROL
R2
R1+R2
• V
IN
1.5µF
TK/SS2
= UVLO THRESHOLD = 1.22V
M3
M4
PGND
SW2
C
SS2
RUN2
V
OUT2
3.3V/4A
L2
1.5µH
COMP2
+
10µF
C
OUT2
INTERNAL
COMP
PGND
60.4k
FREQ
V
FB2
INTERNAL
FILTER
R
SET2
19.1k
SGND
4619 BD
*USE EXTV FOR V ≤ 5.5V, OR TIE V AND EXTV TOGETHER FOR V ≤ 5.5V
CC
IN
IN
CC
IN
Figure 1. Simplified LTM4619 Block Diagram
TA = 25°C. Use Figure 1 configuration.
CONDITIONS
Decoupling requireMenTs
SYMBOL
PARAMETER
MIN
10
TYP
MAX
UNITS
External Input Capacitor Requirement
C
(V = 4.5V to 26.5V, V
= 2.5V, V
= 3.3V)
= 3.3V)
I
= 4A, I = 4A
OUT2
µF
IN
IN
OUT1
OUT2
OUT1
External Output Capacitor Requirement
(V = 4.5V to 26.5V, V = 2.5V, V
C
OUT1
C
OUT2
I
I
= 4A
= 4A
200
200
µF
µF
IN
OUT1
OUT2
OUT1
OUT2
4619fc
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LTM4619
operaTion
The LTM4619 is a dual-output standalone non-isolated
switching mode DC/DC power supply. It can deliver up to
4A(DCcurrent)foreachoutputwithfewexternalinputand
outputcapacitors.Thismoduleprovidespreciselyregulated
output voltages programmable via external resistors from
0.8VDC to 5.0VDC over 4.5V to 26.5V input voltages. The
typical application schematic is shown in Figure 19.
Internal overvoltage and undervoltage comparators pull
the open-drain PGOOD output low if the output feedback
voltageexitsa 7.5%windowaroundtheregulationpoint.
The power good pin is disabled during start-up.
Pulling the RUN pin below 1.2V forces the controller into
its shutdown state, by turning off both MOSFETs. The
TK/SS pin is used for programming the output voltage
ramp and voltage tracking during start-up. See the Ap-
plications Information section.
The LTM4619 has integrated constant frequency current
mode regulators and built-in power MOSFET devices with
fast switching speed. The typical switching frequency is
780kHz. To reduce switching noise, the two outputs are
interleavedwith180°phaseinternallyandcanbesynchro-
nized externally using the MODE/PLLIN pin.
The LTM4619 is internally compensated to be stable over
all operating conditions. LTpowerCAD™ is available for
transient and stability analysis. The V pin is used to
FB
program the output voltage with a single external resistor
to ground. Multiphase operation can be easily employed
with the synchronization.
With current mode control and internal feedback loop
compensation, the LTM4619 module has sufficient stabil-
ity margins and good transient performance with a wide
range of output capacitors, even with all ceramic output
capacitors.
High efficiency at light loads can be accomplished with
selectable Burst Mode operation or pulse-skipping mode
usingtheMODE/PLLINpin.Efficiencygraphsareprovided
for light load operations in the Typical Performance Char-
acteristics section.
Currentmodecontrolprovidescycle-by-cyclefastcurrent
limit and current foldback in a short-circuit condition.
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LTM4619
applicaTions inForMaTion
The typical LTM4619 application circuit is shown in
Figure19.Externalcomponentselectionisprimarilydeter-
mined by the maximum load current and output voltage.
Without considering the inductor ripple current, for each
output, the RMS current of the input capacitor can be
estimated as:
I
OUT(MAX) • D•(1− D)
Output Voltage Programming
ICIN(RMS)
=
η
ThePWMcontrollerhasaninternal0.8Vreferencevoltage.
As shown in the block diagram, a 60.4k internal feedback
In the above equation, η is the estimated efficiency of the
power module. The bulk capacitor can be a switcher-rated
aluminumelectrolyticcapacitororapolymercapacitor.One
10µF ceramic input capacitor is typically rated for 2A of
RMS ripple current, so the RMS input current at the worst
case for each output at 4A maximum current is about 2A.
If a low inductance plane is used to power the device, then
two 10µF ceramic capacitors are enough for both outputs
at 4A load and no external input bulk capacitor is required.
resistor R connects V
to V pin. The output voltage
FB
OUT
FB
will default to 0.8V with no feedback resistor. Adding a
resistor R from V pin to SGND programs the output
SET
FB
voltage:
60.4k+ RSET
VOUT = 0.8V •
RSET
or equivalently
60.4k
Output Capacitors
RSET
=
V
OUT
The LTM4619 is designed for low output voltage ripple
noise. The bulk output capacitors defined as C
–1
0.8V
are
OUT
chosen with low enough effective series resistance (ESR)
to meet the output voltage ripple and transient require-
Table 1. RSET Resistor Table vs Various Output Voltages
V
(V)
0.8
1.2
1.5
1.8
2.5
3.3
5
OUT
ments. C
can be a low ESR tantalum capacitor, a low
OUT
R
(kΩ)
Open
121
68.1
48.7
28.0
19.1
11.5
SET
ESR polymer capacitor or ceramic capacitor. The typical
output capacitance range for each output is from 47µF
to 220µF. Additional output filtering may be required by
the system designer. If further reduction of output ripple
or dynamic transient spikes is required, LTpowerCAD is
available for stability analysis. Multiphase operation will
reduce effective output ripple as a function of the num-
ber of phases. Application Note 77 discusses this noise
reduction versus output ripple current cancellation, but
the output capacitance should be considered carefully as
afunctionofstabilityandtransientresponse. LTpowerCAD
calculates the output ripple reduction as the number of
implemented phases increased by N times.
Input Capacitors
The LTM4619 module should be connected to a low AC-
impedanceDCsource.Two1.5µFinputceramiccapacitors
areincludedinsidethemodule.Additionalinputcapacitors
are needed if a large load is required up to the 4A level.
A 47µF to 100µF surface mount aluminum electrolytic
capacitor can be used for more input bulk capacitance.
This bulk capacitor is only needed if the input source im-
pedance is compromised by long inductive leads, traces
or not enough source capacitance.
For a buck converter, the switching duty-cycle can be
estimated as:
VOUT
D=
V
IN
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LTM4619
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Mode Selections and Phase-Locked Loop
Frequency Selection
The LTM4619 can be enabled to enter high efficiency
BurstModeoperation,constant-frequencypulse-skipping
mode, or forced continuous conduction mode. To select
the forced continuous operation, tie the MODE/PLLIN pin
to a DC voltage below 0.8V. To select pulse-skipping mode
The switching frequency of the LTM4619’s controllers
can be selected using the FREQ/PLLFLTR pin. If the
MODE/PLLIN pin is not being driven by an external clock
source,theFREQ/PLLFLTRpincanbesetfrom0Vto2.4Vto
programthecontroller’soperatingfrequencyfrom250kHz
of operation, tie the MODE/PLLIN pin to INTV . To select
to 780kHz using a voltage divider to INTV (see Figure
CC
CC
Burst Mode operation, float the MODE/PLLIN pin.
20). The typical frequency is 780kHz. If the output is too
low or the minimum on-time is reached, the frequency
needs to decrease to enlarge the turn-on time. Otherwise,
a significant amount of cycle skipping can occur with cor-
respondingly larger current and voltage ripple.
Frequency Synchronization
A phase-lock loop is available on the LTM4619 to syn-
chronize the internal clock to an external clock source
connected on the MODE/PLLIN pin. The clock high level
needs to be higher than 1.6V and the clock low level needs
to be lower than 1V. The frequency programming voltage
and or the programming voltage divider must be removed
from the FREQ/PLLFLTR pin when synchronizing to an
external clock. The FREQ/PLLFLTR pin has the required
onboard PLL filter components for clock synchronization.
TheLTM4619willdefaulttoforcedcontinuousmodewhile
being clock synchronized. Channel 1 is synchronized to
the rising edge on the external clock, and channel 2 is 180
degrees out-of-phase with the external clock.
900
800
700
600
500
400
300
200
100
0
0
0.5
1
1.5
2
2.5
FREQ/PLLFLTR PIN VOLTAGE (V)
4619 F02
Figure 2. Switching Frequency vs FREQ/PLLFLTR Pin Voltage
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LTM4619
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Soft-Start and Tracking
Output voltage tracking can be programmed externally
using the TK/SS pin. The master channel is divided down
with an external resistor divider that is the same as the
slave channel’s feedback divider to implement coincident
tracking. The LTM4619 uses an accurate 60.4k resistor
internally for the top feedback resistor. Figure 3 shows an
example of coincident tracking. Figure 4 shows the output
voltages with coincident tracking.
The LTM4619 has the ability to either soft-start by itself
with a capacitor or track the output of another channel or
externalsupply.Whenoneparticularchannelisconfigured
to soft-start by itself, a capacitor should be connected to
its TK/SS pin. This channel is in the shutdown state if its
RUN pin voltage is below 1.2V. Its TK/SS pin is actively
pulled to ground in this shutdown state.
R1
R2
Once the RUN pin voltage is above 1.2V, the channel pow-
ers up. A soft-start current of 1.3µA then starts to charge
its soft-start capacitor. Note that soft-start or tracking is
achieved not by limiting the maximum output current of
the controller but by controlling the output ramp voltage
according to the ramp rate on the TK/SS pin. Current
foldback is disabled during this phase to ensure smooth
soft-start or tracking. The soft-start or tracking range is
defined to be the voltage range from 0V to 0.8V on the
TK/SS pin. The total soft-start time can be calculated as:
VSLAVE = 1+
•V
TRACK
V
is the track ramp applied to the slave’s TK/SS2
TRACK
pin. V
has a control range of 0V to 0.8V. When the
TRACK
master’s output is divided down with the same resistor
values used to set the slave’s output, then the slave will
coincident track with the master until it reaches its final
value. The master will continue to its final value from the
slave’s regulation point.
Ratiometric modes of tracking can be achieved by select-
ing different divider resistors values to change the output
tracking ratio. The master output must be greater than the
slave output for the tracking to work. Master and slave
data inputs can be used to implement the correct resistors
values for coincident or ratiometric tracking.
0.8V •CSS
tSOFT-START
=
1.3µA
V
MODE/PLLIN INTV
IN
CC
5.5V TO
V
V
FREQ/PLLFLTR
IN
28V
C
IN
V
FB1
FB2
R3
19.1k
R4
MASTER OUTPUT
C2
22pF
C3
22pF
COMP1
COMP2
28k
V
V
LTM4619
OUT2
OUT1
3.3V
V
V
OUT2
OUT1
2.5V
SLAVE OUTPUT
C
C
TK/SS1
RUN1
TK/SS2
RUN2
OUT2
OUT1
OUTPUT
VOLTAGE
C1
0.1µF
V
OUT1
PGOOD
EXTV
CC
R1
60.4k
SGND
PGND
4619 F03
R2
28k
4619 F04
TIME
Figure 3. Eꢁample of Coincident Tracking
Figure 4. Coincident Tracking
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0.60
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
OUT IN
4619 F05
Figure 5. Normalized Input RMS Ripple Current vs Duty Cycle for One to Siꢁ Phases
1.00
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (V /V
)
OUT IN
4619 F06
Figure 6. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOUT T/L
4619fc
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LTM4619
applicaTions inForMaTion
Multiphase Operation
RUN Pin
Multiphase operation with multiple LTM4619 devices in
parallel will lower the effective input RMS ripple current
as well as the output ripple current due to the interleaving
operation of the regulators. Figure 5 provides a ratio of
input RMS ripple current to DC load current as a function
of duty cycle and the number of paralleled phases. Choose
the corresponding duty cycle and the number of phases
to get the correct ripple current value. For example, the
2-phase parallel for one LTM4619 design provides 8A
at 2.5V output from a 12V input. The duty cycle is DC =
2.5V/12V = 0.21. The 2-phase curve has a ratio of ~0.25
for a duty cycle of 0.21. This 0.25 ratio of RMS ripple cur-
rent to a DC load current of 8A equals ~2A of input RMS
ripple current for the external input capacitors.
The RUN pins can be used to enable or sequence the
particular regulator channel. The RUN pins have their own
internal0.5µAcurrentsourcetopullupthepinto1.2V, and
then the current increases to 4.5µA above 1.2V. Careful
considerationisneededtoassurethatboardcontamination
or residue does not load down the 0.5µA pull-up current.
Otherwise active control to these pins can be used to en-
able the regulators. A voltage divider can be used from
V to set an enable point that can also be used as a UVLO
IN
feature for the regulator. The resistor divider needs to be
low enough resistance to swamp out the pull-up current
sources to prevent unintended activation of the device.
See the Simplified Block Diagram.
Power Good
The effective output ripple current is lowered with mul-
tiphase operations as well. Figure 6 provides a ratio of
peak-to-peak output ripple current to the normalized
output ripple current as a function of duty cycle and the
number of paralleled phases. Choose the corresponding
duty cycle and the number of phases to get the correct
output ripple current ratio value. If a 2-phase operation
ThePGOODpinisconnectedtotheopendrainofaninternal
N-channel MOSFET. The MOSFET turns on and pulls the
PGOOD pin low when either V pin voltage is not within
FB
7.5% of the 0.8V reference voltage. The PGOOD pin is
alsopulledlowwheneitherRUNpinisbelow1.2Vorwhen
the LTM4619 is in the soft-start or tracking phase. When
the V pin voltage is within the 7.5% requirement, the
is chosen at 12V to 2.5V
with a duty cycle of 21%,
FB
IN
OUT
MOSFET is turned off and the pin is allowed to be pulled
up by an external resistor to a source of up to 6V. The
PGOOD pin will flag power good immediately when both
then 0.6 is the ratio of the normalized output ripple cur-
rent to inductor ripple DIr at zero duty cycle. This leads
to ~1.3A of the effective output ripple current ΔI if the
L
V
pins are within the 7.5% window. However, there is
DIr is at 2.2A. Refer to Application Note 77 for a detailed
explanation of the output ripple current reduction as a
function of paralleled phases.
FB
an internal 17µs power bad mask when either V goes
FB
out of the 7.5% window.
The output ripple voltage has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
Therefore, the output ripple voltage can be calculated with
the known effective output ripple current. The equation:
ΔV
≈ ΔI /(8 • f • N • C ) + ESR • ΔI
L OUT L
OUT(P-P)
wherefisfrequencyandNisthenumberofparallelphases.
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LTM4619
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Fault Conditions: Current Limit and Overcurrent
Foldback
INTV and EXTV
CC
CC
The INTV is the internal 5V regulator that powers the
CC
The LTM4619 has a current mode controller, which inher-
ently limits the cycle-by-cycle inductor current not only in
steady-state operation, but also in transient.
LTM4619internalcircuitryanddrivesthepowerMOSFETs.
The input voltage of the LTM4619 must be 6V or above
for the INTV to regulate to the proper 5V level due to
CC
the internal LDO dropout from the input voltage. For ap-
To further limit current in the event of an overload condi-
tion,theLTM4619providesfoldbackcurrentlimiting.Ifthe
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to one-third of its
fullcurrentlimitvalue.Foldbackcurrentlimitingisdisabled
during soft-start and tracking up.
plications that need to operate below 6V input, then the
input voltage can be connected directly to the EXTV
CC
pin to bypass the LDO dropout concern, or an external
5V supply can be used to power the EXTV pin when
CC
the input voltage is at high end of the supply range to
reduce power dissipation in the module. For example the
dropout voltage for 24V input would be 24V – 5V = 19V.
This 19V headroom then multiplied by the power MOSFET
drive current of ~15mA would equal ~0.3W additional
power dissipation. So utilizing an external 5V supply on
Thermal Considerations and Output Current Derating
The thermal resistances reported in the Pin Configuration
section of the data sheet are consistent with those param-
eters defined by JESD51-12 and are intended for use with
finiteelementanalysis(FEA)softwaremodelingtoolsthat
leverage the outcome of thermal modeling, simulation,
and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The motivation for providing these thermal coefficients
is found in JESD51-12 (“Guidelines for Reporting and
Using Electronic Package Thermal Information”).
the EXTV would improve design efficiency and reduce
CC
device temperature rise.
Slope Compensation
The module has already been internally compensated for
all output voltages. LTpowerCAD is available for control
loop optimization.
Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to predict the
µModule regulator’s thermal performance in their appli-
cation at various electrical and environmental operating
conditions to compliment any FEA activities. Without FEA
software, the thermal resistances reported in the Pin Con-
figurationsectionare,inandofthemselves,notrelevantto
providing guidance of thermal performance; instead, the
derating curves provided in this data sheet can be used
in a manner that yields insight and guidance pertaining to
one’s application-usage, and can be adapted to correlate
thermal performance to one’s own application.
Burst Mode Operation and Pulse-Skipping Mode
The LTM4619 regulator can be placed into high efficiency
power saving modes at light load condition to conserve
power. The Burst Mode operation can be selected by float-
ingtheMODE/PLLINpin, andpulse-skippingmodecanbe
selected by pulling the MODE/PLLIN pin to INTV . Burst
CC
Mode operation offers the best efficiency at light load, but
output ripple will be higher and lower frequency ranges
arecapablewhichcaninterferewithsomesystems.Pulse-
skipping mode efficiency is not as good as Burst Mode
operation,butthismodeonlyskipspulsestosaveefficiency
and maintains a lower output ripple and a higher switch-
ing frequency. Burst Mode operation and pulse-skipping
mode efficiencies can be reviewed in graph supplied in
the Typical Performance Characteristics section.
The Pin Configuration section gives four thermal coeffi-
cients explicitly defined in JESD51-12; these coefficients
are quoted or paraphrased in the following:
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LTM4619
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1
θ , the thermal resistance from junction to ambient, is
As a practical matter, it should be clear to the reader that
no individual or sub-group of the four thermal resistance
parameters defined by JESD51-12 or provided in the
Pin Configuration section replicates or conveys normal
operating conditions of a µModule regulator. For example,
in normal board-mounted applications, never does 100%
of the device’s total power loss (heat) thermally con-
duct exclusively through the top or exclusively through
bottom of the µModule package—as the standard defines
JA
the natural convection junction-to-ambient air thermal
resistance measured in a one cubic foot sealed enclo-
sure. This environment is sometimes referred to as
“still air” although natural convection causes the air to
move. This value is determined with the part mounted
to a 95mm × 76mm PCB with four layers.
2
θ
, the thermal resistance from junction to the
JCbottom
bottom of the product case, is determined with all of
the component power dissipation flowing through the
bottomofthepackage.InthetypicalµModuleregulator,
the bulk of the heat flows out the bottom of the pack-
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value
may be useful for comparing packages but the test
conditions don’t generally match the user’s application.
for θ
and θ
, respectively. In practice, power
JCtop
JCbottom
loss is thermally dissipated in both directions away from
the package—granted, in the absence of a heat sink and
airflow, a majority of the heat flow is into the board.
Within the LTM4619, be aware there are multiple power
devices and components dissipating power, with a con-
sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
respect to total package power loss. To reconcile this
complicationwithoutsacrificingmodelingsimplicity—but
alsonotignoringpracticalrealities—anapproachhasbeen
taken using FEA software modeling along with laboratory
testing in a controlled-environment chamber to reason-
ably define and correlate the thermal resistance values
supplied in this data sheet: (1) Initially, FEA software is
used to accurately build the mechanical geometry of the
LTM4619 and the specified PCB with all of the correct
materialcoefficientsalongwithaccuratepowerlosssource
definitions; (2) this model simulates a software-defined
JEDECenvironmentconsistentwithJESD51-12topredict
powerlossheatflowandtemperaturereadingsatdifferent
interfacesthatenablethecalculationoftheJEDEC-defined
thermalresistance values;(3)themodeland FEA software
isusedtoevaluatetheLTM4619withheatsinkandairflow;
(4) having solved for and analyzed these thermal resis-
tance values and simulated various operating conditions
in the software model, a thorough laboratory evaluation
replicates the simulated conditions with thermocouples
within a controlled-environment chamber while operat-
ing the device at the same power loss as that which was
simulated. The outcome of this process and due diligence
yields the set of derating curves shown in this data sheet.
3
θ
, the thermal resistance from junction to top of
JCtop
the product case, is determined with nearly all of the
componentpowerdissipationflowingthroughthetopof
the package. As the electrical connections of the typical
µModule regulator are on the bottom of the package, it
is rare for an application to operate such that most of
the heat flows from the junction to the top of the part.
As in the case of θ
for comparing packages but the test conditions don’t
generally match the user’s application.
, this value may be useful
JCbottom
4
θ , the thermal resistance from junction to the printed
JB
circuitboard,isthejunction-to-boardthermalresistance
where almost all of the heat flows through the bottom
oftheµModulepackageandintotheboard, andisreally
the sum of the θ
and the thermal resistance of
JCbottom
the bottom of the part through the solder joints and a
portionoftheboard.Theboardtemperatureismeasured
a specified distance from the package.
A graphical representation of the aforementioned ther-
mal resistances is given in Figure 7; blue resistances are
contained within the µModule regulator, whereas green
resistances are external to the µModule package.
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JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS
JUNCTION-TO-CASE (TOP)
RESISTANCE
CASE (TOP)-TO-AMBIENT
RESISTANCE
JUNCTION-TO-BOARD RESISTANCE
JUNCTION
AMBIENT
JUNCTION-TO-CASE
(BOTTOM) RESISTANCE
CASE (BOTTOM)-TO-BOARD
RESISTANCE
BOARD-TO-AMBIENT
RESISTANCE
4619 F07
µMODULE DEVICE
Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients
The 1.5V and 3.3V power loss curves in Figures 8 and 9
can be used in coordination with the load current derating
curves in Figures 10 to 17 for calculating an approximate
1.5V power loss curve at 5A, and the 1.35 multiplying
factor at 120°C ambient. If the 95°C ambient temperature
is subtracted from the 120°C junction temperature, then
thedifferenceof25°Cdividedby1.83Wequalsa13.6°C/W
Θ thermal resistance for the LTM4619 with various heat
JA
sinking and airflow conditions. The power loss curves are
taken at room temperature, and are increased with a 1.35
multiplicativefactorat120°C. Thederatingcurvesareplot-
ted with CH1 and CH2 in parallel single output operation
starting at 8A of load with low ambient temperature. The
output voltages are 1.5V and 3.3V. These are chosen to
include the lower and higher output voltage ranges for cor-
relatingthethermalresistance.Thermalmodelsarederived
from several temperature measurements in a controlled
temperaturechamberalongwiththermalmodelinganalysis.
Θ thermalresistance. Table2specifiesa13.4°C/Wvalue
JA
whichisprettyclose.Theairflowgraphsaremoreaccurate
duetothefactthattheambienttemperatureenvironmentis
controlled better with airflow. As an example in Figure 14,
the load current is derated to 5A at ~95°C with 400LFM of
airflow and the power loss for the 12V to 3.3V at 5A output
is ~2.5W.The2.5Wlossiscalculatedwiththe~1.85Wroom
temperature loss from the 12V to 3.3V power loss curve at
5A, andthe1.35multiplyingfactorat120°Cambient. Ifthe
95°C ambient temperature is subtracted from the 120°C
junction temperature, then the difference of 25°C divided
The junction temperatures are monitored while ambient
temperature is increased with and without airflow. The
power loss increase with ambient temperature change
is factored into the derating curves. The junctions are
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature.
The decreased output current will decrease the internal
module loss as ambient temperature is increased.
by 2.5W equals a 10°C/W θ thermal resistance. Table 2
JA
specifies a 9.7°C/W value which is pretty close. Tables 2
and 3 provide equivalent thermal resistances for 1.5V and
3.3V outputs with and without airflow and heat sinking.
The derived thermal resistances in Tables 2 and 3 for the
various conditions can be multiplied by the calculated
power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
temperature.Roomtemperaturepowerlosscanbederived
from the efficiency curves and adjusted with the above
ambient temperature multiplicative factors. The printed
circuit board is a 1.6mm thick four layer board with two
ounce copper for the two outer layers and one ounce
copper for the two inner layers. The PCB dimensions are
The monitored junction temperature of 120°C minus
the ambient operating temperature specifies how much
module temperature rise can be allowed. As an example in
Figure 12, the load current is derated to 5A at ~95°C with
no air or heat sink and the power loss for the 12V to 1.5V
at 5A output is about 1.83W. The 1.83W loss is calculated
with the 1.35W room temperature loss from the 12V to
95mm × 76mm. The BGA heat sinks are listed in Table 3.
4619fc
16
For more information www.linear.com/LTM4619
LTM4619
applicaTions inForMaTion
Table 2. 1.5V Output
DERATING CURVE
Figures 10, 12
Figures 10, 12
Figures 10, 12
Figures 11, 13
Figures 11, 13
Figures 11, 13
V
(V)
POWER LOSS CURVE
Figure 8
AIRFLOW (LFM)
HEATSINK
none
Θ
(°C/W)
IN
JA
6, 12
6, 12
6, 12
6, 12
6, 12
6, 12
0
13.4
11.2
9.7
Figure 8
200
400
0
none
Figure 8
none
Figure 8
BGA Heatsink
BGA Heatsink
BGA Heatsink
12.6
10.0
9.6
Figure 8
200
400
Figure 8
Table 3. 3.3V Output
DERATING CURVE
Figures 14, 16
V
(V)
POWER LOSS CURVE
Figure 9
AIRFLOW (LFM)
HEATSINK
none
Θ
JA
(°C/W)
IN
12, 24
0
13.4
11.2
9.7
Figures 14, 16
12, 24
12, 24
12, 24
12, 24
12, 24
Figure 9
200
400
0
none
Figures 14, 16
Figure 9
none
Figures 15, 17
Figure 9
BGA Heatsink
BGA Heatsink
BGA Heatsink
12.6
10.0
9.6
Figures 15, 17
Figure 9
200
400
Figures 15, 17
Figure 9
HEATSINK MANUFACTURER
Aavid Thermalloy
PART NUMBER
WEBSITE
375424B00034G
www.aavidthermalloy.com
www.coolinnovations.com
Cool Innovations
4-050503P to 4-050508P
4.5
3.0
2.5
2.0
1.5
1.0
0.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
12V LOSS
24V LOSS
6V LOSS
12V LOSS
0
0
0
2
4
6
8
2
4
6
8
LOAD CURRENT (A)
LOAD CURRENT (A)
4619 F09
4619 F08
Figure 8. Power Loss at 1.5V Output
Figure 9. Power Loss at 3.3V Output
4619fc
17
For more information www.linear.com/LTM4619
LTM4619
applicaTions inForMaTion
8
7
6
5
4
3
2
8
7
6
5
4
3
2
1
0
6V TO 1.5V
0LFM
200LFM
400LFM
6V TO 1.5V
0LFM
200LFM
400LFM
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
1
0
6V TO 1.5V
6V TO 1.5V
IN
IN
6V TO 1.5V
6V TO 1.5V
IN
IN
70 75 80 85 90 95 100 105 110 115
70 75 80 85 90 95 100 105 110 115
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4619 F10
4619 F11
Figure 11. 6VIN to 1.5VOUT
with Heat Sink
Figure 10. 6VIN to
1.5VOUT without Heat Sink
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
8
7
6
5
4
3
2
12V TO 1.5V
0LFM
200LFM
400LFM
12V TO 1.5V
0LFM
200LFM
400LFM
12V TO 3.3V
0LFM
200LFM
400LFM
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
1
0
1
0
12V TO 1.5V
12V TO 1.5V
12V TO 3.3V
IN
IN
IN
12V TO 1.5V
12V TO 1.5V
12V TO 3.3V
IN
IN
IN
70 75 80 85 90 95 100 105 110 115
70 75 80 85 90 95 100 105 110 115
60 65 70 75 80 85 90 95 100 105 110
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4619 F12
4619 F13
4619 F14
Figure 14. 12VIN to 3.3VOUT
without Heat Sink
Figure 13. 12VIN to 1.5VOUT
with Heat Sink
Figure 12. 12VIN to 1.5VOUT
without Heat Sink
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
8
7
6
5
4
3
2
1
0
12V TO 3.3V
0LFM
200LFM
400LFM
24V TO 3.3V
0LFM
200LFM
400LFM
24V TO 3.3V
0LFM
200LFM
400LFM
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
IN
OUT
OUT
OUT
12V TO 3.3V
24V TO 3.3V
24V TO 3.3V
IN
IN
IN
12V TO 3.3V
24V TO 3.3V
24V TO 3.3V
IN
IN
IN
60 65 70 75 80 85 90 95 100 105 110
40
50
60
70
80
90
100
40
50
60
70
80
90
100
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
AMBIENT TEMPERATURE (°C)
4619 F15
4619 F16
4619 F17
Figure 15. 12VIN to 3.3VOUT
with Heat Sink
Figure 16. 24VIN to 3.3VOUT
without Heat Sink
Figure 17. 24VIN to 3.3VOUT
with Heat Sink
4619fc
18
For more information www.linear.com/LTM4619
LTM4619
applicaTions inForMaTion
Safety Considerations
• Place high frequency ceramic input and output capaci-
tors next to the V , PGND and V
pins to minimize
IN
OUT
The LTM4619 modules do not provide galvanic isolation
high frequency noise.
from V to V . There is no internal fuse. If required,
IN
OUT
a slow blow fuse with a rating twice the maximum input
current needs to be provided to protect each unit from
catastrophic failure.
• Place a dedicated power ground layer underneath the
unit.
• Tominimizetheviaconductionlossandreducemodule
thermal stress, use multiple vias for interconnections
between top layer and other power layers.
Layout Checklist/Eꢁample
The high integration of LTM4619 makes the PCB board
layoutverysimpleandeasy.However,tooptimizeitselectri-
cal and thermal performance, some layout considerations
are still necessary.
• Do not put vias directly on the pads.
• Use a separated SGND ground copper area for com-
ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
• UselargePCBcopperareasforhighcurrentpath,includ-
ing V , PGND, V
and V . It helps to minimize
• Decouple the input and output grounds to lower the
IN
OUT1
OUT2
the PCB conduction loss and thermal stress.
output ripple noise.
Figure18givesagoodexampleoftherecommendedlayout.
TOP VIEW
PGND
V
IN
PGND
M
L
C
C
IN1
IN2
K
J
H
G
F
E
D
C
B
A
1
2
3
4
5
6
7
8
9
10
11
12
C
C
OUT1
OUT2
V
OUT2
PGND
V
OUT1
Figure 18. Recommended PCB Layout
4619fc
19
For more information www.linear.com/LTM4619
LTM4619
Typical applicaTions
MODE/PLLIN INTV
CC
V
IN
V
V
FREQ/PLLFLTR
4.5V TO 26.5V
IN
C
11.5k
19.1k
IN
10µF
V
FB1
FB2
×2
C1
C2
COMP1
COMP2
22pF
22pF
V
V
OUT2
OUT1
5V/4A
V
V
OUT2
OUT1
3.3V/4A
LTM4619
C
C
OUT2
100µF
OUT1
TK/SS1
RUN1
TK/SS2
RUN2
100µF
0.1µF
0.1µF
100k
R1 (OPT*)
INTV
PGOOD
EXTV
V
IN
CC
CC
SGND
PGND
4619 F19
PGOOD
*STUFF WITH A 0Ω RESISTOR FOR 4.5V < V < 5.5V
IN
Figure 19. Typical 4.5V to 26.5V Input, 5V and 3.3V Outputs at 4A Design
4619fc
20
For more information www.linear.com/LTM4619
LTM4619
Typical applicaTions
EXTERNAL 5V SUPPLY FOR
INPUT VOLTAGE BELOW 5.5V
R1
3.83k
R2
1.21k
MODE/PLLIN INTV EXTV
CC
CC
V
IN
V
V
FREQ/PLLFLTR
IN
4.5V TO
26.5V
C
IN
121k
68.1k
10µF
V
FB1
FB2
×2
C1
C2
COMP1
COMP2
22pF
22pF
V
V
OUT2
OUT1
1.2V/4A
V
V
OUT2
OUT1
1.5V/4A
LTM4619
C
C
OUT2
OUT1
TK/SS1
RUN1
TK/SS2
RUN2
100µF
100µF
×2
×2
0.1µF
0.1µF
100k
INTV
PGOOD
CC
SGND
PGND
4619 F20
PGOOD
Figure 20. Typical 4.5V to 26.5V Input, 1.2V and 1.5V
Outputs at 4A Design with Adjusted Frequency at 500kHz
MODE/PLLIN EXTV
INTV
CC
CC
V
IN
V
FREQ/PLLFLTR
IN
6V TO
26.5V
C
IN
COMP1
COMP2
TK/SS1
TK/SS2
PGOOD
V
V
10µF
FB1
FB2
C1
51pF
R1
5.76k
V
V
LTM4619
OUT1
OUT2
V
OUT2
5V/8A
+
C4
100µF
C5
C3
0.1µF
RUN2
RUN1
330µF
SGND
PGND
4619 F21
Figure 21. Output Paralleled LTM4619 Module for 5V Output at 8A Design
4619fc
21
For more information www.linear.com/LTM4619
LTM4619
Typical applicaTions
CLOCK SYNC, 0° PHASE
MODE/PLLIN INTV
CC
V
IN
V
FREQ/PLLFLTR
6V TO 26.5V
IN
+
C
10µF
2x
C
IN2
IN1
V
V
FB1
FB2
330µF
R3
11.5k
R4
19.1k
C10
C11
22pF
COMP1
COMP2
22pF
V
OUT2
V
OUT1
LTM4619
V
V
OUT2
3.3V/4A
OUT1
5V/4A
+
+
V
C3
22µF
C4
22µF
OUT1
C2
220µF
C5
220µF
TK/SS1
RUN1
TK/SS2
RUN2
C1
R1
60.4k
0.1µF
PGOOD
EXTV
CC
R2
19.1k
2 PHASE OSCILLATOR
+
SGND
PGND
V
OUT1
OUT2
MOD
ON/OFF
C3
0.1µF
GND
SET
LTC6908-2
R9
143k
CLOCK SYNC, 90° PHASE
MODE/PLLIN INTV
CC
V
FREQ/PLLFLTR
IN
V
V
FB1
FB2
R7
28k
R8
48.7k
C12
22pF
C13
22pF
COMP1
COMP2
V
OUT4
V
OUT3
LTM4619
V
V
1.8V/4A
OUT1
OUT2
2.5V/4A
+
+
V
V
OUT1
C8
22µF
C6
22µF
OUT1
C9
220µF
C7
220µF
TK/SS1
RUN1
TK/SS2
RUN2
R10
60.4k
R5
60.4k
PGOOD
EXTV
CC
R11
28k
R6
48.7k
SGND
PGND
4619 F22
Figure 22. 4-Phase, Four Outputs (5V, 3.3V, 2.5V and 1.8V) with Tracking
4619fc
22
For more information www.linear.com/LTM4619
LTM4619
package DescripTion
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Pin Assignment Table 4
(Arranged by Pin Function)
PIN NAME
PIN NAME
PIN NAME
PIN NAME
A1
V
V
V
D1
V
V
V
G1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
K1
V
V
V
V
OUT2
OUT2
OUT2
OUT2
OUT2
OUT2
IN
IN
IN
IN
A2
D2
G2
K2
A3
D3
G3
K3
A4
PGND
PGND
PGND
PGND
PGND
PGND
V
V
V
D4
PGND
PGND
PGND
PGND
PGND
PGND
V
V
V
G4
K4
A5
D5
G5
K5
TK/SS2
A6
D6
G6
K6
V
V
FB2
FB1
A7
D7
G7
K7
A8
D8
G8
K8
TK/SS1
A9
D9
G9
K9
V
IN
V
IN
V
IN
V
IN
A10
A11
A12
D10
D11
D12
G10
G11
G12
K10
K11
K12
OUT1
OUT1
OUT1
OUT1
OUT1
OUT1
B1
V
V
V
E1
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
H1
PGND
PGND
SW2
L1
V
V
V
V
V
OUT2
OUT2
OUT2
IN
IN
IN
IN
IN
B2
E2
H2
L2
B3
E3
H3
L3
B4
PGND
PGND
PGND
PGND
PGND
PGND
V
V
V
E4
H4
PGND
PGOOD
SGND
SGND
MODE/PLLIN
PGND
SW1
L4
B5
E5
H5
L5
B6
E6
H6
L6
COMP2
COMP1
B7
E7
H7
L7
B8
E8
H8
L8
V
IN
V
IN
V
IN
V
IN
V
IN
B9
E9
H9
L9
B10
B11
B12
E10
E11
E12
H10
H11
H12
L10
L11
L12
OUT1
OUT1
OUT1
PGND
PGND
C1
V
V
V
F1
PGND
PGND
PGND
PGND
PGND
J1
V
V
V
M1
M2
M3
M4
M5
M6
M7
M8
M9
M10
M11
M12
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
V
IN
OUT2
OUT2
OUT2
IN
IN
IN
C2
F2
J2
C3
F3
J3
C4
PGND
PGND
PGND
PGND
PGND
PGND
V
V
V
F4
J4
EXTV
CC
C5
F5
J5
RUN2
C6
F6
INTV
J6
SGND
CC
C7
F7
PGND
PGND
PGND
PGND
PGND
PGND
J7
SGND
C8
F8
J8
FREQ/PLLFLTR
RUN1
C9
F9
J9
C10
C11
C12
F10
F11
F12
J10
J11
J12
V
IN
V
IN
V
IN
OUT1
OUT1
OUT1
4619fc
23
For more information www.linear.com/LTM4619
LTM4619
package DescripTion
Z
b b b
Z
6 . 9 8 5 0
5 . 7 1 5 0
4 . 4 4 5 0
3 . 1 7 5 0
1 . 9 0 5 0
0 . 6 3 5 0
0 . 0 0 0 0
0 . 6 3 5 0
1 . 9 0 5 0
3 . 1 7 5 0
4 . 4 4 5 0
5 . 7 1 5 0
6 . 9 8 5 0
a a a
Z
4619fc
24
For more information www.linear.com/LTM4619
LTM4619
revision hisTory (Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
08/13 Added “or single 8A” to Description
Changed MODE to MODE/PLLIN
Changed GND to PGND
1
8
22
Added Design Resources
24
C
05/14 Update Order Information Table
Update thermal resistance figures
Update Thermal Considerations Section
2
2, 17
14, 15, 16
4619fc
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
25
LTM4619
package phoTograph
relaTeD parTs
PART NUMBER DESCRIPTION
COMMENTS
LTM4614
LTM4615
LTM4616
LTM4628
Dual, 4A, Low V , DC/DC µModule Regulator
2.375V ≤ V ≤ 5.5V, 0.8V ≤ V
≤ 5V, 15mm × 15mm × 2.82mm LGA
OUT
IN
IN
Triple, Low V , DC/DC µModule Regulator
Two 4A Outputs and One 1.5A, 15mm × 15mm × 2.82mm LGA
2.7V ≤ V ≤ 5.5V, 0.6V ≤ V ≤ 5V, 15mm × 15mm × 2.82mm LGA
IN
Dual, 8A, Low V , DC/DC µModule Regulator
IN
IN
OUT
Dual, 8A, 26V, DC/DC µModule Regulator
4.5V ≤ V ≤ 28.5V, 0.6V ≤ V
≤ 5.5V, Remote Sense Amplifier, Internal
IN
OUT
Temperature Sensing Diode Output, 15mm × 15mm × 4.32mm LGA
LTM4620A
Dual, 16V, 13A, 26A, Step-Down µModule Regulator
4.5V ≤ V ≤ 16V, 0.6V ≤ V ≤ 5.3V, 15mm × 15mm × 4.41mm LGA
IN
OUT
Design resources
SUBJECT
DESCRIPTION
µModule Design and Manufacturing Resources
Design:
Manufacturing:
• Selector Guides
• Quick Start Guide
• Demo Boards and Gerber Files
• Free Simulation Tools
• PCB Design, Assembly and Manufacturing Guidelines
• Package and Board Level Reliability
µModule Regulator Products Search
1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.
TechClip Videos
Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management
Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.
4619fc
LT 0514 REV C • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
26
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM4619
●
●
LINEAR TECHNOLOGY CORPORATION 2009
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