LTC4300A-2IMS8#PBF_技术文档

LTC4300A-1/LTC4300A-2

Hot Swappable

2-Wire Bus Buffers

FEATURES

DESCRIPTION

The LTC^®4300A series hot swappable 2-wire bus buffers

allowI/Ocardinsertionintoalivebackplanewithoutcorrup-

tion of the data and clock busses. When the connection is

made,theLTC4300A-1/LTC4300A-2providebidirectional

buffering, keeping the backplane and card capacitances

isolated. Rise-time accelerator circuitry* allows the use of

weaker DC pull-up currents while still meeting rise-time

requirements. During insertion, the SDA and SCL lines are

precharged to 1V to minimize bus disturbances.

n

Bidirectional Buffer for SDA and SCL Lines

Increases Fanout

n

Prevents SDA and SCL Corruption During Live

Board Insertion and Removal from Backplane

Isolates Input SDA and SCL Lines from Output

n

2

n

Compatible with I C, I C Fast Mode and SMBus

Standards (Up to 400kHz Operation)

n

Low I Chip Disable: <1μA (LTC4300A-1)

CC

READY Open Drain Output (LTC4300A-1)

1V Precharge on all SDA and SCL Lines

Supports Clock Stretching, Arbitration and

Synchronization

The LTC4300A-1 incorporates a CMOS threshold digital

ENABLE input pin, which forces the part into a low current

mode when driven to ground and sets normal operation

n

5V to 3.3V Level Translation (LTC4300A-2)

when driven to V . It also includes an open drain READY

CC

High Impedance SDA, SCL Pins for V = 0V

CC

output pin, which indicates that the backplane and card

Small MSOP 8-Pin Package

sides are connected together. The LTC4300A-2 replaces

the ENABLE pin with a dedicated supply voltage pin, V

,

CC2

APPLICATIONS

for the card side, providing level shifting between 3.3V

and 5V systems. Both the backplane and card may be

powered with supply voltages ranging from 2.7V to 5.5V,

with no constraints on which supply voltage is higher. The

LTC4300A-2 also replaces the READY pin with a digital

CMOS input pin, ACC, which enables and disables the

rise-time accelerator currents.

n

Hot Board Insertion

n

Servers

n

Capacitance Buffer/Bus Extender

Desktop Computer

n

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and Hot

Swap and ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are

the property of their respective owners. *Protected by U.S. Patents, including 6650174.

TheLTC4300Aisavailableinasmall8-pinMSOPpackage.

TYPICAL APPLICATION

V

Input–Output Connection t_PLH

CC

3.3V

C1

0.01μF

R1

R2

R3

R4

10k

OUTPUT

SIDE

INPUT

SIDE

150pF

SCLIN

SDAIN

SCLOUT

50pF

SDAOUT

LTC4300A-1

ENABLE READY

4300a12 TA02

GND

4300a12 TA01

4300a12fa

1

LTC4300A-1/LTC4300A-2

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

V

to GND .................................................... –0.3 to 7V

CC2

SDAIN, SCLIN, SDAOUT, SCLOUT.................. –0.3 to 7V

READY, ENABLE (LTC4300A-1)...................... –0.3 to 7V

ACC (LTC4300A-2)......................................... –0.3 to 7V

Operating Temperature Range

CC

ENABLE/V

*

1

2

3

4

8 V

CC

7 SDAOUT

6 SDAIN

CC2

SCLOUT

SCLIN

GND

to GND (LTC4300A-2)............................ –0.3 to 7V

5 READY/ACC*

MS8 PACKAGE

8-LEAD PLASTIC MSOP

*LTC4300A-2

T

JMAX

= 125°C, θ = 200°C/W

JA

LTC4300A-1C/LTC4300A-2C.................... 0°C to 70°C

LTC4300A-1I/LTC4300A-2I ..................–40°C to 85°C

Storage Temperature Range .................. –65°C to 125°C

Lead Temperature (Soldering, 10 sec)...................300°C

ORDER INFORMATION

LEAD FREE FINISH

TAPE AND REEL

PART MARKING

LTABF

PACKAGE DESCRIPTION

8-Lead Plastic MSOP

TEMPERATURE RANGE

0°C to 70°C

LTC4300A-1CMS8#PBF

LTC4300A-1IMS8#PBF

LTC4300A-2CMS8#PBF

LTC4300A-2IMS8#PBF

LTC4300A-1CMS8#TRPBF

LTC4300A-1IMS8#TRPBF

LTC4300A-2CMS8#TRPBF

LTC4300A-2IMS8#TRPBF

LTABG

–40°C to 85°C

0°C to 70°C

LTACF

LTACG

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges.

Consult LTC Marketing for information on nonstandard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 2.7V to 5.5V, unless otherwise noted.

SYMBOL PARAMETER

Power Supply

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Positive Supply Voltage

Supply Current

2.7

5.5

7

V

mA

μA

V

CC

I

CC

I

SD

V

= 5.5V, V

= V = 0V, LTC4300A-1

SCLIN

5.1

0.1

CC

SDAIN

Supply Current in Shutdown Mode

Card Side Supply Voltage

= 0V, LTC4300A-1

ENABLE

l

V

LTC4300A-2

2.7

5.5

4.1

CC2

I

V

Supply Current

V

= V

= 0V, V

= V

= 5.5V,

3

mA

VCC1

CC

SDAIN

SCLIN

CC1

CC2

LTC4300A-2

I

V

Supply Current

V

= V

= 0V, V

= V = 5.5V,

CC2

2.1

2.9

mA

VCC2

CC2

SDAOUT

SCLOUT

CC1

LTC4300A-2

Start-Up Circuitry

l

V

Precharge Voltage

SDA, SCL Floating

0.8

50

1.0

95

1.2

V

μs

V

PRE

t

Bus Idle Time

150

IDLE

V

ENABLE Threshold Voltage

Disable Threshold Voltage

ENABLE Input Current

LTC4300A-1

0.5 • V

0.1

0.9 • V

EN

CC

LTC4300A-1, ENABLE Pin

ENABLE from 0V to V , LTC4300A-1

0.1 • V

V

DIS

CC

I

1

μA

EN

CC

4300a12fa

2

LTC4300A-1/LTC4300A-2

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. V_CC= 2.7V to 5.5V, unless otherwise noted.

SYMBOL PARAMETER

CONDITIONS

LTC4300A-1

MIN

TYP

10

MAX

UNITS

ns

t

I

ENABLE Delay, On-Off

PHL

PLH

OFF

READY Delay, Off-On

10

ns

ENABLE Delay, Off-On

95

μs

READY Delay, On-Off

10

ns

READY OFF State Leakage Current

READY Output Low Voltage

0.1

μA

V

l

V

I

= 3mA, LTC4300A-1

PULLUP

0.4

OL

Rise-Time Accelerators

I

Transient Boosted Pull-Up Current

Positive Transition on SDA,SCL, V = 2.7V,

1

2

mA

PULLUPAC

CC

Slew Rate = 1.25V/μs (Note 2),

LTC4300A-2, ACC = 0.7 • V , V

= 2.7V

CC2 CC2

V

Accelerator Disable Threshold

Accelerator Enable Threshold

ACC Input Current

LTC4300A-2

0.3 • V

0.5 • V

V

ACCDIS

ACCEN

VACC

CC2

0.7 • V

1

CC2

I

t

0.1

5

μA

ns

ACC Delay, On/Off

PDOFF

Input-Output Connection

l

V

Input-Output Offset Voltage

10k to V on SDA, SCL, V = 3.3V (Note 3),

0

100

175

mV

OS

CC

LTC4300A-2, V

= 3.3V, V = 0.2V

IN

CC2

f

Operating Frequency

Guaranteed by Design, Not Subject to Test

400

10

kHz

pF

V

SCL, SDA

C

V

Digital Input Capacitance

Output Low Voltage, Input = 0V

IN

l

SDA, SCL Pins, I

CC2

= 3mA, V = 2.7V,

0

0.4

OL

SINK

CC

V

= 2.7V, LTC4300A-2

I

Input Leakage Current

SDA, SCL Pins = V = 5.5V,

5

μA

LEAK

CC

LTC4300A-2, V

= 5.5V

CC2

Timing Characteristics

2

f

t

I C Operating Frequency

(Note 4)

0

400

kHz

μs

I2C

Bus Free Time Between Stop

and Start Condition

1.3

BUF

t

Hold Time After (Repeated)

Start Condition

(Note 4)

0.6

μs

hD,STA

t

Repeated Start Condition Setup Time (Note 4)

0.6

μs

ns

μs

ns

su,STA

su,STO

hD, DAT

su, DAT

LOW

Stop Condition Setup Time

Data Hold Time

(Note 4)

300

100

Data Setup Time

(Note 4)

Clock Low Period

(Note 4)

1.3

Clock High Period

Clock, Data Fall Time

Clock, Data Rise Time

(Note 4)

0.6

HIGH

(Notes 4, 5)

20 + 0.1 • C

300

75

f

B

r

l

High-to-Low Propagation Delay

Skew, SCL-SDA

LTC4300A-1: V = 2.7V; V = 5.5V (Note 6)

0

PHL,SKEW

CC

LTC4300A-2: V = 2.7V, V

= 5.5V;

75

CC

CC2

V

= 5.5V; V

= 2.7V (Note 6)

CC

CC2

4300a12fa

3

LTC4300A-1/LTC4300A-2

ELECTRICAL CHARACTERISTICS

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 4: Guaranteed by design, not subject to test.

Note 5: C = total capacitance of one bus line in pF.

B

Note 6: These tests measure the difference in high-to-low propagation

delay t

between the clock and data channels. The delay on each

PHL

Note 2: I

varies with temperature and V voltage, as shown in

PULLUPAC

CC

channel is measured from the 50% point of the falling driven input signal

to the 50% point of the output driven by the LTC4300A-1/LTC4300A-2.

the Typical Performance Characteristics section.

Note 3: The connection circuitry always regulates its output to a higher

voltage than its input. The magnitude of this offset voltage as a function of

The skew is defined as (t

– t

). Testing is performed in

PHL(SCL)

PHL(SDA)

both directions—from input bus to output bus and vice versa. Tests are

performed with approximately 500pF of distributed equivalent capacitance

on each SDA and SCL pin.

the pull-up resistor and V voltage is shown in the Typical Performance

CC

Characteristics section.

TYPICAL PERFORMANCE CHARACTERISTICS

Input – Output t_PHLvs

Temperature (LTC4300A-1)

I_CCvs Temperature (LTC4300A-1)

5.3

5.2

5.1

5.0

4.9

4.8

4.7

4.6

4.5

4.4

4.3

100

80

60

40

20

0

V

= 2.7V

CC

V

= 5.5V

CC

V

= 3.3V

CC

V

= 5.5V

V

= 2.7V

CC

C

= C

PULLUPIN

= 100pF

OUT

IN

R

= R

= 10k

PULLUPOUT

–40

25

TEMPERATURE (°C)

85

–50

–25

0

25

50

75

100

TEMPERATURE (°C)

4300a12 G01

4300a12 G02

I_PULLUPACvs Temperature

Connection Circuitry V_OUT– V_IN

300

250

200

150

100

50

12

10

8

T

= 25°C

IN

A

V

= 0V

V

= 5V

CC

6

V

= 5V

CC

V

= 3V

CC

4

V

= 3.3V

CC

2

= 2.7V

25

0

10,000

20,000

(Ω)

30,000

40,000

–50

–25

0

50

75

100

R

TEMPERATURE (°C)

PULLUP

4300a12 G04

4300a12 G03

4300a12fa

4

LTC4300A-1/LTC4300A-2

PIN FUNCTIONS

ENABLE/V

(Pin 1): Chip Enable Pin/Card Supply Volt-

READY/ACC(Pin5):ConnectionFlag/Rise-TimeAccelera-

tor Control. For the LTC4300A-1, this is an open-drain

NMOS output which pulls low when either ENABLE is

low or the start-up sequence described in the Operation

section has not been completed. READY goes high when

ENABLE is high and start-up is complete. Connect a 10k

CC2

age. For the LTC4300A-1, this is a digital CMOS threshold

input pin. Grounding this pin puts the part in a low current

(<1μA) mode. It also disables the rise-time accelerators,

disables the bus precharge circuitry, drives READY low,

isolates SDAIN from SDAOUT and isolates SCLIN from

SCLOUT. Drive ENABLE all the way to V for normal

resistor from this pin to V to provide the pull up. For

CC

operation. Connect ENABLE to V if this feature is not

the LTC4300A-2, this is a CMOS threshold digital input

pin that enables and disables the rise-time accelerators

on all four SDA and SCL pins. Drive ACC all the way to the

CC

beingused. FortheLTC4300A-2, thisisthesupplyvoltage

2

for the devices on the card I C busses. Connect pull-up

resistors from SDAOUT and SCLOUT to this pin. Place a

bypass capacitor of at least 0.01μF close to this pin for

best results.

V

supply voltage to enable all four accelerators; drive

CC2

ACC to ground to turn them off.

SDAIN (Pin 6): Serial Data Input. Connect this pin to the

SDA bus on the backplane.

SCLOUT (Pin 2): Serial Clock Output. Connect this pin to

the SCL bus on the card.

SDAOUT (Pin 7): Serial Data Output. Connect this pin to

the SDA bus on the card.

SCLIN (Pin 3): Serial Clock Input. Connect this pin to the

SCL bus on the backplane.

V

(Pin 8): Main Input Power Supply from Backplane.

CC

GND (Pin 4): Ground. Connect this pin to a ground plane

for best results.

This is the supply voltage for the devices on the back-

2

plane I C busses. Connect pull-up resistors from SDAIN

and SCLIN (and also from SDAOUT and SCLOUT for the

LTC4300A-1) to this pin. Place a bypass capacitor of at

least 0.01μF close to this pin for best results.

4300a12fa

5

LTC4300A-1/LTC4300A-2

BLOCK DIAGRAM ^(LTC4300A-1)

2-Wire Bus Buffer and Hot Swap™ Controller

2mA

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

8

V

CC

BACKPLANE-TO-CARD

SDAIN

6

47 SDAOUT

CONNECTION

CONNECT

ENABLE

100k

RCH1

100k

RCH3

1V

PRECHARGE

100k

RCH2

100k

RCH4

2mA

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

BACKPLANE-TO-CARD

CONNECTION

SCLIN

3

2 SCLOUT

CONNECT

+

–

V

CC

– 1V

+

–

+

–

STOP BIT AND BUS IDLE

0.5μA

+

–

0.55V

/

CC

5

4

READY

GND

20pF

0.45V

95μs

CONNECT

UVLO

DELAY,

RISING

ONLY

RD

ENABLE

1

QB

S

0.5pF

CONNECT

4300A1 BD

4300a12fa

6

LTC4300A-1/LTC4300A-2

BLOCK DIAGRAM ^(LTC4300A-2)

2-Wire Bus Buffer and Hot Swap Controller

V

CC

8

2mA

1

V

CC2

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

ACC

BACKPLANE-TO-CARD

SDAIN

6

47 SDAOUT

CONNECTION

CONNECT

100k

RCH1

100k

RCH3

1V

PRECHARGE

100k

RCH2

100k

RCH4

2mA

SLEW RATE

DETECTOR

SLEW RATE

DETECTOR

5

2

ACC

BACKPLANE-TO-CARD

CONNECTION

SCLIN

3

SCLOUT

CONNECT

+

–

V

– 1V

CC2

+

–

+

–

STOP BIT AND BUS IDLE

0.5μA

+

–

0.55V

/

CC

20pF

0.45V

95μs

CONNECT CONNECT

DELAY,

RISING

ONLY

UVLO

RD

QB

S

4

GND

0.5pF

4300A2 BD

4300a12fa

7

LTC4300A-1/LTC4300A-2

OPERATION

Start-Up

Another key feature of the connection circuitry is that it

provides bidirectional buffering, keeping the backplane

and card capacitances isolated. Because of this isolation,

the waveforms on the backplane busses look slightly

different than the corresponding card bus waveforms, as

described here.

When the LTC4300A first receives power on its V pin,

CC

either during power-up or during live insertion, it starts

in an undervoltage lockout (UVLO) state, ignoring any

activity on the SDA and SCL pins until V rises above

CC

2.5V. For the LTC4300A-2, the part also waits for V

to

CC2

rise above 2V. This ensures that the part does not try to

function until it has enough voltage to do so.

Input to Output Offset Voltage

When a logic low voltage, V

, is driven on any of the

LOW1

During this time, the 1V precharge circuitry is also ac-

tive and forces 1V through 100k nominal resistors to the

SDA and SCL pins. Because the I/O card is being plugged

into a live backplane, the voltage on the backplane SDA

LTC4300A’s data or clock pins, the LTC4300A regulates

the voltage on the other side of the chip (call it V

)

LOW2

to a slightly higher voltage, as directed by the following

equation:

and SCL busses may be anywhere between 0V and V .

CC

V

LOW2

= V

+ 75mV + (V /R) • 100

LOW1 CC

Precharging the SCL and SDA pins to 1V minimizes the

worst-case voltage differential these pins will see at the

moment of connection, therefore minimizing the amount

of disturbance caused by the I/O card.

where R is the bus pull-up resistance in ohms. For ex-

ample, if a device is forcing SDAOUT to 10mV where

V

CC

= 3.3V and the pull-up resistor R on SDAIN is 10k,

then the voltage on SDAIN = 10mV + 75mV + (3.3/10000)

• 100 = 118mV. See the Typical Performance Character-

istics section for curves showing the offset voltage as a

Once the LTC4300A comes out of UVLO, it assumes that

SDAIN and SCLIN have been inserted into a live system

andthatSDAOUTandSCLOUTarebeingpoweredupatthe

same time as itself. Therefore, it looks for either a stop bit

or bus idle condition on the backplane side to indicate the

completion of a data transaction. When either one occurs,

the part also verifies that both the SDAOUT and SCLOUT

voltages are high. When all of these conditions are met,

theinput-to-outputconnectioncircuitryisactivated,joining

the SDA and SCL busses on the I/O card with those on

the backplane, and the rise time accelerators are enabled.

function of V and R.

CC

Propagation Delays

During a rising edge, the rise-time on each side is deter-

mined by the combined pull-up current of the LTC4300A

boost current and the bus resistor and the equivalent

capacitance on the line. If the pull-up currents are the

same, a difference in rise-time occurs which is directly

proportional to the difference in capacitance between the

Connection Circuitry

two sides. This effect is displayed in Figure 1 for V

=

CC

3.3V and a 10k pull-up resistor on each side (50pF on

one side and 150pF on the other). Since the output side

has less capacitance than the input, it rises faster and the

Oncetheconnectioncircuitryisactivated,thefunctionality

oftheSDAINandSDAOUTpinsisidentical.Alowforcedon

eitherpinatanytimeresultsinbothpinvoltagesbeinglow.

For proper operation, logic low input voltages should be

no higher than 0.4V with respect to the ground pin voltage

of the LTC4300A. SDAIN and SDAOUT enter a logic high

state only when all devices on both SDAIN and SDAOUT

release high. The same is true for SCLIN and SCLOUT.

This importantfeatureensuresthatclockstretching,clock

synchronization,arbitrationandtheacknowledgeprotocol

always work, regardless of how the devices in the system

are tied to the LTC4300A.

effective t

is negative.

PLH

There is a finite propagation delay, t , through the con-

PHL

nection circuitry for falling waveforms. Figure 2 shows

the falling edge waveforms for the same V , pull-up

CC

resistors and equivalent capacitance conditions as used

in Figure 1. An external NMOS device pulls down the volt-

age on the side with 150pF capacitance; the LTC4300A

pulls down the voltage on the opposite side, with a delay

of 55ns. This delay is always positive and is a function of

4300a12fa

8

LTC4300A-1/LTC4300A-2

OPERATION

OUTPUT

SIDE

INPUT

SIDE

150pF

INPUT

SIDE

150pF

OUTPUT

SIDE

50pF

4300a12 F01

4300a12 F02

Figure 1. Input–Output Connection t_PLH

Figure 2. Input–Output Connection t_PHL

supply voltage, temperature and the pull-up resistors and

equivalent bus capacitances on both sides of the bus. The

using the rise-time accelerators, which are activated at a

DC threshold of below 0.65V, the worst-case rise-time is:

(2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the

1μs rise-time requirement.

Typical Performance Characteristics section shows t

PHL

as a function of temperature and voltage for 10k pull-up

resistors and 100pF equivalent capacitance on both sides

READY Digital Output (LTC4300A-1)

of the part. By comparison with Figure 2, the V = 3.3V

CC

curve shows that increasing the capacitance from 50pF

This pin provides a digital flag which is low when either

ENABLE is low or the start-up sequence described earlier

in this section has not been completed. READY goes high

when ENABLE is high and start-up is complete. The pin

is driven by an open drain pull-down capable of sinking

3mA while holding 0.4V on the pin. Connect a resistor of

to 100pF results in a t

increase from 55ns to 75ns.

PHL

Larger output capacitances translate to longer delays (up

to 150ns). Users must quantify the difference in propaga-

tion times for a rising edge versus a falling edge in their

systems and adjust setup and hold times accordingly.

10k to V to provide the pull-up. This feature is available

CC

Rise-Time Accelerators

for the LTC4300A-1 only.

Onceconnectionhasbeenestablished,rise-timeaccelera-

tor circuits on all four SDA and SCL pins are activated.

These allow the user to choose weaker DC pull-up cur-

rents on the bus, reducing power consumption while still

meeting system rise-time requirements. During positive

bus transitions, the LTC4300A switches in 2mA (typical)

of current to quickly slew the SDA and SCL lines once

their DC voltages exceed 0.6V. Using a general rule of

20pF of capacitance for every device on the bus (10pF for

the device and 10pF for interconnect), choose a pull-up

current so that the bus will rise on its own at a rate of at

least 1.25V/μs to guarantee activation of the accelerators.

ENABLE Low Current Disable (LTC4300A-1)

GroundingtheENABLEpindisconnectsthebackplaneside

from the card side, disables the rise-time accelerators,

drives READY low, disables the bus precharge circuitry

and puts the part in a near-zero current state. When the

pin voltage is driven all the way to V , the part waits for

CC

data transactions on both the backplane and card sides to

be complete (as described in the Start-Up section) before

reconnecting the two sides. This feature is available for

the LTC4300A-1 only.

ACC Boost Current Enable (LTC4300A-2)

For example, assume an SMBus system with V = 3V,

CC

a 10k pull-up resistor and equivalent bus capacitance of

Users having lightly loaded systems may wish to disable

therise-timeaccelerators. Drivingthispintogroundturns

off the rise-time accelerators on all four SDA and SCL

200pF. The rise-time of an SMBus system is calculated

from (V

– 0.15V) to (V

+ 0.15V), or 0.65V

IL(MAX)

IH(MIN)

to 2.25V. It takes an RC circuit 0.92 time constants to

traverse this voltage for a 3V supply; in this case, 0.92

• (10k • 200pF) = 1.84μs. Thus, the system exceeds the

maximum allowed rise-time of 1μs by 84%. However,

pins. Driving this pin to the V

voltage enables normal

CC2

operation of the rise-time accelerators, as described in

the Rise-Time Accelerators section above. This feature is

available for the LTC4300A-2 only.

4300a12fa

9

LTC4300A-1/LTC4300A-2

APPLICATIONS INFORMATION

Resistor Pull-Up Value Selection

In addition, regardless of the bus capacitance, always

choose R ≤ 16k for V = 5.5V maximum, R ≤ 24k for

CC

logic high voltages on SDAOUT and SCLOUT to connect

the backplane to the card, and these pull-up values are

needed to overcome the precharge voltage.

CC

The system pull-up resistors must be strong enough to

provide a positive slew rate of 1.25V/μs on the SDA and

SCL pins, in order to activate the boost pull-up currents

during rising edges. Choose maximum resistor value R

using the formula:

V

= 3.6V maximum. The start-up circuitry requires

R ≤ (V

– 0.6) (800,000) / C

Live Insertion and Capacitance Buffering Application

CC(MIN)

where R is the pull-up resistor value in ohms, V

Figures 3 through 6 illustrate the usage of the LTC4300A

in applications that take advantage of both its hot swap

controlling and capacitance buffering features. In all of

CC(MIN)

is the minimum V voltage and C is the equivalent bus

CC

capacitance in picofarads (pF).

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

POWER SUPPLY

HOT SWAP

V

CC

C1

0.01μF

R3

10k

R1

R2

10k

R4

10k

R5

10k

R6

10k

CARD

ENABLE/DISABLE

V

CC

SDAOUT

SCLOUT

READY

CARD_SDA

CARD_SCL

BD_SEL

SDA

ENABLE

U1

SDAIN

SCLIN

LTC4300A-1

SCL

GND

I/O PERIPHERAL CARD 2

C3

POWER SUPPLY

HOT SWAP

R7

10k

R8

10k

R9

10k

R10

10k

0.01μF

CARD

ENABLE/DISABLE

V

CC

SDAOUT

SCLOUT

READY

CARD2_SDA

CARD2_SCL

ENABLE

U2

SDAIN

SCLIN

LTC4300A-1

GND

I/O PERIPHERAL CARD N

C5

POWER SUPPLY

HOT SWAP

R11

10k

R12

10k

R13

10k

R14

10k

0.01μF

CARD

ENABLE/DISABLE

V

CC

SDAOUT

SCLOUT

READY

CARDN_SDA

CARDN_SCL

ENABLE

U3

SDAIN

SCLIN

LTC4300A-1

GND

4300a12 F03

Figure 3. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-1 in a CompactPCI System

4300a12fa

10

LTC4300A-1/LTC4300A-2

APPLICATIONS INFORMATION

these applications, note that if the I/O cards were plugged

directly into the backplane, all of the backplane and card

capacitances would add directly together, making rise-

and fall-time requirements difficult to meet. Placing a

LTC4300Aontheedgeofeachcard, however, isolatesthe

cardcapacitancefromthebackplane. ForagivenI/Ocard,

theLTC4300Adrivesthecapacitanceofeverythingonthe

card and the backplane must drive only the capacitance

of the LTC4300A, which is less than 10pF.

V_CCis monitored by a filtered UVLO circuit. With the V_CC

voltage powering up after all other pins have established

connection, the UVLO circuit ensures that the backplane

and card data and clock busses are not connected until

the transients associated with live insertion have settled.

Owing to their small capacitance, the SDAIN and SCLIN

pins cause minimal disturbance on the backplane busses

when they make contact with the connector.

Figure 4 shows the LTC4300A-2 in a CompactPCI con-

Figure3showstheLTC4300A-1inaCompactPCIconfigu-

ration. Connect V_CCand ENABLE to the output of one of

the CompactPCI power supply Hot Swap circuits. Use a

pull-up resistor to ENABLE for a card side enable/disable.

figuration. The LTC4300A-2 receives its V voltage from

CC

one of the long “early power” pins. Because this power is

not switched, add a 5Ω to 10Ω resistor between the V

CC

pins of the connector and the LTC4300A-2, as shown in

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

POWER SUPPLY

HOT SWAP

V

CC2

C1

0.01μF

R4

10k

R5

10k

R6

10k

BD_SEL

5.1Ω

V

CC2

SDAOUT

SCLOUT

ACC

CARD_SDA

CARD_SCL

V

CC

U1

SDAIN

SCLIN

SDA

SCL

LTC4300A-2

GND

R1

10k

R2

10k

C2 0.01μF

I/O PERIPHERAL CARD 2

C3

POWER SUPPLY

HOT SWAP

R8

10k

R9

10k

R10

10k

0.01μF

5.1Ω

V

CC2

SDAOUT

SCLOUT

ACC

CARD2_SDA

CARD2_SCL

V

CC

U2

SDAIN

SCLIN

LTC4300A-2

GND

C4 0.01μF

I/O PERIPHERAL CARD N

C5

POWER SUPPLY

HOT SWAP

R12

10k

R13

10k

R14

10k

0.01μF

5.1Ω

V

CC2

SDAOUT

SCLOUT

ACC

CARDN_SDA

CARDN_SCL

V

CC

U3

SDAIN

SCLIN

LTC4300A-2

GND

C6 0.01μF

4300a12 F04

Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-2 in a CompactPCI System

4300a12fa

11

LTC4300A-1/LTC4300A-2

APPLICATIONS INFORMATION

the figure. In addition, make sure that the V bypassing

Figure6showstheLTC4300A-2inanapplicationwherethe

user has a custom connector with pins of three different

CC

on the backplane is large compared to the 0.01μF bypass

capacitor on the card. Establishing early power V

lengths available. Making V

the shortest pin ensures

CC

CC2

ensures that the 1V precharge voltage is present at the

thatallotherpinsarefirmlyconnectedbeforeV receives

CC2

ensures that

pin is firmly connected before the LTC4300A-2

SDAIN and SCLIN pins before they make contact. Con-

any voltage. A filtered UVLO circuit on V

CC2

nect V

to the output of one of the CompactPCI power

the V

CC2

supply Hot Swap circuits. V

is monitored by a filtered

connects the backplane to the card.

CC2

UVLO circuit. With the V

voltage powering up after all

CC2

Repeater/Bus Extender Application

other pins have established connection, the UVLO circuit

ensuresthatthebackplaneandcarddataandclockbusses

are not connected until the transients associated with live

insertion have settled.

Userswhowishtoconnecttwo2-wiresystemsseparated

by a distance can do so by connecting two LTC4300A-1s

2

back-to-back, as shown in Figure 7. The I C specification

allows for 400pF maximum bus capacitance, severely

limiting the length of the bus. The SMBus specification

places no restriction on bus capacitance, but the limited

impedances of devices connected to the bus require

systems to remain small if rise- and fall-time specifica-

tions are to be met. The strong pull-up and pull-down

impedances of the LTC4300A-1 are capable of meeting

Figure 5 shows the LTC4300A-1 in a PCI application,

where all of the pins have the same length. In this case,

connect an RC series circuit on the I/O card between V

CC

and ENABLE. An RC product of 10ms provides a filter to

prevent the LTC4300A-1 from becoming activated until

the transients associated with live insertion have settled.

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

C1

V

CC

R1

R2

10k

R3

100k

R4

10k

R5

10k

R6

10k

0.01μF

10k

V

CC

SDAOUT

SCLOUT

READY

CARD_SDA

CARD_SCL

ENABLE

SDAIN

SCLIN

U1

SDA

SCL

LTC4300A-1

GND

C2 0.1μF

I/O PERIPHERAL CARD 2

C3

R7

100k

R8

10k

R9

10k

R10

10k

0.01μF

V

CC

SDAOUT

SCLOUT

READY

CARD2_SDA

CARD2_SCL

ENABLE

SDAIN

SCLIN

U2

LTC4300A-1

GND

C4 0.1μF

4300a12 F05

t

Figure 5. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-1 in a PCI System

4300a12fa

12

LTC4300A-1/LTC4300A-2

APPLICATIONS INFORMATION

BACKPLANE

CONNECTOR

BACKPLANE

I/O PERIPHERAL CARD 1

C1

V

CC2

R4

10k

R5

10k

R6

10k

0.01μF

R1

10k

R2

10k

V

CC2

SDAOUT

SCLOUT

ACC

CARD_SDA

CARD_SCL

V

CC

U1

SDAIN

SCLIN

SDA

SCL

LTC4300A-2

GND

C2 0.01μF

I/O PERIPHERAL CARD 2

C3

R8

10k

R9

10k

R10

10k

0.01μF

V

CC2

SDAOUT

SCLOUT

ACC

CARD2_SDA

CARD2_SCL

V

CC

U2

SDAIN

SCLIN

LTC4300A-2

GND

C4 0.01μF

4300a12 F06

t

Figure 6. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-2 with a Custom Connector

2-WIRE SYSTEM 1

2-WIRE SYSTEM 2

V

= 5V

V

CC

C1

0.01μF

C2

0.01μF

R5

10k

R2

R3

R6

10k

R1

10k

R4

10k

R7

10k

R8

10k

LTC4300A-1

5.1k 5.1k

V

CC

V

CC

ENABLE

SDAIN

SCLIN

ENABLE

SDAOUT

SCLOUT

READY

SCLOUT

READY

SDAIN

SCLIN

SDA1

SCL1

SDA1

SCL1

TO OTHER

SYSTEM 1

DEVICES

TO OTHER

SYSTEM 2

DEVICES

GND

LONG

DISTANCE

BUS

4300a12 F07

Figure 7. Repeater/Bus Extender Application

4300a12fa

13

LTC4300A-1/LTC4300A-2

APPLICATIONS INFORMATION

rise- and fall-time specifications for 1nF of capacitance,

thus allowing much more interconnect distance. In this

situation, thedifferentialgroundvoltagebetweenthetwo

systems may limit the allowed distance, because a valid

logic low voltage with respect to the ground at one end

5V to 3.3V Level Translator and Power Supply

Redundancy (LTC4300A-2)

Systems requiring different supply voltages for the back-

plane side and the card side can use the LTC4300A-2, as

shown in Figure 9. The pull-up resistors on the card side

of the system may violate the allowed V specification

OL

connect from SDAOUT to SCLOUT to V , and those on

CC2

with respect to the ground at the other end. In addition,

the connection circuitry offset voltages of the back-to-

back LTC4300A-1s add together, directly contributing

to the same problem.

thebackplanesideconnectfromSDAINandSCLINtoV .

CC

TheLTC4300A-2functionsforvoltagesrangingfrom2.7V

to 5.5V on both V and V . There is no constraint on

CC

CC2

CC

the voltage magnitudes of V and V

with respect to

CC2

each other.

Systems with Disparate Supply Voltages

(LTC4300A-1)

This application also provides power supply redundancy.

If the V voltage falls below its UVLO threshold, the

CC2

In large 2-wire systems, the V voltages seen by devices

CC

LTC4300A-2 disconnects the backplane from the card,

at various points in the system can differ by a few hun-

so that the backplane can continue to function. If the V

CC

volt-

dred millivolts or more. This situation is well modelled

voltage falls below its UVLO threshold and the V

CC2

by a series resistor in the V line, as shown in Figure 8.

CC

age remains active, ground the ACC pin to ensure proper

operation.

For proper operation of the LTC4300A-1, make sure that

V

≥ V

– 0.5V.

CC(BUS)

CC(LTC4300A)

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

MS8 Package

8-Lead Plastic MSOP

(Reference LTC DWG # 05-08-1660 Rev F)

3.00 0.102

(.118 .004)

(NOTE 3)

0.52

(.0205)

REF

0.889 0.127

(.035 .005)

8

7 6

5

3.00 0.102

(.118 .004)

(NOTE 4)

5.23

(.206)

MIN

4.90 0.152

(.193 .006)

3.20 – 3.45

(.126 – .136)

DETAIL “A”

0° – 6° TYP

0.254

(.010)

GAUGE PLANE

0.65

(.0256)

BSC

0.42 0.038

(.0165 .0015)

TYP

1

2

3

4

0.53 0.152

(.021 .006)

1.10

(.043)

MAX

0.86

(.034)

REF

RECOMMENDED SOLDER PAD LAYOUT

DETAIL “A”

0.18

(.007)

SEATING

PLANE

0.22 – 0.38

0.1016 0.0508

(.009 – .015)

(.004 .002)

0.65

(.0256)

BSC

TYP

MSOP (MS8) 0307 REV F

NOTE:

1. DIMENSIONS IN MILLIMETER/(INCH)

2. DRAWING NOT TO SCALE

4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.

INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX

3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.

MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE

4300a12fa

14

LTC4300A-1/LTC4300A-2

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

7/12

Added T

parameter to Electrical Characteristics

3

PHL,SKEW

4300a12fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

15

LTC4300A-1/LTC4300A-2

TYPICAL APPLICATIONS

R

V

(LTC4300A)

CC

DROP

V

(BUS)

CC

C2

0.01μF

R1

10k

R2

10k

R3

10k

R4

10k

R5

10k

V

CC

ENABLE

SDAOUT

SCLOUT

READY

SDA2

SCL2

U1

SDAIN

SCLIN

SDA

SCL

LTC4300A-1

GND

4300a12 F08

Figure 8. System with Disparate V_CCVoltages

V

CC

CARD_V , 3.3V

CC

5V

C2

0.01μF

C1

0.01μF

R3

10k

R2

10k

R1

10k

R4

10k

V

CC2

CC

SDAIN

SCLIN

SDAOUT

SCLOUT

ACC

CARD_SDA

CARD_SCL

SDA

SCL

U1

LTC4300A-2

4300a12 F09

GND

Figure 9. 5V to 3.3V Level Translator

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PART NUMBER

DESCRIPTION

COMMENTS

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4300a12fa

LT 0712 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

16

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC4300A-2IMS8#PBF
厂家：	Linear
描述：	LTC4300A-2 - Hot Swappable 2-Wire Bus Buffers; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C 光电二极管
文件：	总16页 (文件大小：187K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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