LTC4300A-2IMS8#TR [Linear]
LTC4300A-2 - Hot Swappable 2-Wire Bus Buffers; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C;
| 型号： | LTC4300A-2IMS8#TR |
| 厂家： | 
Linear |
| 描述： | LTC4300A-2 - Hot Swappable 2-Wire Bus Buffers; Package: MSOP; Pins: 8; Temperature Range: -40°C to 85°C 电源电路 电源管理电路 光电二极管 |
| 文件： | 总16页 (文件大小：282K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4300A-1/LTC4300A-2
Hot Swappable
2-Wire Bus Buffers
U
DESCRIPTIO
FEATURES
■
Bidirectional Buffer for SDA and SCL Lines
The LTC®4300A series hot swappable 2-wire bus buffers
allow I/O card insertion into a live backplane without
corruption of the data and clock busses. When the con-
nection is made, the LTC4300A-1/LTC4300A-2 provide
bidirectional buffering, keeping the backplane and card
capacitances isolated. Rise-time accelerator circuitry*
allows the use of weaker DC pull-up currents while still
meeting rise-time requirements. During insertion, the
SDA and SCL lines are precharged to 1V to minimize bus
disturbances.
Increases Fanout
■
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
■
Isolates Input SDA and SCL Lines from Output
Compatible with I2CTM, I2C Fast Mode and SMBus
■
Standards (Up to 400kHz Operation)
Small MSOP 8-Pin Package
■
■
Low ICC Chip Disable: <1µA (LTC4300A-1)
■
READY Open Drain Output (LTC4300A-1)
■
1V Precharge on all SDA and SCL Lines
The LTC4300A-1 incorporates a CMOS threshold digital
ENABLE input pin, which forces the part into a low current
modewhendriventogroundandsetsnormaloperationwhen
driven to VCC. It also includes an open drain READY output
pin, which indicates that the backplane and card sides are
connectedtogether. TheLTC4300A-2replacestheENABLE
pin with a dedicated supply voltage pin, VCC2, for the card
side, providinglevelshiftingbetween3.3Vand5Vsystems.
Both the backplane and card may be powered with supply
voltages ranging from 2.7V to 5.5V, with no contraints on
which supply voltage is higher. The LTC4300A-2 also re-
places the READY pin with a digital CMOS input pin, ACC,
whichenablesanddisablestherise-timeacceleratorcurrents.
■
Supports Clock Stretching, Arbitration and
Synchronization
■
5V to 3.3V Level Translation (LTC4300A-2)
■
High Impedance SDA, SCL Pins for VCC = 0V
U
APPLICATIO S
■
Hot Board Insertion
Servers
■
■
Capacitance Buffer/Bus Extender
■
Desktop Computer
, LTC and LT are registered trademarks of Linear Technology Corporation.
I2C is a trademark of Philips Electronics N. V.
*U.S. Patent No. 6,650,174
The LTC4300A is available in a small 8-pin MSOP package.
U
TYPICAL APPLICATIO
V
CC
Input–Output Connection tPLH
3.3V
C1
0.01µF
R1
R2
R3
R4
8
10k
10k
10k
10k
3
6
2
SCLIN
SCLOUT
OUTPUT
SIDE
50pF
INPUT
SIDE
150pF
7
5
SDAIN
SDAOUT
LTC4300A-1
1
ENABLE
READY
GND
4
4300A TA02
4300A-1/2 TA01
sn4300a12 4300a12fs
1
LTC4300A-1/LTC4300A-2
W W U W
ABSOLUTE AXI U RATI GS
(Note 1)
U
W
U
PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
VCC to GND .................................................... –0.3 to 7V
VCC2 to GND (LTC4300A-2) ........................... –0.3 to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT................. –0.3 to 7V
READY, ENABLE (LTC4300A-1) .................... –0.3 to 7V
ACC (LTC4300A-2) ........................................ –0.3 to 7V
Operating Temperature Range
LTC4300A-1C/LTC4300A-2C ................... 0°C to 70°C
LTC4300A-1I/LTC4300A-2I ................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec).................. 300°C
LTC4300A-1CMS8
LTC4300A-1IMS8
LTC4300A-2CMS8
LTC4300A-2IMS8
TOP VIEW
ENABLE/V
*
1
2
3
4
8 V
CC
7 SDAOUT
6 SDAIN
CC2
SCLOUT
SCLIN
GND
5 READY/ACC*
MS8 PACKAGE
8-LEAD PLASTIC MSOP
*LTC4300A-2
MS8
PART MARKING
TJMAX = 125°C, θJA = 200°C/W
LTABF
LTABG
LTACF
LTACG
Consult LTC marketing for parts specified with wider operating temperature ranges.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER
Power Supply
CONDITIONS
MIN
TYP
MAX
UNITS
V
Positive Supply Voltage
Supply Current
●
●
2.7
5.5
7
V
mA
µA
V
CC
I
I
V
V
= 5.5V, V
= V = 0V, LTC4300A-1
SCLIN
5.1
0.1
CC
SD
CC
SDAIN
Supply Current in Shutdown Mode
Card Side Supply Voltage
= 0V, LTC4300A-1
ENABLE
V
LTC4300A-2
●
2.7
5.5
4.1
CC2
I
V
CC
Supply Current
V
= V
= 0V, V
= V
= 5.5V,
3
mA
VCC1
SDAIN
SCLIN
CC1
CC2
LTC4300A-2
I
V
CC2
Supply Current
V
= V
= 0V, V
= V = 5.5V,
CC2
2.1
2.9
mA
VCC2
SDAOUT
SCLOUT
CC1
LTC4300A-2
Start-Up Circuitry
V
Precharge Voltage
SDA, SCL Floating
LTC4300A-1
●
●
0.8
50
1.0
95
1.2
V
µs
V
PRE
t
Bus Idle Time
150
IDLE
V
V
ENABLE Threshold Voltage
Disable Threshold Voltage
ENABLE Input Current
ENABLE Delay, On-Off
READY Delay, Off-On
ENABLE Delay, Off-On
READY Delay, On-Off
READY OFF State Leakage Current
READY Output Low Voltage
0.5 • V
0.5 • V
±0.1
10
0.9 • V
CC
EN
CC
LTC4300A-1, ENABLE Pin
0.1 • V
V
DIS
CC
CC
I
t
ENABLE from 0V to V , LTC4300A-1
±1
µA
ns
ns
µs
ns
µA
V
EN
CC
LTC4300A-1
LTC4300A-1
LTC4300A-1
LTC4300A-1
LTC4300A-1
PHL
PLH
OFF
10
t
I
95
10
±0.1
V
I
= 3mA, LTC4300A-1
PULLUP
●
0.4
OL
sn4300a12 4300a12fs
2
LTC4300A-1/LTC4300A-2
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER
Rise-Time Accelerators
CONDITIONS
MIN
TYP
MAX
UNITS
I
Transient Boosted Pull-Up Current
Positive Transition on SDA,SCL, V = 2.7V,
Slew Rate = 1.25V/µs (Note 2),
1
2
mA
PULLUPAC
CC
LTC4300A-2, ACC = 0.7 • V , V
= 2.7V
CC2 CC2
V
V
Accelerator Disable Threshold
Accelerator Enable Threshold
ACC Input Current
LTC4300A-2
LTC4300A-2
LTC4300A-2
LTC4300A-2
0.3 • V
0.5 • V
0.5 • V
V
V
ACCDIS
ACCEN
VACC
CC2
CC2
CC2
0.7 • V
CC2
I
t
±0.1
±1
µA
ns
ACC Delay, On/Off
5
PDOFF
Input-Output Connection
V
Input-Output Offset Voltage
10k to V on SDA, SCL, V = 3.3V (Note 3),
●
●
0
0
100
175
mV
OS
CC
CC
LTC4300A-2, V
= 3.3V, V = 0.2V
CC2
IN
f
Operating Frequency
Guaranteed by Design, Not Subject to Test
Guaranteed by Design, Not Subject to Test
400
10
kHz
pF
V
SCL, SDA
C
V
Digital Input Capacitance
Output Low Voltage, Input = 0V
IN
SDA, SCL Pins, I
= 3mA, V = 2.7V,
0
0.4
OL
SINK
CC
V
= 2.7V, LTC4300A-2
CC2
I
Input Leakage Current
SDA, SCL Pins = V = 5.5V,
±5
µA
LEAK
CC
LTC4300A-2, V
= 5.5V
CC2
Timing Characteristics
2
f
t
I C Operating Frequency
(Note 4)
(Note 4)
0
400
kHz
I2C
Bus Free Time Between Stop
and Start Condition
1.3
µs
BUF
t
Hold Time After (Repeated)
Start Condition
(Note 4)
0.6
µs
hD,STA
t
t
t
t
t
t
t
t
Repeated Start Condition Setup Time (Note 4)
0.6
0.6
µs
µs
ns
ns
µs
µs
ns
ns
su,STA
su,STO
hD, DAT
su, DAT
LOW
HIGH
f
Stop Condition Setup Time
Data Hold Time
(Note 4)
(Note 4)
300
100
Data Setup Time
(Note 4)
Clock Low Period
(Note 4)
1.3
Clock High Period
Clock, Data Fall Time
Clock, Data Rise Time
(Note 4)
0.6
(Notes 4, 5)
(Notes 4, 5)
20 + 0.1 • C
20 + 0.1 • C
300
300
B
r
B
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired
Note 4: Guaranteed by design, not subject to test.
Note 5: C = total capacitance of one bus line in pF.
B
Note 2: I
varies with temperature and V voltage, as shown in
CC
PULLUPAC
the Typical Performance Characteristics section.
Note 3: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pullup resistor and V voltage is shown in the Typical Performance
CC
Characteristics section.
sn4300a12 4300a12fs
3
LTC4300A-1/LTC4300A-2
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TYPICAL PERFOR A CE CHARACTERISTICS
Input – Output tPHL vs Temperature
(LTC4300A-1)
ICC vs Temperature (LTC4300A-1)
5.3
100
80
60
40
20
0
V
= 2.7V
CC
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
V
= 5.5V
CC
V
= 3.3V
CC
V
= 2.7V
V
= 5.5V
CC
CC
C
= C
PULLUPIN
= 100pF
OUT
IN
R
= R
= 10k
PULLUPOUT
–40
25
TEMPERATURE (°C)
85
–50
–25
0
25
50
75
100
TEMPERATURE (°C)
4300-1/2 G01
4300-1/2 G02
IPULLUPAC vs Temperature
Connection Circuitry VOUT – VIN
12
10
8
300
250
200
150
100
50
T
= 25°C
IN
A
V
= 0V
V
= 5V
CC
6
V
= 5V
CC
V
V
= 3V
CC
CC
4
V
= 3.3V
CC
2
= 2.7V
25
0
0
–50
–25
0
50
75
100
0
10,000
20,000
R (Ω)
PULLUP
30,000
40,000
TEMPERATURE (°C)
4300-1/2 G03
4300-1/2 G04
sn4300a12 4300a12fs
4
LTC4300A-1/LTC4300A-2
U
U
U
PI FU CTIO S
ENABLE/VCC2 (Pin 1): Chip Enable Pin/Card Supply Volt-
age. For the LTC4300A-1, this is a digital CMOS threshold
input pin. Grounding this pin puts the part in a low current
(<1µA) mode. It also disables the rise-time accelerators,
disables the bus precharge circuitry, drives READY low,
isolates SDAIN from SDAOUT and isolates SCLIN from
SCLOUT. Drive ENABLE all the way to VCC for normal
operation. Connect ENABLE to VCC if this feature is not
beingused. FortheLTC4300A-2, thisisthesupplyvoltage
for the devices on the card I2C busses. Connect pull-up
resistors from SDAOUT and SCLOUT to this pin. Place a
bypasscapacitorofatleast0.01µFclosetothispinforbest
results.
READY/ACC (Pin 5): Connection Flag/Rise-Time Accel-
erator Control. For the LTC4300A-1, this is an open-drain
NMOS output which pulls low when either ENABLE is low
or the start-up sequence described in the Operation sec-
tion has not been completed. READY goes high when
ENABLE is high and start-up is complete. Connect a 10k
resistor from this pin to VCC to provide the pull up. For the
LTC4300A-2, this is a CMOS threshold digital input pin
that enables and disables the rise-time accelerators on all
four SDA and SCL pins. Drive ACC all the way to the VCC2
supply voltage to enable all four accelerators; drive ACC to
ground to turn them off.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to the
SCL bus on the backplane.
VCC (Pin 8): Main Input Power Supply from Backplane.
This is the supply voltage for the devices on the backplane
I2C busses. Connect pull-up resistors from SDAIN and
SCLIN (and also from SDAOUT and SCLOUT for the
LTC4300A-1) to this pin. Place a bypass capacitor of at
least 0.01µF close to this pin for best results.
GND (Pin 4): Ground. Connect this pin to a ground plane
for best results.
sn4300a12 4300a12fs
5
LTC4300A-1/LTC4300A-2
W
BLOCK DIAGRA
(LTC4300A-1)
2-Wire Bus Buffer and Hot SwapTM Controller
2mA
2mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
8
V
CC
BACKPLANE-TO-CARD
SDAIN
6
7 SDAOUT
CONNECTION
CONNECT
CONNECT
CONNECT
ENABLE
100k
RCH1
100k
RCH3
1V
PRECHARGE
100k
RCH2
100k
RCH4
2mA
2mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
SCLIN
3
2 SCLOUT
CONNECT
CONNECT
+
–
V
CC
– 1V
+
–
+
–
STOP BIT AND BUS IDLE
0.5µA
+
–
0.55V
/
CC
CC
5
4
READY
GND
20pF
0.45V
95µs
CONNECT
UVLO
DELAY,
RISING
ONLY
RD
S
ENABLE
1
QB
0.5pF
CONNECT
4300A-1 BD
Hot Swap is a trademark of Linear Technology Corporation.
sn4300a12 4300a12fs
6
LTC4300A-1/LTC4300A-2
W
BLOCK DIAGRA
(LTC4300A-2)
2-Wire Bus Buffer and Hot Swap Controller
V
8
CC
2mA
2mA
1
V
CC2
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
ACC
BACKPLANE-TO-CARD
SDAIN
6
7 SDAOUT
CONNECTION
CONNECT
CONNECT
CONNECT
100k
RCH1
100k
RCH3
1V
PRECHARGE
100k
RCH2
100k
RCH4
2mA
2mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
5
2
ACC
ACC
BACKPLANE-TO-CARD
CONNECTION
SCLIN
3
SCLOUT
CONNECT
CONNECT
+
–
V
– 1V
CC2
+
–
+
–
STOP BIT AND BUS IDLE
0.5µA
+
–
0.55V
/
CC
CC
20pF
0.45V
95µs
CONNECT CONNECT
DELAY,
RISING
ONLY
UVLO
RD
S
QB
4
GND
0.5pF
4300A-2 BD
sn4300a12 4300a12fs
7
LTC4300A-1/LTC4300A-2
U
OPERATIO
Start-Up
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as
described here.
When the LTC4300A first receives power on its VCC pin,
either during power-up or during live insertion, it starts in
an undervoltage lockout (UVLO) state, ignoring any activ-
ityontheSDAandSCLpinsuntilVCC risesabove2.5V. For
the LTC4300A-2, the part also waits for VCC2 to rise above
2V. This ensures that the part does not try to function until
it has enough voltage to do so.
Input to Output Offset Voltage
When a logic low voltage, VLOW1, is driven on any of the
LTC4300A’s data or clock pins, the LTC4300A regulates
the voltage on the other side of the chip (call it VLOW2) to
a slightly higher voltage, as directed by the following
equation:
During this time, the 1V precharge circuitry is also active
and forces 1V through 100k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged into
alivebackplane,thevoltageonthebackplaneSDAandSCL
bussesmaybeanywherebetween0VandVCC.Precharging
the SCL and SDA pins to 1V minimizes the worst-case
voltagedifferentialthesepinswillseeatthemomentofcon-
nection, therefore minimizing the amount of disturbance
caused by the I/O card.
VLOW2 = VLOW1 + 75mV + (VCC/R) • 100
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where
VCC =3.3Vandthepull-upresistorRonSDAINis10k,then
the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 100
= 118mV. See the Typical Performance Characteristics
section for curves showing the offset voltage as a function
of VCC and R.
Once the LTC4300A comes out of UVLO, it assumes that
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the backplane side to indicate
the completion of a data transaction. When either one
occurs, the part also verifies that both the SDAOUT and
SCLOUT voltages are high. When all of these conditions
are met, the input-to-output connection circuitry is acti-
vated, joiningtheSDAandSCLbussesontheI/Ocardwith
those on the backplane, and the rise time accelerators are
enabled.
Propagation Delays
During a rising edge, the rise-time on each side is deter-
mined by the combined pull-up current of the LTC4300A
boost current and the bus resistor and the equivalent
capacitance on the line. If the pull-up currents are the
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between the
twosides.ThiseffectisdisplayedinFigure1forVCC =3.3V
and a 10k pull-up resistor on each side (50pF on one side
and 150pF on the other). Since the output side has less
capacitance than the input, it rises faster and the effective
Connection Circuitry
Once the connection circuitry is activated, the functional-
ityoftheSDAINandSDAOUTpinsisidentical.Alowforced
on either pin at any time results in both pin voltages being
low. For proper operation, logic low input voltages should
benohigherthan0.4Vwithrespecttothegroundpinvoltage
of the LTC4300A. SDAIN and SDAOUT enter a logic high
state only when all devices on both SDAIN and SDAOUT
releasehigh.ThesameistrueforSCLINandSCLOUT.This
importantfeatureensuresthatclockstretching,clocksyn-
chronization, arbitration and the acknowledge protocol al-
wayswork,regardlessofhowthedevicesinthesystemare
tied to the LTC4300A.
tPLH is negative.
There is a finite propagation delay, tPHL, through the
connectioncircuitryforfallingwaveforms. Figure2shows
the falling edge waveforms for the same VCC, pull-up
resistorsandequivalentcapacitanceconditionsasusedin
Figure 1. An external NMOS device pulls down the voltage
on the side with 150pF capacitance; the LTC4300A pulls
down the voltage on the opposite side, with a delay of
55ns. This delay is always positive and is a function of
sn4300a12 4300a12fs
8
LTC4300A-1/LTC4300A-2
U
OPERATIO
OUTPUT
SIDE
50pF
INPUT
SIDE
150pF
INPUT
SIDE
150pF
OUTPUT
SIDE
50pF
Figure 1. Input–Output Connection tPLH
Figure 2. Input–Output Connection tPHL
supply voltage, temperature and the pull-up resistors and
equivalent bus capacitances on both sides of the bus. The
Typical Performance Characteristics section shows tPHL
as a function of temperature and voltage for 10k pull-up
resistors and 100pF equivalent capacitance on both sides
of the part. By comparison with Figure 2, the VCC = 3.3V
curve shows that increasing the capacitance from 50pF to
100pF results in a tPHL increase from 55ns to 75ns. Larger
output capacitances translate to longer delays (up to
150ns). Users must quantify the difference in propagation
times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
using the rise-time accelerators, which are activated at a
DC threshold of below 0.65V, the worst-case rise-time is:
(2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the
1µs rise-time requirement.
READY Digital Output (LTC4300A-1)
This pin provides a digital flag which is low when either
ENABLE is low or the start-up sequence described earlier
in this section has not been completed. READY goes high
when ENABLE is high and start-up is complete. The pin is
driven by an open drain pull-down capable of sinking 3mA
while holding 0.4V on the pin. Connect a resistor of 10k to
VCC to provide the pull-up. This feature is available for the
LTC4300A-1 only.
Rise-Time Accelerators
Onceconnectionhasbeenestablished,rise-timeaccelera-
tor circuits on all four SDA and SCL pins are activated.
TheseallowtheusertochooseweakerDCpull-upcurrents
on the bus, reducing power consumption while still meet-
ing system rise-time requirements. During positive bus
transitions, the LTC4300A switches in 2mA (typical) of
current to quickly slew the SDA and SCL lines once their
DC voltages exceed 0.6V. Using a general rule of 20pF of
capacitance for every device on the bus (10pF for the
device and 10pF for interconnect), choose a pull-up cur-
rent so that the bus will rise on its own at a rate of at least
1.25V/µs to guarantee activation of the accelerators.
ENABLE Low Current Disable (LTC4300A-1)
Grounding the ENABLE pin disconnects the backplane
side from the card side, disables the rise-time accelera-
tors, drives READY low, disables the bus precharge cir-
cuitry and puts the part in a near-zero current state. When
the pin voltage is driven all the way to VCC, the part waits
fordatatransactionsonboththebackplaneandcardsides
to be complete (as described in the Start-Up section)
beforereconnectingthetwosides.Thisfeatureisavailable
for the LTC4300A-1 only.
ACC Boost Current Enable (LTC4300A-2)
For example, assume an SMBus system with VCC = 3V, a
10k pull-up resistor and equivalent bus capacitance of
200pF. The rise-time of an SMBus system is calculated
from (VIL(MAX) – 0.15V) to (VIH(MIN) + 0.15V), or 0.65V to
2.25V. It takes an RC circuit 0.92 time constants to
traverse this voltage for a 3V supply; in this case, 0.92 •
(10k • 200pF) = 1.84µs. Thus, the system exceeds the
maximum allowed rise-time of 1µs by 84%. However,
Users having lightly loaded systems may wish to disable
the rise-time accelerators. Driving this pin to ground turns
offtherise-timeacceleratorsonallfourSDAandSCLpins.
Driving this pin to the VCC2 voltage enables normal opera-
tion of the rise-time accelerators, as described in the Rise-
Time Accelerators section above. This feature is available
for the LTC4300A-2 only.
sn4300a12 4300a12fs
9
LTC4300A-1/LTC4300A-2
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APPLICATIO S I FOR ATIO
Resistor Pull-Up Value Selection
In addition, regardless of the bus capacitance, always
choose R ≤ 16k for VCC = 5.5V maximum, R ≤ 24k for
VCC = 3.6Vmaximum.Thestart-upcircuitryrequireslogic
high voltages on SDAOUT and SCLOUT to connect the
backplanetothecard, andthesepull-upvaluesareneeded
to overcome the precharge voltage.
The system pull-up resistors must be strong enough to
provide a positive slew rate of 1.25V/µs on the SDA and
SCL pins, in order to activate the boost pull-up currents
during rising edges. Choose maximum resistor value R
using the formula:
R ≤ (VCC(MIN) – 0.6) (800,000) / C
Live Insertion and Capacitance Buffering Application
where R is the pull-up resistor value in ohms, VCC(MIN) is
the minimum VCC voltage and C is the equivalent bus
capacitance in picofarads (pF).
Figures 3 through 6 illustrate the usage of the LTC4300A
in applications that take advantage of both its hot swap
controlling and capacitance buffering features. In all of
BACKPLANE
CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD 1
POWER SUPPLY
HOT SWAP
V
CC
C1
0.01µF
R3
10k
R1
R2
10k
R4
10k
R5
10k
R6
10k
10k
CARD
ENABLE/DISABLE
V
CC
SDAOUT
SCLOUT
READY
CARD_SDA
CARD_SCL
BD_SEL
SDA
ENABLE
U1
SDAIN
SCLIN
LTC4300A-1
SCL
GND
I/O PERIPHERAL CARD 2
C3
POWER SUPPLY
HOT SWAP
R7
10k
R8
10k
R9
10k
R10
10k
0.01µF
CARD
ENABLE/DISABLE
V
CC
SDAOUT
SCLOUT
READY
CARD2_SDA
CARD2_SCL
ENABLE
U2
SDAIN
SCLIN
LTC4300A-1
GND
I/O PERIPHERAL CARD N
C5
POWER SUPPLY
HOT SWAP
R11
10k
R12
10k
R13
10k
R14
10k
0.01µF
CARD
ENABLE/DISABLE
V
CC
SDAOUT
SCLOUT
READY
CARDN_SDA
CARDN_SCL
ENABLE
U3
SDAIN
SCLIN
LTC4300A-1
GND
4300A-1/2 F03
Figure 3. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-1 in a CompactPCI System
sn4300a12 4300a12fs
10
LTC4300A-1/LTC4300A-2
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APPLICATIO S I FOR ATIO
these applications, note that if the I/O cards were plugged
directly into the backplane, all of the backplane and card
capacitanceswouldadddirectlytogether,makingrise-and
fall-time requirements difficult to meet. Placing a
LTC4300Aontheedgeofeachcard, however, isolatesthe
cardcapacitancefromthebackplane. ForagivenI/Ocard,
the LTC4300A drives the capacitance of everything on the
cardandthebackplanemustdriveonlythecapacitanceof
the LTC4300A, which is less than 10pF.
Figure 3 shows the LTC4300A-1 in a CompactPCITM con-
figuration. Connect VCC and ENABLE to the output of one
of the CompactPCI power supply Hot Swap circuits. Use
apull-upresistortoENABLEforacardsideenable/disable.
VCC is monitored by a filtered UVLO circuit. With the VCC
voltage powering up after all other pins have established
connection, the UVLO circuit ensures that the backplane
andcarddataandclockbussesarenotconnecteduntilthe
transientsassociatedwithliveinsertionhavesettled.Owing
totheirsmallcapacitance,theSDAINandSCLINpinscause
minimal disturbance on the backplane busses when they
make contact with the connector.
Figure4showstheLTC4300A-2inaCompactPCIconfigu-
ration. The LTC4300A-2 receives its VCC voltage from one
of the long “early power” pins. Because this power is not
switched, add a 5Ω to 10Ω resistor between the VCC pins
CompactPCI is a trademark of the PCI Industrial Computer Manufacturers Group.
BACKPLANE
CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD 1
POWER SUPPLY
HOT SWAP
V
CC2
C1
R4
10k
R5
10k
R6
10k
0.01µF
BD_SEL
5.1Ω
V
CC2
SDAOUT
SCLOUT
ACC
CARD_SDA
CARD_SCL
V
V
CC
CC
U1
SDAIN
SCLIN
SDA
SCL
LTC4300A-2
GND
R1
10k
R2
10k
C2 0.01µF
I/O PERIPHERAL CARD 2
C3
POWER SUPPLY
HOT SWAP
R8
10k
R9
10k
R10
10k
0.01µF
5.1Ω
V
CC2
SDAOUT
SCLOUT
ACC
CARD2_SDA
CARD2_SCL
V
CC
U2
SDAIN
SCLIN
LTC4300A-2
GND
C4 0.01µF
I/O PERIPHERAL CARD N
C5
POWER SUPPLY
HOT SWAP
R12
10k
R13
10k
R14
10k
0.01µF
5.1Ω
V
CC2
SDAOUT
SCLOUT
ACC
CARDN_SDA
CARDN_SCL
V
CC
U3
SDAIN
SCLIN
LTC4300A-2
GND
C6 0.01µF
4300A-1/2 F04
Figure 4. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-2 in a CompactPCI System
sn4300a12 4300a12fs
11
LTC4300A-1/LTC4300A-2
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APPLICATIO S I FOR ATIO
of the connector and the LTC4300A-2, as shown in the
figure. In addition, make sure that the VCC bypassing on
the backplane is large compared to the 0.01µF bypass
capacitor on the card. Establishing early power VCC en-
sures that the 1V precharge voltage is present at the
SDAIN and SCLIN pins before they make contact. Connect
Figure 6 shows the LTC4300A-2 in an application where
the user has a custom connector with pins of three
different lengths available. Making VCC2 the shortest pin
ensures that all other pins are firmly connected before
V
CC2 receives any voltage. A filtered UVLO circuit on VCC2
ensures that the VCC2 pin is firmly connected before the
LTC4300A-2 connects the backplane to the card.
V
CC2 to the output of one of the CompactPCI power supply
Hot Swap circuits. VCC2 is monitored by a filtered UVLO
circuit. With the VCC2 voltage powering up after all other
pins have established connection, the UVLO circuit en-
sures that the backplane and card data and clock busses
are not connected until the transients associated with live
insertion have settled.
Repeater/Bus Extender Application
Users who wish to connect two 2-wire systems sepa-
rated by a distance can do so by connecting two
LTC4300A-1s back-to-back, as shown in Figure 7. The
I2C specification allows for 400pF maximum bus capaci-
tance, severely limiting the length of the bus. The SMBus
specification places no restriction on bus capacitance,
but the limited impedances of devices connected to the
bus require systems to remain small if rise- and fall-time
specifications are to be met. The strong pull-up and pull-
down impedances of the LTC4300A-1 are capable of
Figure 5 shows the LTC4300A-1 in a PCI application,
where all of the pins have the same length. In this case,
connect an RC series circuit on the I/O card between VCC
and ENABLE. An RC product of 10ms provides a filter to
prevent the LTC4300A-1 from becoming activated until
the transients associated with live insertion have settled.
BACKPLANE
CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD 1
C1
V
CC
R1
R2
10k
R3
100k
R4
10k
R5
10k
R6
10k
0.01µF
10k
V
CC
SDAOUT
SCLOUT
READY
CARD_SDA
CARD_SCL
ENABLE
SDAIN
SCLIN
U1
SDA
SCL
LTC4300A-1
GND
C2 0.1µF
I/O PERIPHERAL CARD 2
C3
R7
100k
R8
10k
R9
10k
R10
10k
0.01µF
V
CC
SDAOUT
SCLOUT
READY
CARD2_SDA
CARD2_SCL
ENABLE
SDAIN
SCLIN
U2
LTC4300A-1
GND
C4 0.1µF
4300A-1/2 F05
•
•
•
Figure 5. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-1 in a PCI System
sn4300a12 4300a12fs
12
LTC4300A-1/LTC4300A-2
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APPLICATIO S I FOR ATIO
BACKPLANE
CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD 1
C1
V
CC2
R4
10k
R5
10k
R6
10k
0.01µF
R1
10k
R2
10k
V
CC2
SDAOUT
SCLOUT
ACC
CARD_SDA
CARD_SCL
V
V
CC
CC
U1
SDAIN
SCLIN
SDA
SCL
LTC4300A-2
GND
C2 0.01µF
I/O PERIPHERAL CARD 2
C3
R8
10k
R9
10k
R10
10k
0.01µF
V
CC2
SDAOUT
SCLOUT
ACC
CARD2_SDA
CARD2_SCL
V
CC
U2
SDAIN
SCLIN
LTC4300A-2
GND
C4 0.01µF
4300A-1/2 F06
•
•
•
Figure 6. Inserting Multiple I/O Cards into a Live Backplane Using the LTC4300A-2 with a Custom Connector
2-WIRE SYSTEM 1
2-WIRE SYSTEM 2
V
= 5V
V
CC
CC
C1
0.01µF
C2
0.01µF
R5
10k
R2
R3
R6
10k
R1
10k
R4
10k
R7
10k
R8
10k
LTC4300A-1
LTC4300A-1
5.1k 5.1k
V
CC
V
CC
ENABLE
SDAIN
SCLIN
ENABLE
SDAOUT
SDAOUT
SCLOUT
READY
SCLOUT
READY
SDAIN
SCLIN
SDA1
SCL1
SDA1
SCL1
TO OTHER
SYSTEM 1
DEVICES
TO OTHER
SYSTEM 2
DEVICES
GND
GND
LONG
DISTANCE
BUS
4300A-1/2 F07
Figure 7. Repeater/Bus Extender Application
sn4300a12 4300a12fs
13
LTC4300A-1/LTC4300A-2
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APPLICATIO S I FOR ATIO
meetingrise-andfall-timespecificationsforonenanofarad
of capacitance, thus allowing much more interconnect
distance. In this situation, the differential ground voltage
between the two systems may limit the allowed distance,
because a valid logic low voltage with respect to the
ground at one end of the system may violate the allowed
5V to 3.3V Level Translator and Power Supply
Redundancy (LTC4300A-2)
Systems requiring different supply voltages for the
backplane side and the card side can use the LTC4300A-2,
asshowninFigure9.Thepull-upresistorsonthecardside
connect from SDAOUT to SCLOUT to VCC2, and those on
thebackplanesideconnectfromSDAINandSCLINtoVCC.
TheLTC4300A-2functionsforvoltagesrangingfrom2.7V
to5.5VonbothVCC andVCC2. Thereisnoconstraintonthe
voltage magnitudes of VCC and VCC2 with respect to each
other.
V
OL specification with respect to the ground at the other
end. In addition, the connection circuitry offset voltages
of the back-to-back LTC4300A-1s add together, directly
contributing to the same problem.
Systems with Disparate Supply Voltages
(LTC4300A-1)
This application also provides power supply redundancy.
If the VCC2 voltage falls below its UVLO threshold, the
LTC4300A-2 disconnects the backplane from the card, so
that the backplane can continue to function. If the VCC
voltage falls below its UVLO threshold and the VCC2
voltage remains active, ground the ACC pin to ensure
proper operation.
In large 2-wire systems, the VCC voltages seen by devices
at various points in the system can differ by a few hundred
millivolts or more. This situation is well modelled by a
series resistor in the VCC line, as shown in Figure 8. For
proper operation of the LTC4300A-1, make sure that
V
CC(BUS) ≥ VCC(LTC4300A) – 0.5V.
sn4300a12 4300a12fs
14
LTC4300A-1/LTC4300A-2
U
PACKAGE DESCRIPTION
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
0.889 ± 0.127
(.035 ± .005)
5.23
(.206)
MIN
3.2 – 3.45
(.126 – .136)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.206)
REF
0.65
(.0256)
BSC
0.42 ± 0.04
(.0165 ± .0015)
8
7 6 5
TYP
RECOMMENDED SOLDER PAD LAYOUT
3.00 ± 0.102
(.118 ± .004)
NOTE 4
4.90 ± 0.15
(1.93 ± .006)
DETAIL “A”
0.254
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
0.53 ± 0.015
(.021 ± .006)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.077)
SEATING
PLANE
0.22 – 0.38
(.009 – .015)
TYP
0.13 ± 0.076
(.005 ± .003)
0.65
(.0256)
BSC
MSOP (MS8) 0802
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
sn4300a12 4300a12fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
15
LTC4300A-1/LTC4300A-2
U
TYPICAL APPLICATIO S
R
DROP
V
CC
(LTC4300A)
V
CC
(BUS)
C2
0.01µF
R1
10k
R2
10k
R3
10k
R4
10k
R5
10k
V
CC
ENABLE
SDAOUT
SCLOUT
READY
SDA2
SCL2
U1
SDAIN
SCLIN
SDA
SCL
LTC4300A-1
GND
4300-1/2 F08
Figure 8. System with Disparate VCC Voltages
V
CC
CARD_V , 3.3V
CC
5V
C2
0.01µF
C1
0.01µF
R3
10k
R2
10k
R1
10k
R4
10k
V
V
CC2
CC
SDAIN
SCLIN
SDAOUT
SCLOUT
ACC
CARD_SDA
CARD_SCL
SDA
SCL
U1
LTC4300A-2
4300-1/2 F09
GND
Figure 9. 5V to 3.3V Level Translator
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1380/LTC1393
Single-Ended 8-Channel/Differential 4-Channel Analog
Mux with SMBus Interface
Low R : 35Ω Single-Ended/70Ω Differential,
Expandable to 32 Single or 16 Differential Channels
ON
LTC1427-50
Micropower, 10-Bit Current Output DAC
with SMBus Interface
Precision 50µA ± 2.5% Tolerance Over Temperature,
4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale
LTC1623
Dual High Side Switch Controller with SMBus Interface
SMBus Interface 10-Bit Rail-to-Rail Micropower DAC
SMBus Accelerator
8 Selectable Addresses/16-Channel Capability
DNL < 0.75LSB Max, 5-Lead SOT-23 Package
LTC1663
2
LTC1694/LTC1694-1
Improved SMBus/I C Rise-Time,
Ensures Data Integrity with Multiple SMBus/I C Devices
2
LT1786F
LTC1695
LTC1840
SMBus Controlled CCFL Switching Regulator
1.25A, 200kHz, Floating or Grounded Lamp Configurations
0.75Ω PMOS 180mA Regulator, 6-Bit DAC
TM
2
SMBus/I C Fan Speed Controller in ThinSOT
2
Dual I C Fan Speed Controller
Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0
ThinSOT is a trademark of Linear Technology Corporation.
sn4300a12 4300a12fs
LT/TP 0203 2K • PRINTED IN USA
16 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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