LTC4300A-3CMS8#TRPBF [Linear]
LTC4300A-3 - Level Shifting Hot Swappable 2-Wire Bus Buffer with Enable; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C;
| 型号： | LTC4300A-3CMS8#TRPBF |
| 厂家： | 
Linear |
| 描述： | LTC4300A-3 - Level Shifting Hot Swappable 2-Wire Bus Buffer with Enable; Package: MSOP; Pins: 8; Temperature Range: 0°C to 70°C |
| 文件： | 总12页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC4300A-3
Level Shifting
Hot Swappable 2-Wire
Bus Buffer with Enable
U
DESCRIPTIO
FEATURES
■
Bidirectional Buffer* for SDA and SCL Lines
The LTC®4300A-3 hot swappable 2-wire bus buffer allows
I/O card insertion into a live backplane without corruption
of the data and clock busses. When the connection is
made, the LTC4300A-3 provides bidirectional buffering,
keeping the backplane and card capacitances isolated.
Rise-time accelerator circuitry allows the use of weaker
DC pull-up currents while still meeting rise-time require-
ments. During insertion, the SDA and SCL lines are
precharged to 1V to minimize bus disturbances.
Increases Fanout
■
Prevents SDA and SCL Corruption During Live
Board Insertion and Removal from Backplane
■
Logic Threshold ENABLE Input
■
Isolates Input SDA and SCL Lines from Output
Compatible with I2CTM, I2C Fast Mode and SMBus
■
Standards (Up to 400kHz Operation)
■
1V Precharge on all SDA and SCL Lines
■
Supports Clock Stretching, Arbitration and
The LTC4300A-3 provides level translation between 3.3V
and 5V supplies. The backplane and card can both be
powered with supplies ranging from 2.7V to 5.5V. The
LTC4300A-3alsoincorporatesaCMOSthresholdENABLE
pin which forces the part into a low current mode and iso-
latesthecardfromthebackplane. WhendriventoVCC, the
ENABLE pin sets normal operation.
Synchronization
5V to 3.3V Level Translation
■
■
High Impedance SDA, SCL Pins for VCC = 0V,
VCC2 = 0V
Small 8-Pin DFN and MSOP Packages
■
U
APPLICATIO S
TheLTC4300A-3isavailableintheMSOPand3mm×3mm
DFN packages.
, LTC and LT are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
*Patent pending.
■
Hot Board Insertion
Servers
Capacitance Buffer/Bus Extender
Desktop Computer
■
■
■
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TYPICAL APPLICATIO
V
3.3V
CC
V
CC2
Input–Output Connection
0.01µF
0.01µF
10k
10k
3
10k
10k
8
1
INPUT
SIDE
150pF
OUTPUT
SIDE
50pF
2
7
SCLIN
SCLOUT
0.5V/DIV
6
SDAIN
SDAOUT
LTC4300A-3
5
ENABLE
OFF ON
GND
4
4300A-3 TA01
200ns/DIV
4300A TA02
sn4300a3 4300a3fs
1
LTC4300A-3
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ABSOLUTE AXI U RATI GS (Note 1)
Storage Temperature Range
VCC to GND .................................................... –0.3 to 7V
VCC2 to GND .................................................. –0.3 to 7V
SDAIN, SCLIN, SDAOUT, SCLOUT................. –0.3 to 7V
ENABLE ......................................................... –0.3 to 7V
Operating Temperature Range
MSOP ............................................... –65°C to 150°C
DFN .................................................. –65°C to 125°C
Lead Temperature (Soldering, 10 sec)
MSOP Only ....................................................... 300°C
LTC4300A-3C ......................................... 0°C to 70°C
LTC4300A-3I ...................................... –40°C to 85°C
U
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
ORDER PART
NUMBER
TOP VIEW
TOP VIEW
V
1
2
3
4
8
7
6
5
V
CC
CC2
LTC4300A-3CDD
LTC4300A-3IDD
LTC4300A-3CMS8
LTC4300A-3IMS8
V
1
2
3
4
8 V
CC
7 SDAOUT
6 SDAIN
SCLOUT
SCLIN
GND
SDAOUT
SDAIN
CC2
9
SCLOUT
SCLIN
GND
ENABLE
5 ENABLE
DD
MS8
PART MARKING
MS8 PACKAGE
8-LEAD PLASTIC MSOP
PART MARKING*
DD PACKAGE
8-LEAD (3mm × 3mm) PLASTIC DFN
TJMAX = 125°C, θJA = 200°C/W
LBHG
LBHG
LTBHD
LTBHF
TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 9) PCB CONNECTION IS OPTIONAL
Consult LTC marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER
Power Supply
CONDITIONS
MIN
TYP
MAX
UNITS
V
V
Positive Supply Voltage
●
●
2.7
2.7
5.5
5.5
V
V
CC
Card Side Supply Voltage
Supply Current in Shutdown Mode
CC2
I
I
I
V
V
V
= 0V
20
3
µA
mA
mA
SD
ENABLE
V
V
Supply Current
= V
= 0V, V
= V
= 5.5V
4.1
2.9
VCC1
VCC2
CC
SDAIN
SCLIN
CC1
CC2
Supply Current
= V
= 0V, V
= V = 5.5V
CC2
2.1
CC2
SDAOUT
SCLOUT
CC1
Start-Up Circuitry
V
Precharge Voltage
SDA, SCL Floating
●
●
0.8
50
1.0
95
1.2
V
µs
V
PRE
t
Bus Idle Time
150
IDLE
V
V
ENABLE Threshold Voltage
Disable Threshold Voltage
ENABLE Input Current
ENABLE Delay, On-Off
ENABLE Delay, Off-On
0.5 • V
0.5 • V
±0.1
10
0.9 • V
CC
EN
CC
ENABLE Pin
0.1 • V
V
DIS
CC
CC
I
t
t
ENABLE from 0V to V
±1
µA
ns
µs
EN
CC
PHL
PLH
95
sn4300a3 4300a3fs
2
LTC4300A-3
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specfications are at TA = 25°C. VCC = 2.7V to 5.5V, VCC2 = 2.7V to 5.5V, unless otherwise noted.
SYMBOL PARAMETER
Rise-Time Accelerators
CONDITIONS
MIN
TYP
MAX
UNITS
I
Transient Boosted Pull-Up Current
Positive Transition on SDA, SCL, V = 2.7V,
1
2
mA
PULLUPAC
CC
V
= 2.7V, Slew Rate = 1.25V/µs (Note 2)
CC2
Input-Output Connection
V
Input-Output Offset Voltage
10k to V on SDA, SCL, V = 3.3V (Note 3),
●
●
0
0
100
175
mV
OS
CC
CC
V
= 3.3V, V = 0.2V
CC2
IN
f
Operating Frequency
Guaranteed by Design, Not Subject to Test
Guaranteed by Design, Not Subject to Test
400
10
kHz
pF
V
SCL, SDA
C
V
Digital Input Capacitance
Output Low Voltage, Input = 0V
IN
SDA, SCL Pins, I
= 3mA, V = 2.7V,
0
0.4
OL
SINK
CC
V
= 2.7V
CC2
I
Input Leakage Current
SDA, SCL Pins = V = 5.5V, V
= 5.5V
±5
µA
LEAK
CC
CC2
Timing Characteristics
2
f
t
I C Operating Frequency
(Note 4)
(Note 4)
0
400
kHz
I2C
Bus Free Time Between Stop
and Start Condition
1.3
µs
BUF
t
Hold Time After (Repeated)
Start Condition
(Note 4)
0.6
µs
hD,STA
t
t
t
t
t
t
t
t
Repeated Start Condition Setup Time (Note 4)
0.6
0.6
µs
µs
ns
ns
µs
µs
ns
ns
su,STA
su,STO
hD, DAT
su, DAT
LOW
HIGH
f
Stop Condition Setup Time
Data Hold Time
(Note 4)
(Note 4)
300
Data Setup Time
(Note 4)
100
Clock Low Period
(Note 4)
1.3
Clock High Period
Clock, Data Fall Time
Clock, Data Rise Time
(Note 4)
0.6
(Notes 4, 5)
(Notes 4, 5)
20 + 0.1 • C
20 + 0.1 • C
300
300
B
r
B
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 4: Guaranteed by design, not subject to test.
Note 5: C = total capacitance of one bus line in pF.
B
Note 2: I
varies with temperature and V voltage, as shown in
PULLUPAC
CC
the Typical Performance Characteristics section.
Note 3: The connection circuitry always regulates its output to a higher
voltage than its input. The magnitude of this offset voltage as a function of
the pullup resistor and V voltage is shown in the Typical Performance
CC
Characteristics section.
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LTC4300A-3
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TYPICAL PERFOR A CE CHARACTERISTICS
Input–Output High to Low
Propagation Delay vs Temperature
IPULLUPAC vs Temperature
ICC vs Temperature
5.3
5.2
5.1
5.0
4.9
4.8
4.7
4.6
4.5
4.4
4.3
12
10
8
100
80
60
40
20
0
V
V
= 2.7V
= 3.3V
CC
CC
V
= 5.5V
CC
V
= 5V
CC
6
V
V
= 3V
V
CC
= 2.7V
V
= 5.5V
CC
CC
CC
4
2
C
= C
OUT
PULLUPIN
= 100pF
= R
= 2.7V
25
IN
R
= 10k
50
PULLUPOUT
25
TEMPERATURE (°C)
0
–50
–25
0
25
50
75
100
–50
–25
0
50
75
100
–50
–25
0
75
100
TEMPERATURE (°C)
TEMPERATURE (°C)
4300-3 G01
4300-3 G03
4300-3 G02
Connection Circuitry VOUT – VIN
ISD vs Temperature
35
30
25
20
15
10
5
300
250
200
150
100
50
T
= 25°C
IN
A
V
= 0V
V
= 5.5V
CC
V
= 5V
CC
V
= 3.3V
CC
V
= 2.7V
25
CC
0
0
50
100
–50 –25
0
75
0
10,000
20,000
(Ω)
30,000
40,000
R
TEMPERATURE (°C)
PULLUP
4300A G05
4300-3 G04
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4
LTC4300A-3
U
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PI FU CTIO S
VCC2 (Pin 1): Card Supply Voltage. This is the supply
voltage for the devices on the card I2C busses. Connect
pull-up resistors from SDAOUT and SCLOUT to this pin.
Placeabypasscapacitorofatleast0.01µFclosetothispin
for best results.
isolates SCLIN from SCLOUT. For active operation, drive
this pin to VCC. If this feature is unused, tie to VCC. Since
ENABLE is VCC referenced, do not connect to VCC2 or pull
up to VCC2
.
SDAIN (Pin 6): Serial Data Input. Connect this pin to the
SDA bus on the backplane.
SCLOUT (Pin 2): Serial Clock Output. Connect this pin to
the SCL bus on the card.
SDAOUT (Pin 7): Serial Data Output. Connect this pin to
the SDA bus on the card.
SCLIN (Pin 3): Serial Clock Input. Connect this pin to the
SCL bus on the backplane.
VCC (Pin 8): Main Input Power Supply from Backplane.
This is the supply voltage for the devices on the backplane
I2C busses. Connect pull-up resistors from SDAIN and
SCLIN to this pin. Place a bypass capacitor of at least
0.01µF close to this pin for best results.
GND (Pin 4): Device Ground. Connect this pin to a ground
plane for best results.
ENABLE(Pin5):DigitalCMOSThresholdInput. Ground-
ing this pin puts the part in a low current mode. It also
disables the rise-time accelerators, disables the bus
discharge circuitry, isolates SDAIN from SDOUT and
Exposed Pad (Pin 9, DFN Package Only): Exposed Pad
may by be left open or connected to device ground.
sn4300a3 4300a3fs
5
LTC4300A-3
W
BLOCK DIAGRA
2-Wire Bus Buffer and Hot SwapTM Controller
V
CC
8
2mA
2mA
1
V
CC2
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
SDAIN
6
7 SDAOUT
CONNECTION
CONNECT
CONNECT
CONNECT
100k
100k
100k
100k
1V
PRECHARGE
2mA
2mA
SLEW RATE
DETECTOR
SLEW RATE
DETECTOR
BACKPLANE-TO-CARD
CONNECTION
SCLIN
3
2
SCLOUT
– 1V
CONNECT
CONNECT
+
–
V
CC2
+
–
+
–
STOP BIT AND BUS IDLE
0.5µA
+
–
0.55V
/
CC
CC
20pF
0.45V
95µs
CONNECT CONNECT
UVLO
DELAY,
RISING
ONLY
RD
S
ENABLE
5
QB
4
GND
0.5pF
4300A-3 BD
Hot Swap is a trademark of Linear Technology Corporation.
sn4300a3 4300a3fs
6
LTC4300A-3
U
OPERATIO
Start-Up
Another key feature of the connection circuitry is that it
provides bidirectional buffering, keeping the backplane
and card capacitances isolated. Because of this isolation,
the waveforms on the backplane busses look slightly
different than the corresponding card bus waveforms, as
described here.
When the LTC4300A-3 first receives power on its VCC pin,
either during power-up or during live insertion, it starts in
an undervoltage lockout (UVLO) state, ignoring any activ-
ityontheSDAandSCLpinsuntilVCC risesabove2.5V.The
part also waits for VCC2 to rise above 2V. This ensures that
the part does not try to function until it has enough voltage
to do so.
Input to Output Offset Voltage
When a logic low voltage, VLOW1, is driven on any of the
LTC4300A-3’s data or clock pins, the LTC4300A-3 regu-
lates the voltage on the other side of the part (call it
During this time, the 1V precharge circuitry is also active
and forces 1V through 100k nominal resistors to the SDA
and SCL pins. Because the I/O card is being plugged into
alivebackplane,thevoltageonthebackplaneSDAandSCL
bussesmaybeanywherebetween0VandVCC.Precharging
the SCL and SDA pins to 1V minimizes the worst-case
voltagedifferentialthesepinswillseeatthemomentofcon-
nection, therefore minimizing the amount of disturbance
caused by the I/O card.
V
LOW2) to a slightly higher voltage, as directed by the
following equation (typical):
VLOW2 = VLOW1 + 75mV + (VCC/R) • 70 [Ω]
where R is the bus pull-up resistance in ohms. For ex-
ample, if a device is forcing SDAOUT to 10mV where
VCC =3.3Vandthepull-upresistorRonSDAINis10k,then
the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 70
= 108mV (typical). See the Typical Performance Charac-
teristics section for curves showing the offset voltage as
a function of VCC and R.
OncetheLTC4300A-3comesoutofUVLO, itassumesthat
SDAIN and SCLIN have been inserted into a live system
and that SDAOUT and SCLOUT are being powered up at
the same time as itself. Therefore, it looks for either a stop
bit or bus idle condition on the backplane side to indicate
the completion of a data transaction. When either one
occurs, the part also verifies that both the SDAOUT and
SCLOUT voltages are high. When all of these conditions
are met, the input-to-output connection circuitry is acti-
vated, joiningtheSDAandSCLbussesontheI/Ocardwith
those on the backplane, and the rise time accelerators are
enabled.
Propagation Delays
During a rising edge, the rise-time on each side is deter-
mined by the combined pull-up current of the LTC4300A-
3 boost current and the bus resistor and the equivalent
capacitance on the line. If the pull-up currents are the
same, a difference in rise-time occurs which is directly
proportional to the difference in capacitance between the
twosides.ThiseffectisdisplayedinFigure1forVCC =VCC2
=3.3Vanda10kpull-upresistoroneachside(50pFonone
side and 150pF on the other). Since the output side has
less capacitance than the input, it rises faster and the
effective propagation delay is negative.
Connection Circuitry
Once the connection circuitry is activated, the functional-
ityoftheSDAINandSDAOUTpinsisidentical.Alowforced
on either pin at any time results in both pin voltages being
low. For proper operation, logic low input voltages should
benohigherthan0.4Vwithrespecttothegroundpinvoltage
of the LTC4300A-3. SDAIN and SDAOUT enter a logic high
state only when all devices on both SDAIN and SDAOUT
releasehigh.ThesameistrueforSCLINandSCLOUT.This
importantfeatureensuresthatclockstretching,clocksyn-
chronization, arbitration and the acknowledge protocol al-
wayswork,regardlessofhowthedevicesinthesystemare
tied to the LTC4300A-3.
There is a finite propagation delay through the connection
circuitry for falling waveforms. Figure 2 shows the falling
edge waveforms for the same VCC, pull-up resistors and
equivalent capacitance conditions as used in Figure 1. An
external NMOS device pulls down the voltage on the side
with 150pF capacitance; the LTC4300A-3 pulls down the
voltage on the opposite side, with a delay of 55ns. This
delayisalwayspositiveandisafunctionofsupplyvoltage,
sn4300a3 4300a3fs
7
LTC4300A-3
U
OPERATIO
OUTPUT
SIDE
50pF
INPUT
SIDE
150pF
INPUT
SIDE
150pF
OUTPUT
SIDE
50pF
0.5V/DIV
0.5V/DIV
200ns/DIV
4300A-3 F01
200ns/DIV
4300A-3 F02
Figure 1. Input–Output Connection Low to High Transition
Figure 2. Input–Output Connection High to Low Transition
temperature and the pull-up resistors and equivalent bus
capacitances on both sides of the bus. The Typical Perfor-
mance Characteristics section shows tPHL as a function of
temperature and voltage for 10k pull-up resistors and
100pF equivalent capacitance on both sides of the part. By
comparison with Figure 2, the VCC = VCC2 = 3.3V curve
showsthatincreasingthecapacitancefrom50pFto100pF
results in a propagation delay increase from 55ns to 75ns.
Larger output capacitances translate to longer delays (up
to 150ns). Users must quantify the difference in propaga-
tion times for a rising edge versus a falling edge in their
systems and adjust setup and hold times accordingly.
For example, assume an SMBus system with VCC = 3V, a
10k pull-up resistor and equivalent bus capacitance of
200pF. The rise-time of an SMBus system is calculated
from (VIL(MAX) – 0.15V) to (VIH(MIN) + 0.15V), or 0.65V to
2.25V. It takes an RC circuit 0.92 time constants to
traverse this voltage for a 3V supply; in this case, 0.92 •
(10k • 200pF) = 1.84µs. Thus, the system exceeds the
maximum allowed rise-time of 1µs by 84%. However,
using the rise-time accelerators, which are activated at a
DC threshold of below 0.65V, the worst-case rise-time is:
(2.25V – 0.65V) • 200pF/1mA = 320ns, which meets the
1µs rise-time requirement.
Rise-Time Accelerators
ENABLE Low Current Disable
Onceconnectionhasbeenestablished,rise-timeaccelera-
tor circuits on all four SDA and SCL pins are activated.
TheseallowtheusertochooseweakerDCpull-upcurrents
on the bus, reducing power consumption while still meet-
ing system rise-time requirements. During positive bus
transitions, the LTC4300A-3 switches in 2mA (typical) of
current to quickly slew the SDA and SCL lines once their
DC voltages exceed 0.6V. Using a general rule of 20pF of
capacitance for every device on the bus (10pF for the
device and 10pF for interconnect), choose a pull-up cur-
rent so that the bus will rise on its own at a rate of at least
1.25V/µs to guarantee activation of the accelerators.
Grounding the ENABLE pin disconnects the backplane
side from the card side, disables the rise-time accelera-
tors, disablesthebusprechargecircuitryandputsthepart
in a near-zero current state. When the pin voltage is driven
all the way to VCC, the part waits for data transactions on
both the backplane and card sides to be complete (as
describedintheStart-Upsection)beforereconnectingthe
two sides.
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8
LTC4300A-3
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APPLICATIO S I FOR ATIO
Resistor Pull-Up Value Selection
Live Insertion and Capacitance Buffering Application
The system pull-up resistors must be strong enough to
provide a positive slew rate of 1.25V/µs on the SDA and
SCL pins, in order to activate the boost pull-up currents
during rising edges. Choose maximum resistor value R
using the formula:
Figures 3 and 4 illustrate the usage of the LTC4300A-3 in
applicationsthattakeadvantageofbothitsHotSwapcon-
trolling and capacitance buffering features. In all of these
applications, note that if the I/O cards were plugged di-
rectly into the backplane, all of the backplane and card ca-
pacitances would add directly together, making rise- and
fall-time requirements difficult to meet. Placing a
LTC4300A-3 on the edge of each card, however, isolates
the card capacitance from the backplane. For a given I/O
card,theLTC4300A-3drivesthecapacitanceofeverything
on the card and the backplane must drive only the capaci-
tance of the LTC4300A-3, which is less than 10pF.
R ≤ (VCC(MIN) – 0.6)(800,000)/C
where R is the pull-up resistor value in ohms, VCC(MIN) is
the minimum VCC voltage and C is the equivalent bus
capacitance in picofarads (pF).
In addition, regardless of the bus capacitance, always
choose R ≤ 16k for VCC = 5.5V maximum, R ≤ 24k for
VCC = 3.6Vmaximum.Thestart-upcircuitryrequireslogic
high voltages on SDAOUT and SCLOUT to connect the
backplanetothecard, andthesepull-upvaluesareneeded
to overcome the precharge voltage.
BACKPLANE
CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD 1
C1
V
CC2
R1
10k
R2
10k
0.01µF
R7
10k
R8
10k
V
CC2
SDAOUT
SCLOUT
ENABLE
CARD_SDA
CARD_SCL
V
V
CC
CC
SDAIN
SCLIN
LTC4300A-3
GND
SDA
SCL
C2 0.01µF
R3
10k
ENA1
I/O PERIPHERAL CARD 2
C3
R4
10k
R5
10k
0.01µF
V
CC2
SDAOUT
SCLOUT
ENABLE
CARD2_SDA
CARD2_SCL
V
CC
SDAIN
SCLIN
LTC4300A-3
GND
C4 0.01µF
R6
10k
ENA2
4300A-3 F03
Figure 3. The LTC4300A-3 in a PCI Application Where All the Pins Have the Same Length.
ENABLE Should be Held Low Until All Transients Associated with the Live Insertion Have Settled
sn4300a3 4300a3fs
9
LTC4300A-3
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APPLICATIO S I FOR ATIO
BACKPLANE
CONNECTOR
BACKPLANE
I/O PERIPHERAL CARD 1
C1
V
CC2
R1
10k
R2
0.01µF
R7
10k
R8
10k
10k
V
CC2
SDAOUT
SCLOUT
ENABLE
CARD_SDA
CARD_SCL
V
V
CC
CC
SDAIN
SCLIN
SDA
SCL
LTC4300A-3
GND
C2 0.01µF
R3
10k
ENA1
I/O PERIPHERAL CARD 2
C3
R4
10k
R5
10k
0.01µF
V
CC2
SDAOUT
SCLOUT
ENABLE
CARD2_SDA
CARD2_SCL
V
CC
LTC4300A-3
GND
SDAIN
SCLIN
C4 0.01µF
R6
10k
ENA2
4300A-3 F04
Figure 4. The LTC4300A-3 in a Custom Application. Making ENABLE the Shortest Pin Ensures that
VCC and VCC2 Connect Before ENABLE is Allowed to Go High, Connecting the Card to the Backplane
5V to 3.3V Level Translator and Power Supply
Redundancy
voltage magnitudes of VCC and VCC2 with respect to each
other.
Systems requiring different supply voltages for the
backplane side and the card side can use the LTC4300A-3,
asshowninFigure5.Thepull-upresistorsonthecardside
connect from SDAOUT to SCLOUT to VCC2, and those on
thebackplanesideconnectfromSDAINandSCLINtoVCC.
TheLTC4300A-3functionsforvoltagesrangingfrom2.7V
to5.5VonbothVCC andVCC2. Thereisnoconstraintonthe
This application also provides power supply redundancy.
If the VCC2 voltage falls below its UVLO threshold, the
LTC4300A-3 disconnects the backplane from the card, so
that the backplane can continue to function. If the VCC
voltage falls below its UVLO threshold and the VCC2
voltage remains active, hold ENABLE at ground to ensure
proper operation.
sn4300a3 4300a3fs
10
LTC4300A-3
U
PACKAGE DESCRIPTION
DD Package
8-Lead Plastic DFN (3mm × 3mm)
(Reference LTC DWG # 05-08-1698)
R = 0.115
0.38 ± 0.10
TYP
5
8
0.675 ±0.05
3.5 ±0.05
2.15 ±0.05 (2 SIDES)
1.65 ±0.05
3.00 ±0.10
(4 SIDES)
1.65 ± 0.10
(2 SIDES)
PIN 1
TOP MARK
(NOTE 6)
PACKAGE
OUTLINE
(DD8) DFN 1203
4
1
0.25 ± 0.05
0.75 ±0.05
0.200 REF
0.25 ± 0.05
0.50 BSC
0.50
BSC
2.38 ±0.05
(2 SIDES)
2.38 ±0.10
(2 SIDES)
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
NOTE:
1. DRAWING TO BE MADE A JEDEC PACKAGE OUTLINE M0-229 VARIATION OF (WEED-1)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON TOP AND BOTTOM OF PACKAGE
MS8 Package
8-Lead Plastic MSOP
(Reference LTC DWG # 05-08-1660)
3.00 ± 0.102
(.118 ± .004)
(NOTE 3)
0.52
(.0205)
REF
8
7 6
5
3.00 ± 0.102
(.118 ± .004)
(NOTE 4)
4.90 ± 0.152
(.193 ± .006)
DETAIL “A”
0.254
0.889 ± 0.127
(.035 ± .005)
(.010)
0° – 6° TYP
GAUGE PLANE
1
2
3
4
5.23
(.206)
MIN
0.53 ± 0.152
(.021 ± .006)
3.20 – 3.45
(.126 – .136)
1.10
(.043)
MAX
0.86
(.034)
REF
DETAIL “A”
0.18
(.007)
0.65
(.0256)
BSC
0.42 ± 0.038
SEATING
PLANE
(.0165 ± .0015)
TYP
0.22 – 0.38
0.127 ± 0.076
(.009 – .015)
(.005 ± .003)
RECOMMENDED SOLDER PAD LAYOUT
0.65
(.0256)
BSC
TYP
MSOP (MS8) 0204
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
sn4300a3 4300a3fs
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
11
LTC4300A-3
U
TYPICAL APPLICATIO S
V
CC
CARD_V , 3.3V
CC
5V
C2
0.01µF
C1
0.01µF
R3
10k
R2
10k
R1
10k
R4
10k
V
V
CC2
CC
SDAIN
SCLIN
SDAOUT
SCLOUT
CARD_SDA
CARD_SCL
SDA
SCL
LTC4300A-3
GND
4300A-3 F05
ENABLE
Figure 5. 5V to 3.3V Level Translator
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1380/LTC1393
Single-Ended 8-Channel/Differential 4-Channel Analog Low R : 35Ω Single-Ended/70Ω Differential,
ON
Mux with SMBus Interface
Expandable to 32 Single or 16 Differential Channels
LTC1427-50
Micropower, 10-Bit Current Output DAC
with SMBus Interface
Precision 50µA ± 2.5% Tolerance Over Temperature,
4 Selectable SMBus Addresses, DAC Powers up at Zero or Midscale
LTC1623
Dual High Side Switch Controller with SMBus Interface 8 Selectable Addresses/16-Channel Capability
LTC1663
SMBus Interface 10-Bit Rail-to-Rail Micropower DAC
SMBus Accelerator
DNL < 0.75LSB Max, 5-Lead SOT-23 Package
2
LTC1694/LTC1694-1
Improved SMBus/I C Rise-Time,
Ensures Data Integrity with Multiple SMBus/I C Devices
2
LT1786F
LTC1695
LTC1840
SMBus Controlled CCFL Switching Regulator
1.25A, 200kHz, Floating or Grounded Lamp Configurations
0.75Ω PMOS 180mA Regulator, 6-Bit DAC
TM
2
SMBus/I C Fan Speed Controller in ThinSOT
2
Dual I C Fan Speed Controller
Two 100µA 8-Bit DACs, Two Tach Inputs, Four GPI0
LTC4300A-1/LTC4300A-2 Hot Swappable 2-Wire Bus Buffer
Preserves Data integrity Under Hot Swap Conditions, Provides
Capacitive Buffering, Rise-Time Acceleration
LTC4301
Supply Independent 2-Wire Bus Buffer
Provides Capacitive Buffer, 3.3V to 5V Level Translation with Only
the Card Bus V Supply
CC
LTC4301L
Hot-Swappable 2-Wire Bus Buffer with Low Voltage
Level Translation
Level Translators, 1V Signals to Standard 3.3V and 5V Logic Rails
2
LTC4302-1/LTC4302-2
Addressable I C and SMBus Compatible Bus Buffers
Provides Capacitive Buffering, Rise-Time Acceleration, and Input to
Output Connection Control Using 2-Wire Bus Commands
ThinSOT is a trademark of Linear Technology Corporation.
sn4300a3 4300a3fs
LT/TP 0404 1K • PRINTED IN USA
12 LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
©LINEAR TECHNOLOGY CORPORATION 2004
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