LTC3890EGN-1PBF_技术文档

LTC3890-1

60V Low I ,

Q

Dual, 2-Phase Synchronous

Step-Down DC/DC Controller

DESCRIPTION

FEATURES

The LTC^®3890-1 is a high performance dual step-down

switching regulator DC/DC controller that drives all N-

channel synchronous power MOSFET stages. A constant

frequencycurrentmodearchitectureallowsaphase-lock-

able frequency of up to 850kHz. Power loss and supply

noiseareminimizedbyoperatingthetwocontrolleroutput

stages out-of-phase.

n

Wide V Range: 4V to 60V (65V Abs Max)

IN

n

Low Operating I : 50μA (One Channel On)

Q

Wide Output Voltage Range: 0.8V ≤ V

≤ 24V

OUT

R

or DCR Current Sensing

SENSE

Out-of-Phase Controllers Reduce Required Input

Capacitance and Power Supply Induced Noise

Phase-Lockable Frequency (75kHz to 850kHz)

Programmable Fixed Frequency (50kHz to 900kHz)

Selectable Continuous, Pulse Skipping or Low Ripple

Burst Mode^®Operation at Light Loads

n

The50ꢀAno-loadquiescentcurrentextendsoperatinglife

in battery-powered systems. OPTI-LOOP^®compensation

allows the transient response to be optimized over a wide

range of output capacitance and ESR values. A wide 4V

to 60V input supply range encompasses a wide range of

intermediate bus voltages and battery chemistries.

n

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Output Voltage Soft-Start or Tracking

Power Good Output Voltage Monitor

Output Overvoltage Protection

Independent TRACK/SS pins for each controller ramp the

output voltages during start-up. Current foldback limits

MOSFET heat dissipation during short-circuit conditions.

ThePLLIN/MODEpinselectsamongBurstModeoperation,

pulse skipping mode, or continuous conduction mode at

light loads.

Low Shutdown I : <14μA

Internal LDO Powers Gate Drive from V or EXTV

No Current Foldback During Start-Up

Narrow SSOP Package

Q

IN

CC

APPLICATIONS

Foraleadless32-pinQFNpackagewithadditionalfeatures

of adjustable current limit, clock out, phase modulation

and two PGOOD outputs, see the LTC3890 data sheet.

L, LT, LTC, LTM, Linear Technology, Burst Mode, OPTI-LOOP and the Linear logo are

registered trademarks of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents including 5481178, 5705919,

5929620, 6100678, 6144194, 6177787, 6304066, 6580258, 7230497.

n

Automotive Always-On Systems

Battery Operated Digital Devices

n

Distributed DC Power Systems

TYPICAL APPLICATION

Efﬁciency and Power Loss

vs Output Current (Buck)

High Efﬁciency Dual 8.5V/3.3V Output Step-Down Converter

V

IN

9V TO 60V

10000

1000

100

90

80

70

60

50

40

30

20

22μF

4.7μF

V

= 12V

IN

OUT

= 3.3V

V

INTV

CC

IN

TG1

TG2

0.1μF

BOOST1

SW1

BOOST2

SW2

4.7μH

8μH

BG1

BG2

LTC3890-1

PGND

10

+

SENSE1

SENSE2

1

0.01Ω

0.008Ω

10

0

–

V

8.5V

3A

SENSE2

OUT2

V

OUT1

3.3V

5A

V

0.1

10

FB1

FB2

0.0001 0.001

0.01

0.1

1

100k

470μF

100k

10.5k

ITH1

ITH2

OUTPUT CURRENT (A)

1000pF

34.8k

1000pF

34.8k

330μF

TRACK/SS1 SGND TRACK/SS2

0.1μF

38901 TA01b

31.6k

0.1μF

38901 TA01

38901f

1

LTC3890-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Input Supply Voltage (V )......................... –0.3V to 65V

IN

Topside Driver Voltages

1

TRACK/SS1

PGOOD1

TG1

28

ITH1

2

3

27

26

25

24

23

22

21

20

19

18

17

16

15

V

FB1

BOOST1, BOOST2 ................................. –0.3V to 71V

Switch Voltage (SW1, SW2) ........................ –5V to 65V

(BOOST1-SW1), (BOOST2-SW2) ................ –0.3V to 6V

RUN1, RUN2 ............................................... –0.3V to 8V

Maximum Current Sourced into Pin from

+

SENSE1

–

4

SW1

SENSE1

5

BOOST1

BG1

FREQ

PLLIN/MODE

SGND

6

7

V

IN

Source >8V.......................................................100μA

8

PGND

RUN1

+

–

+

–

SENSE1 , SENSE2 , SENSE1

9

EXTV

CC

RUN2

SENSE2 Voltages...................................... –0.3V to 28V

–

10

11

12

13

14

INTV

CC

SENSE2

PLLIN/MODE, FREQ Voltages .............. –0.3V to INTV

+

CC

BG2

SENSE2

EXTV ...................................................... –0.3V to 14V

CC

BOOST2

SW2

V

FB2

ITH1, ITH2, V , V Voltages................... –0.3V to 6V

FB1 FB2

ITH2

PGOOD1 Voltage ......................................... –0.3V to 6V

TRACK/SS1, TRACK/SS2 Voltages .............. –0.3V to 6V

Operating Junction Temperature Range

(Note 2) ................................................. –40°C to 125°C

Maximum Junction Temperature (Note 3) ............ 125°C

Storage Temperature Range................... –65°C to 150°C

TG2

TRACK/SS2

GN PACKAGE

28-LEAD PLASTIC SSOP

T

= 125°C, θ = 90°C/W

JA

JMAX

ORDER INFORMATION

LEAD FREE FINISH

LTC3890EGN-1#PBF

LTC3890IGN-1#PBF

TAPE AND REEL

PART MARKING*

LTC3890GN-1

PACKAGE DESCRIPTION

28-Lead Plastic SSOP

TEMPERATURE RANGE

–40°C to 125°C

LTC3890EGN-1#TRPBF

LTC3890IGN-1#TRPBF

–40°C to 125°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based ﬁnish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_J= 25°C. V_IN= 12V, V_RUN1,2= 5V, EXTV_CC= 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Supply Operating Voltage Range

Regulated Feedback Voltage

4

60

V

IN

I

Voltage = 1.2V (Note 4)

FB1,2

TH1,2

–40°C to 125°C

–40°C to 85°C

l

0.788

0.792

0.800

0.812

0.808

V

I

Feedback Current

(Note 4)

5

50

nA

FB1,2

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 4.5V to 60V (Note 4)

0.002

0.02

%/V

REFLNREG

LOADREG

IN

(Note4)

l

Measured in Servo Loop,

0.01

0.1

%

Δ

Voltage = 1.2V to 0.7V

ITH

(Note4)

Measured in Servo Loop,

–0.01

–0.1

%

Δ

Voltage = 1.2V to 2V

ITH

38901f

2

LTC3890-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_J= 25°C. V_IN= 12V, V_RUN1,2= 5V, EXTV_CC= 0V unless otherwise noted.

SYMBOL

PARAMETER

CONDITIONS

= 1.2V, Sink/Source = 5μA (Note 4)

MIN

TYP

MAX

UNITS

g

Transconductance Ampliﬁer g

Input DC Supply Current

I

TH1,2

2

mmho

m1,2

m

I

(Note 5)

Q

Pulse Skip or Forced Continuous Mode RUN1 = 5V and RUN2 = 0V or

(One Channel On) RUN1 = 0V and RUN2 = 5V,

= 0.83V (No Load)

2

mA

V

FB1

Pulse Skip or Forced Continuous Mode RUN1,2 = 5V, V

(Both Channels On)

= 0.83V (No Load)

2

mA

μA

FB1,2

Sleep Mode (One Channel On)

RUN1 = 5V and RUN2 = 0V or

RUN1 = 0V and RUN2 = 5V,

50

75

V

= 0.83V (No Load)

FB1

Sleep Mode (Both Channels On)

Shutdown

RUN1,2 = 5V, V

RUN1,2 = 0V

= 0.83V (No Load)

60

14

100

25

μA

FB1,2

l

UVLO

Undervoltage Lockout

INTV Ramping Up

4.0

3.8

4.2

4.0

V

CC

INTV Ramping Down

3.6

7

CC

V

OVL

Feedback Overvoltage Protection

Measured at V

Each Channel

, Relative to Regulated V

FB1,2 FB1,2

10

13

1

%

+

–

+

I

SENSE Pin Current

μA

SENSE

–

SENSE Pins Current

Each Channel

–

V

SENSE

V

SENSE

< INTV – 0.5V

1

μA

CC

> INTV + 0.5V

700

99

CC

DF

Maximum Duty Factor

In Dropout

= 0V

98

%

MAX

I

Soft-Start Charge Current

V

0.7

1.0

1.4

μA

TRACK/SS1,2

TRACK1,2

l

V

On

RUN1 Pin On Threshold

RUN2 Pin On Threshold

V

RUN1

V

RUN2

Rising

1.15

1.20

1.21

1.25

1.27

1.30

V

RUN1

RUN2

V

Hyst RUN Pin Hysteresis

50

75

mV

RUN1,2

l

Maximum Current Sense Threshold

V

FB1,2

= 0.7V, V

–, – = 3.3V, I = 0

64

85

SENSE(MAX)

SENSE1

2

LIM

Gate Driver

TG1,2

Pull-Up On-Resistance

Pull-Down On-Resistance

2.5

1.5

ꢁ

BG1,2

Pull-Up On-Resistance

Pull-Down On-Resistance

2.4

1.1

ꢁ

TG Transition Time:

Rise Time

Fall Time

(Note 6)

TG1,2 t

C

= 3300pF

25

ns

r

f

LOAD

= 3300pF

BG Transition Time:

Rise Time

Fall Time

(Note 6)

LOAD

BG1,2 t

C

= 3300pF

25

ns

r

f

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

= 3300pF Each Driver

30

95

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

C

= 3300pF Each Driver

1D

LOAD

t

Minimum On-Time

(Note 7)

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

6V < V < 60V, V = 0V

EXTVCC

4.85

5.1

0.7

5.1

5.35

1.1

V

%

V

INTVCCVIN

LDOVIN

CC

IN

INTV Load Regulation

I

CC

= 0mA to 50mA, V

= 0V

CC

EXTVCC

Internal V Voltage

6V < V < 13V

EXTVCC

5.35

INTVCCEXT

CC

38901f

3

LTC3890-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the speciﬁcations which apply over the full operating

junction temperature range, otherwise speciﬁcations are at T_J= 25°C. V_IN= 12V, V_RUN1,2= 5V, EXTV_CC= 0V unless otherwise noted.

SYMBOL

PARAMETER

INTV Load Regulation

CONDITIONS

= 0mA to 50mA, V

MIN

TYP

0.6

MAX

1.1

UNITS

%

V

I

CC

= 8.5V

EXTVCC

LDOEXT

EXTVCC

LDOHYS

CC

EXTV Switchover Voltage

EXTV Ramping Positive

4.5

4.7

4.9

V

CC

EXTV Hysteresis

250

mV

CC

Oscillator and Phase-Locked Loop

f

Programmable Frequency

Low Fixed Frequency

R

= 25k, PLLIN/MODE = DC Voltage

= 65k, PLLIN/MODE = DC Voltage

= 105k, PLLIN/MODE = DC Voltage

= 0V, PLLIN/MODE = DC Voltage

105

440

835

350

535

kHz

25kꢁ

65kꢁ

105kꢁ

LOW

FREQ

375

505

V

320

485

75

380

585

850

High Fixed Frequency

= INTV , PLLIN/MODE = DC Voltage

CC

HIGH

SYNC

l

Synchronizable Frequency

PLLIN/MODE = External Clock

PGOOD1 Output

V

PGOOD1 Voltage Low

PGOOD1 Leakage Current

PGOOD1 Trip Level

I

= 2mA

= 5V

0.2

0.4

1

V

PGL

PGOOD

I

V

μA

PGOOD

V

with Respect to Set Regulated Voltage

Ramping Negative

PG

FB

–13

7

–10

2.5

–7

13

%

Hysteresis

V

with Respect to Set Regulated Voltage

Ramping Positive

FB

10

2.5

%

Hysteresis

t

Delay for Reporting a Fault

25

μs

PG

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Ratings for extended periods may affect device reliability and

lifetime.

Note 4: The LTC3890-1 is tested in a feedback loop that servos V

to

ITH1,2

a speciﬁed voltage and measures the resultant V . The speciﬁcation at

FB1,2

85°C is not tested in production. This speciﬁcation is assured by design,

characterization and correlation to production testing at 125°C.

Note 2: The LTC3890E-1 is guaranteed to meet performance speciﬁcations

from 0°C to 125°C. Speciﬁcations over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3890I-1 is guaranteed

over the full –40°C to 125°C operating junction temperature range.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See Applications information.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The minimum on-time condition is speciﬁed for an inductor peak-

Note 3: T is calculated from the ambient temperature T and power

J

A

to-peak ripple current ≥ of I

(See Minimum On-Time Considerations in

MAX

dissipation P according to the following formula:

D

the Applications Information section).

T = T + (P • 90°C/W)

J

A

D

38901f

4

LTC3890-1

TYPICAL PERFORMANCE CHARACTERISTICS

Efﬁciency and Power Loss

vs Output Current

Efﬁciency vs Output Current

Efﬁciency vs Input Voltage

100

98

96

94

92

90

88

86

84

10000

1000

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

V

= 12V

IN

OUT

V

= 8.5V

BURST EFFICIENCY

OUT

= 3.3V

V

= 3.3V

OUT

V

= 8.5V

OUT2

CCM LOSS

BURST LOSS

PULSE-SKIPPING

LOSS

V

= 3.3V

10

OUT1

CCM EFFICIENCY

1

Burst Mode OPERATION

PULSE-SKIPPING

EFFICIENCY

82

80

10

0

10

0

I

= 2A

V

= 12V

LOAD

IN

0.1

10

0

5

10 15 20 25 30 35 40 45 50 55 60

INPUT VOLTAGE (V)

0.0001 0.001

0.01

OUTPUT CURRENT (A)

FIGURE 13 CIRCUIT

0.1

1

10

0.0001 0.001

0.01

0.1

1

OUTPUT CURRENT (A)

38901 G03

38901 G02

38901 G01

FIGURE 13 CIRCUIT

Load Step

Burst Mode Operation

Load Step

Pulse-Skipping Mode

Load Step

Forced Continuous Mode

V

OUT

100mV/DIV

AC-

100mV/DIV

AC-

100mV/DIV

AC-

COUPLED

I

L

I

L

2A/DIV

38901 G04

38901 G05

38901 G06

50μs/DIV

V

= 12V

V

= 12V

V

= 12V

IN

OUT

IN

OUT

IN

OUT

= 3.3V

FIGURE 13 CIRCUIT

Inductor Current at Light Load

Soft Start-Up

Tracking Start-Up

FORCED

CONTINUOUS

MODE

V

OUT2

2V/DIV

Burst Mode

OPERATION

1A/DIV

V

OUT1

2V/DIV

PULSE-SKIPPING

MODE

38901 G09

38901 G08

38901 G07

2ms/DIV

FIGURE 13 CIRCUIT

2ms/DIV

FIGURE 13 CIRCUIT

5μs/DIV

V

LOAD

= 12V

IN

= 3.3V

OUT

I

= 200μA

38901f

5

LTC3890-1

TYPICAL PERFORMANCE CHARACTERISTICS

Total Input Supply Current

vs Input Voltage

EXTV_CCSwitchover and INTV_CC

Voltages vs Temperature

INTV_CCLine Regulation

5.2

300

250

200

150

100

6.0

5.8

5.6

5.4

5.2

5.0

4.8

4.6

4.4

4.2

4.0

5.1

5.0

4.9

4.8

INTV

CC

300μA

EXTV RISING

CC

EXTV FALLING

CC

NO LOAD

50

0

5

10 15 20 25 30 35 40 45 50 55 60 65

–45

5

30

55

80 105 130

5

10 15 20 25 30 35 40 45 50 55 60 65

–20

INPUT VOLTAGE (V)

TEMPERATURE (°C)

38901 G12

38901 G10

38901 G11

Maximum Current Sense Voltage

vs I_THVoltage

Maximum Current Sense

Threshold vs Duty Cycle

SENSE^–Pin Input Bias Current

80

60

40

20

0

90

85

80

75

70

65

60

–100

–200

–300

–400

–500

–600

–700

–800

PULSE SKIPPING MODE

Burst Mode

OPERATION

0

–20

–40

FORCED CONTINUOUS MODE

0.8

(V)

1.2

1.4

0

0.2

0.4 0.6

V

1.0

0

10

15

20

25

5

0

10 20 30 40 50 60 70 80 90 100

INPUT VOLTAGE (V)

ITH

DUTY CYCLE (%)

38901 G13

38901 G14

38901 G15

Foldback Current Limit

Quiescent Current vs Temperature

INTV_CCvs Load Current

5.20

5.15

5.10

80

70

60

50

40

30

20

10

0

V

= 12V

IN

75

70

65

60

55

50

45

EXTV = 0V

CC

5.05

5.00

4.95

EXTV = 8.5V

CC

40

0

20 40 60 80 100 120 140 160 180 200

–20

5

55

80 105 130

–45

30

0

100 200 300 400 500 600 700 800

FEEDBACK VOLTAGE (MV)

3890 G16

LOAD CURRENT (mA)

TEMPERATURE (°C)

38901 G18

38901 G17

38901f

6

LTC3890-1

TYPICAL PERFORMANCE CHARACTERISTICS

Regulated Feedback Voltage

vs Temperature

TRACK/SS Pull-Up Current

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

800

1.10

1.05

1.00

0.95

1.40

1.35

806

804

1.30

1.25

1.20

1.15

1.10

1.05

1.00

RUN1 RISING

RUN2 RISING

802

800

798

796

794

RUN1 FALLING

RUN2 FALLING

792

0.90

–20

5

55

80 105 130

–45

30

–45 –20

5

30

55

80 105 130

55

TEMPERATURE (°C)

105 130

–45 –20

5

30

80

TEMPERATURE (°C)

38901 G21

38901 G19

38901 G20

SENSE^–Pin Total Input Bias Current

vs Temperature

Shutdown Current vs Input

Voltage

Oscillator Frequency

vs Temperature

50

0

600

550

500

450

30

25

20

15

10

5

V

< INTV – 0.5V

CC

–50

OUT

FREQ = INTV

CC

–100

–150

–200

–250

–300

–350

–400

–450

–500

–550

–600

–650

–700

–750

–800

400

350

300

FREQ = GND

V

> INTV – 0.5V

CC

OUT

0

55

TEMPERATURE (°C)

105 130

–45 –25 –5 15 35 55 75 95 115

–45 –20

5

30

80

5

10 15 20 25 30 35 40 45 50 55 60 65

TEMPERATURE (°C)

INPUT VOLTAGE (V)

38901 G22

38901 G23

38901 G24

Undervoltage Lockout Threshold

vs Temperature

Oscillator Frequency vs Input

Voltage

Shutdown Current vs Temperature

4.4

22

20

18

356

354

352

350

348

V

= 12V

FREQ = GND

IN

4.3

4.2

4.1

4.0

3.9

3.8

3.7

3.6

3.5

3.4

RISING

16

14

12

10

8

FALLING

346

344

–45

5

30

55

80 105 130

–45 –20

5

30

55

80 105 130

–20

5

10 15 20 25 30 35 40 45 50 55 60 65

TEMPERATURE (°C)

INPUT VOLTAGE (V)

38901 G27

38901 G26

38901 G25

38901f

7

LTC3890-1

PIN FUNCTIONS

ITH1, ITH2 (Pin 1, Pin 13): Error Ampliﬁer Outputs and

Switching Regulator Compensation Points. Each associ-

ated channel’s current comparator trip point increases

with this control voltage.

atlightloads.PullingthispintogroundselectsBurstMode

operation. An internal 100k resistor to ground also invokes

Burst Mode Operation when the pin is ﬂoated. Tying this

pintoINTV forcescontinuousinductorcurrentoperation.

CC

Tying this pin to a voltage greater than 1.2V and less than

V

, V (Pin 2, Pin 12): Receives the remotely sensed

FB1 FB2

INTV – 1.3V selects pulse skipping operation.

CC

feedback voltage for each controller from an external

resistive divider across the output.

SGND (Pin 7): Small-signal ground common to both

controllers, must be routed separately from high current

+

SENSE1 , SENSE2 (Pin 3, Pin 11): The (+) input to the

differential current comparators are normally connected

to DCR sensing networks or current sensing resistors.

The ITH pin voltage and controlled offsets between the

grounds to the common (–) terminals of the C capaci-

IN

tors.

RUN1, RUN2 (Pin 8, Pin 9): Digital Run Control Inputs for

Each Controller. Forcing either of these pins below 1.2V

shuts down that controller. Forcing both of these pins

below 0.7V shuts down the entire LTC3890-1, reducing

quiescent current to approximately 14μA.

–

+

SENSE and SENSE pins in conjunction with R

the current trip threshold.

set

SENSE

–

SENSE1 , SENSE2 (Pin 4, Pin 10): The (–) Input to the

Differential Current Comparators. When greater than

–

INTV – 0.5V, the SENSE pin supplies current to the

INTV (Pin19):OutputoftheInternalLinearLowDropout

CC

current comparator.

Regulator. The driver and control circuits are powered

from this voltage source. Must be decoupled to power

ground with a minimum of 4.7μF ceramic or other low

FREQ (Pin 5): The Frequency Control Pin for the Internal

VCO. Connecting the pin to GND forces the VCO to a ﬁxed

ESR capacitor. Do not use the INTV pin for any other

CC

low frequency of 350kHz. Connecting the pin to INTV

CC

purpose.

forces the VCO to a ﬁxed high frequency of 535kHz.

Other frequencies between 50kHz and 900kHz can be

programmed using a resistor between FREQ and GND.

An internal 20μA pull-up current develops the voltage to

be used by the VCO to control the frequency.

EXTV (Pin 20): External Power Input to an Internal LDO

CC

Connected to INTV . This LDO supplies INTV power,

CC

bypassing the internal LDO powered from V whenever

IN

EXTV is higher than 4.7V. See EXTV Connection in

CC

the Applications Information section. Do not exceed 14V

PLLIN/MODE (Pin 6): External Synchronization Input to

PhaseDetectorandForcedContinuousModeInput.When

an external clock is applied to this pin, the phase-locked

loop will force the rising TG1 signal to be synchronized

with the rising edge of the external clock. When not syn-

chronizing to an external clock, this input, which acts on

bothcontrollers,determineshowtheLTC3890-1operates

on this pin.

PGND (Pin 21): Driver Power Ground. Connects to the

sources of bottom (synchronous) N-channel MOSFETs

and the (–) terminal(s) of C .

IN

V (Pin 22): Main Supply Pin. A bypass capacitor should

IN

be tied between this pin and the signal ground pin.

38901f

8

LTC3890-1

PIN FUNCTIONS

BG1, BG2 (Pin 23, Pin 18): High Current Gate Drives for

PGOOD1 (Pin 27): Open-Drain Logic Output. PGOOD1 is

Bottom (Synchronous) N-Channel MOSFETs. Voltage

pulled to ground when the voltage on the V pin is not

FB1

swing at these pins is from ground to INTV .

within 10% of its set point.

CC

BOOST1,BOOST2(Pin24,Pin17):BootstrappedSupplies

to the Topside Floating Drivers. Capacitors are connected

betweentheBOOSTandSWpinsandSchottkydiodesare

tied between the BOOST and INTV_CCpins. Voltage swing

at the BOOST pins is from INTV_CCto (V_IN+ INTV_CC).

TRACK/SS1, TRACK/SS2 (Pin 28, Pin 14): External

Tracking and Soft-Start Input. The LTC3890-1 regulates

the V

voltage to the smaller of 0.8V or the voltage

FB1,2

on the TRACK/SS1,2 pin. An internal 1μA pull-up current

source is connected to this pin. A capacitor to ground at

this pin sets the ramp time to ﬁnal regulated output volt-

age. Alternatively, a resistor divider on another voltage

supply connected to this pin allows the LTC3890-1 output

to track the other supply during start-up.

SW1, SW2 (Pin 25, Pin 16): Switch Node Connections

to Inductors.

TG1, TG2 (Pin 26, Pin 15): High Current Gate Drives for

Top N-Channel MOSFETs. These are the outputs of ﬂoat-

ing drivers with a voltage swing equal to INTV – 0.5V

CC

superimposed on the switch node voltage SW.

38901f

9

LTC3890-1

FUNCTIONAL DIAGRAM

INTV

V

IN

CC

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

BOOST

D

B

C

B

TG

DROP

OUT

DET

TOP

BOT

+

C

IN

PGOOD1

0.88V

D

BOT

–

SW

TOP ON

V

S

R

Q

FB1

+

INTV

CC

Q

–

SWITCH

LOGIC

0.72V

BG

SHDN

C

OUT

PGND

20μA

FREQ

V

OUT

VCO

CLK2

CLK1

+

–

R

SENSE

0.425V

SLEEP

L

ICMP

IR

–

+

–

PFD

C

LP

+

–

+

3mV

SENSE

SYNC

DET

2.7V

0.65V

PLLIN/MODE

–

100k

SLOPE COMP

V

FB

R

B

+

V

IN

0.80V

TRACK/SS

EA

–

R

A

EXTV

CC

+

–

OV

C

0.88V

ITH

5.1V

LDO

EN

5.1V

LDO

EN

7μA (RUN1)

0.5μA (RUN2)

SHDN

RST

FB

C

C2

R

C

FOLDBACK

1μA

TRACK/SS

+

–

2(V

)

4.7V

11V

C

SHDN

SS

38901 FD

SGND

INTV

RUN

CC

38901f

10

LTC3890-1

OPERATION ^{(Refer to the Functional Diagram)}

Main Control Loop

Shutdown and Start-Up (RUN1, RUN2 and

TRACK/ SS1, TRACK/SS2 Pins)

The LTC3890-1 uses a constant frequency, current mode

step-down architecture with the two controller channels

operating 180 degrees out of phase. During normal op-

eration, each external top MOSFET is turned on when the

clock for that channel sets the RS latch, and is turned off

when the main current comparator, ICMP, resets the RS

latch. The peak inductor current at which ICMP trips and

resets the latch is controlled by the voltage on the ITH pin,

which is the output of the error ampliﬁer, EA. The error

ampliﬁer compares the output voltage feedback signal at

The two channels of the LTC3890-1 can be independently

shut down using the RUN1 and RUN2 pins. Pulling either

ofthesepinsbelow1.2Vshutsdownthemaincontrolloop

for that controller. Pulling both pins below 0.7V disables

both controllers and most internal circuits, including the

INTV LDOs. In this state, the LTC3890-1 draws only

CC

14μA of quiescent current.

Releasing either RUN pin allows a small internal current to

pull up the pin to enable that controller. The RUN1 pin has a

7μApull-upcurrentwhiletheRUN2pinhasasmaller0.5μA.

The 7μA current on RUN1 is designed to be large enough

so that the RUN1 pin can be safely ﬂoated (to always en-

able the controller) without worry of condensation or other

small board leakage pulling the pin down. This is ideal for

always-on applications where one or both controllers are

enabled continuously and never shut down.

the V pin, (which is generated with an external resistor

FB

divider connected across the output voltage, V , to

OUT

ground) to the internal 0.800V reference voltage. When

the load current increases, it causes a slight decrease

in V relative to the reference, which causes the EA to

FB

increase the ITH voltage until the average inductor current

matches the new load current.

After the top MOSFET is turned off each cycle, the bot-

tom MOSFET is turned on until either the inductor current

starts to reverse, as indicated by the current comparator

IR, or the beginning of the next clock cycle.

The RUN pin may be externally pulled up or driven directly

by logic. When driving the RUN pin with a low impedance

source, do not exceed the absolute maximum rating of

8V. The RUN pin has an internal 11V voltage clamp that

allows the RUN pin to be connected through a resistor to a

INTV /EXTV Power

CC

higher voltage (for example, V ), solongasthemaximum

IN

Power for the top and bottom MOSFET drivers and most

current into the RUN pin does not exceed 100μA.

other internal circuitry is derived from the INTV pin.

CC

The start-up of each controller’s output voltage V

is

When the EXTV pin is left open or tied to a voltage less

OUT

CC

controlled by the voltage on the TRACK/SS pin for that

channel. When the voltage on the TRACK/SS pin is less

than the 0.8V internal reference, the LTC3890-1 regulates

than 4.7V, the V LDO (low dropout linear regulator) sup-

IN

plies 5.1V from V to INTV . If EXTV is taken above

IN

CC

4.7V, the V LDO is turned off and an EXTV LDO is

IN

CC

the V voltage to the TRACK/SS pin voltage instead of

turned on. Once enabled, the EXTV LDO supplies 5.1V

FB

CC

the 0.8V reference. This allows the TRACK/SS pin to be

used to program a soft-start by connecting an external

capacitor from the TRACK/SS pin to SGND. An internal

1μA pull-up current charges this capacitor creating a

voltage ramp on the TRACK/SS pin. As the TRACK/SS

voltage rises linearly from 0V to 0.8V (and beyond up to

from EXTV to INTV . Using the EXTV pin allows

CC

the INTV power to be derived from a high efﬁciency

CC

external source such as one of the LTC3890-1 switching

regulator outputs.

Each top MOSFET driver is biased from the ﬂoating boot-

strap capacitor C , which normally recharges during each

B

5V), the output voltage V

its ﬁnal value.

rises smoothly from zero to

OUT

cycle through an external diode when the top MOSFET

turns off. If the input voltage, V , decreases to a voltage

IN

Alternatively the TRACK/SS pin can be used to cause the

start-up of V to track that of another supply. Typically,

close to V , the loop may enter dropout and attempt

OUT

to turn on the top MOSFET continuously. The dropout

detector detects this and forces the top MOSFET off for

about one-twelfth of the clock period every tenth cycle to

OUT

this requires connecting to the TRACK/SS pin an external

resistor divider from the other supply to ground (see Ap-

plications Information section).

allow C to recharge.

B

38901f

11

LTC3890-1

OPERATION ^{(Refer to the Functional Diagram)}

Light Load Current Operation (Burst Mode Operation,

Pulse Skipping, or Forced Continuous Mode)

(PLLIN/MODE Pin)

preventing it from reversing and going negative. Thus,

the controller operates in discontinuous operation.

In forced continuous operation or clocked by an external

clock source to use the phase-locked loop (see Frequency

Selection and Phase-Locked Loop section), the induc-

tor current is allowed to reverse at light loads or under

large transient conditions. The peak inductor current

is determined by the voltage on the ITH pin, just as in

normal operation. In this mode, the efﬁciency at light

loads is lower than in Burst Mode operation. However,

continuous operation has the advantage of lower output

voltage ripple and less interference to audio circuitry. In

forced continuous mode, the output ripple is independent

of load current.

The LTC3890-1 can be enabled to enter high efﬁciency

Burst Mode operation, constant frequency pulse skipping

mode, or forced continuous conduction mode at low load

currents. To select Burst Mode operation, tie the PLLIN/

MODE pin to a DC voltage below 0.8V (e.g., SGND). To

select forced continuous operation, tie the PLLIN/MODE

pin to INTV . To select pulse-skipping mode, tie the

CC

PLLIN/MODE pin to a DC voltage greater than 1.2V and

less than INTV – 1.3V.

CC

WhenacontrollerisenabledforBurstModeoperation,the

minimum peak current in the inductor is set to approxi-

mately 25% of the maximum sense voltage even though

the voltage on the ITH pin indicates a lower value. If the

average inductor current is higher than the load current,

the error ampliﬁer, EA, will decrease the voltage on the

ITH pin. When the ITH voltage drops below 0.425V, the

internal sleep signal goes high (enabling sleep mode)

and both external MOSFETs are turned off. The ITH pin is

then disconnected from the output of the EA and parked

at 0.450V.

WhenthePLLIN/MODEpinisconnectedforpulseskipping

mode, the LTC3890-1 operates in PWM pulse skipping

mode at light loads. In this mode, constant frequency

operation is maintained down to approximately 1% of

designed maximum output current. At ver y light loads, the

current comparator, ICMP, may remain tripped for several

cycles and force the external top MOSFET to stay off for

the same number of cycles (i.e., skipping pulses). The

inductor current is not allowed to reverse (discontinuous

operation). This mode, like forced continuous operation,

exhibits low output ripple as well as low audio noise and

reduced RF interference as compared to Burst Mode

operation. It provides higher low current efﬁciency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

In sleep mode, much of the internal circuitry is turned off,

reducing the quiescent current that the LTC3890-1 draws.

If one channel is shut down and the other channel is in

sleep mode, the LTC3890-1 draws only 50μA of quiescent

current.Ifbothchannelsareinsleepmode,theLTC3890-1

draws only 60μA of quiescent current. In sleep mode,

the load current is supplied by the output capacitor. As

the output voltage decreases, the EA’s output begins to

rise. When the output voltage drops enough, the ITH pin

is reconnected to the output of the EA, the sleep signal

goes low, and the controller resumes normal operation

by turning on the top external MOSFET on the next cycle

of the internal oscillator.

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efﬁciency and component size. Low frequency operation

increases efﬁciency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

When a controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

current comparator, IR, turns off the bottom external

MOSFET just before the inductor current reaches zero,

The switching frequency of the LTC3890-1’s controllers

can be selected using the FREQ pin.

38901f

12

LTC3890-1

OPERATION ^{(Refer to the Functional Diagram)}

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to SGND, tied to

INTV_CCor programmed through an external resistor.

Tying FREQ to SGND selects 350kHz while tying FREQ

to INTV_CCselects 535kHz. Placing a resistor between

FREQ and SGND allows the frequency to be programmed

between 50kHz and 900kHz, as shown in Figure 10.

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

Power Good (PGOOD1 Pin)

ThePGOOD1pinisconnectedtoanopendrainofaninternal

N-channel MOSFET. The MOSFET turns on and pulls the

PGOOD1 pin low when the corresponding V pin volt-

FB1

age is not within 10% of the 0.8V reference voltage. The

A phase-locked loop (PLL) is available on the LTC3890-1

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC3890-1’s phase detector adjusts the voltage (through

an internal lowpass ﬁlter) of the VCO input to align the

turn-on of controller 1’s external top MOSFET to the ris-

ing edge of the synchronizing signal. Thus, the turn-on of

controller 2’s external top MOSFET is 180 degrees out of

phase to the rising edge of the external clock source.

PGOOD1 pin is also pulled low when the corresponding

RUN1 pin is low (shut down). When the V pin voltage

FB1

is within the 10% requirement, the MOSFET is turned

off and the pin is allowed to be pulled up by an external

resistor to a source no greater than 6V.

Foldback Current

When the output voltage falls to less than 70% of its

nominal level, foldback current limiting is activated, pro-

gressively lowering the peak current limit in proportion to

the severity of the overcurrent or short-circuit condition.

Foldback current limiting is disabled during the soft-start

The VCO input voltage is prebiased to the operating fre-

quency set by the FREQ pin before the external clock is

applied. A resistor connected between the FREQ pin and

SGND can prebias VCO’s input voltage to the desired

frequency. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG1. The ability to

prebias the loop ﬁlter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

interval (as long as the V voltage is keeping up with the

FB

TRACK/SS voltage).

Theory and Beneﬁts of 2-Phase Operation

Why the need for 2-phase operation? Up until the 2-phase

family, constant-frequency dual switching regulators

operated both channels in phase (i.e., single phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

inputcapacitorandbattery. Theselargeamplitudecurrent

pulses increased the total RMS current ﬂowing from the

input capacitor, requiring the use of more expensive input

capacitorsandincreasingbothEMIandlossesintheinput

capacitor and battery.

The typical capture range of the phase-locked loop is

from approximately 55kHz to 1MHz, with a guarantee

to be between 75kHz and 850kHz. In other words, the

LTC3890-1’s PLL is guaranteed to lock to an ex ternal clock

source whose frequency is between 75kHz and 850kHz.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.2V (falling).

Output Overvoltage Protection

With 2-phase operation, the two channels of the dual

switchingregulatorareoperated180degreesoutofphase.

Thiseffectivelyinterleavesthecurrentpulsesdrawnbythe

switches,greatlyreducingtheoverlaptimewheretheyadd

Anovervoltagecomparatorguardsagainsttransientover-

shoots as well as other more serious conditions that may

overvoltage the output. When the V pin rises by more

FB

than 10% above its regulation point of 0.800V, the top

38901f

13

LTC3890-1

OPERATION ^{(Refer to the Functional Diagram)}

together. The result is a signiﬁcant reduction in total RMS

input current, which in turn allows less expensive input

capacitors to be used, reduces shielding requirements for

EMI and improves real world operating efﬁciency.

It can readily be seen that the advantages of 2-phase

operation are not just limited to a narrow operating range,

formostapplicationsisthat2-phaseoperationwillreduce

theinputcapacitorrequirementtothatforjustonechannel

operating at maximum current and 50% duty cycle.

Figure1comparestheinputwaveformsforarepresentative

single-phase dual switching regulator to the LTC3890-1

2-phase dual switching regulator. An actual measure-

ment of the RMS input current under these conditions

shows that 2-phase operation dropped the input current

The schematic on the ﬁrst page is a basic LTC3890-1 ap-

plication circuit. External component selection is driven

by the load requirement, and begins with the selection of

R

and the inductor value. Next, the power MOSFETs

SENSE

from 2.53A

to 1.55A

. While this is an impressive

are selected. Finally, C and C

are selected

RMS

IN

OUT

reduction in itself, remember that the power losses are

2

proportional to I

, meaning that the actual power

RMS

3.0

wasted is reduced by a factor of 2.66. The reduced input

ripple voltage also means less power is lost in the input

power path, which could include batteries, switches,

trace/connector resistances and protection circuitry.

Improvements in both conducted and radiated EMI also

directly accrue as a result of the reduced RMS input cur-

rent and voltage.

SINGLE PHASE

DUAL CONTROLLER

2.5

2.0

1.5

1.0

0.5

0

2-PHASE

DUAL CONTROLLER

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

V

= 5V/3A

O1

O2

= 3.3V/3A

0

10

20

30

40

INPUT VOLTAGE (V)

38901 F02

voltage V (Duty Cycle = V /V ). Figure 2 shows how

IN

OUT IN

the RMS input current varies for single phase and 2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

Figure 2. RMS Input Current Comparison

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

38901 F01

I

= 2.53A

I

= 1.55A

IN(MEAS) RMS

IN(MEAS)

RMS

Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators

Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows

Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efﬁciency

38901f

14

LTC3890-1

APPLICATIONS INFORMATION

The Typical Application on the ﬁrst page is a basic

LTC3890-1 application circuit. LTC3890-1 can be conﬁg-

uredtouseeitherDCR(inductorresistance)sensingorlow

valueresistorsensing.Thechoicebetweenthetwocurrent

sensing schemes is largely a design trade-off between

cost, power consumption, and accuracy. DCR sensing

is becoming popular because it saves expensive current

sensing resistors and is more power efﬁcient, especially

in high current applications. However, current sensing

resistors provide the most accurate current limits for the

controller. Other external component selection is driven

by the load requirement, and begins with the selection of

programmed current limit unpredictable. If inductor DCR

sensing is used (Figure 4b), sense resistor R1 should be

placed close to the switching node, to prevent noise from

coupling into sensitive small-signal nodes.

TO SENSE FILTER,

NEXT TO THE CONTROLLER

C

OUT

38901 F03

INDUCTOR OR R

SENSE

Figure 3. Sense Lines Placement with Inductor or Sense Resistor

R

(if R

is used) and inductor value. Next, the

SENSE

V

powerMOSFETsandSchottkydiodesareselected.Finally,

input and output capacitors are selected.

IN

INTV

CC

BOOST

TG

+

–

SENSE and SENSE Pins

R

SENSE

SW

V

OUT

+

–

The SENSE and SENSE pins are the inputs to the cur-

rent comparators. The common mode voltage range on

these pins is 0V to 28V (abs max), enabling the LTC3857

to regulate output voltages up to a nominal 24V (allowing

margin for tolerances and transients).

LTC3890-1

BG

+

SENSE

PLACE CAPACITOR NEAR

SENSE PINS

–

SENSE

SGND

+

The SENSE pin is high impedance over the full common

38901 F04a

mode range, drawing at most 1μA. This high impedance

allows the current comparators to be used in inductor

DCR sensing.

(4a) Using a Resistor to Sense Current

V

INTV

V

IN

–

The impedance of the SENSE pin changes depending on

CC

–

the common mode voltage. When SENSE is less than

INDUCTOR

DCR

BOOST

TG

INTV – 0.5V, a small current of less than 1μA ﬂows out

CC

L

–

of the pin. When SENSE is above INTV + 0.5V, a higher

SW

V

OUT

CC

LTC3890-1

current (~700μA) ﬂows into the pin. Between INTV

CC

BG

– 0.5V and INTV + 0.5V, the current transitions from

CC

R1

C1* R2

the smaller current to the higher current.

+

SENSE

Filter components mutual to the sense lines should be

placed close to the LTC3890-1, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 3). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

–

SENSE

SGND

38901 F04b

R2

R1 + R2

L

DCR

||

(R1 R2) • C1 =

*PLACE C1 NEAR

SENSE PINS

R

= DCR

SENSE(EQ)

(4b) Using the Inductor DCR to Sense Current

Figure 4. Current Sensing Methods

38901f

15

LTC3890-1

APPLICATIONS INFORMATION

Low Value Resistor Current Sensing

If the external (R1||R2) • C1 time constant is chosen to be

exactlyequaltotheL/DCRtimeconstant, thevoltagedrop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external ﬁlter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature; consult the

manufacturers’ data sheets for detailed information.

A typical sensing circuit using a discrete resistor is shown

in Figure 4a. R

output current.

is chosen based on the required

SENSE

The current comparator has a maximum threshold

. The current comparator threshold voltage

V

SENSE(MAX)

sets the peak of the inductor current, yielding a maximum

average output current, I

, equal to the peak value less

MAX

half the peak-to-peak ripple current, ΔI . To calculate the

L

sense resistor value, use the equation:

Using the inductor ripple current value from the Inductor

Value Calculation section, the target sense resistor value

is:

V_SENSE(MAX)

R_SENSE

=

ΔI_L

2

I_MAX

+

V_SENSE(MAX)

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimumvaluefortheMaximumCurrentSenseThreshold

R_SENSE(EQUIV)

=

ΔI_L

I_MAX

+

2

(V

).

SENSE(MAX)

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimumvaluefortheMaximumCurrentSenseThreshold

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due

to the internal compensation required to meet stability

criterion for buck regulators operating at greater than

50% duty factor. A curve is provided in the Typical Perfor-

mance Characteristics section to estimate this reduction

in peak inductor current depending upon the operating

duty factor.

(V

).

SENSE(MAX)

Next, determine the DCR of the inductor. When provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefﬁcient of copper resistance, which is approximately

0.4%/°C. A conservative value for T

is 100°C.

L(MAX)

Inductor DCR Sensing

To scale the maximum inductor DCR to the desired sense

resistor value (R ), use the divider ratio:

D

For applications requiring the highest possible efﬁciency

at high load currents, the LTC3890-1 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 4b. The DCR of the inductor represents the small

amount of DC resistance of the copper wire, which can be

lessthan1mꢁfortoday’slowvalue,highcurrentinductors.

In a high current application requiring such an inductor,

power loss through a sense resistor would cost several

points of efﬁciency compared to inductor DCR sensing.

R_SENSE(EQUIV)

R_D=

DCR_MAXatT

L(MAX)

C1 is usually selected to be in the range of 0.1μF to 0.47μF.

This forces R1|| R2 to around 2k, reducing error that might

+

have been caused by the SENSE pin’s 1μA current.

38901f

16

LTC3890-1

APPLICATIONS INFORMATION

The equivalent resistance R1|| R2 is scaled to the room

temperature inductance and maximum DCR:

Accepting larger values of ΔI allows the use of low

L

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

L

setting ripple current is ΔI =0.3(I

L

). The maximum

R1||R2 =

L

MAX

DCR at 20°C •C1

(

)

ΔI occurs at the maximum input voltage.

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

The sense resistor values are:

R1•R_D

1–R_D

R1||R2

R_D

R1=

; R2 =

25% of the current limit determined by R

. Lower

SENSE

inductor values (higher ΔI ) will cause this to occur at

L

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

lower load currents, which can cause a dip in efﬁciency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

V

_IN(MAX)– V_OUT• V

(

R1=

)

OUT

P

LOSS

Inductor Core Selection

R1

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

af ford the core loss found in low cost powdered iron cores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

ﬁxedinductorvalue,butitisverydependentoninductance

value selected. As inductance increases, core losses go

down. Unfortunately, increasedinductance requires more

turns of wire and therefore copper losses will increase.

Ensure that R1 has a power rating higher than this value.

If high efﬁciency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor, due

totheextraswitchinglossesincurredthroughR1.However,

DCRsensingeliminatesasenseresistor, reducesconduc-

tion losses and provides higher efﬁciency at heavy loads.

Peak efﬁciency is about the same with either method.

Ferrite designs have very low core loss and are preferred

for high switching frequencies, so design goals can

concentrate on copper loss and preventing saturation.

Ferrite core material saturates hard, which means that

inductance collapses abruptly when the peak design

current is exceeded. This results in an abrupt increase

in inductor ripple current and consequent output voltage

ripple. Do not allow the core to saturate!

Inductor Value Calculation

The operating frequency and inductor selection are inter-

relatedinthathigheroperatingfrequenciesallowtheuseof

smallerinductorandcapacitorvalues.Sowhywouldanyone

ever choose to operate at lower frequencies with larger

components? The answer is efﬁciency. A higher frequency

generally results in lower efﬁciency because of MOSFET

switching and gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

Power MOSFET and Schottky Diode

(Optional) Selection

Two external power MOSFETs must be selected for each

controller in the LTC3890-1: one N-channel MOSFET for

the top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

The inductor value has a direct effect on ripple current. The

inductor ripple current, ΔI , decreases with higher induc-

L

tance or higher frequency and increases with higher V :

IN

ꢁ

ꢄ

V

IN

1

^OUTꢆ

1–

_OUTꢃ

ꢀI_L=

V

f L

( )( )

ꢂ

ꢅ

38901f

17

LTC3890-1

APPLICATIONS INFORMATION

The peak-to-peak drive levels are set by the INTV

where δ is the temperature dependency of R

and

CC

DS(ON)

voltage. This voltage is typically 5.1V during start-up

R

(approximately 2ꢁ) is the effective driver resistance

DR

(see EXTV Pin Connection). Consequently, logic-level

at the MOSFET’s Miller threshold voltage. V

typical MOSFET minimum threshold voltage.

is the

THMIN

CC

threshold MOSFETs must be used in most applications.

Pay close attention to the BV

MOSFETs as well.

speciﬁcation for the

2

DSS

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

Selection criteria for the power MOSFETs include the

on-resistance,R ,Millercapacitance,C ,input

which are highest at high input voltages. For V < 20V

IN

the high current efﬁciency generally improves with larger

DS(ON)

MILLER

voltage and maximum output current. Miller capacitance,

MOSFETs, while for V > 20V the transition losses rapidly

IN

C

, can be approximated from the gate charge curve

increasetothepointthattheuseofahigherR

device

DS(ON)

MILLER

usually provided on the MOSFET manufacturers’ data

sheet. C is equal to the increase in gate charge

withlowerC

actually provides higher ef ﬁciency. The

MILLER

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

MILLER

along the horizontal axis while the curve is approximately

ﬂat divided by the speciﬁed change in V . This result is

DS

then multiplied by the ratio of the application applied V

DS

to the Gate charge curve speciﬁed V . When the IC is

DS

The term (1+ δ) is generally given for a MOSFET in the

operating in continuous mode the duty cycles for the top

form of a normalized R

vs Temperature curve, but

DS(ON)

and bottom MOSFETs are given by:

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

V_OUT

Main Switch Duty Cycle =

V

The optional Schottky diodes D3 and D4 shown in

Figure 11 conduct during the dead-time between the

conduction of the two power MOSFETs. This prevents

the body diode of the bottom MOSFET from turning on,

storing charge during the dead-time and requiring a

reverse recovery period that could cost as much as 3%

IN

V − V_OUT

IN

Synchronous Switch Duty Cycle =

V

IN

The MOSFET power dissipations at maximum output

current are given by:

in efﬁciency at high V . A 1A to 3A Schottky is generally

IN

V_OUT

2

a good compromise for both regions of operation due

to the relatively small average current. Larger diodes

result in additional transition losses due to their larger

junction capacitance.

P_MAIN

=

I

1+ ꢀ R

+

DS(ON)

(

_MAX) (

)

V

IN

₂ꢁ

ꢃ

ꢂ

ꢄ

ꢆ

ꢅ

I_MAX

2

V

R

C

•

(

)

(

_DR)(

)

IN

MILLER

C and C

Selection

ꢇ

ꢉ

ꢈ

ꢊ

IN

OUT

1

+

f

( )

ꢌ

The selection of C is simpliﬁed by the 2-phase architec-

V

_INTVCC– V_THMINV_THMIN

IN

ꢋ

ture and its impact on the worst-case RMS current drawn

through the input network (battery/fuse/capacitor). It can

beshownthattheworst-casecapacitorRMScurrentoccurs

when only one controller is operating. The controller with

V – V_OUT

2

IN

P_SYNC

=

I

1+ ꢀ R

(

_MAX) (

)

DS(ON)

V

IN

the highest (V )(I ) product needs to be used in the

OUT OUT

formula shown in Equation 1 to determine the maximum

38901f

18

LTC3890-1

APPLICATIONS INFORMATION

RMS capacitor current requirement. Increasing the out-

put current drawn from the other controller will actually

decrease the input RMS ripple current from its maximum

value. The out-of-phase technique typically reduces the

input capacitor’s RMS ripple current by a factor of 30%

to 70% when compared to a single phase power supply

solution.

1cm of each other and share a common C (s). Separating

IN

the drains and C may produce undesirable voltage and

IN

current resonances at V .

IN

A small (0.1μF to 1μF) bypass capacitor between the chip

V

pin and ground, placed close to the LTC3890-1, is

IN

also suggested. A 10ꢁ resistor placed between C (C1)

IN

and the V pin provides further isolation between the

two channels.

IN

Incontinuousmode,thesourcecurrentofthetopMOSFET

is a square wave of duty cycle (V )/(V ). To prevent

OUT

IN

The selection of C

is driven by the effective series

OUT

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

resistance (ESR). Typically, once the ESR requirement

is satisﬁed, the capacitance is adequate for ﬁltering. The

output ripple (ΔV ) is approximated by:

OUT

1/2

⎦

I_MAX

⎡

⎤

ꢂ

ꢅ

ꢇ

ꢆ

(1)

C_INRequired I_RMS

≈

V

V – V

IN OUT

1

(

_OUT)(

)

⎣

ꢀV_OUTꢁ ꢀI ESR+

_Lꢄ

V

IN

8 • f • C_OUT

ꢃ

This formula has a maximum at V = 2V , where I

IN

OUT

RMS

where f is the operating frequency, C

is the output

OUT

= I /2. This simple worst-case condition is commonly

OUT

capacitance and ΔI is the ripple current in the inductor.

L

used for design because even signiﬁcant deviations do not

offermuchrelief.Notethatcapacitormanufacturers’ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operatingfrequencyoftheLTC3890-1,ceramiccapacitors

The output ripple is highest at maximum input voltage

since ΔI increases with input voltage.

L

Setting Output Voltage

The LTC3890-1 output voltages are each set by an exter-

nal feedback resistor divider carefully placed across the

output, asshowninFigure5. Theregulatedoutputvoltage

is determined by:

can also be used for C . Always consult the manufacturer

IN

if there is any question.

ꢀ

ꢃ

R

R_A

V_OUT= 0.8V 1+

ꢂ

^Bꢅ

The beneﬁt of the LTC3890-1 2-phase operation can be

calculatedbyusingEquation1forthehigherpowercontrol-

ler and then calculating the loss that would have resulted

if both controller channels switched on at the same time.

The total RMS power lost is lower when both controllers

are operating due to the reduced overlap of current pulses

required through the input capacitor’s ESR. This is why

the input capacitor’s requirement calculated above for the

worst-case controller is adequate for the dual controller

design. Also, the input protection fuse resistance, battery

resistance, and PC board trace resistance losses are also

reduced due to the reduced peak currents in a 2-phase

system. The overall beneﬁt of a multiphase design will

only be fully realized when the source impedance of the

power supply/battery is included in the efﬁciency testing.

The drains of the top MOSFETs should be placed within

ꢁ

ꢄ

To improve the frequency response, a feedforward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

V

OUT

R

C

FF

1/2 LTC3890-1

V

B

A

FB

R

38901 F05

Figure 5. Setting Output Voltage

38901f

19

LTC3890-1

APPLICATIONS INFORMATION

Tracking and Soft-Start (TRACK/SS Pins)

V

X(MASTER)

OUT(SLAVE)

The start-up of each V

is controlled by the voltage on

OUT

the respective TRACK/SS pin. When the voltage on the

TRACK/SS pin is less than the internal 0.8V reference, the

LTC3890-1 regulates the V pin voltage to the voltage on

FB

the TRACK/SS pin instead of 0.8V. The TRACK/SS pin can

be used to program an external soft-start function or to

allow V

to track another supply during start-up.

OUT

38901 F07a

TIME

Soft-start is enabled by simply connecting a capacitor

from the TRACK/SS pin to ground, as shown in Figure 6.

An internal 1μA current source charges the capacitor,

providing a linear ramping voltage at the TRACK/SS pin.

(7a) Coincident Tracking

V

X(MASTER)

OUT(SLAVE)

The LTC3890-1 will regulate the V pin (and hence V

)

FB

OUT

according to the voltage on the TRACK/SS pin, allowing

V

to rise smoothly from 0V to its ﬁnal regulated value.

OUT

The total soft-start time will be approximately:

0.8V

1μA

t_SS= C_SS

•

38901 F07b

TIME

1/2 LTC3890-1

TRACK/SS

(7b) Ratiometric Tracking

C

SS

Figure 7. Two Different Modes of Output Voltage Tracking

SGND

38901 F06

V

OUT

x

Figure 6. Using the TRACK/SS Pin to Program Soft-Start

1/2 LTC3890-1

R

B

A

V

FB

Alternatively, the TRACK/SS pin can be used to track two

(or more) supplies during start-up, as shown qualitatively

in Figures 7a and 7b. To do this, a resistor divider should

R

TRACKB

TRACKA

TRACK/SS

38901 F08

be connected from the master supply (V ) to the TRACK/

X

SS pin of the slave supply (V ), as shown in Figure 8.

OUT

During start-up V

will track V according to the ratio

OUT

X

Figure 8. Using the TRACK/SS Pin for Tracking

set by the resistor divider:

INTV Regulators

R

_TRACKA+R_TRACKB

V_X

R_A

CC

=

•

V_OUTR_TRACKA

R_A+R_B

= V during start-up):

The LTC3890-1 features two separate internal P-channel

low dropout linear regulators (LDO) that supply power

For coincident tracking (V

R = R

OUT

X

at the INTV pin from either the V supply pin or the

CC

IN

EXTV pin depending on the connection of the EXTV

CC

A

TRACKA

TRACKB

pin. INTV powers the gate drivers and much of the

CC

R = R

B

LTC3890-1’sinternalcircuitry.TheV LDOandtheEXTV

IN

CC

38901f

20

LTC3890-1

APPLICATIONS INFORMATION

LDO regulate INTV to 5.1V. Each of these can supply a

switching regulator outputs (4.7V ≤ V_OUT≤ 14V) during

normal operation and from the V_INLDO when the out-

put is out of regulation (e.g., start-up, short-circuit). If

more current is required through the EXTV_CCLDO than

is speciﬁed, an external Schottky diode can be added

between the EXTV_CCand INTV_CCpins. In this case, do

not apply more than 6V to the EXTV_CCpin and make sure

that EXTV_CC≤ V_IN.

CC

peak current of 50mA and must be bypassed to ground

with a minimum of 4.7μF ceramic capacitor. No matter

what type of bulk capacitor is used, an additional 1μF

ceramic capacitor placed directly adjacent to the INTV

CC

and PGND IC pins is highly recommended. Good bypassing

is needed to supply the high transient currents required

by the MOSFET gate drivers and to prevent interaction

between the channels.

Signiﬁcant efﬁciency and thermal gains can be realized

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3890-1 to

by powering INTV from the output, since the V cur-

CC

IN

rent resulting from the driver and control currents will be

scaled by a factor of (Duty Cycle)/(Switcher Efﬁciency).

For 5V to 14V regulator outputs, this means connecting

the EXTV pin directly to V . Tying the EXTV pin to

be exceeded. The INTV current, which is dominated by

CC

the gate charge current, may be supplied by either the V

IN

CC

OUT

CC

LDO or the EXTV LDO. When the voltage on the EXT-

an 8.5V supply reduces the junction temperature in the

previous example from 125°C to:

CC

V

CC

pin is less than 4.7V, the V LDO is enabled. Power

IN

dissipation for the IC in this case is highest and is equal

to V • I . The gate charge current is dependent

T = 70°C + (15mA)(8.5V)(90°C/W) = 82°C

J

IN

INTVCC

However, for 3.3V and other low voltage outputs, addi-

on operating frequency as discussed in the Efﬁciency

Considerations section. The junction temperature can be

estimated by using the equations given in Note 3 of the

Electrical Characteristics. For example, the LTC3890-1

tional circuitry is required to derive INTV power from

CC

the output.

The following list summarizes the four possible connec-

INTV current is limited to less than 15mA from a 40V

CC

tions for EXTV :

CC

supply when not using the EXTV supply at 70°C ambi-

CC

1. EXTV Left Open (or Grounded). This will cause

CC

ent temperature:

INTV to be powered from the internal 5.1V regulator

CC

T = 70°C + (15mA)(40V)(90°C/W) = 125°C

J

resulting in an efﬁciency penalty of up to 10% at high

input voltages.

To prevent the maximum junction temperature from be-

ing exceeded, the input supply current must be checked

while operating in forced continuous mode (PLLIN/MODE

2. EXTV Connected directly to V . This is the normal

CC

OUT

connection for a 5V to 14V regulator and provides the

= INTV ) at maximum V .

CC

IN

highest efﬁciency.

When the voltage applied to EXTV rises above 4.7V, the

CC

3. EXTV Connected to an External supply. If an exter-

CC

V LDO is turned off and the EXTV LDO is enabled. The

IN

CC

nal supply is available in the 5V to 14V range, it may

EXTV LDO remains on as long as the voltage applied to

CC

be used to power EXTV providing it is compatible

CC

EXTV remains above 4.5V. The EXTV LDO attempts

CC

withtheMOSFETgatedriverequirements. Ensurethat

to regulate the INTV voltage to 5.1V, so while EXTV

CC

EXTV < V .

CC

IN

is less than 5.1V, the LDO is in dropout and the INTV

4. EXTV ConnectedtoanOutput-DerivedBoostNetwork.

CC

voltage is approximately equal to EXTV . When EXTV

CC

For 3.3V and other low voltage regulators, efﬁciency

is greater than 5.1V, up to an absolute maximum of 14V,

gains can still be realized by connecting EXTV to an

CC

INTV is regulated to 5.1V.

CC

output-derivedvoltagethathasbeenboostedtogreater

Using the EXTV_CCLDO allows the MOSFET driver and

control power to be derived from one of the LTC3890-1’s

than 4.7V. This can be done with the capacitive charge

pump shown in Figure 9. Ensure that EXTV < V .

CC

IN

38901f

21

LTC3890-1

APPLICATIONS INFORMATION

output voltage falls below 70% of its nominal output level,

thenthemaximumsensevoltageisprogressivelylowered

from 100% to 45% of its maximum selected value. Under

short-circuit conditions with very low duty cycles, the

LTC3890-1 will begin cycle skipping in order to limit the

short-circuit current. In this situation the bottom MOSFET

willbedissipatingmostofthepowerbutlessthaninnormal

operation.Theshort-circuitripplecurrentisdeterminedby

C

IN

BAT85

V

IN

MTOP

MBOT

NDS7002

TG1

1/2 LTC3890-1

L

R

SENSE

V

EXTV

SW

OUT

CC

theminimumon-time.t

,oftheLTC3890-1(≈90ns),

ON(MIN)

C

OUT

D

BG1

the input voltage and inductor value:

38901 F09

PGND

ꢁ

ꢄ

V

L

_ON(MIN)ꢃ ^INꢆ

ꢀI_L(SC)= t

ꢂ

ꢅ

Figure 9. Capacitive Charge Pump for EXTV_CC

The resulting average short-circuit current is:

Topside MOSFET Driver Supply (C , D )

B

1

2

I

_SC= 45% •I_LIM(MAX)– ꢀI_L(SC)

Externalbootstrapcapacitors,C ,connectedtotheBOOST

B

pinssupplythegatedrivevoltagesforthetopsideMOSFETs.

Capacitor C in the Functional Diagram is charged though

B

Fault Conditions: Overvoltage Protection (Crowbar)

external diode D from INTV when the SW pin is low.

B

CC

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

muchhigherthannominallevels.Thecrowbarcauseshuge

currents to ﬂow, that blow the fuse to protect against a

shorted top MOSFET if the short occurs while the control-

ler is operating.

When one of the topside MOSFETs is to be turned on, the

driver places the C voltage across the gate-source of the

B

desired MOSFET. This enhances the top MOSFET switch

and turns it on. The switch node voltage, SW, rises to V

IN

and the BOOST pin follows. With the topside MOSFET on,

the boost voltage is above the input supply: V = V

BOOST

IN

+ V

. The value of the boost capacitor, C , needs

INTVCC

B

A comparator monitors the output for overvoltage condi-

tions. The comparator detects faults greater than 10%

above the nominal output voltage. When this condition

is sensed, the top MOSFET is turned off and the bottom

MOSFET is turned on until the overvoltage condition is

cleared. The bottom MOSFET remains on continuously

to be 100 times that of the total input capacitance of the

topsideMOSFET(s).Thereversebreakdownoftheexternal

Schottky diode must be greater than V

.

IN(MAX)

When adjusting the gate drive level, the ﬁnal arbiter is the

total input current for the regulator. If a change is made

and the input current decreases, then the efﬁciency has

improved. If there is no change in input current, then there

is no change in efﬁciency.

for as long as the overvoltage condition persists; if V

OUT

returns to a safe level, normal operation automatically

resumes.

AshortedtopMOSFETwillresultinahighcurrentcondition

which will open the system fuse. The switching regulator

will regulate properly with a leaky top MOSFET by altering

the duty cycle to accommodate the leakage.

Fault Conditions: Current Limit and Current Foldback

The LTC3890-1 includes current foldback to help limit

load current when the output is shorted to ground. If the

38901f

22

LTC3890-1

APPLICATIONS INFORMATION

Phase-Locked Loop and Frequency Synchronization

1000

900

800

700

600

500

400

300

200

100

0

The LTC3890-1 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass ﬁlter,

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET of controller 1 to be locked to

the rising edge of an external clock signal applied to the

PLLIN/MODEpin.Theturn-onofcontroller2’stopMOSFET

is thus 180 degrees out of phase with the external clock.

The phase detector is an edge sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kΩ)

38901 F10

Figure 10. Relationship Between Oscillator Frequency

and Resistor Value at the FREQ Pin

If the external clock frequency is greater than the inter-

nal oscillator’s frequency, f , then current is sourced

OSC

continuously from the phase detector output, pulling up

the VCO input. When the external clock frequency is less

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

than f , current is sunk continuously, pulling down the

OSC

VCO input. If the external and internal frequencies are the

same but exhibit a phase difference, the current sources

turn on for an amount of time corresponding to the phase

difference. The voltage at the VCO input is adjusted until

the phase and frequency of the internal and external oscil-

latorsareidentical.Atthestableoperatingpoint,thephase

detector output is high impedance and the internal ﬁlter

capacitor, CLP, holds the voltage at the VCO input.

Table 2 summarizes the different states in which the FREQ

pin can be used.

Table 2

FREQ PIN

PLLIN/MODE PIN

DC Voltage

FREQUENCY

350kHz

0V

INTV

DC Voltage

535kHz

CC

Resistor

DC Voltage

50kHz to 900kHz

Any of the Above

External Clock

Phase Locked to

External Clock

Note that the LTC3890-1 can only be synchronized to

an external clock whose frequency is within range of

the LTC3890-1’s internal VCO, which is nominally 55kHz

to 1MHz. This is guaranteed to be between 75kHz and

850kHz.

Minimum On-Time Considerations

Minimum on-time, t , is the smallest time dura-

ON(MIN)

tion that the LTC3890-1 is capable of turning on the top

MOSFET. Itisdeterminedbyinternaltimingdelaysandthe

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

Typically, the external clock (on the PLLIN/MODE pin)

input high threshold is 1.6V, while the input low threshold

is 1.1V.

RapidphaselockingcanbeachievedbyusingtheFREQpin

to set a free-running frequency near the desired synchro-

nization frequency. The VCO’s input voltage is prebiased

at a frequency corresponding to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase lock and synchro-

nization. Although it is not required that the free-running

frequency be near external clock frequency, doing so will

V_OUT

V f

_IN( )

t_ON(MIN)

<

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

38901f

23

LTC3890-1

APPLICATIONS INFORMATION

Theminimumon-timefortheLTC3890-1isapproximately

90ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases up to about TBDns.

This is of particular concern in forced continuous applica-

tions with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a signiﬁcant amount of cycle skipping can occur with

correspondingly larger current and voltage ripple.

SupplyingINTV fromanoutput-derivedsourcepower

CC

through EXTV will scale the V current required

CC

IN

for the driver and control circuits by a factor of (Duty

Cycle)/(Efﬁciency). Forexample, ina20Vto5Vapplica-

tion, 10mA of INTV current results in approximately

CC

2.5mA of V current. This reduces the midcurrent loss

IN

from 10% or more (if the driver was powered directly

from V ) to only a few percent.

IN

2

3. I R losses are predicted from the DC resistances of the

Efﬁciency Considerations

fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current ﬂows through L and

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

R

, but is chopped between the topside MOSFET

SENSE

and the synchronous MOSFET. If the two MOSFETs

have approximately the same R

, then the resis-

DS(ON)

tance of one MOSFET can simply be summed with the

2

resistances of L, R

and ESR to obtain I R losses.

SENSE

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

For example, if each R

= 30mꢁ, R = 50mꢁ,

= 40mꢁ (sum of both input

DS(ON)

L

where L1, L2, etc. are the individual losses as a percent-

age of input power.

R

SENSE

= 10mꢁ and R

ESR

andoutputcapacitancelosses),thenthetotalresistance

is 130mꢁ. This results in losses ranging from 3% to

13% as the output current increases from 1A to 5A for

a 5V output, or a 4% to 20% loss for a 3.3V output.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3890-1 circuits: 1) IC V_INcurrent, 2) INTV_CC

regulator current, 3) I²R losses, 4) topside MOSFET

Efﬁciency varies as the inverse square of V

for the

OUT

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

and higher currents required by high per formance digital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

transition losses

.

1. The V current is the DC supply current given in the

IN

ElectricalCharacteristicstable,whichexcludesMOSFET

driverandcontrolcurrents.V currenttypicallyresults

IN

in a small (<0.1%) loss.

4. Transition losses apply only to the topside MOSFET(s),

and become signiﬁcant only when operating at high

2. INTV current is the sum of the MOSFET driver and

CC

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

input voltages (typically 15V or greater). Transition

losses can be estimated from:

Transition Loss = (1.7) • V • 2 • I

• C

• f

IN

O(MAX)

RSS

from INTV to ground. The resulting dQ/dt is a current

CC

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5%

to 10% efﬁciency degradation in portable systems. It

is very important to include these system level losses

out of INTV that is typically much larger than the

CC

control circuit current. In continuous mode, I

GATECHG

= f(Q + Q ), where Q and Q are the gate charges of

T

B

T

B

the topside and bottom side MOSFETs.

38901f

24

LTC3890-1

APPLICATIONS INFORMATION

during the design phase. The internal battery and fuse

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1μs to 10μs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop.

resistance losses can be minimized by making sure that

C has adequate charge storage and very low ESR at

IN

the switching frequency. A 25W supply will typically

require a minimum of 20μF to 40μF of capacitance

having a maximum of 20mꢁ to 50mꢁ of ESR. The

LTC3890-1 2-phase architecture typically halves this

input capacitance requirement over competing solu-

tions.OtherlossesincludingSchottkyconductionlosses

during dead-time and inductor core losses generally

account for less than 2% total additional loss.

Placing a power MOSFET directly across the output

capacitor and driving the gate with an appropriate signal

generatorisapracticalwaytoproducearealisticloadstep

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better to

look at the ITH pin signal which is in the feedback loop and

is the ﬁltered and compensated control loop response.

Checking Transient Response

The regulator loop response can be checked by looking at

theloadcurrenttransientresponse. Switchingregulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V_OUTshifts by

an amount equal to ΔI_LOAD(ESR), where ESR is the ef-

fective series resistance of C_OUT. ΔI_LOADalso begins to

charge or discharge C_OUTgenerating the feedback error

signal that forces the regulator to adapt to the current

change and return V_OUTto its steady-state value. During

this recovery time V_OUTcan be monitored for excessive

overshoot or ringing, which would indicate a stability

problem. OPTI-LOOP compensation allows the transient

response to be optimized over a wide range of output

capacitanceandESRvalues. TheavailabilityoftheITHpin

not only allows optimization of control loop behavior, but

it also provides a DC coupled and AC ﬁltered closed-loop

response test point. The DC step, rise time and settling

at this test point truly reﬂects the closed-loop response.

Assuming a predominantly second order system, phase

margin and/or damping factor can be estimated using the

percentage of overshoot seen at this pin. The bandwidth

can also be estimated by examining the rise time at the

pin. The ITH external components shown in Figure 13

circuit will provide an adequate starting point for most

applications.

The gain of the loop will be increased by increasing R

C

and the bandwidth of the loop will be increased by de-

creasing C . If R is increased by the same factor that C

C

is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

A second, more severe transient is caused by switching

in loads with large (>1μF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C

to C

is greater than 1:50, the switch rise time

LOAD

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10μF capacitor would

LOAD

require a 250μs rise time, limiting the charging current

to about 200mA.

The ITH series R -C ﬁlter sets the dominant pole-zero

C

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

38901f

25

LTC3890-1

APPLICATIONS INFORMATION

Design Example

A short-circuit to ground will result in a folded back cur-

rent of:

As a design example for one channel, assume V

=

IN

= 5A,

12V(nominal), V = 22V (max), V

SENSE(MAX)

= 3.3V, I

ꢁ

ꢃ

ꢂ

ꢄ

ꢆ

ꢅ

IN

OUT

MAX

95ns 22V

(

)

34mV

0.01ꢀ

1

2

I_SC

=

–

= 3.18A

V

= 75mV and f = 350kHz.

4.7μH

Theinductancevalueischosenﬁrstbasedona30%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the FREQ pin

to GND, generating 350kHz operation. The minimum

inductance for 30% ripple current is:

with a typical value of R

and δ = (0.005/°C)(25°C)

DS(ON)

= 0.125. The resulting power dissipated in the bottom

MOSFET is:

2

P

= 3.18A 1.125 0.022Ω

ꢁ

ꢃ

ꢂ

ꢄ

(

) (

)(

)

SYNC

V_OUT

f L

( )( )

V_OUT

ꢆ

ꢀI_L=

1–

_IN(NOM)ꢆ

V

= 250mW

ꢅ

which is less than under full-load conditions.

C is chosen for an RMS current rating of at least 3A at

A 4.7μH inductor will produce 29% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 5.73A. Increasing the ripple

current will also help ensure that the minimum on-time

of 95ns is not violated. The minimum on-time occurs at

IN

temperature assuming only this channel is on. C

is

OUT

chosen with an ESR of 0.02ꢁ for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

maximum V :

IN

V_OUT

3.3V

t_ON(MIN)

=

= 429ns

V

= R (ΔI ) = 0.02ꢁ(1.45A) = 29mV

ESR L P-P

ORIPPLE

V

f

22V 350kHz

_IN(MAX)( )

(

)

PC Board Layout Checklist

The equivalent R

resistor value can be calculated by

SENSE

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layoutdiagramofFigure11.Figure12illustratesthecurrent

waveformspresentinthevariousbranchesofthe2-phase

synchronousregulatorsoperatinginthecontinuousmode.

Check the following in your layout:

using the minimum value for the maximum current sense

threshold (43mV):

64mV

5.73A

R_SENSE

≤

≈ 0.01Ω

Choosing 1% resistors: R = 25k and R = 78.7k yields

A

B

an output voltage of 3.32V.

1. Are the top N-channel MOSFETs MTOP1 and MTOP2

located within 1cm of each other with a common drain

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

connection at C ? Do not attempt to split the input

IN

results in: R

= 0.035ꢁ/0.022ꢁ, C

= 215pF. At

DS(ON)

MILLER

decoupling for the two channels as it can cause a large

resonant loop.

maximum input voltage with T(estimated) = 50°C:

²ꢀ

5A 1+ 0.005 50°C – 25°C

)( )

ꢂ

3.3V

22V

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

P_MAIN

=

(

)

(

ꢁ

ꢃ

2

5A

2

of C

must return to the combined C

(–) termi-

INTVCC

OUT

0.035ꢄ + 22V

) (

2.5ꢄ 215pF •

)(

(

)

(

)

nals. The path formed by the top N-channel MOSFET,

ꢀ

ꢂ

Schottky diode and the C capacitor should have short

1

IN

+

350kHz = 331mW

ꢅ

ꢆ

(

)

5V – 2.3V 2.3V

ꢁ

ꢃ

38901f

26

LTC3890-1

APPLICATIONS INFORMATION

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop described above.

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output

switchingnode(SWpin)tosynchronizetheoscilloscopeto

the internal oscillator and probe the actual output voltage

as well. Check for proper performance over the operating

voltage and current range expected in the application. The

frequency of operation should be maintained over the input

voltage range down to dropout and until the output load

drops below the low current operation threshold—typi-

cally 15% of the maximum designed current level in Burst

Mode operation.

3. DotheLTC3890-1V pins’resistivedividersconnectto

FB

the (+) terminals of C ? The resistive divider must be

OUT

connected between the (+) terminal of C

and signal

OUT

ground. The feedback resistor connections should not

be along the high current input feeds from the input

capacitor(s).

–

+

4. Are the SENSE and SENSE leads routed together

with minimum PC trace spacing? The ﬁlter capacitor

+

–

between SENSE and SENSE should be as close as

possibletotheIC.Ensureaccuratecurrentsensingwith

Kelvin connections at the SENSE resistor.

Thedutycyclepercentageshouldbemaintainedfromcycle

tocycleinawell-designed,lownoisePCBimplementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regula-

tor bandwidth optimization is not required. Only after

each controller is checked for its individual performance

should both controllers be turned on at the same time.

A particularly difﬁcult region of operation is when one

controller channel is nearing its current comparator trip

pointwhentheotherchannelisturningonitstopMOSFET.

This occurs around 50% duty cycle on either channel due

to the phasing of the internal clocks and may cause minor

duty cycle jitter.

5. Is the INTV decoupling capacitor connected close

CC

to the IC, between the INTV and the power ground

CC

pins? This capacitor carries the MOSFET drivers’ cur-

rent peaks. An additional 1μF ceramic capacitor placed

immediately next to the INTV and PGND pins can

CC

help improve noise performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), and boost nodes (BOOST1, BOOST2) away

from sensitive small-signal nodes, especially from

the opposites channel’s voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on

the output side of the LTC3890-1 and occupy minimum

PC trace area.

Reduce V from its nominal level to verify operation

IN

of the regulator in dropout. Check the operation of the

undervoltage lockout circuit by further lowering V while

IN

7. Useamodiﬁedstargroundtechnique:alowimpedance,

large copper area central grounding point on the same

side of the PC board as the input and output capacitors

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

with tie-ins for the bottom of the INTV decoupling

CC

capacitor, the bottom of the voltage feedback resistive

divider and the SGND pin of the IC.

38901f

27

LTC3890-1

APPLICATIONS INFORMATION

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effectsofdifferentialnoiseinjectionduetohighfrequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

whenthecurrentsensingleadsarehookedupbackwards.

The output voltage under this improper hookup will still

bemaintainedbuttheadvantagesofcurrentmodecontrol

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

for inductive coupling between C , Schottky and the top

IN

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

38901f

28

LTC3890-1

APPLICATIONS INFORMATION

ITH1

TRACK/SS1

PGOOD1

TG1

R

PU1

V

PULL-UP

V

PGOOD1

FB1

L1

R

SENSE

D1

+

–

V

SENSE1

OUT1

SW1

LTC3890-1

BOOST1

C

B1

M1

M2

BG1

FREQ

R

IN

C

OUT1

V

f

IN

1μF

IN

PLLIN/MODE

RUN1

+

C

CERAMIC

VIN

PGND

GND

RUN2

+

EXTV

CC

C

+

IN

V

SGND

C

IN

INTVCC

–

INTV

SENSE2

OUT2

1μF

CERAMIC

+

BG2

SENSE2

M4

L2

M3

D2

BOOST2

V

FB2

C

B2

SW2

TG2

ITH2

R

SENSE

V

OUT2

TRACK/SS2

38901 F11

Figure 11. Recommended Printed Circuit Layout Diagram

38901f

29

LTC3890-1

APPLICATIONS INFORMATION

SW1

L1

R

SENSE1

V

OUT1

D1

C

R

L1

OUT1

V

IN

R

IN

C

IN

SW2

L2

R

SENSE2

V

OUT2

D2

C

R

L2

OUT2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

38901 F12

Figure 12. Branch Current Waveforms

38901f

30

LTC3890-1

TYPICAL APPLICATIONS

+

–

SENSE1

INTV

CC

C1

1nF

R

B1

100k

SENSE1

R

PGOOD1

BG1

A1

31.6k

V

FB1

C

100pF

R

ITH1A

MBOT1

R

SENSE1

8mΩ

V

3.3V

5A

OUT1

C

1000pF

ITH1

SW1

ITH1

34.8k

L1

BOOST1

ITH1

4.7μH

C

OUT1

470μF

C

LTC3890-1

C

SS1

0.01μF

B1

0.1μF

TRACK/SS1

TG1

MTOP1

D1

V

IN

V

IN

9V TO 60V

C

IN

220μF

PLLIN/MODE

SGND

INTV

CC

C

INT

4.7μF

PGND

EXTV

V

CC

OUT2

RUN1

RUN2

FREQ

R

FREQ

41.2k

D2

TG2

MTOP2

C

0.01μF

SS2

C

0.1μF

B2

L2

8μH

R

TRACK/SS2

ITH2

BOOST2

SW2

SENSE2

R

ITH2

34.8k

C

470pF

10mΩ

V

8.5V

3A

ITH2

R

OUT2

C

OUT2

A2

10.5k

330μF

MBOT2

V

FB2

BG2

R

B2

100k

–

SENSE2

C2

1nF

+

SENSE2

38901 TA07a

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1: COILCRAFT SER1360-472KL

L2: COILCRAFT SER1360-802KL

C

: SANYO 6TPE470M

: SANYO 10TPE330M

OUT1

OUT2

D1, D2: DFLS1100

Figure 13. High Efﬁciency Dual 8.5V/3.3V Step-Down Converter

Efﬁciency and Power Loss

vs Output Current

Efﬁciency vs Load Current

Efﬁciency vs Input Voltage

100

98

96

94

92

90

88

86

84

10000

1000

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

V

= 12V

IN

OUT

V

= 8.5V

BURST EFFICIENCY

OUT

= 3.3V

V

OUT

= 3.3V

V

= 8.5V

OUT2

CCM LOSS

BURST LOSS

PULSE-SKIPPING

LOSS

V

OUT1

= 3.3V

10

CCM EFFICIENCY

1

PULSE-SKIPPING

EFFICIENCY

82

80

10

0

10

0

I

= 2A

V

IN

= 12V

LOAD

5

0.1

10

0

10 15 20 25 30 35 40 45 50 55 60

0.0001 0.001

0.01

0.1

1

10

0.0001 0.001

0.01

0.1

1

INPUT VOLTAGE (V)

OUTPUT CURRENT (A)

38901 TA07d

38901 TA07c

38901 TA07b

38901f

31

LTC3890-1

TYPICAL APPLICATIONS

High Efﬁciency 8.5V Dual-Phase Step-Down Converter

+

–

SENSE1

INTV

C1

1nF

CC

R

B1

100k

R

A1

PGOOD1

BG1

10.5k

V

FB1

MBOT1

C

100pF

ITH1A

L1

8μH

V

8.5V

6A

OUT1

SW1

R

34.8k

ITH1

C

R

SENSE1

BOOST1

ITH1

10mΩ

C

OUT1

330μF

C

ITH1

C

0.01μF

LTC3890-1

B1

SS1

470pF

0.1μF

TRACK/SS1

TG1

MTOP1

D1

V

IN

INTV

V

R

CC

IN

MODE

9V TO 60V

C

100k

IN

220μF

PLLIN/MODE

SGND

INTV

CC

C

INT

4.7μF

R

PGND

RUN

1000k

V

OUT

EXTV

CC

V

IN

RUN1

RUN2

FREQ

D2

R

41.2k

FREQ

TG2

MTOP2

C

0.1μF

B2

TRACK/SS2

C

ITH2

100pF

R

L2

8μH

BOOST2

SW2

SENSE2

10mΩ

ITH2

C

OUT2

MBOT2

BG2

330μF

V

FB2

–

+

SENSE2

C2

1nF

SENSE2

38901 TA03

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1, L2: COILCRAFT SER1360-802KL

C

, C

: SANYO 10TPE330M

OUT1 OUT2

D1, D2: DFLS1100

38901f

32

LTC3890-1

TYPICAL APPLICATIONS

High Efﬁciency Dual 12V/5V Step-Down Converter

+

SENSE1

INTV

CC

C1

1nF

R

B1

100k

–

PGOOD1

BG1

SENSE1

R

A1

6.98k

V

FB1

C

100pF

R

ITH1A

MBOT1

R

SENSE1

9mΩ

V

12V

3A

OUT1

C

470pF

C

ITH1

SW1

34.8k

L1

C

OUT1

BOOST1

ITH1

8μH

180μF

C

LTC3890-1

TRACK/SS1

0.01μF

B1

SS1

0.47μF

TG1

MTOP1

D1

V

IN

V

IN

12.5V TO 60V

C

IN

220μF

PLLIN/MODE INTV

SGND

CC

C

INT

4.7μF

PGND

EXTV

CC

RUN1

RUN2

FREQ

R

FREQ

D2

41.2k

TG2

MTOP2

C

0.47μF

C

0.01μF

B2

SS2

L2

4.7μH

R

BOOST2

SW2

SENSE2

TRACK/SS2

ITH2

10mΩ

V

5V

5A

OUT2

R

ITH2

20k

C

470pF

ITH2

C

OUT2

MBOT2

BG2

470μF

R

A2

18.7k

V

FB2

–

+

SENSE2

R

B2

C2

1nF

100k

SENSE2

38901 TA04

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1: COILCRAFT SER1360-802KL

L2: COILCRAFT SER1360-472KL

C

: 16SVP180MX

OUT1

OUT2

: SANYO 6TPE470M

D1, D2: DFLS1100

38901f

33

LTC3890-1

TYPICAL APPLICATIONS

High Efﬁciency Dual 24V/5V Step-Down Converter

R

B1

487k

+

SENSE1

INTV

CC

C1

1nF

C

33pF

F1

100k

–

SENSE1

PGOOD1

BG1

R

A1

16.9k

V

FB1

C

100pF

R

ITH1A

L1

22μH

MBOT1

MTOP1

R

SENSE1

V

24V

1A

25mΩ

OUT1

C

680pF

C

ITH1

46k

ITH1

SW1

BOOST1

ITH1

C

OUT1

22μF

C

LTC3890-1

TRACK/SS1

0.01μF

B1

SS1

×2 CERAMIC

0.47μF

TG1

D1

V

IN

V

IN

28V TO 60V

C

IN

220μF

PLLIN/MODE INTV

SGND

CC

C

INT

4.7μF

PGND

EXTV

CC

RUN1

RUN2

FREQ

R

FREQ

D2

60k

TG2

MTOP2

C

0.47μF

C

0.01μF

R

B2

SS2

L2

4.7μH

R

BOOST2

SW2

SENSE2

TRACK/SS2

ITH2

10mΩ

V

C

470pF

ITH2

20k

OUT2

5V

5A

ITH2

C

OUT2

MBOT2

BG2

470μF

V

FB2

R

A2

R

100k

18.7k

B2

–

+

SENSE2

C2

1nF

38901 TA05

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1: SUMIDA CDR7D43MN

L2: COILCRAFT SER1360-472KL

C

: KEMET T525D476MO16E035

: SANYO 6TPE470M

OUT1

OUT2

C

D1, D2: DFLS1100

38901f

34

LTC3890-1

PACKAGE DESCRIPTION

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 p.005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 p.0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 p .004

(0.38 p 0.10)

.0532 – .0688

(1.35 – 1.75)

s 45o

.004 – .0098

(0.102 – 0.249)

.0075 – .0098

(0.19 – 0.25)

0o – 8o TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

38901f

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-

t ion t h a t t he in ter c onne c t ion o f i t s cir cui t s a s de s cr ib e d her ein w ill no t in fr inge on ex is t ing p a ten t r igh t s.

35

LTC3890-1

TYPICAL APPLICATION

High Efﬁciency Dual 12V/3.3V Step-Down Converter

+

SENSE1

INTV

CC

C1

1nF

R

B1

100k

–

PGOOD1

BG1

SENSE1

R

A1

6.98k

V

FB1

C

100pF

R

ITH1A

MBOT1

R

SENSE1

9mΩ

V

12V

3A

OUT1

C

470pF

ITH1

SW1

34.8k

L1

8μH

C

OUT1

BOOST1

ITH1

180μF

C

LTC3890-1

C

SS1

0.01μF

B1

0.47μF

TRACK/SS1

TG1

MTOP1

D1

V

IN

V

IN

12.5V TO 60V

C

IN

220μF

PLLIN/MODE

SGND

INTV

CC

C

INT

4.7μF

PGND

EXTV

CC

RUN1

RUN2

FREQ

R

FREQ

D2

41.2k

TG2

MTOP2

C

0.47μF

C

SS2

0.01μF

B2

L2

4.7μH

R

BOOST2

SW2

SENSE2

TRACK/SS2

ITH2

10mΩ

V

3.3V

5A

OUT2

R

ITH2

34.8k

C

1000pF

ITH2

C

OUT2

ITH2A

MBOT2

BG2

470μF

100pF

V

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1: COILCRAFT SER1360-802KL

FB2

R

A2

–

SENSE2

31.6k

L2: COILCRAFT SER1360-472KL

R

B2

C2

1nF

C

OUT1

C

OUT2

: 16SVP180MX

: SANYO 6TPE470M

100k

+

D1, D2: DFLS1100

SENSE2

38901 TA06

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,

LTC3857/LTC3857-1 Low I , Dual Output 2-Phase Synchronous Step-Down

Q

IN

DC/DC Controllers with 99% Duty Cycle

0.8V ≤ V

≤ 24V, I = 50μA

OUT Q

LTC3858/LTC3858-1 Low I , Dual Output 2-Phase Synchronous Step-Down

Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,

IN

Q

DC/DC Controllers with 99% Duty Cycle

0.8V ≤ V

≤ 24V, I = 170μA

OUT Q

LTC3868/LTC3868-1 Low I , Dual Output 2-Phase Synchronous Step-Down

Phase-Lockable Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 24V,

IN

Q

DC/DC Controller with 99% Duty Cycle

0.8V ≤ V

≤ 14V, I = 170μA

OUT Q

LTC3834/LTC3834-1 Low I , Synchronous Step-Down DC/DC Controller with Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V ≤ V ≤ 36V,

Q

IN

99% Duty Cycle

0.8V ≤ V

≤ 10V, I = 30μA

OUT Q

LTC3835/LTC3835-1 Low I , Synchronous Step-Down DC/DC Controller with Phase-Lockable Fixed Frequency 140kHz to 650kHz, 4V ≤ V ≤ 36V,

Q

IN

99% Duty Cycle

0.8V ≤ V

≤ 10V, I = 80μA

OUT Q

LT3845

Low I , High Voltage Synchronous Step-Down DC/DC

Adjustable Fixed Frequency 100kHz to 500kHz, 4V ≤ V ≤ 60V,

IN

Q

Controller

1.23V ≤ V

≤ 36V, I = 120μA, TSSOP-16

OUT Q

38901f

LT 0210 • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

36

●

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3890EGN-1PBF
厂家：	Linear
描述：	60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller 60V低IQ ，双通道，两相同步降压型DC / DC控制器控制器
文件：	总36页 (文件大小：498K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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