LTC3890HGN-1#PBF_技术文档

LTC3890-1

60V Low I , Dual, 2-Phase

Q

Synchronous Step-Down

DC/DC Controller

DESCRIPTION

FEATURES

The LTC^®3890-1 is a high performance dual step-down

switching regulator DC/DC controller that drives all

N-channelsynchronouspowerMOSFETstages.Aconstant

frequency current mode architecture allows a phase-

lockablefrequencyofupto850kHz.Powerlossandsupply

noiseareminimizedbyoperatingthetwocontrolleroutput

stages out-of-phase.

n

Wide V Range: 4V to 60V (65V Abs Max)

IN

n

Low Operating I : 50µA (One Channel On)

Q

n

Wide Output Voltage Range: 0.8V ≤ V

≤ 24V

OUT

R

SENSE

or DCR Current Sensing

Out-of-Phase Controllers Reduce Required Input

Capacitance and Power Supply Induced Noise

Phase-Lockable Frequency (75kHz to 850kHz)

Programmable Fixed Frequency (50kHz to 900kHz)

Selectable Continuous, Pulse-Skipping or Low Ripple

Burst Mode^®Operation at Light Loads

Very Low Dropout Operation: 99% Duty Cycle

Adjustable Output Voltage Soft-Start or Tracking

Power Good Output Voltage Monitor

Output Overvoltage Protection

Low Shutdown I : <14µA

Internal LDO Powers Gate Drive from V or EXTV

No Current Foldback During Start-Up

Narrow SSOP Package

n

The50μAno-loadquiescentcurrentextendsoperatinglife

in battery-powered systems. OPTI-LOOP^®compensation

allows the transient response to be optimized over a wide

range of output capacitance and ESR values. A wide 4V

to 60V input supply range encompasses a wide range of

intermediate bus voltages and battery chemistries.

n

Independent TRACK/SS pins for each controller ramp the

output voltages during start-up. Current foldback limits

MOSFET heat dissipation during short-circuit conditions.

ThePLLIN/MODEpinselectsamongBurstModeoperation,

pulse-skipping mode, or continuous conduction mode at

light loads.

Q

IN

CC

APPLICATIONS

Foraleadless32-pinQFNpackagewithadditionalfeatures

of adjustable current limit, clock out, phase modulation

and two PGOOD outputs, see the LTC3890 data sheet.

L, LT, LTC, LTM, Linear Technology, Burst Mode, OPTI-LOOP and the Linear logo are

registered trademarks of Linear Technology Corporation. All other trademarks are the property

of their respective owners. Protected by U.S. Patents including 5481178, 5705919, 5929620,

6100678, 6144194, 6177787, 6304066, 6580258, 7230497.

n

Automotive Always-On Systems

n

Battery Operated Digital Devices

n

Distributed DC Power Systems

TYPICAL APPLICATION

High Efficiency Dual 8.5V/3.3V Output Step-Down Converter

Efficiency and Power Loss

V

vs Output Current

IN

9V TO 60V

22µF

10000

1000

100

90

80

70

60

50

40

30

20

4.7µF

V

= 12V

IN

OUT

V

IN

INTV

CC

= 3.3V

TG1

TG2

0.1µF

BOOST1

SW1

BOOST2

SW2

4.7µH

8µH

BG1

BG2

LTC3890-1

PGND

10

+

SENSE1

SENSE2

0.01Ω

0.008Ω

1

–

V

8.5V

3A

SENSE2

10

0

OUT2

V

OUT1

3.3V

5A

V

FB1

FB2

0.1

10

100k

470µF

100k

10.5k

ITH1

ITH2

0.0001 0.001

0.01

0.1

1

1000pF

34.8k

1000pF

OUTPUT CURRENT (A)

330µF

TRACK/SS1 SGND TRACK/SS2

0.1µF

38901 TA01b

31.6k

34.8k

0.1µF

38901 TA01a

38901fb

1

LTC3890-1

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION

(Note 1)

TOP VIEW

Input Supply Voltage (V )......................... –0.3V to 65V

IN

Topside Driver Voltages

1

2

TRACK/SS1

PGOOD1

TG1

28

27

26

25

24

23

22

21

20

19

18

17

16

15

ITH1

BOOST1, BOOST2 ..................................–0.3V to 71V

Switch Voltage (SW1, SW2) ......................... –5V to 65V

(BOOST1-SW1), (BOOST2-SW2) ................ –0.3V to 6V

RUN1, RUN2 ............................................... –0.3V to 8V

Maximum Current Sourced into Pin

V

FB1

+

3

SENSE1

–

4

SW1

5

BOOST1

BG1

FREQ

PLLIN/MODE

SGND

6

7

V

IN

from Source >8V...................................................100µA

8

PGND

RUN1

+

–

+

–

SENSE1 , SENSE2 , SENSE1

9

EXTV

CC

RUN2

SENSE2 Voltages ..................................... –0.3V to 28V

–

10

11

12

13

14

INTV

CC

SENSE2

PLLIN/MODE, INTV Voltages ................... –0.3V to 6V

CC

+

BG2

SENSE2

FREQ Voltage........................................–0.3V to INTV

CC

BOOST2

SW2

V

FB2

EXTV ..................................................... –0.3V to 14V

CC

ITH2

ITH1, ITH2, V , V Voltages................... –0.3V to 6V

TG2

FB1 FB2

TRACK/SS2

PGOOD1 Voltage ......................................... –0.3V to 6V

TRACK/SS1, TRACK/SS2 Voltages ............. –0.3V to 6V

Operating Junction Temperature Range (Notes 2, 3)

LTC3890E-1, LTC3890I-1 ................... –40°C to 125°C

LTC3890H-1....................................... –40°C to 150°C

LTC3890MP-1 .................................... –55°C to 150°C

Storage Temperature Range .................. –65°C to 150°C

GN PACKAGE

28-LEAD PLASTIC SSOP

T

= 150°C, θ = 90°C/W

JA

JMAX

ORDER INFORMATION

LEAD FREE FINISH

LTC3890EGN-1#PBF

LTC3890IGN-1#PBF

LTC3890HGN-1#PBF

LTC3890MPGN-1#PBF

TAPE AND REEL

PART MARKING*

LTC3890GN-1

PACKAGE DESCRIPTION

28-Lead Plastic SSOP

TEMPERATURE RANGE

–40°C to 125°C

–40°C to 150°C

–55°C to 150°C

LTC3890EGN-1#TRPBF

LTC3890IGN-1#TRPBF

LTC3890HGN-1#TRPBF

LTC3890MPGN-1#TRPBF

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

38901fb

2

LTC3890-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, V_RUN1,2= 5V, EXTV_CC= 0V unless otherwise noted. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

V

Input Supply Operating Voltage Range

Regulated Feedback Voltage

4

60

V

IN

I

Voltage = 1.2V (Note 4)

TH1,2

FB1,2

–40°C to 85°C, All Grades

LTC3890E-1, LTC3890I-1,

LTC3890H-1, LTC3890MP-1

0.792

0.788

0.786

0.800

0.808

0.812

V

l

I

Feedback Current

(Note 4)

5

50

nA

FB1,2

V

Reference Voltage Line Regulation

Output Voltage Load Regulation

V

= 4.5V to 60V (Note 4)

IN

0.002

0.02

%/V

REFLNREG

LOADREG

(Note 4)

l

Measured in Servo Loop,

0.01

0.1

%

∆

Voltage = 1.2V to 0.7V

ITH

(Note 4)

Measured in Servo Loop,

–0.01

2

–0.1

%

∆

Voltage = 1.2V to 2V

ITH

g

m1,2

Transconductance Amplifier g

Input DC Supply Current

I

= 1.2V, Sink/Source = 5µA (Note 4)

mmho

m

TH1,2

I

Q

(Note 5)

Pulse-Skipping or Forced Continuous

Mode (One Channel On)

RUN1 = 5V and RUN2 = 0V, V = 0.83V or

2

mA

µA

FB1

RUN1 = 0V and RUN2 = 5V, V = 0.83V

FB2

Pulse-Skipping or Forced Continuous

Mode (Both Channels On)

RUN1,2 = 5V, V

= 0.83V (No Load)

FB1,2

Sleep Mode (One Channel On)

RUN1 = 5V and RUN2 = 0V, V = 0.83V or

50

75

FB1

RUN1 = 0V and RUN2 = 5V, V = 0.83V

FB2

Sleep Mode (Both Channels On)

Shutdown

RUN1,2 = 5V, V

RUN1,2 = 0V

= 0.83V (No Load)

60

14

100

25

µA

FB1,2

l

UVLO

Undervoltage Lockout

INTV Ramping Up

3.92

3.80

4.2

4.0

V

CC

INTV Ramping Down

3.6

7

CC

V

OVL

Feedback Overvoltage Protection

Measured at V

Each Channel

, Relative to Regulated V

FB1,2 FB1,2

10

13

1

%

+

–

+

I

SENSE Pin Current

µA

SENSE

–

SENSE Pins Current

Each Channel

–

V

< INTV – 0.5V

1

µA

SENSE

CC

> INTV + 0.5V

700

99

CC

DF

MAX

Maximum Duty Factor

In Dropout

98

%

I

Soft-Start Charge Current

V

= 0V

TRACK1,2

0.7

1.0

1.4

µA

TRACK/SS1,2

l

V

RUN1

V

RUN2

On

RUN1 Pin On Threshold

RUN2 Pin On Threshold

V

RUN1

V

RUN2

Rising

1.15

1.20

1.21

1.25

1.27

1.30

V

Hyst RUN Pin Hysteresis

50

75

mV

RUN1,2

l

Maximum Current Sense Threshold

V

= 0.7V, V

–, – = 3.3V, I = 0

64

85

SENSE(MAX)

FB1,2

SENSE1

2

LIM

Gate Driver

TG1,2

Pull-Up On-Resistance

Pull-Down On-Resistance

2.5

1.5

Ω

BG1,2

Pull-Up On-Resistance

Pull-Down On-Resistance

2.4

1.1

Ω

TG Transition Time:

Rise Time

(Note 6)

TG1,2 t

C

= 3300pF

25

ns

r

f

LOAD

Fall Time

= 3300pF

BG Transition Time:

Rise Time

(Note 6)

LOAD

BG1,2 t

C

= 3300pF

25

ns

r

f

Fall Time

38901fb

3

LTC3890-1

ELECTRICAL CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating junction

temperature range, otherwise specifications are at T_A= 25°C. V_IN= 12V, V_RUN1,2= 5V, EXTV_CC= 0V unless otherwise noted. (Note 2)

SYMBOL

PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

TG/BG t

Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time

C

= 3300pF Each Driver

30

ns

1D

LOAD

BG/TG t

Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time

C

= 3300pF Each Driver

30

95

ns

1D

LOAD

t

Minimum On-Time

(Note 7)

ON(MIN)

INTV Linear Regulator

CC

V

Internal V Voltage

6V < V < 60V, V = 0V

EXTVCC

4.85

4.5

5.1

0.7

5.1

0.6

4.7

250

5.35

1.1

V

%

V

INTVCCVIN

LDOVIN

CC

IN

INTV Load Regulation

I

CC

= 0mA to 50mA, V

= 0V

CC

EXTVCC

Internal V Voltage

6V < V < 13V

EXTVCC

5.35

1.1

INTVCCEXT

LDOEXT

CC

INTV Load Regulation

I

CC

= 0mA to 50mA, V

= 8.5V

%

V

CC

EXTVCC

EXTV Switchover Voltage

EXTV Ramping Positive

4.9

EXTVCC

CC

EXTV Hysteresis

mV

LDOHYS

CC

Oscillator and Phase-Locked Loop

f

Programmable Frequency

Low Fixed Frequency

R

= 25k, PLLIN/MODE = DC Voltage

= 65k, PLLIN/MODE = DC Voltage

= 105k, PLLIN/MODE = DC Voltage

= 0V, PLLIN/MODE = DC Voltage

105

440

835

350

535

kHz

25kΩ

65kΩ

105kΩ

LOW

FREQ

375

505

V

320

485

75

380

585

850

High Fixed Frequency

= INTV , PLLIN/MODE = DC Voltage

CC

HIGH

SYNC

l

Synchronizable Frequency

PLLIN/MODE = External Clock

PGOOD1 Output

V

PGOOD1 Voltage Low

PGOOD1 Leakage Current

PGOOD1 Trip Level

I

= 2mA

= 5V

0.2

0.4

1

V

PGL

PGOOD

I

V

µA

PGOOD

V

PG

with Respect to Set Regulated Voltage

FB

V

Ramping Negative

–13

7

–10

2.5

–7

13

%

FB

Hysteresis

V

with Respect to Set Regulated Voltage

FB

V

Ramping Positive

10

2.5

%

FB

Hysteresis

t

PG

Delay for Reporting a Fault

25

µs

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Ratings for extended periods may affect device reliability and

lifetime.

Note 3: T is calculated from the ambient temperature T and power

J A

dissipation P according to the following formula:

D

T = T + (P • 90°C/W)

J

A

D

Note 4: The LTC3890-1 is tested in a feedback loop that servos V

to

ITH1,2

Note 2: The LTC3890-1 is tested under pulsed load condition such that

a specified voltage and measures the resultant V . The specification at

FB

T ≈ T .The LTC3890E-1 is guaranteed to meet performance specifications

85°C is not tested in production and is assured by design, characterization

and correlation to production testing at other temperatures (125°C for the

LTC3890E-1/LTC3890I-1, 150°C for the LTC3890H-1/LTC3890MP-1). For

the LTC3890MP-1, the specification at –40°C is not tested in production

and is assured by design, characterization and correlation to production

testing at –55°C.

J

A

from 0°C to 85°C. Specifications over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3890I-1 is guaranteed

over the –40°C to 125°C operating junction temperature range, the

LTC3890H-1 is guaranteed over the –40°C to 150°C operating junction

temperature range and the LTC3890MP-1 is tested and guaranteed over

the –55°C to 150°C operating junction temperature range.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See the Applications information section.

High junction temperatures degrade operating lifetimes; operating lifetime

is derated for junction temperatures greater than 125°C. Note that the

maximum ambient temperature consistent with these specifications is

determined by specific operating conditions in conjunction with board layout,

the rated package thermal impedance and other environmental factors.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The minimum on-time condition is specified for an inductor peak-

to-peak ripple current ≥ of I

(See Minimum On-Time Considerations in

MAX

the Applications Information section).

38901fb

4

LTC3890-1

TYPICAL PERFORMANCE CHARACTERISTICS

Efficiency and Power Loss

vs Output Current

Efficiency vs Output Current

Efficiency vs Input Voltage

10000

1000

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

100

98

96

94

92

90

88

86

84

V

= 12V

IN

OUT

BURST EFFICIENCY

V

= 8.5V

OUT

= 3.3V

V

= 3.3V

OUT

V

= 8.5V

OUT2

CCM LOSS

BURST LOSS

PULSE-SKIPPING

LOSS

10

V

= 3.3V

OUT1

CCM EFFICIENCY

1

Burst Mode OPERATION

PULSE-SKIPPING

EFFICIENCY

10

0

10

0

82

80

V

IN

= 12V

I

= 2A

LOAD

5

0.1

10

0.0001 0.001

0.01

0.1

1

0.0001 0.001

0.01

0.1

1

10

0

10 15 20 25 30 35 40 45 50 55 60

INPUT VOLTAGE (V)

OUTPUT CURRENT (A)

38901 G01

38901 G02

38901 G03

FIGURE 13 CIRCUIT

Load Step

Burst Mode Operation

Load Step

Pulse-Skipping Mode

Load Step

Forced Continuous Mode

V

OUT

100mV/DIV

AC-

100mV/DIV

AC-

100mV/DIV

AC-

COUPLED

I

L

I

L

2A/DIV

38901 G04

38901 G05

38901 G06

50µs/DIV

V

= 12V

V

= 12V

V

= 12V

IN

OUT

IN

OUT

IN

OUT

= 3.3V

FIGURE 13 CIRCUIT

Inductor Current at Light Load

Soft Start-Up

Tracking Start-Up

FORCED

CONTINUOUS

MODE

V

OUT2

2V/DIV

Burst Mode

OPERATION

1A/DIV

V

OUT1

2V/DIV

PULSE-SKIPPING

MODE

38901 G09

38901 G08

38901 G07

2ms/DIV

FIGURE 13 CIRCUIT

2ms/DIV

FIGURE 13 CIRCUIT

5µs/DIV

V

LOAD

= 12V

IN

= 3.3V

OUT

I

= 200µA

38901fb

5

LTC3890-1

TYPICAL PERFORMANCE CHARACTERISTICS

Total Input Supply Current

vs Input Voltage

EXTV_CCSwitchover and INTV_CC

Voltages vs Temperature

INTV_CCLine Regulation

300

250

200

150

100

6.0

5.8

5.6

5.4

5.2

5.0

4.8

4.6

4.4

4.2

4.0

5.5

5.0

V

= 3.3V

OUT

FIGURE 13 CIRCUIT

INTV

CC

300µA LOAD

4.5

4.0

3.5

3.0

EXTV RISING

CC

EXTV FALLING

CC

NO LOAD

50

0

I

= 10mA

LOAD

–75 –50 –25

0

25 50 75 100 125 150

0 5

10 15 20 25 30 35 40 45 50 55 60 65

INPUT VOLTAGE (V)

5

10 15 20 25 30 35 40 45 50 55 60 65

INPUT VOLTAGE (V)

TEMPERATURE (°C)

38901 G10

38901 G12

38901 G11

Maximum Current Sense Voltage

vs I_THVoltage

Maximum Current Sense

Threshold vs Duty Cycle

SENSE^–Pin Input Bias Current

800

700

600

500

400

300

200

100

0

80

60

40

20

90

85

80

75

70

65

60

5% DUTY CYCLE

PULSE-SKIPPING MODE

Burst Mode

OPERATION

0

–20

–40

FORCED CONTINUOUS MODE

–100

5

10

15

25

0.8

(V)

1.2

1.4

0

20

0

0.2

0.4 0.6

V

1.0

0

10 20 30 40 50 60 70 80 90 100

V

COMMON MODE VOLTAGE (V)

DUTY CYCLE (%)

SENSE

ITH

38901 G14

38901 G13

38901 G15

Foldback Current Limit

Quiescent Current vs Temperature

INTV_CCvs Load Current

5.50

5.25

5.00

80

70

60

50

40

30

20

10

0

80

75

70

65

60

55

50

45

40

35

30

V

= 12V

V

= 12V

IN

EXTV = 0V

CC

EXTV = 8.5V

CC

4.75

4.50

4.25

4.00

EXTV = 5V

CC

20

60

LOAD CURRENT (mA)

80

100

0

40

0

100 200 300 400 500 600 700 800

FEEDBACK VOLTAGE (MV)

38901 G16

–75

–50 –25

0

25 50

75 100 125 150

TEMPERATURE (°C)

38901 G18

38901 G17

38901fb

6

LTC3890-1

TYPICAL PERFORMANCE CHARACTERISTICS

Regulated Feedback Voltage

vs Temperature

TRACK/SS Pull-Up Current

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

1.40

1.35

808

1.10

1.05

1.00

0.95

806

804

RUN1 RISING

1.30

1.25

1.20

1.15

1.10

1.05

1.00

RUN2 RISING

802

800

798

796

794

RUN1 FALLING

RUN2 FALLING

100

0.90

792

25 50 75

125 150

–50 –25

75 100 125 150

TEMPERATURE (°C)

–75 –50 –25

0

25 50 75 100 125 150

–75 –50 –25

0

–75

0

25 50

TEMPERATURE (°C)

38901 G19

38901 G20

38901 G21

SENSE^–Pin Total Input Bias Current

vs Temperature

Shutdown Current

vs Input Voltage

Oscillator Frequency

vs Temperature

30

25

20

15

10

5

800

700

600

500

400

300

200

100

0

600

550

500

450

FREQ = INTV

CC

V

> INTV + 0.5V

CC

OUT

400

350

300

FREQ = GND

25 50

V

< INTV – 0.5V

CC

OUT

0

–100

5

10 15 20 25 30 35 40 45 50 55 60 65

–50 –25

75 100 125 150

75 125 150

100

–75

25 50

–75 –50 –25

0

INPUT VOLTAGE (V)

TEMPERATURE (°C)

38901 G23

38901 G22

38901 G24

Undervoltage Lockout Threshold

vs Temperature

Oscillator Frequency

vs Input Voltage

Shutdown Current vs Temperature

22

20

18

4.2

4.1

4.0

3.9

3.8

3.7

3.6

356

354

352

350

348

V

= 12V

FREQ = GND

IN

RISING

16

14

12

10

8

FALLING

346

344

–75

–25

0

25 50 75 100 125 150

–75 –50 –25

0

25 50 75 100 125 150

–50

5

10 15 20 25 30 35 40 45 50 55 60 65

TEMPERATURE (°C)

INPUT VOLTAGE (V)

38901 G27

38901 G26

38901 G25

38901fb

7

LTC3890-1

PIN FUNCTIONS

ITH1, ITH2 (Pin 1, Pin 13): Error Amplifier Outputs and

Switching Regulator Compensation Points. Each associ-

ated channel’s current comparator trip point increases

with this control voltage.

both controllers, determines how the LTC3890-1 operates

atlightloads.PullingthispintogroundselectsBurstMode

operation.Aninternal100kresistortogroundalsoinvokes

Burst Mode Operation when the pin is floated. Tying this

pintoINTV forcescontinuousinductorcurrentoperation.

CC

V

, V (Pin 2, Pin 12): Receives the remotely sensed

FB1 FB2

Tying this pin to a voltage greater than 1.2V and less than

feedback voltage for each controller from an external

INTV – 1.3V selects pulse-skipping operation.

CC

resistive divider across the output.

SGND (Pin 7): Small-signal ground common to both

+

SENSE1 , SENSE2 (Pin 3, Pin 11): The (+) input to the

differential current comparators are normally connected

to DCR sensing networks or current sensing resistors.

The ITH pin voltage and controlled offsets between the

controllers, must be routed separately from high current

groundstothecommon(–)terminalsoftheC capacitors.

IN

RUN1, RUN2 (Pin 8, Pin 9): Digital Run Control Inputs

for Each Controller. Forcing RUN1 below 1.16V or RUN2

below 1.20V shuts down that controller. Forcing both of

these pins below 0.7V shuts down the entire LTC3890-1,

reducing quiescent current to approximately 14µA.

–

+

SENSE and SENSE pins in conjunction with R

the current trip threshold.

set

SENSE

–

SENSE1 , SENSE2 (Pin 4, Pin 10): The (–) Input to

the Differential Current Comparators. When greater than

–

INTV – 0.5V, the SENSE pin supplies current to the

INTV (Pin19):OutputoftheInternalLinearLowDropout

CC

current comparator.

Regulator.Thedriverandcontrolcircuitsarepoweredfrom

this voltage source. Must be decoupled to power ground

with a minimum of 4.7µF ceramic or other low ESR ca-

FREQ (Pin 5): The Frequency Control Pin for the Internal

VCO. Connecting the pin to GND forces the VCO to a fixed

pacitor. Do not use the INTV pin for any other purpose.

CC

low frequency of 350kHz. Connecting the pin to INTV

CC

forces the VCO to a fixed high frequency of 535kHz.

Other frequencies between 50kHz and 900kHz can be

programmed using a resistor between FREQ and GND.

An internal 20µA pull-up current develops the voltage to

be used by the VCO to control the frequency.

EXTV (Pin 20): External Power Input to an Internal LDO

CC

Connected to INTV . This LDO supplies INTV power,

CC

bypassing the internal LDO powered from V whenever

IN

EXTV is higher than 4.7V. See EXTV Connection in the

CC

Applications Information section. Do not float or exceed

14V on this pin.

PLLIN/MODE (Pin 6): External Synchronization Input to

PhaseDetectorandForcedContinuousModeInput. When

an external clock is applied to this pin, the phase-locked

loop will force the rising TG1 signal to be synchronized

with the rising edge of the external clock. When not syn-

chronizing to an external clock, this input, which acts on

PGND (Pin 21): Driver Power Ground. Connects to the

sources of bottom (synchronous) N-channel MOSFETs

and the (–) terminal(s) of C .

IN

V (Pin 22): Main Supply Pin. A bypass capacitor should

IN

be tied between this pin and the signal ground pin.

38901fb

8

LTC3890-1

PIN FUNCTIONS

BG1, BG2 (Pin 23, Pin 18): High Current Gate Drives

PGOOD1 (Pin 27): Open-Drain Logic Output. PGOOD1 is

for Bottom (Synchronous) N-Channel MOSFETs. Voltage

pulled to ground when the voltage on the V pin is not

FB1

swing at these pins is from ground to INTV .

within 10% of its set point.

CC

BOOST1,BOOST2(Pin24,Pin17):BootstrappedSupplies

to the Topside Floating Drivers. Capacitors are connected

betweentheBOOSTandSWpinsandSchottkydiodesare

tied between the BOOST and INTV_CCpins. Voltage swing

at the BOOST pins is from INTV_CCto (V_IN+ INTV_CC).

TRACK/SS1, TRACK/SS2(Pin28, Pin14):ExternalTrack-

ing and Soft-Start Input. The LTC3890-1 regulates the

V

FB1,2

voltage to the smaller of 0.8V or the voltage on the

TRACK/SS1,2 pin. An internal 1µA pull-up current source

is connected to this pin. A capacitor to ground at this

pin sets the ramp time to final regulated output voltage.

Alternatively, a resistor divider on another voltage supply

connected to this pin allows theLTC3890-1outputto track

the other supply during start-up.

SW1, SW2 (Pin 25, Pin 16): Switch Node Connections

to Inductors.

TG1, TG2 (Pin 26, Pin 15): High Current Gate Drives for

Top N-Channel MOSFETs. These are the outputs of float-

ing drivers with a voltage swing equal to INTV – 0.5V

CC

superimposed on the switch node voltage SW.

38901fb

9

LTC3890-1

FUNCTIONAL DIAGRAM

INTV

V

IN

CC

DUPLICATE FOR SECOND

CONTROLLER CHANNEL

BOOST

D

B

C

B

TG

DROP

OUT

DET

TOP

BOT

+

C

PGOOD1

0.88V

IN

D

BOT

–

SW

TOP ON

V

S

R

Q

FB1

+

INTV

CC

Q

–

SWITCH

LOGIC

0.72V

BG

SHDN

C

OUT

PGND

20µA

FREQ

V

OUT

VCO

CLK2

CLK1

+

–

R

SENSE

0.425V

SLEEP

L

ICMP

IR

–

+

–

PFD

C

LP

+

–

+

3mV

SENSE

SYNC

DET

2.7V

0.65V

PLLIN/MODE

–

100k

SLOPE COMP

V

FB

R

B

+

V

IN

0.80V

TRACK/SS

EA

–

R

A

EXTV

CC

+

–

OV

C

0.88V

ITH

5.1V

LDO

EN

5.1V

LDO

EN

7µA (RUN1)

0.5µA (RUN2)

SHDN

RST

FB

C

R

C

C2

FOLDBACK

1µA

TRACK/SS

+

–

2(V

)

4.7V

11V

C

SHDN

SS

SGND

INTV

RUN

CC

38901 FD

38901fb

10

LTC3890-1

OPERATION ^{(Refer to the Functional Diagram)}

Main Control Loop

Shutdown and Start-Up (RUN1, RUN2 and

TRACK/ SS1, TRACK/SS2 Pins)

The LTC3890-1 uses a constant frequency, current mode

step-down architecture with the two controller channels

operating 180 degrees out-of-phase. During normal op-

eration, each external top MOSFET is turned on when the

clock for that channel sets the RS latch, and is turned off

when the main current comparator, ICMP, resets the RS

latch. The peak inductor current at which ICMP trips and

resets the latch is controlled by the voltage on the ITH pin,

which is the output of the error amplifier, EA. The error

amplifier compares the output voltage feedback signal at

The two channels of the LTC3890-1 can be independently

shutdownusingtheRUN1andRUN2pins.Pullingeitherof

these pins below 1.15V shuts down the main control loop

for that controller. Pulling both pins below 0.7V disables

both controllers and most internal circuits, including the

INTV LDOs. In this state, the LTC3890-1 draws only

CC

14µA of quiescent current.

Releasing either RUN pin allows a small internal current to

pull up the pin to enable that controller. The RUN1 pin has a

7µApull-upcurrentwhiletheRUN2pinhasasmaller0.5µA.

The 7µA current on RUN1 is designed to be large enough

so that the RUN1 pin can be safely floated (to always en-

able the controller) without worry of condensation or other

small board leakage pulling the pin down. This is ideal for

always-on applications where one or both controllers are

enabled continuously and never shut down.

the V pin, (which is generated with an external resistor

FB

divider connected across the output voltage, V , to

OUT

ground)totheinternal0.800Vreferencevoltage.Whenthe

load current increases, it causes a slight decrease in V

FB

relative to the reference, which causes the EA to increase

the ITH voltage until the average inductor current matches

the new load current.

After the top MOSFET is turned off each cycle, the bottom

MOSFETisturnedonuntileithertheinductorcurrentstarts

to reverse, as indicated by the current comparator IR, or

the beginning of the next clock cycle.

The RUN pin may be externally pulled up or driven directly

by logic. When driving the RUN pin with a low impedance

source, do not exceed the absolute maximum rating of

8V. The RUN pin has an internal 11V voltage clamp that

allows the RUN pin to be connected through a resistor to a

INTV /EXTV Power

CC

highervoltage(forexample,V ),solongasthemaximum

IN

Power for the top and bottom MOSFET drivers and most

current into the RUN pin does not exceed 100µA.

other internal circuitry is derived from the INTV pin.

CC

The start-up of each controller’s output voltage V

is

When the EXTV pin is tied to a voltage less than 4.7V,

OUT

CC

controlled by the voltage on the TRACK/SS pin for that

channel. When the voltage on the TRACK/SS pin is less

than the 0.8V internal reference, the LTC3890-1 regulates

the V LDO (low dropout linear regulator) supplies 5.1V

IN

from V to INTV . If EXTV is taken above 4.7V, the V

IN

CC

IN

LDO is turned off and an EXTV LDO is turned on. Once

CC

the V voltage to the TRACK/SS pin voltage instead of the

enabled, the EXTV LDO supplies 5.1V from EXTV to

FB

CC

0.8V reference. This allows the TRACK/SS pin to be used

toprogramasoft-startbyconnectinganexternalcapacitor

from the TRACK/SS pin to SGND. An internal 1µA pull-up

current charges this capacitor creating a voltage ramp on

the TRACK/SS pin. As the TRACK/SS voltage rises linearly

from 0V to 0.8V (and beyond up to 5V), the output voltage

INTV . Using the EXTV pin allows the INTV power

CC

to be derived from a high efficiency external source such

as one of the LTC3890-1 switching regulator outputs.

Each top MOSFET driver is biased from the floating boot-

strap capacitor C , which normally recharges during each

B

cycle through an external diode when the top MOSFET

V

OUT

rises smoothly from zero to its final value.

turns off. If the input voltage, V , decreases to a voltage

IN

Alternatively the TRACK/SS pin can be used to cause the

start-up of V to track that of another supply. Typically,

close to V , the loop may enter dropout and attempt

OUT

to turn on the top MOSFET continuously. The dropout

detector detects this and forces the top MOSFET off for

about one-twelfth of the clock period every tenth cycle to

OUT

this requires connecting to the TRACK/SS pin an external

resistor divider from the other supply to ground (see the

Applications Information section).

allow C to recharge.

B

38901fb

11

LTC3890-1

OPERATION ^{(Refer to the Functional Diagram)}

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping, or Forced Continuous Mode)

(PLLIN/MODE Pin)

just before the inductor current reaches zero, preventing

it from reversing and going negative. Thus, the controller

operates in discontinuous operation.

The LTC3890-1 can be enabled to enter high efficiency

BurstModeoperation, constantfrequency pulse-skipping

mode, or forced continuous conduction mode at low load

currents. To select Burst Mode operation, tie the PLLIN/

MODE pin to a DC voltage below 0.8V (e.g., SGND). To

select forced continuous operation, tie the PLLIN/MODE

In forced continuous operation or clocked by an external

clock source to use the phase-locked loop (see Frequency

Selection and Phase-Locked Loop section), the inductor

current is allowed to reverse at light loads or under large

transient conditions. The peak inductor current is deter-

mined by the voltage on the ITH pin, just as in normal

operation. In this mode, the efficiency at light loads is

lower than in Burst Mode operation. However, continuous

operation has the advantage of lower output voltage ripple

and less interference to audio circuitry. In forced continu-

ousmode,theoutputrippleisindependentofloadcurrent.

pin to INTV . To select pulse-skipping mode, tie the

CC

PLLIN/MODE pin to a DC voltage greater than 1.2V and

less than INTV – 1.3V.

CC

WhenacontrollerisenabledforBurstModeoperation, the

minimum peak current in the inductor is set to approxi-

mately 25% of the maximum sense voltage even though

the voltage on the ITH pin indicates a lower value. If the

average inductor current is higher than the load current,

the error amplifier, EA, will decrease the voltage on the

ITH pin. When the ITH voltage drops below 0.425V, the

internal sleep signal goes high (enabling sleep mode)

and both external MOSFETs are turned off. The ITH pin is

then disconnected from the output of the EA and parked

at 0.450V.

WhenthePLLIN/MODEpinisconnectedforpulse-skipping

mode, the LTC3890-1 operates in PWM pulse-skipping

mode at light loads. In this mode, constant frequency

operation is maintained down to approximately 1% of

designedmaximumoutputcurrent. Atverylightloads, the

current comparator, ICMP, may remain tripped for several

cycles and force the external top MOSFET to stay off for

the same number of cycles (i.e., skipping pulses). The

inductor current is not allowed to reverse (discontinuous

operation). This mode, like forced continuous operation,

exhibits low output ripple as well as low audio noise and

reduced RF interference as compared to Burst Mode

operation. It provides higher low current efficiency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

In sleep mode, much of the internal circuitry is turned off,

reducing the quiescent current that the LTC3890-1 draws.

If one channel is shut down and the other channel is in

sleep mode, the LTC3890-1 draws only 50µA of quiescent

current. Ifbothchannelsareinsleepmode, theLTC3890-1

draws only 60µA of quiescent current. In sleep mode,

the load current is supplied by the output capacitor. As

the output voltage decreases, the EA’s output begins to

rise. When the output voltage drops enough, the ITH pin

is reconnected to the output of the EA, the sleep signal

goes low, and the controller resumes normal operation

by turning on the top external MOSFET on the next cycle

of the internal oscillator.

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

Theselectionofswitchingfrequencyisatrade-offbetween

efficiency and component size. Low frequency opera-

tion increases efficiency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

WhenacontrollerisenabledforBurstModeoperation, the

inductorcurrentisnotallowedtoreverse. Thereversecur-

rentcomparator,IR,turnsoffthebottomexternalMOSFET

The switching frequency of the LTC3890-1’s controllers

can be selected using the FREQ pin.

38901fb

12

LTC3890-1

OPERATION ^{(Refer to the Functional Diagram)}

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to SGND, tied to

INTV_CCorprogrammedthroughanexternalresistor.Tying

FREQtoSGNDselects350kHzwhiletyingFREQtoINTV_CC

selects 535kHz. Placing a resistor between FREQ and

SGND allows the frequency to be programmed between

50kHz and 900kHz, as shown in Figure 10.

MOSFET is turned off and the bottom MOSFET is turned

on until the overvoltage condition is cleared.

Power Good (PGOOD1 Pin)

ThePGOOD1pinisconnectedtoanopendrainofaninternal

N-channel MOSFET. The MOSFET turns on and pulls the

PGOOD1 pin low when the corresponding V pin volt-

FB1

age is not within 10% of the 0.8V reference voltage. The

A phase-locked loop (PLL) is available on the LTC3890-1

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC3890-1’s phase detector adjusts the voltage (through

an internal lowpass filter) of the VCO input to align the

turn-on of controller 1’s external top MOSFET to the ris-

ing edge of the synchronizing signal. Thus, the turn-on

of controller 2’s external top MOSFET is 180 degrees out

of phase to the rising edge of the external clock source.

PGOOD1 pin is also pulled low when the corresponding

RUN1 pin is low (shut down). When the V pin voltage

FB1

is within the 10% requirement, the MOSFET is turned

off and the pin is allowed to be pulled up by an external

resistor to a source no greater than 6V.

Foldback Current

When the output voltage falls to less than 70% of its

nominal level, foldback current limiting is activated, pro-

gressively lowering the peak current limit in proportion to

the severity of the overcurrent or short-circuit condition.

Foldback current limiting is disabled during the soft-start

The VCO input voltage is prebiased to the operating

frequency set by the FREQ pin before the external clock

is applied. A resistor connected between the FREQ pin

and SGND can prebias VCO’s input voltage to the desired

frequency. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG1. The ability to

prebias the loop filter allows the PLL to lock-in rapidly

without deviating far from the desired frequency.

interval (as long as the V voltage is keeping up with the

FB

TRACK/SS voltage).

Theory and Benefits of 2-Phase Operation

Why the need for 2-phase operation? Up until the 2-phase

family, constant-frequency dual switching regulators

operated both channels in phase (i.e., single phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

input capacitor and battery. These large amplitude current

pulses increased the total RMS current flowing from the

input capacitor, requiring the use of more expensive input

capacitorsandincreasingbothEMIandlossesintheinput

capacitor and battery.

The typical capture range of the phase-locked loop is

from approximately 55kHz to 1MHz, with a guarantee

to be between 75kHz and 850kHz. In other words, the

LTC3890-1’sPLL isguaranteed to lock to anexternal clock

source whose frequency is between 75kHz and 850kHz.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.2V (falling).

Output Overvoltage Protection

With 2-phase operation, the two channels of the dual

switchingregulatorareoperated180degreesout-of-phase.

Thiseffectivelyinterleavesthecurrentpulsesdrawnbythe

switches,greatlyreducingtheoverlaptimewheretheyadd

An overvoltage comparator guards against transient over-

shoots as well as other more serious conditions that may

overvoltage the output. When the V pin rises by more

FB

than 10% above its regulation point of 0.800V, the top

38901fb

13

LTC3890-1

OPERATION ^{(Refer to the Functional Diagram)}

together. The result is a significant reduction in total RMS

input current, which in turn allows less expensive input

capacitors to be used, reduces shielding requirements for

EMI and improves real world operating efficiency.

the RMS input current varies for single phase and 2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

It can readily be seen that the advantages of 2-phase op-

eration are not just limited to a narrow operating range,

for most applications is that 2-phase operation will reduce

the input capacitor requirement to that for just one chan-

nel operating at maximum current and 50% duty cycle.

Figure1comparestheinputwaveformsforarepresentative

single-phase dual switching regulator to the LTC3890-1

2-phase dual switching regulator. An actual measure-

ment of the RMS input current under these conditions

shows that 2-phase operation dropped the input current

3.0

from 2.53A

to 1.55A

. While this is an impressive

RMS

SINGLE PHASE

reduction in itself, remember that the power losses are

DUAL CONTROLLER

2.5

2.0

1.5

1.0

0.5

0

2

proportionaltoI

,meaningthattheactualpowerwasted

RMS

is reduced by a factor of 2.66. The reduced input ripple

voltage also means less power is lost in the input power

path, which could include batteries, switches, trace/con-

nectorresistancesandprotectioncircuitry.Improvements

in both conducted and radiated EMI also directly accrue

as a result of the reduced RMS input current and voltage.

2-PHASE

DUAL CONTROLLER

V

O1

V

O2

= 5V/3A

= 3.3V/3A

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

0

10

20

30

40

INPUT VOLTAGE (V)

38901 F02

Figure 2. RMS Input Current Comparison

voltage V (Duty Cycle = V /V ). Figure 2 shows how

IN

OUT IN

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

38901 F01

I

= 2.53A

I = 1.55A

IN(MEAS) RMS

IN(MEAS)

RMS

Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching Regulators

Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator Allows

Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efficiency

38901fb

14

LTC3890-1

APPLICATIONS INFORMATION

The Typical Application on the first page is a basic

LTC3890-1applicationcircuit.LTC3890-1canbeconfigured

to use either DCR (inductor resistance) sensing or low

valueresistorsensing.Thechoicebetweenthetwocurrent

sensing schemes is largely a design trade-off between

cost, power consumption, and accuracy. DCR sensing

is becoming popular because it saves expensive current

sensing resistors and is more power efficient, especially

in high current applications. However, current sensing

resistors provide the most accurate current limits for the

controller. Other external component selection is driven

by the load requirement, and begins with the selection of

programmed current limit unpredictable. If inductor DCR

sensing is used (Figure 4b), sense resistor R1 should be

placed close to the switching node, to prevent noise from

coupling into sensitive small-signal nodes.

TO SENSE FILTER,

NEXT TO THE CONTROLLER

C

OUT

38901 F03

INDUCTOR OR R

SENSE

Figure 3. Sense Lines Placement with Inductor or Sense Resistor

R

(if R

is used) and inductor value. Next, the

SENSE

V

powerMOSFETsandSchottkydiodesareselected. Finally,

input and output capacitors are selected.

V

IN

INTV

CC

BOOST

TG

+

–

SENSE and SENSE Pins

R

SENSE

SW

V

OUT

+

–

The SENSE and SENSE pins are the inputs to the current

comparators. The common mode voltage range on these

pins is 0V to 28V (abs max), enabling the LTC3890-1 to

regulate output voltages up to a nominal 24V (allowing

margin for tolerances and transients).

LTC3890-1

BG

R1*

+

SENSE

PLACE CAPACITOR NEAR

SENSE PINS

C1*

–

SENSE

SGND

+

The SENSE pin is high impedance over the full common

*R1 AND C1 ARE OPTIONAL.

38901 F04a

mode range, drawing at most 1µA. This high impedance

allows the current comparators to be used in inductor

DCR sensing.

(4a) Using a Resistor to Sense Current

V

INTV

V

IN

–

The impedance of the SENSE pin changes depending on

CC

–

the common mode voltage. When SENSE is less than

INDUCTOR

DCR

BOOST

TG

INTV – 0.5V, a small current of less than 1µA flows out

CC

L

–

of the pin. When SENSE is above INTV + 0.5V, a higher

SW

V

OUT

CC

LTC3890-1

current (~700µA) flows into the pin. Between INTV

–

CC

BG

0.5V and INTV + 0.5V, the current transitions from the

CC

R1

C1* R2

+

smaller current to the higher current.

SENSE

Filter components mutual to the sense lines should be

placed close to the LTC3890-1, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 3). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

–

SENSE

SGND

38901 F04b

R2

R1 + R2

L

DCR

||

(R1 R2) • C1 =

*PLACE C1 NEAR

SENSE PINS

R

= DCR

SENSE(EQ)

(4b) Using the Inductor DCR to Sense Current

Figure 4. Current Sensing Methods

38901fb

15

LTC3890-1

APPLICATIONS INFORMATION

Low Value Resistor Current Sensing

the DCR is greater than the target sense resistor value.

To properly dimension the external filter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature; consult

the manufacturers’ data sheets for detailed information.

A typical sensing circuit using a discrete resistor is shown

in Figure 4a. R

output current.

is chosen based on the required

SENSE

The current comparator has a maximum threshold

. The current comparator threshold voltage

V

SENSE(MAX)

Using the inductor ripple current value from the Inductor

Value Calculation section, the target sense resistor value is:

sets the peak of the inductor current, yielding a maximum

average output current, I

, equal to the peak value less

MAX

V_SENSE(MAX)

half the peak-to-peak ripple current, ∆I . To calculate the

L

R_SENSE(EQUIV)

=

sense resistor value, use the equation:

∆I_L

I_MAX

+

2

V_SENSE(MAX)

R_SENSE

=

∆I_L

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimumvaluefortheMaximumCurrentSenseThreshold

I_MAX

+

2

To ensure that the application will deliver full load current

over the full operating temperature range, choose the

minimumvaluefortheMaximumCurrentSenseThreshold

(V

).

SENSE(MAX)

Next, determine the DCR of the inductor. When provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefficient of copper resistance, which is approximately

(V

).

SENSE(MAX)

When using the controller in very low dropout conditions,

the maximum output current level will be reduced due to

the internal compensation required to meet stability cri-

terion for buck regulators operating at greater than 50%

duty factor. A curve is provided in the Typical Performance

Characteristics section to estimate this reduction in peak

inductorcurrentdependingupontheoperatingdutyfactor.

0.4%/°C. A conservative value for T

is 100°C.

L(MAX)

To scale the maximum inductor DCR to the desired sense

resistor value (R ), use the divider ratio:

D

R_SENSE(EQUIV)

R_D=

DCR_MAXatT

L(MAX)

Inductor DCR Sensing

C1 is usually selected to be in the range of 0.1µF to 0.47µF.

ThisforcesR1||R2toaround2k, reducingerrorthatmight

For applications requiring the highest possible efficiency

at high load currents, the LTC3890-1 is capable of sensing

the voltage drop across the inductor DCR, as shown in

Figure 4b. The DCR of the inductor represents the small

amount of DC resistance of the copper wire, which can be

lessthan1mΩfortoday’slowvalue,highcurrentinductors.

In a high current application requiring such an inductor,

power loss through a sense resistor would cost several

points of efficiency compared to inductor DCR sensing.

+

have been caused by the SENSE pin’s 1µA current.

The equivalent resistance R1|| R2 is scaled to the room

temperature inductance and maximum DCR:

L

R1||R2 =

DCR at 20°C • C1

(

)

The sense resistor values are:

If the external (R1||R2) • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

theinductorDCRmultipliedbyR2/(R1+R2).R2scalesthe

voltage across the sense terminals for applications where

R1||R2

R_D

R1•R_D

1– R_D

R1=

; R2 =

38901fb

16

LTC3890-1

APPLICATIONS INFORMATION

The maximum power loss in R1 is related to duty cycle,

and will occur in continuous mode at the maximum input

voltage:

25% of the current limit determined by R

. Lower

SENSE

inductor values (higher ∆I ) will cause this to occur at

L

lower load currents, which can cause a dip in efficiency in

the upper range of low current operation. In Burst Mode

operation, lower inductance values will cause the burst

frequency to decrease.

V

_IN(MAX)– V_OUT• V

(

)

OUT

P_LOSSR1=

R1

Ensure that R1 has a power rating higher than this value.

If high efficiency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor, due

totheextraswitchinglossesincurredthroughR1.However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efficiency at heavy loads.

Peak efficiency is about the same with either method.

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efficiency converters generally cannot

affordthecorelossfoundinlowcostpowderedironcores,

forcingtheuseofmoreexpensiveferriteormolypermalloy

cores. Actual core loss is independent of core size for a

fixedinductorvalue,butitisverydependentoninductance

value selected. As inductance increases, core losses go

down. Unfortunately, increased inductance requires more

turns of wire and therefore copper losses will increase.

Inductor Value Calculation

Ferrite designs have very low core loss and are preferred

for high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates hard, which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efficiency. A higher

frequency generally results in lower efficiency because of

MOSFET switching and gate charge losses. In addition to

this basic trade-off, the effect of inductor value on ripple

currentandlowcurrentoperationmustalsobeconsidered.

Power MOSFET and Schottky Diode

(Optional) Selection

The inductor value has a direct effect on ripple current. The

inductor ripple current, ∆I , decreases with higher induc-

L

Two external power MOSFETs must be selected for each

controller in the LTC3890-1: one N-channel MOSFET for

the top (main) switch, and one N-channel MOSFET for the

bottom (synchronous) switch.

tance or higher frequency and increases with higher V :

IN









V_OUT

1

∆I_L=

V

1–

_OUT

f L

( ) ( )

V



IN

Thepeak-to-peakdrivelevelsaresetbytheINTV voltage.

CC

Accepting larger values of ∆I allows the use of low in-

This voltage is typically 5.1V during start-up (see EXTV

L

CC

ductances, but results in higher output voltage ripple and

Pin Connection). Consequently, logic-level threshold

greater core losses. A reasonable starting point for setting

MOSFETs must be used in most applications. Pay close

ripple current is ∆I =0.3(I

). The maximum ∆I occurs

L

attentiontotheBV specificationfortheMOSFETsaswell.

L

MAX

DSS

at the maximum input voltage.

Selection criteria for the power MOSFETs include the

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

on-resistance, R

, Miller capacitance, C

, input

DS(ON)

MILLER

voltage and maximum output current. Miller capacitance,

C

, can be approximated from the gate charge curve

MILLER

38901fb

17

LTC3890-1

APPLICATIONS INFORMATION

usually provided on the MOSFET manufacturers’ data

The term (1+ δ) is generally given for a MOSFET in the

sheet. C

is equal to the increase in gate charge

form of a normalized R

vs Temperature curve, but

MILLER

DS(ON)

along the horizontal axis while the curve is approximately

flat divided by the specified change in V . This result is

δ = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

DS

then multiplied by the ratio of the application applied V

DS

The optional Schottky diodes D3 and D4 shown in

Figure 11 conduct during the dead-time between the

conduction of the two power MOSFETs. This prevents

the body diode of the bottom MOSFET from turning on,

storing charge during the dead-time and requiring a

reverse recovery period that could cost as much as 3%

to the Gate charge curve specified V . When the IC is

DS

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

V_OUT

Main Switch Duty Cycle =

V

IN

in efficiency at high V . A 1A to 3A Schottky is generally

IN

V − V

IN

OUT

a good compromise for both regions of operation due

to the relatively small average current. Larger diodes

result in additional transition losses due to their larger

junction capacitance.

Synchronous Switch Duty Cycle =

V

IN

The MOSFET power dissipations at maximum output

current are given by:

C and C

Selection

IN

OUT

V_OUT

2

P_MAIN

=

I

1+ δ R

+

)

(

_MAX) (

)

DS(ON)

The selection of C is simplified by the 2-phase architec-

V

IN

ture and its impact on the worst-case RMS current drawn

throughtheinputnetwork(battery/fuse/capacitor).Itcanbe

shown that the worst-case capacitor RMS current occurs

when only one controller is operating. The controller with



²









I_MAX

2

V

R

(

C

)

(

•

(

)

IN

DR

MILLER









1

+

f



( )

the highest (V )(I ) product needs to be used in the

OUT OUT

V_INTVCC– V_THMIN

V

_THMIN

formula shown in Equation 1 to determine the maximum

RMS capacitor current requirement. Increasing the out-

put current drawn from the other controller will actually

decrease the input RMS ripple current from its maximum

value. The out-of-phase technique typically reduces the

input capacitor’s RMS ripple current by a factor of 30%

to 70% when compared to a single phase power supply

solution.

V – V

2

IN

OUT

P

I

1+ δ R

(

_MAX) (

)

SYNC

DS(ON)

V

IN

where δ is the temperature dependency of R

and

DS(ON)

R

(approximately 2Ω) is the effective driver resistance

DR

at the MOSFET’s Miller threshold voltage. V

typical MOSFET minimum threshold voltage.

is the

THMIN

Incontinuousmode,thesourcecurrentofthetopMOSFET

is a square wave of duty cycle (V )/(V ). To prevent

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

2

BothMOSFETshaveI RlosseswhilethetopsideN-channel

equation includes an additional term for transition losses,

OUT

IN

which are highest at high input voltages. For V < 20V

IN

the high current efficiency generally improves with larger

MOSFETs, while for V > 20V the transition losses rapidly

IN

I_MAX

increasetothepointthattheuseofahigherR

device





^1/2



DS(ON)

(1)

C_INRequired I_RMS

≈

V

V – V

IN

OUT

(

)

(

)

OUT

withlowerC

actuallyprovideshigherefficiency.The

MILLER

V_IN

synchronous MOSFET losses are greatest at high input

voltage when the top switch duty factor is low or during

a short-circuit when the synchronous switch is on close

to 100% of the period.

This formula has a maximum at V = 2V , where I

IN

OUT

RMS

= I /2. This simple worst-case condition is commonly

OUT

usedfordesignbecauseevensignificantdeviationsdonot

38901fb

18

LTC3890-1

APPLICATIONS INFORMATION

offermuchrelief.Notethatcapacitormanufacturers’ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operatingfrequencyoftheLTC3890-1, ceramiccapacitors

The output ripple is highest at maximum input voltage

since ∆I increases with input voltage.

L

Setting Output Voltage

The LTC3890-1 output voltages are each set by an exter-

nal feedback resistor divider carefully placed across the

output, as shown in Figure 5. The regulated output voltage

is determined by:

can also be used for C . Always consult the manufacturer

IN

if there is any question.









R_B

R_A

The benefit of the LTC3890-1 2-phase operation can be

calculatedbyusingEquation1forthehigherpowercontrol-

ler and then calculating the loss that would have resulted

if both controller channels switched on at the same time.

The total RMS power lost is lower when both controllers

are operating due to the reduced overlap of current pulses

required through the input capacitor’s ESR. This is why

the input capacitor’s requirement calculated above for the

worst-case controller is adequate for the dual controller

design. Also, the input protection fuse resistance, battery

resistance, and PC board trace resistance losses are also

reduced due to the reduced peak currents in a 2-phase

system. The overall benefit of a multiphase design will

only be fully realized when the source impedance of the

power supply/battery is included in the efficiency testing.

The drains of the top MOSFETs should be placed within

V_OUT= 0.8V 1+





To improve the frequency response, a feedforward ca-

pacitor, C , may be used. Great care should be taken to

FF

route the V line away from noise sources, such as the

FB

inductor or the SW line.

V

OUT

R

B

C

FF

1/2 LTC3890-1

V

FB

R

A

38901 F05

Figure 5. Setting Output Voltage

Tracking and Soft-Start (TRACK/SS Pins)

1cmofeachotherandshareacommonC (s). Separating

IN

The start-up of each V

is controlled by the voltage on

OUT

the drains and C may produce undesirable voltage and

IN

the respective TRACK/SS pin. When the voltage on the

TRACK/SS pin is less than the internal 0.8V reference, the

current resonances at V .

IN

A small (0.1µF to 1µF) bypass capacitor between the chip

LTC3890-1 regulates the V pin voltage to the voltage on

FB

V

pin and ground, placed close to the LTC3890-1, is

IN

the TRACK/SS pin instead of 0.8V. The TRACK/SS pin can

also suggested. A 10Ω resistor placed between C (C1)

IN

be used to program an external soft-start function or to

and the V pin provides further isolation between the

two channels.

IN

allow V

to track another supply during start-up.

OUT

Soft-start is enabled by simply connecting a capacitor

from the TRACK/SS pin to ground, as shown in Figure 6.

An internal 1µA current source charges the capacitor,

providing a linear ramping voltage at the TRACK/SS pin.

The selection of C

is driven by the effective series

OUT

resistance (ESR). Typically, once the ESR requirement

is satisfied, the capacitance is adequate for filtering. The

output ripple (∆V ) is approximated by:

OUT

The LTC3890-1 will regulate the V pin (and hence V

)

FB

OUT

according to the voltage on the TRACK/SS pin, allowing









1

∆V_OUT≈ ∆I ESR+

_L

V

OUT

to rise smoothly from 0V to its final regulated value.

8 • f • C_OUT



The total soft-start time will be approximately:

where f is the operating frequency, C

is the output

OUT

0.8V

1µA

t_SS= C_SS

•

capacitance and ∆I is the ripple current in the inductor.

L

38901fb

19

LTC3890-1

APPLICATIONS INFORMATION

1/2 LTC3890-1

TRACK/SS

V

X(MASTER)

C

SS

SGND

38901 F06

OUT(SLAVE)

Figure 6. Using the TRACK/SS Pin to Program Soft-Start

Alternatively, the TRACK/SS pin can be used to track two

(or more) supplies during start-up, as shown qualitatively

in Figures 7a and 7b. To do this, a resistor divider should

38901 F07a

TIME

be connected from the master supply (V ) to the TRACK/

X

(7a) Coincident Tracking

SS pin of the slave supply (V ), as shown in Figure 8.

OUT

During start-up V

will track V according to the ratio

OUT

X

set by the resistor divider:

V

X(MASTER)

OUT(SLAVE)

R_TRACKA+ R_TRACKB

R_A+ R_B

V_X

R_A

=

•

V_OUTR_TRACKA

For coincident tracking (V

= V during start-up):

X

OUT

R = R

A

TRACKA

TRACKB

R = R

B

38901 F07b

TIME

INTV Regulators

CC

(7b) Ratiometric Tracking

The LTC3890-1 features two separate internal P-channel

low dropout linear regulators (LDO) that supply power at

Figure 7. Two Different Modes of Output Voltage Tracking

theINTV pinfromeithertheV supplypinortheEXTV

CC

IN

CC

pindependingontheconnectionoftheEXTV pin.INTV

CC

powers the gate drivers and much of the LTC3890-1’s

V

OUT

x

internalcircuitry.TheV LDOandtheEXTV LDOregulate

IN

CC

INTV to 5.1V. Each of these can supply a peak current of

CC

1/2 LTC3890-1

R

B

50mA and must be bypassed to ground with a minimum

of 4.7µF ceramic capacitor. No matter what type of bulk

capacitor is used, an additional 1µF ceramic capacitor

V

FB

R

A

R

TRACKB

placed directly adjacent to the INTV and PGND IC pins is

TRACK/SS

CC

38901 F08

highlyrecommended.Goodbypassingisneededtosupply

the high transient currents required by the MOSFET gate

drivers and to prevent interaction between the channels.

TRACKA

Figure 8. Using the TRACK/SS Pin for Tracking

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3890-1 to be

exceeded. The INTV current, which is dominated by the

CC

gate charge current, may be supplied by either the V

IN

LDO or the EXTV LDO. When the voltage on the EXTV

CC

38901fb

20

LTC3890-1

APPLICATIONS INFORMATION

pin is less than 4.7V, the V LDO is enabled. Power dis-

an 8.5V supply reduces the junction temperature in the

previous example from 125°C to:

IN

sipation for the IC in this case is highest and is equal to

V

• I

. The gate charge current is dependent on

IN

INTVCC

T = 70°C + (15mA)(8.5V)(90°C/W) = 82°C

J

operating frequency as discussed in the Efficiency Con-

siderations section. The junction temperature can be

estimated by using the equations given in Note 3 of the

Electrical Characteristics. For example, the LTC3890-1

However,for3.3Vandotherlowvoltageoutputs,additional

circuitryisrequiredtoderiveINTV powerfromtheoutput.

CC

The following list summarizes the four possible connec-

INTV current is limited to less than 15mA from a 40V

CC

tions for EXTV :

CC

supply when not using the EXTV supply at 70°C ambi-

CC

1. EXTV Grounded.ThiswillcauseINTV tobepowered

CC

ent temperature:

fromtheinternal5.1Vregulatorresultinginanefficiency

T = 70°C + (15mA)(40V)(90°C/W) = 125°C

J

penalty of up to 10% at high input voltages.

To prevent the maximum junction temperature from be-

ing exceeded, the input supply current must be checked

while operating in forced continuous mode (PLLIN/MODE

2. EXTV Connected directly to V . This is the normal

CC

OUT

connection for a 5V to 14V regulator and provides the

highest efficiency.

= INTV ) at maximum V .

CC

IN

3. EXTV ConnectedtoanExternalsupply. Ifanexternal

CC

When the voltage applied to EXTV rises above 4.7V, the

CC

supply is available in the 5V to 14V range, it may be

V LDO is turned off and the EXTV LDO is enabled. The

IN

CC

used to power EXTV providing it is compatible with

CC

EXTV LDO remains on as long as the voltage applied to

CC

the MOSFET gate drive requirements. Ensure that

EXTV remains above 4.5V. The EXTV LDO attempts

CC

EXTV < V .

CC

IN

to regulate the INTV voltage to 5.1V, so while EXTV

CC

4. EXTV ConnectedtoanOutput-DerivedBoostNetwork.

CC

is less than 5.1V, the LDO is in dropout and the INTV

For 3.3V and other low voltage regulators, efficiency

voltage is approximately equal to EXTV . When EXTV

CC

gains can still be realized by connecting EXTV to an

CC

is greater than 5.1V, up to an absolute maximum of 14V,

output-derivedvoltagethathasbeenboostedtogreater

INTV is regulated to 5.1V.

CC

than 4.7V. This can be done with the capacitive charge

Using the EXTV_CCLDO allows the MOSFET driver and

control power to be derived from one of the LTC3890-1’s

switching regulator outputs (4.7V ≤ V_OUT≤ 14V) during

normal operation and from the V_INLDO when the out-

put is out of regulation (e.g., start-up, short-circuit). If

more current is required through the EXTV_CCLDO than

is specified, an external Schottky diode can be added

between the EXTV_CCand INTV_CCpins. In this case, do

not apply more than 6V to the EXTV_CCpin and make sure

that EXTV_CC≤ V_IN.

pump shown in Figure 9. Ensure that EXTV < V .

CC

IN

C

IN

BAT85

V

IN

MTOP

MBOT

NDS7002

TG1

1/2 LTC3890-1

L

R

SENSE

V

EXTV

SW

OUT

CC

Significant efficiency and thermal gains can be realized

C

D

BG1

OUT

by powering INTV from the output, since the V cur-

CC

IN

rent resulting from the driver and control currents will be

scaled by a factor of (Duty Cycle)/(Switcher Efficiency).

For 5V to 14V regulator outputs, this means connecting

38901 F09

PGND

Figure 9. Capacitive Charge Pump for EXTV_CC

the EXTV pin directly to V . Tying the EXTV pin to

CC

OUT

CC

38901fb

21

LTC3890-1

APPLICATIONS INFORMATION

than this amount in shutdown, INTV can be loaded

Topside MOSFET Driver Supply (C , D )

CC

B

with an external resistor or clamped with a Zener diode.

Alternatively, the PGOOD resistor can be used to sink the

Externalbootstrapcapacitors,C ,connectedtotheBOOST

B

pinssupplythegatedrivevoltagesforthetopsideMOSFETs.

current (assuming the resistor pulls up to INTV ) since

CC

Capacitor C in the Functional Diagram is charged though

B

PGOOD is pulled low when the converter is shut down.

Nonetheless, using a low-leakage diode is the best choice

to maintain low quiescent current under all conditions.

external diode D from INTV when the SW pin is low.

B

CC

When one of the topside MOSFETs is to be turned on, the

driver places the C voltage across the gate-source of the

B

desired MOSFET. This enhances the top MOSFET switch

Fault Conditions: Current Limit and Current Foldback

and turns it on. The switch node voltage, SW, rises to V

IN

The LTC3890-1 includes current foldback to help limit

load current when the output is shorted to ground. If

the output voltage falls below 70% of its nominal output

level, then the maximum sense voltage is progressively

lowered from 100% to 45% of its maximum selected

value. Under short-circuit conditions with very low duty

cycles, the LTC3890-1 will begin cycle skipping in order to

limit the short-circuit current. In this situation the bottom

MOSFET will be dissipating most of the power but less

than in normal operation. The short-circuit ripple current

and the BOOST pin follows. With the topside MOSFET

on, the boost voltage is above the input supply: V

=

BOOST

V + V

. The value of the boost capacitor, C , needs

IN

INTVCC

B

to be 100 times that of the total input capacitance of the

topsideMOSFET(s).Thereversebreakdownoftheexternal

Schottky diode must be greater than V

.

IN(MAX)

The external diode D can be a Schottky diode or silicon

B

diode, but in either case it should have low-leakage and

fast recovery. Pay close attention to the reverse leakage

current specification for this diode, especially at high

temperatures where it generally increases substantially.

For applications with output voltages greater than ~5V

is determined by the minimum on-time. t

, of the

ON(MIN)

LTC3890-1 (≈90ns), the input voltage and inductor value:









V

L

^IN

∆I_L(SC)= t

^ON(MIN)

that are switching infrequently, a leaky diode D can fully

B

discharge the bootstrap capacitor C , creating a current

B

path from the output voltage to the BOOST pin to INTV .

CC

The resulting average short-circuit current is:

Not only does this increase the quiescent current of the

1

2

converter, but it can cause INTV to rise to dangerous

CC

I_SC= 45% •I_LIM(MAX)– ∆I_L(SC)

levels if the leakage exceeds the current consumption on

INTV .

CC

Fault Conditions: Overvoltage Protection (Crowbar)

Particularly, this is a concern in Burst Mode operation at

no load or very light loads, where the part is switching

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the regulator rises

muchhigherthannominallevels.Thecrowbarcauseshuge

currents to flow, that blow the fuse to protect against a

shorted top MOSFET if the short occurs while the control-

ler is operating.

very infrequently and the current draw on INTV is very

CC

low (typically about 35µA). Generally, pulse-skipping and

forced continuous modes are less sensitive to leakage,

since the more frequent switching keeps the bootstrap

capacitor C charged, preventing a current path from the

B

output voltage to INTV .

CC

A comparator monitors the output for overvoltage condi-

tions. The comparator detects faults greater than 10%

above the nominal output voltage. When this condition

is sensed, the top MOSFET is turned off and the bottom

MOSFET is turned on until the overvoltage condition is

cleared. ThebottomMOSFETremainsoncontinuouslyfor

However, in cases where the converter has been operat-

ing (in any mode) and then is shut down, if the leakage

of diode D fully discharges the bootstrap capacitor C

B

before the output voltage discharges to below ~5V, then

the leakage current path can be created from the output

aslongastheovervoltageconditionpersists;ifV returns

OUT

voltage to INTV . In shutdown, the INTV pin is able to

CC

to a safe level, normal operation automatically resumes.

sink about 30µA. To accommodate diode leakage greater

38901fb

22

LTC3890-1

APPLICATIONS INFORMATION

1000

900

800

700

600

500

400

300

200

100

0

AshortedtopMOSFETwillresultinahighcurrentcondition

which will open the system fuse. The switching regulator

will regulate properly with a leaky top MOSFET by altering

the duty cycle to accommodate the leakage.

Phase-Locked Loop and Frequency Synchronization

The LTC3890-1 has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass filter,

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET of controller 1 to be locked to

the rising edge of an external clock signal applied to the

PLLIN/MODEpin.Theturn-onofcontroller2’stopMOSFET

is thus 180 degrees out of phase with the external clock.

The phase detector is an edge sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

15 25 35 45 55 65 75 85 95 105 115 125

FREQ PIN RESISTOR (kΩ)

38901 F10

Figure 10. Relationship Between Oscillator Frequency

and Resistor Value at the FREQ Pin

frequency be near external clock frequency, doing so will

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

If the external clock frequency is greater than the internal

oscillator’sfrequency,f ,thencurrentissourcedcontinu-

OSC

Table 2 summarizes the different states in which the FREQ

pin can be used.

ously from the phase detector output, pulling up the VCO

input. When the external clock frequency is less than f

,

OSC

current is sunk continuously, pulling down the VCO input.

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal filter capacitor,

CLP, holds the voltage at the VCO input.

Table 2

FREQ PIN

PLLIN/MODE PIN

DC Voltage

FREQUENCY

350kHz

0V

INTV

DC Voltage

535kHz

CC

Resistor

DC Voltage

50kHz to 900kHz

Any of the Above

External Clock

Phase-Locked to

External Clock

Minimum On-Time Considerations

Minimum on-time, t , is the smallest time dura-

tion that the LTC3890-1 is capable of turning on the top

MOSFET. It is determined by internal timing delays and the

gate charge required to turn on the top MOSFET. Low duty

cycle applications may approach this minimum on-time

limit and care should be taken to ensure that:

Note that the LTC3890-1 can only be synchronized to an

external clock whose frequency is within range of the

LTC3890-1’s internal VCO, which is nominally 55kHz to

1MHz.Thisisguaranteedtobebetween75kHzand850kHz.

ON(MIN)

Typically,theexternalclock(onthePLLIN/MODEpin)input

highthresholdis1.6V,whiletheinputlowthresholdis1.1V.

V_OUT

V f

_IN( )

RapidphaselockingcanbeachievedbyusingtheFREQpin

to set a free-running frequency near the desired synchro-

nization frequency. The VCO’s input voltage is prebiased

at a frequency corresponding to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase lock and synchro-

nization. Although it is not required that the free-running

t_ON(MIN)

<

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

38901fb

23

LTC3890-1

APPLICATIONS INFORMATION

(Efficiency). For example, in a 20V to 5V application,

Theminimumon-timefortheLTC3890-1isapproximately

90ns. However, as the peak sense voltage decreases the

minimum on-time gradually increases up to about TBDns.

This is of particular concern in forced continuous applica-

tions with low ripple current at light loads. If the duty cycle

drops below the minimum on-time limit in this situation,

a significant amount of cycle skipping can occur with cor-

respondingly larger current and voltage ripple.

10mAofINTV currentresultsinapproximately2.5mA

CC

of V current. This reduces the midcurrent loss from

IN

10% or more (if the driver was powered directly from

V ) to only a few percent.

IN

2

3. I R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current flows through L and

Efficiency Considerations

R

, but is chopped between the topside MOSFET

SENSE

The percent efficiency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efficiency and which change would

produce the most improvement. Percent efficiency can

be expressed as:

andthesynchronousMOSFET.IfthetwoMOSFETshave

approximately the same R

, then the resistance

DS(ON)

of one MOSFET can simply be summed with the resis-

2

tances of L, R

and ESR to obtain I R losses. For

DS(ON)

SENSE

example, if each R

= 30mΩ, R = 50mΩ, R

L SENSE

= 10mΩ and R

= 40mΩ (sum of both input and

ESR

output capacitance losses), then the total resistance

is 130mΩ. This results in losses ranging from 3% to

13% as the output current increases from 1A to 5A for

a 5V output, or a 4% to 20% loss for a 3.3V output.

%Efficiency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Efficiency varies as the inverse square of V

for the

OUT

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3890-1 circuits: 1) IC V_INcurrent, 2) INTV_CC

regulator current, 3) I²R losses, 4) topside MOSFET

sameexternalcomponentsandoutputpowerlevel. The

combined effects of increasingly lower output voltages

andhighercurrentsrequiredbyhighperformancedigital

systemsisnotdoublingbutquadruplingtheimportance

of loss terms in the switching regulator system!

transition losses

.

1. The V current is the DC supply current given in the

IN

4. Transition losses apply only to the topside MOSFET(s),

and become significant only when operating at high

ElectricalCharacteristicstable,whichexcludesMOSFET

driverandcontrolcurrents. V currenttypicallyresults

IN

input voltages (t

ypically 15V or greater). Transition

in a small (<0.1%) loss.

losses can be estimated from:

2. INTV current is the sum of the MOSFET driver and

CC

Transition Loss = (1.7) • V • 2 • I

• C

• f

IN

O(MAX)

RSS

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5%

to 10% efficiency degradation in portable systems. It

is very important to include these system level losses

during the design phase. The internal battery and fuse

resistancelossescanbeminimizedbymakingsurethat

from INTV to ground. The resulting dQ/dt is a current

CC

out of INTV that is typically much larger than the

CC

control circuit current. In continuous mode, I

GATECHG

= f(Q + Q ), where Q and Q are the gate charges of

T

B

T

B

C has adequate charge storage and very low ESR at

IN

the topside and bottom side MOSFETs.

the switching frequency. A 25W supply will typically

require a minimum of 20µF to 40µF of capacitance

having a maximum of 20mΩ to 50mΩ of ESR. The

LTC3890-1 2-phase architecture typically halves this

SupplyingINTV fromanoutput-derivedsourcepower

CC

through EXTV will scale the V current required for

CC

IN

thedriverandcontrolcircuitsbyafactorof(DutyCycle)/

38901fb

24

LTC3890-1

APPLICATIONS INFORMATION

input capacitance requirement over competing solu-

tions.OtherlossesincludingSchottkyconductionlosses

during dead-time and inductor core losses generally

account for less than 2% total additional loss.

Placing a power MOSFET directly across the output ca-

pacitor and driving the gate with an appropriate signal

generator is a practical wayto producea realistic load step

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better

to look at the ITH pin signal which is in the feedback loop

andisthefilteredandcompensatedcontrolloopresponse.

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, V_OUTshifts by an

amount equal to ∆I_LOAD(ESR), where ESR is the effective

seriesresistanceofC_OUT. ∆I_LOADalsobeginstochargeor

discharge C_OUTgenerating the feedback error signal that

forces the regulator to adapt to the current change and

return V_OUTto its steady-state value. During this recovery

time V_OUTcan be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values. The availability of the ITH pin not only allows

optimization of control loop behavior, but it also provides

a DC coupled and AC filtered closed-loop response test

point. The DC step, rise time and settling at this test

point truly reflects the closed-loop response. Assuming

apredominantlysecondordersystem,phasemarginand/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also

be estimated by examining the rise time at the pin. The

ITH external components shown in Figure 13 circuit will

provide an adequate starting point for most applications.

The gain of the loop will be increased by increasing R

C

and the bandwidth of the loop will be increased by de-

creasing C . If R is increased by the same factor that C

C

is decreased, the zero frequency will be kept the same,

thereby keeping the phase shift the same in the most

critical frequency range of the feedback loop. The output

voltage settling behavior is related to the stability of the

closed-loopsystemandwilldemonstratetheactualoverall

supply performance.

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

dischargedbypasscapacitorsareeffectivelyputinparallel

with C , causing a rapid drop in V . No regulator can

OUT

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

C

LOAD

to C

is greater than 1:50, the switch rise time

OUT

should be controlled so that the load rise time is limited

to approximately 25 • C . Thus a 10µF capacitor would

LOAD

require a 250µs rise time, limiting the charging current

to about 200mA.

The ITH series R -C filter sets the dominant pole-zero

C

Design Example

loop compensation. The values can be modified slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the final PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1µs to 10µs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop.

As a design example for one channel, assume V

=

IN

= 5A,

12V(nominal), V = 22V (max), V

= 3.3V, I

IN

OUT

MAX

V

= 75mV and f = 350kHz.

SENSE(MAX)

Theinductancevalueischosenfirstbasedona30%ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the FREQ pin

to GND, generating 350kHz operation. The minimum

inductance for 30% ripple current is:







V_OUT

f L

( ) ( )

V_OUT





∆I_L=

1–

_IN(NOM)

V



38901fb

25

LTC3890-1

APPLICATIONS INFORMATION

A 4.7µH inductor will produce 29% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 5.73A. Increasing the ripple

current will also help ensure that the minimum on-time

of 95ns is not violated. The minimum on-time occurs at

C is chosen for an RMS current rating of at least 3A at

IN

temperature assuming only this channel is on. C

is

OUT

chosen with an ESR of 0.02Ω for low output ripple. The

output ripple in continuous mode will be highest at the

maximum input voltage. The output voltage ripple due to

ESR is approximately:

maximum V :

IN

V_OUT

3.3V

V

= R

(∆I ) = 0.02Ω(1.45A) = 29mV

ORIPPLE

ESR L P-P

t_ON(MIN)

=

= 429ns

V

f

22V 350kHz

_IN(MAX)( )

(

)

PC Board Layout Checklist

The equivalent R

using the minimum value for the maximum current sense

threshold (43mV):

resistor value can be calculated by

SENSE

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layoutdiagramofFigure11.Figure12illustratesthecurrent

waveforms present in the various branches of the 2-phase

synchronousregulatorsoperatinginthecontinuousmode.

Check the following in your layout:

64mV

5.73A

R_SENSE

≤

≈ 0.01Ω

Choosing 1% resistors: R = 25k and R = 78.7k yields

an output voltage of 3.32V.

A

B

1. Are the top N-channel MOSFETs MTOP1 and MTOP2

located within 1cm of each other with a common drain

ThepowerdissipationonthetopsideMOSFETcanbeeasily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

connection at C ? Do not attempt to split the input

IN

decoupling for the two channels as it can cause a large

results in: R

= 0.035Ω/0.022Ω, C

= 215pF. At

DS(ON)

MILLER

resonant loop.

maximum input voltage with T(estimated) = 50°C:

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

3.3V

22V

²



P_MAIN

=

5A 1+ 0.005 50°C – 25°C

(

)

(

)

(

)





of C

must return to the combined C

(–) ter-

INTVCC

OUT

₂5A

0.035Ω + 22V

) (

2.5Ω 215pF •

) (

(

)

(

)

minals. The path formed by the top N-channel MOSFET,

2

Schottky diode and the C capacitor should have short

IN







1

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop described above.

+

350kHz = 331mW

(

)







5V – 2.3V 2.3V

A short-circuit to ground will result in a folded back cur-

rent of:













95ns 22V

34mV

0.01Ω 2

1

3. DotheLTC3890-1V pins’resistivedividersconnectto

(

)

FB

I_SC=

–

= 3.18A

the (+) terminals of C ? The resistive divider must be

OUT

4.7µH

connected between the (+) terminal of C

and signal

OUT

ground. The feedback resistor connections should not

be along the high current input feeds from the input

capacitor(s).

with a typical value of R

and δ = (0.005/°C)(25°C)

DS(ON)

= 0.125. The resulting power dissipated in the bottom

MOSFET is:

2

P

= 3.18A 1.125 0.022Ω

(

) (

)

SYNC

= 250mW

which is less than under full-load conditions.

38901fb

26

LTC3890-1

APPLICATIONS INFORMATION

–

+

suggest noise pickup at the current or voltage sensing

inputs or inadequate loop compensation. Overcompensa-

tion of the loop can be used to tame a poor PC layout if

regulatorbandwidthoptimizationisnotrequired.Onlyafter

each controller is checked for its individual performance

should both controllers be turned on at the same time.

A particularly difficult region of operation is when one

controller channel is nearing its current comparator trip

pointwhentheotherchannelisturningonitstopMOSFET.

This occurs around 50% duty cycle on either channel due

to the phasing of the internal clocks and may cause minor

duty cycle jitter.

4. Are the SENSE and SENSE leads routed together with

minimumPCtracespacing?Thefiltercapacitorbetween

+

–

SENSE and SENSE should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the SENSE resistor.

5. Is the INTV decoupling capacitor connected close

CC

to the IC, between the INTV and the power ground

CC

pins? This capacitor carries the MOSFET drivers’ cur-

rent peaks. An additional 1µF ceramic capacitor placed

immediatelynexttotheINTV andPGNDpinscanhelp

CC

improve noise performance substantially.

6. Keep the switching nodes (SW1, SW2), top gate nodes

(TG1, TG2), andboostnodes(BOOST1, BOOST2)away

from sensitive small-signal nodes, especially from

the opposites channel’s voltage and current sensing

feedback pins. All of these nodes have very large and

fast moving signals and therefore should be kept on

the output side of the LTC3890-1 and occupy minimum

PC trace area.

Reduce V from its nominal level to verify operation of

IN

the regulator in dropout. Check the operation of the un-

dervoltage lockout circuit by further lowering V while

IN

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

7.Useamodifiedstargroundtechnique:alowimpedance,

large copper area central grounding point on the same

side of the PC board as the input and output capacitors

with tie-ins for the bottom of the INTV decoupling

CC

capacitor, the bottom of the voltage feedback resistive

divider and the SGND pin of the IC.

PC Board Layout Debugging

for inductive coupling between C , Schottky and the top

IN

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductorwhiletestingthecircuit.Monitortheoutputswitch-

ing node (SW pin) to synchronize the oscilloscope to the

internal oscillator and probe the actual output voltage as

well. Check for proper performance over the operating

voltage and current range expected in the application.

The frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 25% of the maximum designed current level in

Burst Mode operation.

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

Thedutycyclepercentageshouldbemaintainedfromcycle

to cycle in a well-designed, low noise PCB implementa-

tion. Variation in the duty cycle at a subharmonic rate can

38901fb

27

LTC3890-1

APPLICATIONS INFORMATION

ITH1

TRACK/SS1

PGOOD1

TG1

R

PU1

V

PULL-UP

V

PGOOD1

FB1

L1

R

R1*

C1*

SENSE

D1*

V

+

–

OUT1

SENSE1

SW1

C

B1

LTC3890-1

BOOST1

M1

M2

BG1

FREQ

R

IN

C

OUT1

V

f

IN

1µF

CERAMIC

IN

PLLIN/MODE

RUN1

+

C

VIN

PGND

GND

RUN2

+

EXTV

CC

C

IN

+

V

SGND

C

IN

INTVCC

–

INTV

SENSE2

C

OUT2

1µF

C2*

CERAMIC

+

SENSE2

BG2

R2*

M4

L2

M3

D2*

BOOST2

V

FB2

C

B2

SW2

TG2

ITH2

R

SENSE

V

OUT2

TRACK/SS2

38901 F11

*R1, R2, C1, C2, D1, D2 ARE OPTIONAL.

Figure 11. Recommended Printed Circuit Layout Diagram

38901fb

28

LTC3890-1

APPLICATIONS INFORMATION

SW1

L1

R

SENSE1

V

OUT1

D1

C

R

L1

OUT1

V

IN

R

IN

C

IN

SW2

L2

R

SENSE2

V

OUT2

D2

C

R

L2

OUT2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

38901 F12

Figure 12. Branch Current Waveforms

38901fb

29

LTC3890-1

TYPICAL APPLICATIONS

+

–

SENSE1

INTV

C1

1nF

CC

R

B1

100k

R

PGOOD1

BG1

A1

31.6k

V

FB1

C

100pF

R

ITH1A

MBOT1

R

SENSE1

8mΩ

V

3.3V

5A

OUT1

C

1000pF

ITH1

SW1

ITH1

34.8k

L1

BOOST1

ITH1

4.7µH

C

OUT1

470µF

C

LTC3890-1

C

SS1

0.01µF

B1

0.1µF

TRACK/SS1

TG1

MTOP1

D1

V

IN

V

IN

9V TO 60V

C

IN

220µF

PLLIN/MODE

SGND

INTV

CC

C

INT

4.7µF

PGND

EXTV

V

CC

OUT2

RUN1

RUN2

FREQ

R

FREQ

41.2k

D2

TG2

MTOP2

C

SS2

0.01µF

C

0.1µF

B2

L2

8µH

R

TRACK/SS2

ITH2

BOOST2

SW2

SENSE2

R

ITH2

34.8k

C

470pF

10mΩ

V

8.5V

3A

ITH2

R

OUT2

C

OUT2

A2

10.5k

330µF

MBOT2

V

BG2

FB2

R

B2

100k

–

SENSE2

C2

1nF

+

SENSE2

38901 TA02a

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1: COILCRAFT SER1360-472KL

L2: COILCRAFT SER1360-802KL

C

: SANYO 6TPE470M

: SANYO 10TPE330M

OUT1

OUT2

D1, D2: DFLS1100

Figure 13. High Efficiency Dual 8.5V/3.3V Step-Down Converter

Efficiency and Power Loss

vs Output Current

Efficiency vs Load Current

Efficiency vs Input Voltage

10000

1000

100

90

80

70

60

50

40

30

20

100

90

80

70

60

50

40

30

20

100

98

96

94

92

90

88

86

84

V

= 12V

IN

OUT

V

= 8.5V

BURST EFFICIENCY

OUT

= 3.3V

V

OUT

= 3.3V

V

= 8.5V

OUT2

CCM LOSS

BURST LOSS

PULSE-SKIPPING

LOSS

10

V

OUT1

= 3.3V

CCM EFFICIENCY

1

PULSE-SKIPPING

EFFICIENCY

10

0

10

0

82

80

V

IN

= 12V

I

= 2A

LOAD

5

0.1

10

0.0001 0.001

0.01

0.1

1

0.0001 0.001

0.01

0.1

1

10

0

10 15 20 25 30 35 40 45 50 55 60

OUTPUT CURRENT (A)

INPUT VOLTAGE (V)

38901 TA02b

38901 TA02c

38901 TA02d

38901fb

30

LTC3890-1

TYPICAL APPLICATIONS

High Efficiency 8.5V Dual-Phase Step-Down Converter

+

–

SENSE1

INTV

C1

1nF

CC

R

B1

100k

R

A1

PGOOD1

BG1

10.5k

V

FB1

MBOT1

C

100pF

ITH1A

L1

8µH

V

8.5V

6A

OUT1

SW1

R

ITH1

34.8k

R

SENSE1

BOOST1

ITH1

10mΩ

C

OUT1

330µF

C

ITH1

C

SS1

0.01µF

LTC3890-1

B1

470pF

0.1µF

TRACK/SS1

TG1

MTOP1

D1

V

IN

INTV

V

R

CC

IN

MODE

9V TO 60V

C

100k

IN

220µF

PLLIN/MODE

SGND

INTV

CC

C

INT

4.7µF

R

PGND

RUN

1000k

V

OUT

EXTV

CC

V

IN

RUN1

RUN2

FREQ

D2

R

FREQ

41.2k

TG2

MTOP2

C

0.1µF

B2

TRACK/SS2

C

ITH2

100pF

R

L2

8µH

BOOST2

SW2

SENSE2

10mΩ

ITH2

C

OUT2

MBOT2

BG2

330µF

V

FB2

–

+

SENSE2

C2

1nF

SENSE2

38901 TA03

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1, L2: COILCRAFT SER1360-802KL

C

, C

: SANYO 10TPE330M

OUT1 OUT2

D1, D2: DFLS1100

38901fb

31

LTC3890-1

TYPICAL APPLICATIONS

High Efficiency Dual 12V/5V Step-Down Converter

+

SENSE1

INTV

CC

C1

1nF

R

B1

100k

–

PGOOD1

BG1

SENSE1

R

A1

6.98k

V

FB1

C

100pF

R

ITH1A

MBOT1

R

SENSE1

9mΩ

V

12V

3A

OUT1

C

470pF

ITH1

SW1

34.8k

L1

8µH

C

OUT1

BOOST1

ITH1

180µF

C

LTC3890-1

TRACK/SS1

C

SS1

0.01µF

B1

0.47µF

TG1

MTOP1

D1

V

IN

V

IN

12.5V TO 60V

C

IN

220µF

PLLIN/MODE INTV

SGND

CC

C

INT

4.7µF

PGND

EXTV

CC

RUN1

RUN2

FREQ

R

FREQ

D2

41.2k

TG2

MTOP2

C

0.47µF

C

SS2

0.01µF

B2

L2

4.7µH

R

BOOST2

SW2

SENSE2

TRACK/SS2

ITH2

10mΩ

V

5V

5A

OUT2

R

ITH2

20k

C

470pF

ITH2

C

OUT2

MBOT2

BG2

470µF

R

A2

18.7k

V

FB2

–

+

SENSE2

R

B2

C2

1nF

100k

SENSE2

38901 TA04

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1: COILCRAFT SER1360-802KL

L2: COILCRAFT SER1360-472KL

C

: 16SVP180MX

OUT1

OUT2

: SANYO 6TPE470M

D1, D2: DFLS1100

38901fb

32

LTC3890-1

TYPICAL APPLICATIONS

High Efficiency Dual 24V/5V Step-Down Converter

R

B1

487k

+

SENSE1

INTV

CC

C1

1nF

C

33pF

F1

100k

–

SENSE1

PGOOD1

BG1

R

A1

16.9k

V

FB1

C

100pF

R

ITH1A

L1

22µH

MBOT1

MTOP1

R

SENSE1

V

24V

1A

25mΩ

OUT1

C

680pF

ITH1

46k

ITH1

SW1

BOOST1

ITH1

C

OUT1

22µF

C

LTC3890-1

TRACK/SS1

C

SS1

0.01µF

B1

×2 CERAMIC

0.47µF

TG1

D1

V

IN

V

IN

28V TO 60V

C

IN

220µF

PLLIN/MODE INTV

SGND

CC

C

INT

4.7µF

PGND

EXTV

CC

RUN1

RUN2

FREQ

R

FREQ

D2

60k

TG2

MTOP2

C

0.47µF

C

SS2

0.01µF

R

B2

L2

4.7µH

R

BOOST2

SW2

SENSE2

TRACK/SS2

ITH2

10mΩ

V

C

470pF

ITH2

20k

OUT2

5V

5A

ITH2

C

OUT2

MBOT2

BG2

470µF

V

FB2

R

A2

R

B2

100k

18.7k

–

+

SENSE2

C2

1nF

38901 TA05

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1: SUMIDA CDR7D43MN

L2: COILCRAFT SER1360-472KL

C

: KEMET T525D476MO16E035

: SANYO 6TPE470M

OUT1

OUT2

C

D1, D2: DFLS1100

38901fb

33

LTC3890-1

PACKAGE DESCRIPTION

GN Package

28-Lead Plastic SSOP (Narrow .150 Inch)

(Reference LTC DWG # 05-08-1641)

.386 – .393*

(9.804 – 9.982)

.045 ±.005

.033

(0.838)

REF

28 27 26 25 24 23 22 21 20 19 18 17 1615

.254 MIN

.150 – .165

.229 – .244

.150 – .157**

(5.817 – 6.198)

(3.810 – 3.988)

.0165 ±.0015

.0250 BSC

1

2

3

4

5

6

7

8

9 10 11 12 13 14

RECOMMENDED SOLDER PAD LAYOUT

.015 ± .004

(0.38 ± 0.10)

.0532 – .0688

(1.35 – 1.75)

× 45°

.004 – .0098

(0.102 – 0.249)

.0075 – .0098

(0.19 – 0.25)

0° – 8° TYP

.016 – .050

(0.406 – 1.270)

.008 – .012

.0250

(0.635)

BSC

GN28 (SSOP) 0204

(0.203 – 0.305)

TYP

NOTE:

1. CONTROLLING DIMENSION: INCHES

INCHES

2. DIMENSIONS ARE IN

(MILLIMETERS)

3. DRAWING NOT TO SCALE

*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE

**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD

FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE

38901fb

34

LTC3890-1

REVISION HISTORY

REV

DATE

01/11 Added MP-grade and H-grade. Changes reflected throughout the data sheet.

10/12 Added INTV to Absolute Maximum Ratings

DESCRIPTION

PAGE NUMBER

A

1-36

2

B

CC

38901fb

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

35

LTC3890-1

TYPICAL APPLICATION

High Efficiency Dual 12V/3.3V Step-Down Converter

+

SENSE1

INTV

CC

C1

1nF

R

B1

100k

–

PGOOD1

BG1

SENSE1

R

A1

6.98k

V

FB1

C

100pF

R

ITH1A

MBOT1

R

SENSE1

9mΩ

V

12V

3A

OUT1

C

470pF

ITH1

SW1

34.8k

L1

8µH

C

OUT1

BOOST1

ITH1

180µF

C

LTC3890-1

C

SS1

0.01µF

B1

0.47µF

TRACK/SS1

TG1

MTOP1

D1

V

IN

V

IN

12.5V TO 60V

C

IN

220µF

PLLIN/MODE

SGND

INTV

CC

C

INT

4.7µF

PGND

V

OUT1

EXTV

CC

RUN1

RUN2

FREQ

R

FREQ

D2

41.2k

TG2

MTOP2

C

0.47µF

C

SS2

0.01µF

B2

L2

4.7µH

R

BOOST2

SW2

SENSE2

TRACK/SS2

ITH2

10mΩ

V

3.3V

5A

OUT2

R

ITH2

34.8k

C

1000pF

ITH2

C

ITH2A

OUT2

MBOT2

BG2

100pF

470µF

V

FB2

R

A2

–

+

SENSE2

31.6k

R

B2

C2

1nF

MTOP1, MTOP2, MBOT1, MBOT2: RJK0651DPB

L1: COILCRAFT SER1360-802KL

100k

L2: COILCRAFT SER1360-472KL

SENSE2

C

: 16SVP180MX

: SANYO 6TPE470M

OUT1

OUT2

D1, D2: DFLS1100

38901 TA06

RELATED PARTS

PART NUMBER

DESCRIPTION

COMMENTS

LT3891

60V, Low I , Synchronous Step-Down DC/DC Controller

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 60V,

IN

Q

0.8V ≤ V

≤ 24V, TSSOP-20E, 3mm × 4mm QFN-20

OUT

LTC3857/LTC3857-1/ Low I , Dual Output 2-Phase Synchronous Step-Down

PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ V ≤ 38V,

IN

Q

LTC3858/LTC3858-1 DC/DC Controllers with 99% Duty Cycle

0.8V ≤ V

≤ 24V, I = 50µA/170µA

OUT Q

LTC3834/LTC3834-1/ Low I , Single Output Synchronous Step-Down

PLL Fixed Frequency 140kHz to 650kHz, 4V ≤ V ≤ 36V,

IN

Q

LTC3835/LTC3835-1 DC/DC Controllers with 99% Duty Cycle

0.8V ≤ V

≤ 10V, I = 30µA/80µA

OUT Q

LTC3810

100V Synchronous Step-Down DC/DC Controller

Constant On-Time Valley Current Mode, 4V ≤ V ≤ 100V,

IN

0.8V ≤ V

≤ 0.93V , SSOP-28

IN

OUT

LTC3859

Low I , Triple Output Buck/Buck/Boost Synchronous

Outputs (≥5V) Remain in Regulation Through Cold Crank,

2.5V ≤ V ≤ 38V, V Up to 24V, V Up to 60V

Q

DC/DC Controller

IN

OUT(BUCK)

OUT(BOOST)

38901fb

LT 1012 REV B • PRINTED IN USA

36 ^{LinearTechnology Corporation}

1630 McCarthy Blvd., Milpitas, CA 95035-7417

●

 LINEAR TECHNOLOGY CORPORATION 2010

(408) 432-1900 FAX: (408) 434-0507 www.linear.com


型号：	LTC3890HGN-1#PBF
厂家：	Linear
描述：	LTC3890-1 - 60V Low IQ, Dual, 2-Phase Synchronous Step-Down DC/DC Controller; Package: SSOP; Pins: 28; Temperature Range: -40°C to 125°C 开关光电二极管
文件：	总36页 (文件大小：876K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC3890HGN-1#PBF [Linear]

相关型号：

LTC3890HUH#PBF

LTC3890HUH-2#PBF

LTC3890IGN-1

LTC3890IGN-1#PBF

LTC3890IGN-1#TRPBF

LTC3890IGN-1PBF

LTC3890IGN-1TRPBF

LTC3890IGN-3#PBF

LTC3890IUH

LTC3890IUH#PBF

LTC3890IUH-2#PBF

LTC3890IUHPBF