LTC2170-12 [Linear]
14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs; 14位,125Msps / 105MSPS / 80Msps的低功耗八通道ADC型号: | LTC2170-12 |
厂家: | Linear |
描述: | 14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs |
文件: | 总36页 (文件大小:449K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Electrical SpecificatiLonTsMSub9je0ct1to1C-h1an4g/e
LTM9010-14/LTM9009-14
14-Bit, 125Msps/105Msps/
80Msps Low Power Octal ADCs
FeaTures
DescripTion
The LTM®9011-14/LTM9010-14/LTM9009-14 are 8-channel,
simultaneous sampling 14-bit A/D converters designed
for digitizing high frequency, wide dynamic range signals.
AC performance includes 73.1dB SNR and 88dB spurious
free dynamic range (SFDR). Low power consumption per
channel reduces heat in high channel count applications.
Integrated bypass capacitance and flow-through pinout
reduces overall board space requirements.
n
8-Channel Simultaneous Sampling ADC
n
73.1dB SNR
n
88dB SFDR
n
Low Power: 140mW/113mW/94mW per Channel
n
Single 1.8V Supply
n
Serial LVDS Outputs: 1 or 2 Bits per Channel
n
Selectable Input Ranges: 1V to 2V
P-P
P-P
n
n
n
n
800MHz Full Power Bandwidth S/H
Shutdown and Nap Modes
DC specs include 1LSB INL (typ), 0.3LSB DNL (typ) and
no missing codes over temperature. The transition noise
Serial SPI Port for Configuration
Internal Bypass Capacitance, No External
Components
is a low 1.2LSB
.
RMS
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
per channel option (1-lane mode).
n
140-Pin (9mm × 11.25mm) BGA Package
applicaTions
n
Communications
+
–
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n
Cellular Base Stations
n
Software Defined Radios
n
Portable Medical Imaging
n
Multichannel Data Acquisition
n
Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V
1.8V
OV
LTM9011-14, 125Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
V
DD
DD
CHANNEL 1
ANALOG
INPUT
0
–10
–20
–30
–40
14-BIT
OUT1A
OUT1B
S/H
S/H
ADC CORE
CHANNEL 2
ANALOG
INPUT
OUT2A
OUT2B
14-BIT
ADC CORE
DATA
SERIALIZER
–50
–60
–70
SERIALIZED
LVDS
OUTPUTS
CHANNEL 8
ANALOG
INPUT
OUT8A
OUT8B
14-BIT
ADC CORE
S/H
–80
–90
–100
–110
–120
DATA
CLOCK
OUT
ENCODE
INPUT
PLL
FRAME
0
20
30
40
50
60
10
FREQUENCY (MHz)
9009101114 TA01b
GND
OGND
9009101114 TA01
9009101114p
1
LTM9011-14/
LTM9010-14/LTM9009-14
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1, 2)
TOP VIEW
Supply Voltages
V , OV ................................................ –0.3V to 2V
DD
DD
+
–
A
B
C
D
E
Analog Input Voltage (A , A
,
IN
IN
PAR/SER, SENSE) (Note 3)...........–0.3V to (V + 0.2V)
DD
+
–
Digital Input Voltage (ENC , ENC , CS,
SDI, SCK) (Note 4).................................... –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
F
Digital Output Voltage ................ –0.3V to (OV + 0.3V)
Operating Temperature Range
LTM9011C, 9010C, 9009C....................... 0°C to 70°C
LTM9011I, 9010I, 9009I ...................... –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
DD
G
H
J
K
L
M
N
P
1
2
3
4
5
6
7
8
9
10
BGA PACKAGE
140-LEAD (11.25mm × 9.00mm × 2.72mm)
T
JMAX
= 150°C, θ = 28°C/W
JA
orDer inForMaTion
LEAD FREE FINISH
LTM9011CY-14#PBF
LTM9011IY-14#PBF
LTM9010CY-14#PBF
LTM9010IY-14#PBF
LTM9009CY-14#PBF
LTM9009IY-14#PBF
TRAY
PART MARKING*
LTM9011Y14
LTM9011Y14
LTM9010Y14
LTM9010Y14
LTM9009Y14
LTM9009Y14
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTM9011CY-14#PBF
LTM9011IY-14#PBF
LTM9010CY-14#PBF
LTM9010IY-14#PBF
LTM9009CY-14#PBF
LTM9009IY-14#PBF
140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA 0°C to 70°C
140-Lead (11.25mm × 9mm × 2.72mm) BGA –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
9009101114p
2
LTM9011-14/
LTM9010-14/LTM9009-14
converTer characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTM9011-14
LTM9010-14
LTM9009-14
MIN TYP MAX
PARAMETER
CONDITIONS
MIN
14
TYP
MAX
MIN
14
TYP
MAX
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
14
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
–4.1
–0.9
–12
1.2
0.3
3
4.1
0.9
12
–3.25
–0.8
–12
1
0.3
3
3.25 –2.75
1
0.3
3
2.75
0.8
12
LSB
LSB
mV
0.8
12
–0.8
–12
Gain Error
Internal Reference
External Reference
–1.3
–1.3
–1.3
–1.3
–1.3
–1.3
%FS
%FS
l
–2.6
0
–2.6
0
–2.6
0
Offset Drift
20
20
20
µV/°C
Full-Scale Drift
Internal Reference
External Reference
35
25
35
25
35
25
ppm/°C
ppm/°C
Gain Matching
Offset Matching
Transition Noise
External Reference
0.2
3
0.2
3
0.2
3
%FS
mV
External Reference
1.2
1.2
1.2
LSB
RMS
analog inpuT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
1.7V < V < 1.9V
MIN
TYP
MAX
UNITS
+
–
l
l
l
V
V
V
Analog Input Range (A – A
)
+
1 to 2
V
P-P
IN
IN
IN
DD
–
Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)
V
CM
– 100mV
0.625
V
CM
V
CM
+ 100mV
1.300
V
IN(CM)
SENSE
INCM
IN
IN
External Voltage Reference Applied to SENSE External Reference Mode
1.250
V
I
Analog Input Common Mode Current
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
155
130
100
µA
µA
µA
+
–
l
l
l
I
I
I
t
t
Analog Input Leakage Current No Encode
PAR/SER Input Leakage Current
0 < A , A < V
,
DD
–1
–3
–6
1
3
6
µA
µA
µA
ns
IN1
IN
IN
0 < PAR/SER < V
IN2
DD
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
IN3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
Full-Power Bandwidth
0
AP
0.15
80
ps
RMS
JITTER
CMRR
BW-3B
dB
Figure 6 Test Circuit
800
MHz
9009101114p
3
LTM9011-14/
LTM9010-14/LTM9009-14
DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTM9011-14
LTM9010-14
LTM9009-14
MIN TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
SNR
Signal-to-Noise Ratio
5MHz Input
73.1
73
73
73
dBFS
dBFS
dBFS
l
l
l
l
70MHz Input
140MHz Input
71.1
70.7
72.9
72.6
70.9
77
72.9
72.5
72.6
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
88
85
82
88
85
82
88
85
82
dBFS
dBFS
dBFS
70MHz Input
140MHz Input
75
84
75
84
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
90
90
90
90
90
90
90
90
90
dBFS
dBFS
dBFS
70MHz Input
140MHz Input
85
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
73
72.6
72
73
72.6
72
72.9
72.6
72
dBFS
dBFS
dBFS
69.6
70.2
70.4
Crosstalk, Near Channel
Crosstalk, Far Channel
10MHz Input (Note 12)
10MHz Input (Note 12)
–90
–90
–90
dBc
dBc
–105
–105
–105
inTernal reFerence characTerisTics The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
PARAMETER
CONDITIONS
= 0
MIN
TYP
0.5 • V
25
MAX
UNITS
V
V
CM
V
CM
V
CM
V
REF
V
REF
V
REF
V
REF
Output Voltage
I
0.5 • V – 25mV
0.5 • V + 25mV
OUT
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
ppm/°C
Ω
–600µA < I
< 1mA
< 1mA
4
OUT
I
= 0
1.225
1.250
25
1.275
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400µA < I
7
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
9009101114p
4
LTM9011-14/
LTM9010-14/LTM9009-14
DigiTal inpuTs anD ouTpuTs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
–
Differential Encode Mode (ENC Not Tied to GND)
l
V
V
Differential Input Voltage
(Note 8)
0.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
1.2
V
V
ICM
l
l
1.1
0.2
1.6
3.6
+
–
V
IN
Input Voltage Range
Input Resistance
ENC , ENC to GND
(See Figure 10)
V
kΩ
pF
R
10
IN
IN
C
Input Capacitance
3.5
–
Single-Ended Encode Mode (ENC Tied to GND)
l
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
V
V
= 1.8V
= 1.8V
1.2
0
V
V
IH
IL
IN
DD
DD
0.6
3.6
+
ENC to GND
V
R
(See Figure 11)
30
kΩ
pF
IN
IN
C
Input Capacitance
3.5
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 1.8V
1.3
V
V
IH
IL
DD
DD
IN
l
l
= 1.8V
0.6
10
I
IN
= 0V to 3.6V
–10
µA
pF
C
IN
Input Capacitance
3
200
3
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2kΩ Pull-Up Resistor if SDO Is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
= 1.8V, SDO = 0V
DD
Ω
µA
pF
OL
l
I
SDO = 0V to 3.6V
–10
10
OH
C
OUT
DIGITAL DATA OUTPUTS
l
l
V
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
125
350
175
454
250
mV
mV
OD
l
l
V
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.125
1.250
1.250
1.375
1.375
V
V
OS
R
Termination Enabled, OV = 1.8V
100
Ω
TERM
DD
9009101114p
5
LTM9011-14/
LTM9010-14/LTM9009-14
power requireMenTs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTM9011-14
LTM9010-14
LTM9009-14
SYMBOL PARAMETER
CONDITIONS
(Note 10)
MIN TYP MAX MIN
TYP
1.8
MAX MIN TYP MAX UNITS
l
l
l
V
Analog Supply Voltage
Output Supply Voltage
Analog Supply Current
Digital Supply Current
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
V
V
DD
OV
(Note 10)
1.8
DD
I
I
Sine Wave Input
566
610
448
486
368
400
mA
VDD
OVDD
l
l
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
54
98
62
108
52
96
62
106
50
94
58
104
mA
mA
l
l
P
Power Dissipation
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
1116 1210
1196 1292
900
980
986
1066
752
832
824
908
mW
mW
DISS
P
P
P
Sleep Mode Power
Nap Mode Power
2
2
2
mW
mW
mW
SLEEP
NAP
170
40
170
40
170
40
Power Increase With Differential Encode Mode Enabled
(No Increase for Sleep Mode)
DIFFCLK
TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTM9011-14
LTM9010-14
LTM9009-14
MIN TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
MIN
TYP
MAX
l
f
t
Sampling Frequency
(Notes 10,11)
5
125
5
105
5
80
MHz
S
l
l
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
3.8
2
4
4
100
100
4.52
2
4.76
4.76
100
100
5.93
2
6.25
6.25
100
100
ns
ns
ENCL
l
l
t
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
3.8
2
4
4
100
100
4.52
2
4.76
4.76
100
100
5.93
2
6.25
6.25
100
100
ns
ns
ENCH
AP
t
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
SYMBOL PARAMETER
Digital Data Outputs (R
CONDITIONS
= 100Ω Differential, C = 2pF to GND on Each Output)
MIN
TYP
MAX
UNITS
TERM
L
t
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1/(8 • f )
s
s
s
s
s
s
SER
S
1/(7 • f )
S
1/(6 • f )
S
1/(16 • f )
S
1/(14 • f )
S
1/(12 • f )
S
l
l
l
t
t
t
t
t
FR to DCO Delay
DATA to DCO Delay
Propagation Delay
Output Rise Time
Output Fall Time
(Note 8)
0.35 • t
0.35 • t
0.5 • t
0.5 • t
0.65 • t
0.65 • t
s
s
FRAME
DATA
PD
SER
SER
SER
SER
(Note 8)
SER
SER
(Note 8)
0.7n + 2 • t
1.1n + 2 • t
1.5n + 2 • t
SER
s
SER
SER
Data, DCO, FR, 20% to 80%
Data, DCO, FR, 20% to 80%
0.17
0.17
60
ns
ns
R
F
DCO Cycle-Cycle Jitter
Pipeline Latency
t
= 1ns
ps
P-P
SER
6
Cycles
9009101114p
6
LTM9011-14/
LTM9010-14/LTM9009-14
TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
SPI Port Timing (Note 8)
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
t
SCK Period
Write Mode
40
ns
ns
SCK
Read Back Mode, C
= 20pF,
= 20pF,
250
SDO
R
= 2k
PULLUP
l
l
l
l
l
t
t
t
t
t
CS to SCK Setup Time
SCK to CS Setup Time
SDI Setup Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO Valid
Read Back Mode, C
125
SDO
R
= 2k
PULLUP
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 8: Guaranteed by design, not subject to test.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 9: V = OV = 1.8V, f
(LTM9010), or 80MHz (LTM9009), 2-lane output mode, ENC = single-
ended 1.8V square wave, ENC = 0V, input range = 2V with differential
= 125MHz (LTM9011), 105MHz
DD
DD
SAMPLE
+
–
Note 3: When these pin voltages are taken below GND or above V , they
P-P
DD
drive, unless otherwise noted. The supply current and power dissipation
specifications are totals for the entire chip, not per channel.
will be clamped by internal diodes. This product can handle input currents
of greater than 100mA below GND or above V without latchup.
DD
Note 10: Recommended operating conditions.
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
DD
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
data rate is 1000Mbps so t
must be greater than or equal to 1ns.
SER
Note 5: V = OV = 1.8V, f
= 125MHz (LTM9011), 105MHz
DD
DD
SAMPLE
Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.7 to Ch.8.
Far-channel crosstalk refers to Ch.1 to Ch.7, Ch.1 to Ch.8, Ch.2 to Ch.7, and
Ch.2 to Ch.8.
+
(LTM9010), or 80MHz (LTM9009), 2-lane output mode, differential ENC /
–
ENC = 2V sine wave, input range = 2V with differential drive, unless
P-P
P-P
otherwise noted.
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
9009101114p
7
LTM9011-14/
LTM9010-14/LTM9009-14
TiMing DiagraMs
2-Lane Output Mode, 16-Bit Serialization*
t
AP
N+1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
t
SER
PD
–
OUT#A
D5 D3 D1
0
0
D13 D11 D9 D7 D5 D3 D1
0
D13 D11 D9
D12 D10 D8
+
OUT#A
–
OUT#B
D4 D2 D0
SAMPLE N-6
D12 D10 D8 D6 D4 D2 D0
SAMPLE N-5
0
+
OUT#B
SAMPLE N-4
9009101114 TD01
*SEE THE DIGITAL OUTPUTS SECTION
2-Lane Output Mode, 14-Bit Serialization
t
AP
N+2
ANALOG
INPUT
N
N+1
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
t
SER
PD
–
OUT#A
D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9 D7 D5 D3 D1 D13 D11 D9
+
OUT#A
–
OUT#B
D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8 D6 D4 D2 D0 D12 D10 D8
+
OUT#B
SAMPLE N-6
SAMPLE N-5
–
SAMPLE N-4
SAMPLE N-3
9009101114 TD02
+
+
–
NOTE THAT IN THIS MODE FR /FR HAS TWO TIMES THE PERIOD OF ENC /ENC
9009101114p
8
LTM9011-14/
LTM9010-14/LTM9009-14
TiMing DiagraMs
2-Lane Output Mode, 12-Bit Serialization
t
AP
ANALOG
INPUT
N
N+1
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
t
SER
FRAME
DATA
+
FR
–
FR
t
PD
SER
–
OUT#A
D9 D7 D5 D3 D13 D11 D9 D7 D5 D3 D13 D11 D9
+
OUT#A
–
OUT#B
D8 D6 D4 D2 D12 D10 D8 D6 D4 D2 D12 D10 D8
+
OUT#B
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
9009101114 TD03
1-Lane Output Mode, 16-Bit Serialization
t
AP
N+1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
t
SER
PD
–
OUT#A
D1 D0
0
0
D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
0
0
D13 D12 D11 D10
+
OUT#A
9009101114 TD0
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
+
–
OUT#B , OUT#B ARE DISABLED
9009101114p
9
LTM9011-14/
LTM9010-14/LTM9009-14
TiMing DiagraMs
One-Lane Output Mode, 14-Bit Serialization
t
AP
N+1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
t
SER
PD
–
OUT#A
D3 D2 D1 D0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D13 D12 D11 D10
+
OUT#A
SAMPLE N-6
SAMPLE N-5
SAMPLE N-49009101114 TD06
+
–
OUT#B , OUT#B ARE DISABLED
One-Lane Output Mode, 12-Bit Serialization
t
AP
N+1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
t
SER
PD
–
OUT#A
D5 D4 D3 D2 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D13 D12 D11
+
OUT#A
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
9009101114 TD07
+
–
OUT#B , OUT#B ARE DISABLED
9009101114p
10
LTM9011-14/
LTM9010-14/LTM9009-14
TiMing DiagraMs
SPI Port Timing (Readback Mode)
t
S
t
DS
t
DH
t
t
H
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
A3
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SDO
9009101114 TD08
HIGH IMPEDANCE
9009101114p
11
LTM9011-14/
LTM9010-14/LTM9009-14
Typical perForMance characTerisTics
LTM9011-14: Integral
Nonlinearity (INL)
LTM9011-14: Differential
Nonlinearity (DNL)
LTM9011-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 125Msps
2.0
1.5
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
0
8192
12288
16384
0
8192
12288
16384
0
10
20
30
40
50
60
4096
4096
OUTPUT CODE
OUTPUT CODE
FREQUENCY (MHz)
217514 G01
217514 G02
217514 G03
LTM9011-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 125Msps
LTM9011-14: 8k Point FFT, fIN
70MHz –1dBFS, 125Msps
=
LTM9011-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
50
60
0
20
30
40
50
60
10
10
0
20
30
40
50
60
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
217514 G05
217514 G06
217514 G04
LTM9011-14: SNR vs Input
Frequency, –1dB, 2V Range,
125Msps
LTM9011-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
125Msps
LTM9011-14: Shorted Input
Histogram
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
74
73
72
71
70
69
68
67
66
–80
–90
–100
–110
–120
2000
1000
0
0
20
30
40
50
60
8178
8182
8184
8186
10
8180
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
FREQUENCY (MHz)
OUTPUT CODE
217514 G07
217514 G08
217514 G09
9009101114p
12
LTM9011-14/
LTM9010-14/LTM9009-14
Typical perForMance characTerisTics
LTM9011-14: SFDR vs Input
Frequency, –1dB, 2V Range,
125Msps
LTM9011-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
LTM9011-14: SNR vs Input Level,
fIN = 70MHz, 2V Range, 125Msps
95
90
85
80
75
70
65
110
100
90
80
70
60
50
40
30
20
10
0
dBFS
dBFS
80
dBc
70
60
50
40
30
20
10
0
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
50
–70
–60
–50
–40
–30
–20
–10
0
INPUT LEVEL (dBFS)
217514 G10
217514 G11
217514 G50
LTM9011-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTM9011-14: SNR vs SENSE,
IN = 5MHz, –1dB
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dB
f
50
40
30
290
280
270
260
250
74
73
72
71
70
69
2-LANE, 3.5mA
1-LANE, 3.5mA
2-LANE, 1.75mA
20
10
0
240
230
220
210
1-LANE, 1.75mA
68
67
66
0
25
50
75
100
125
0
25
50
75
100
125
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
SENSE PIN (V)
217514 G51
217514 G53
217514 G12
LTM9010-14: Integral Nonlinearity
(INL)
LTM9010-14: Differential
Nonlinearity (DNL)
LTM9010-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 105Msps
2.0
1.5
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
0
8192
12288
16384
0
8192
12288
16384
0
20
30
40
50
4096
4096
10
OUTPUT CODE
OUTPUT CODE
FREQUENCY (MHz)
217514 G14
217514 G15
217514 G16
9009101114p
13
LTM9011-14/
LTM9010-14/LTM9009-14
Typical perForMance characTerisTics
LTM9010-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 105Msps
LTM9010-14: 8k Point FFT, fIN
70MHz –1dBFS, 105Msps
=
LTM9010-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
50
0
10
20
30
40
50
0
10
20
30
40
50
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
217514 G17
217514 G18
217514 G19
LTM9010-14: SNR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTM9010-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
105Msps
LTM9010-14: Shorted Input
Histogram
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
74
73
72
71
70
69
68
67
66
–80
–90
–100
–110
–120
2000
1000
0
0
20
30
40
50
8195
8199
8201
8203
10
8197
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
FREQUENCY (MHz)
OUTPUT CODE
217514 G20
217514 G21
217514 G22
LTM9010-14: SFDR vs Input
Frequency, –1dB, 2V Range,
105Msps
LTM9010-14: SFDR vs Input Level,
LTM9010-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
f
IN = 70MHz, 2V Range, 105Msps
95
90
85
80
75
70
65
110
100
90
230
220
210
200
dBFS
80
70
60
50
40
30
20
10
0
190
180
170
160
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
25
50
75
100
–70
SAMPLE RATE (Msps)
217514 G23
217514 G24
217514 G54
9009101114p
14
LTM9011-14/
LTM9010-14/LTM9009-14
Typical perForMance characTerisTics
LTM9010-14: SNR vs SENSE,
fIN = 5MHz, –1dB
LTM9009-14: Integral Nonlinearity
(INL)
LTM9009-14: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
74
73
72
71
70
69
2.0
1.5
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
68
67
66
0
8192
12288
16384
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
8192
12288
16384
4096
4096
OUTPUT CODE
SENSE PIN (V)
OUTPUT CODE
217514 G27
217514 G25
217514 G26
LTM9009-14: 8k Point FFT, fIN = 30MHz
–1dBFS, 80Msps
LTM9009-14: 8k Point FFT, fIN
70MHz –1dBFS, 80Msps
=
LTM9009-14: 8k Point FFT, fIN = 5MHz
–1dBFS, 80Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
0
20
30
40
0
20
30
40
10
10
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
217514 G29
217514 G30
217514 G28
LTM9009-14: 8k Point 2-Tone FFT,
fIN = 70MHz, 75MHz, –1dBFS,
80Msps
LTM9009-14: 8k Point FFT, fIN = 140MHz
–1dBFS, 80Msps
LTM9009-14: Shorted Input
Histogram
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
–80
–90
–100
–110
–120
–80
–90
–100
–110
–120
2000
1000
0
0
20
30
40
10
0
20
30
40
8184
8188
8190
8192
10
8186
FREQUENCY (MHz)
FREQUENCY (MHz)
OUTPUT CODE
217514 G32
217514 G31
217514 G33
9009101114p
15
LTM9011-14/
LTM9010-14/LTM9009-14
Typical perForMance characTerisTics
LTM9009-14: SNR vs Input
Frequency, –1dB, 2V Range,
80Msps
LTM9009-14: SFDR vs Input
Frequency, –1dB, 2V Range,
80Msps
LTM9009-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
74
73
72
71
70
95
90
85
80
75
70
65
110
100
90
dBFS
80
70
60
50
40
30
20
10
0
69
68
67
66
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
0
50
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
217514 G34
217514 G35
217514 G36
LTM9009-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dB
LTM9009-14: SNR vs SENSE,
fIN = 5MHz, –1dB
DCO Cycle-Cycle Jitter vs Serial
Data Rate
190
180
170
160
350
300
250
200
150
74
73
72
71
70
69
100
50
0
68
67
66
150
140
0
20
40
60
80
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
200
400
600
800
1000
SAMPLE RATE (Msps)
SENSE PIN (V)
SERIAL DATA RATE (Mbps)
217514 G55
217514 G37
217514 G52
9009101114p
16
LTM9011-14/
LTM9010-14/LTM9009-14
pin FuncTions
+
+
–
A
A
V
(B2): Channel 1 Positive Differential Analog Input.
A
A
V
(N1): Channel 8 Positive Differential Analog Input.
(N2): Channel 8 Negative Differential Analog Input
IN1
IN8
IN8
DD
–
(B1): Channel 1 Negative Differential Analog Input.
IN1
(B3): Common Mode Bias Output, Nominally Equal
(D3, D4, E3, E4, K3, K4, L3, L4): 1.8V Analog Power
CM12
to V /2. V should be used to bias the common mode
Supply. V is internally bypassed to ground with 0.1μF
DD
CM
DD
of the analog inputs of channels 1 and 2. V is internally
ceramic capacitors.
CM
bypassed to ground with a 0.1µF ceramic capacitor. No
+
ENC (P5): Encode Input. Conversion starts on the rising
external capacitance is required.
edge.
+
A
A
A
A
V
(C2): Channel 2 Positive Differential Analog Input.
(C1): Channel 2 Negative Differential Analog Input.
(E2): Channel 3 Positive Differential Analog Input.
(E1): Channel 3 Negative Differential Analog Input.
(F3): Common Mode Bias Output, Nominally Equal
–
IN2
IN2
IN3
IN3
ENC (P6): Encode Complement Input. Conversion starts
–
+
–
on the falling edge.
CSA (L5): In serial programming mode, (PAR/SER = 0V),
CSA is the serial interface chip select input for registers
controlling channels 1, 4, 5 and 8. When CS is low, SCK
is enabled for shifting data on SDI into the mode control
CM34
to V /2. V should be used to bias the common mode
registers.Inparallelprogrammingmode(PAR/SER=V ),
DD
CM
DD
of the analog inputs of channels 3 and 4. V is internally
CS selects 2-lane or 1-lane output mode. CS can be driven
CM
bypassed to ground with a 0.1µF ceramic capacitor. No
with 1.8V to 3.3V logic.
external capacitance is required.
CSB (M5): In serial programming mode, (PAR/SER = 0V),
CSB is the serial interface chip select input for registers
controlling channels 2, 3, 6 and 7. When CS is low, SCK
is enabled for shifting data on SDI into the mode control
+
A
A
A
A
V
(G2): Channel 4 Positive Differential Analog Input.
(G1): Channel 4 Negative Differential Analog Input.
(H1): Channel 5 Positive Differential Analog Input.
(H2): Channel 5 Negative Differential Analog Input.
IN4
IN4
IN5
IN5
–
+
–
registers.Inparallelprogrammingmode(PAR/SER=V ),
DD
CS selects 2-lane or 1-lane output mode. CS can be driven
with 1.8V to 3.3V logic.
(J3): Common Mode Bias Output, Nominally Equal
CM56
SCK (L6): In serial programming mode, (PAR/SER = 0V),
to V /2. V should be used to bias the common mode
DD
CM
SCK is the serial interface clock input. In parallel pro-
of the analog inputs of channels 5 and 6. V is internally
CM
gramming mode (PAR/SER = V ), SCK selects 3.5mA
bypassed to ground with a 0.1µF ceramic capacitor. No
DD
or 1.75mA LVDS output currents. SCK can be driven with
external capacitance is required.
1.8V to 3.3V logic.
+
A
A
A
A
V
(K1): Channel 6 Positive Differential Analog Input.
(K2): Channel 6 Negative Differential Analog Input.
(M1): Channel 7 Positive Differential Analog Input.
(M2): Channel 7 Negative Differential Analog Input.
(N3): Common Mode Bias Output, Nominally Equal
IN6
IN6
SDI (M6): In serial programming mode, (PAR/SER = 0V),
SDIistheserialinterfacedataInput.DataonSDIisclocked
into the mode control registers on the rising edge of SCK.
–
+
IN7
In parallel programming mode (PAR/SER = V ), SDI can
–
DD
IN7
be used to power down the part. SDI can be driven with
1.8V to 3.3V logic.
CM78
to V /2. V should be used to bias the common mode
DD
CM
GND (See Pin Configuration Table): ADC Power Ground.
Use multiple vias close to pins.
of the analog inputs of channels 7 and 8. V is internally
CM
bypassed to ground with a 0.1µF ceramic capacitor. No
external capacitance is required.
9009101114p
17
LTM9011-14/
LTM9010-14/LTM9009-14
pin FuncTions
OV (G9, G10): Output Driver Supply. OV is internally
LVDS Outputs
DD
DD
bypassed to ground with a 0.1µF ceramic capacitor.
All pins in this section are differential LVDS outputs.
The output current level is programmable. There is an
optional internal 100Ω termination resistor between
the pins of each LVDS output pair.
SDOA(E6):Inserialprogrammingmode,(PAR/SER = 0V),
SDOA is the optional serial interface data output for
registers controlling channels 1 through 4. Data on SDO
is read back from the mode control registers and can be
latched on the falling edge of SCK. SDO is an open-drain
N-channel MOSFET output that requires an external 2k
pull-up resistor from 1.8V to 3.3V. If read back from the
mode control registers is not needed, the pull-up resistor
is not necessary and SDO can be left unconnected. In
–
+
–
+
OUT1A /OUT1A ,OUT1B /OUT1B (E7/E8, C8/D8): Serial
Data Outputs for Channel 1. In 1-lane output mode only
–
+
OUT1A /OUT1A are used.
–
+
–
+
OUT2A /OUT2A , OUT2B /OUT2B (B8/A8, D7/C7):
Serial Data Outputs for Channel 2. In 1-lane output mode
only OUT2A /OUT2A are used.
–
+
parallelprogrammingmode(PAR/SER =V ), SDOAisan
DD
–
+
–
+
input that enables internal 100Ω termination resistors on
the digital outputs of channels 1, 4, 5 and 8. When used
as an input, SDO can be driven with 1.8V to 3.3V logic
through a 1k series resistor.
OUT3A /OUT3A , OUT3B /OUT3B (D10/D9, E10/E9):
Serial Data Outputs for Channel 3. In 1-lane output mode
only OUT3A /OUT3A are used.
–
+
–
+
–
+
OUT4A /OUT4A , OUT4B /OUT4B (C9/C10, F7/F8):
SDOB (D6): Serial Data Output Pin for Channels 2, 3, 6
and 7. See description for SDOA.
Serial Data Outputs for Channel 4. In 1-lane output mode
only OUT4A /OUT4A are used.
–
+
–
+
–
+
PAR/SER(A7):ProgrammingModeSelectionPin.Connect
to ground to enable the serial programming mode. CSA,
CSB, SCK, SDI, SDOAandSDOBbecomeaserialinterface
OUT5A /OUT5A ,OUT5B /OUT5B (J8/J7,K8/K7):Serial
Data Outputs for Channel 5. In 1-lane output mode only
–
+
OUT5A /OUT5A are used.
that control the A/D operating modes. Connect to V to
DD
–
+
–
+
OUT6A /OUT6A , OUT6B /OUT6B (K9/K10, L9/L10):
enableparallelprogrammingmodewhereCSA,CSB,SCK,
SDI, SDOA and SDOB become parallel logic inputs that
control a reduced set of the A/D operating modes. PAR/
Serial Data Outputs for Channel 6. In 1-lane output mode
–
+
only OUT6A /OUT6A are used.
–
+
–
+
SER should be connected directly to ground or the V
of the part and not be driven by a logic signal.
OUT7A /OUT7A , OUT7B /OUT7B (M7/L7, P8/N8):
DD
Serial Data Outputs for Channel 7. In 1-lane output mode
–
+
only OUT7A /OUT7A are used.
V
(B6): Reference Voltage Output. V
is internally
REF
REF
–
+
–
+
bypassed to ground with a 1μF ceramic capacitor, nomi-
OUT8A /OUT8A , OUT8B /OUT8B (L8/M8, M10/M9):
nally 1.25V.
Serial Data Outputs for Channel 8. In 1-lane output mode
–
+
only OUT8A /OUT8A are used.
SENSE (C5): Reference Programming Pin. Connecting
–
+
SENSE to V selects the internal reference and a 1V
FRA /FRA (H7/H8): Frame Start Outputs for Channels
1, 4, 5 and 8.
DD
input range. Connecting SENSE to ground selects the
internal reference and a 0.5V input range. An external
reference between 0.625V and 1.3V applied to SENSE
–
+
FRB /FRB (J9/J10): Frame Start Outputs for Channels
2, 3, 6 and 7.
selects an input range of ±0.8 • V
. SENSE is inter-
SENSE
–
+
nally bypassed to ground with a 0.1µF ceramic capacitor.
DCOA /DCOA (G8/G7): Data Clock Outputs for Channels
1, 4, 5 and 8.
–
+
DCOB /DCOB (F10, F9): Data Clock Outputs for Chan-
nels 2, 3, 6 and 7.
9009101114p
18
LTM9011-14/
LTM9010-14/LTM9009-14
pin conFiguraTion Table
1
2
3
4
5
6
7
8
9
10
+
–
–
+
+
+
A
B
C
D
E
GND
GND
GND
GND
GND
GND
GND
GND
PAR/SER
O2A
O2A
OGND
OGND
–
+
AIN1
AIN1
V
V
REF
GND
OGND
OGND
CM12
–
+
+
–
+
AIN2
AIN2
GND
GND
SENSE
GND
GND
GND
GND
GND
GND
GND
CSA
GND
SDOB
SDOA
GND
GND
GND
GND
GND
SCK
O2B
O1B
O1B
O1A
O4B
O4A
O4A
–
+
–
GND
GND
V
V
V
V
O2B
O3A
O3A
DD
DD
DD
DD
–
+
–
+
–
AIN3
AIN3
O1A
O3B
O3B
–
+
–
F
GND
GND
V
GND
GND
GND
GND
O4B
DCOB
OV
DCOB
OV
CM34
–
+
+
–
G
H
J
AIN4
AIN4
GND
DCOA
DCOA
DD
DD
+
–
–
+
AIN5
AIN5
GND
FRA
FRA
OGND
OGND
+
–
–
+
GND
GND
V
O5A
O5A
O5B
O8A
O8A
O7B
O7B
FRB
FRB
CM56
+
–
+
–
–
+
+
–
–
+
K
L
AIN6
AIN6
V
DD
V
DD
V
DD
V
DD
O5B
O6A
O6A
+
–
+
GND
GND
O7A
O6B
O6B
+
–
–
+
–
M
N
P
AIN7
AIN7
GND
GND
GND
GND
CSB
SDI
O7A
O8B
O8B
+
–
AIN8
AIN8
V
GND
GND
GND
GND
OGND
OGND
OGND
OGND
CM78
+
–
GND
GND
GND
CLK
CLK
Top View of BGA Package (Looking Through Component).
9009101114p
19
LTM9011-14/
LTM9010-14/LTM9009-14
FuncTional block DiagraM
V
DD
= 1.8V
OV = 1.8V
DD
+
–
+
–
OUT1A
OUT1A
OUT1B
OUT1B
CH 1
ANALOG
INPUT
14-BIT
S/H
S/H
S/H
S/H
S/H
S/H
S/H
S/H
ADC CORE
+
–
+
–
OUT1A
OUT1A
OUT1B
OUT1B
CH 2
ANALOG
INPUT
14-BIT
ADC CORE
+
–
+
–
OUT1A
OUT1A
OUT1B
OUT1B
CH 3
ANALOG
INPUT
14-BIT
ADC CORE
+
–
+
–
OUT1A
OUT1A
OUT1B
OUT1B
CH 4
ANALOG
INPUT
14-BIT
ADC CORE
DATA
SERIALIZER
+
–
+
–
OUT1A
OUT1A
OUT1B
OUT1B
CH 5
ANALOG
INPUT
14-BIT
ADC CORE
+
–
+
–
OUT1A
OUT1A
OUT1B
OUT1B
CH 6
ANALOG
INPUT
14-BIT
ADC CORE
+
–
+
–
OUT1A
OUT1A
OUT1B
OUT1B
CH 7
ANALOG
INPUT
14-BIT
ADC CORE
+
–
+
–
OUT1A
OUT1A
OUT1B
OUT1B
CH 8
ANALOG
INPUT
14-BIT
ADC CORE
+
ENC
ENC
DCOA
DCOB
FRA
PLL
–
FRB
1.25V
REFERENCE
SDOA
SDOB
SDI
V
REF
REFH
REFL
MODE
CONTROL
REGISTERS
SCK
RANGE
SELECT
CSA
CSB
PAR/SER
REF
BUFFER
V
DD
/2
DIFF
REF
AMP
GND
9009101114 F01
SENSE
VCM12
VCM34
VCM56
VCM78
Figure 1. Functional Block Diagram
9009101114p
20
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
CONVERTER OPERATION
INPUT DRIVE CIRCUITS
The LTM9011-14/LTM9010-14/LTM9009-14 are low
power,8-channel,14-bit,125Msps/105Msps/80MspsA/D
converters that are powered by a single 1.8V supply. The
analog inputs should be driven differentially. The encode
input can be driven differentially for optimal jitter perfor-
mance,orsingle-endedforlowerpowerconsumption.The
digital outputs are serial LVDS to minimize the number
of data lines. Each channel outputs two bits at a time
(2-lane mode). At lower sampling rates there is a one bit
perchanneloption(1-lanemode).Manyadditionalfeatures
canbechosenbyprogrammingthemodecontrolregisters
through a serial SPI port.
Input Filtering
If possible, there should be an RC low pass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitry from the A/D sample-and-hold switching, and
alsolimitswidebandnoisefromthedrivecircuitry.Figure3
showsanexampleofaninputRCfilter. TheRCcomponent
values should be chosen based on the application’s input
frequency.
Transformer Coupled Circuits
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with V , setting the A/D input at its opti-
mal DC level. At higher input frequencies a transmission
line balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
ANALOG INPUT
CM
The analog inputs are differential CMOS sample-and-hold
circuits(Figure2).Theinputsshouldbedrivendifferentially
around a common mode voltage set by the appropriate
V
output pins, which are nominally V /2. For the 2V
CM
DD
input range, the inputs should swing from V – 0.5V
50Ω
CM
V
CM
to V + 0.5V. There should be 180° phase difference
CM
0.1µF
between the inputs.
0.1µF
T1
1:1
+
25Ω
A
IN
ANALOG
INPUT
Theeightchannelsaresimultaneouslysampledbyashared
encode circuit (Figure 2).
LTM9011-14
0.1µF
25Ω
25Ω
12pF
–
25Ω
A
IN
LTM9011-14
10Ω
V
DD
C
SAMPLE
3.5pF
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
R
ON
9009101114 F03
25Ω
+
–
A
IN
IN
C
C
PARASITIC
1.8pF
V
DD
C
SAMPLE
3.5pF
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
R
25Ω
ON
10Ω
A
PARASITIC
1.8pF
V
DD
1.2V
10k
+
–
ENC
ENC
10k
1.2V
9009101114 F02
Figure 2. Equivalent Input Circuit. Only One
of the Eight Analog Channels Is Shown
9009101114p
21
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
Amplifier Circuits
4 to 6) should convert the signal to differential before
driving the A/D.
Figure 7 shows the analog input being driven by a
highspeeddifferentialamplifier.Theoutputoftheamplifier
isAC-coupledtotheA/Dsotheamplifier’soutputcommon
mode voltage can be optimally set to minimize distortion.
Reference
TheLTM9011-14/LTM9010-14/LTM9009-14hasaninternal
1.25V voltage reference. For a 2V input range using the
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
internal reference, connect SENSE to V . For a 1V input
DD
range using the internal reference, connect SENSE to
ground. For a 2V input range with an external reference,
50Ω
V
50Ω
V
CM
CM
0.1µF
0.1µF
0.1µF
0.1µF
+
+
A
A
ANALOG
INPUT
IN
ANALOG
INPUT
IN
T2
T2
LTM9011-14
LTM9011-14
T1
T1
0.1µF
0.1µF
25Ω
25Ω
25Ω
25Ω
4.7pF
1.8pF
0.1µF
0.1µF
–
–
A
A
IN
IN
9009101114 F04
9009101114 F05
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 5. Recommended Front End Circuit for Input
Frequencies from 170MHz to 300MHz
Figure 4. Recommended Front End Circuit for Input
Frequencies from 70MHz to 170MHz
50Ω
V
V
CM
CM
0.1µF
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
A
200Ω 200Ω
25Ω
0.1µF
0.1µF
0.1µF
0.1µF
2.7nH
0.1µF
+
+
–
A
IN
IN
ANALOG
INPUT
LTM9011-14
LTM9011-14
ANALOG
INPUT
25Ω
25Ω
+
+
T1
12pF
–
–
–
2.7nH
A
IN
25Ω
A
IN
9009101114 F06
9009101114 F07
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 7. Front End Circuit Using a High Speed
Differential Amplifier
Figure 6. Recommended Front End Circuit for Input
Frequencies Above 300MHz
9009101114p
22
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
apply a 1.25V reference voltage to SENSE (Figure 9).
Encode Input
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
will then be 1.6 • V
. The reference is shared by all
SENSE
eight ADC channels, so it is not possible to independently
adjust the input range of individual channels.
The V , REFH and REFL pins are internally bypassed,
REF
as shown in Figure 8.
V
LTM9011-14
REF
5Ω
1.25V
1.25V BANDGAP
REFERENCE
1µF
0.625V
RANGE
DETECT
AND
CONTROL
TIE TO V FOR 2V RANGE;
DD
SENSE
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • V
FOR
SENSE
INTERNAL ADC
HIGH REFERENCE
0.65V < V
< 1.300V
BUFFER
SENSE
0.1µF
REFH
2.2µF
0.1µF
0.1µF
0.8x
DIFF AMP
REFL
INTERNAL ADC
LOW REFERENCE
9009101114 F08
Figure 8. Reference Circuit
LTM9011-14
LTM9011-14
30k
LTM9011-14
SENSE
V
DD
1.25V
EXTERNAL
REFERENCE
1.8V TO
+
–
3.3V
ENC
DIFFERENTIAL
COMPARATOR
1µF
0V
V
DD
ENC
CMOS LOGIC
BUFFER
9009101114 F09
15k
30k
9009101114 F11
+
ENC
Figure 9. Using an External
1.25V Reference
–
Figure 11. Equivalent Encode
Input Circuit for Single-Ended
Encode Mode
ENC
9009101114 F10
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
9009101114p
23
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12 and 13).
The encode inputs are internally biased to 1.2V through
10kequivalentresistance. The encode inputs canbe taken
rise and fall times.
Clock PLL and Duty Cycle Stabilizer
Theencodeclockismultipliedbyaninternalphase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25µs to lock onto the input clock.
above V (up to 3.6V), and the common mode range is
DD
–
from 1.1V to 1.6V. In the differential encode mode, ENC
should stay at least 200mV above ground to avoid falsely
triggering the single-ended encode mode. For good jitter
+
performance ENC should have fast rise and fall times.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
Thesingle-endedencodemodeshouldbeusedwithCMOS
–
encode inputs. To select this mode, ENC is connected
+
to ground and ENC is driven with a square wave encode
+
input. ENC can be taken above V (up to 3.6V) so 1.8V
DD
+
to3.3VCMOSlogiclevelscanbeused.TheENC threshold
is0.9V. ForgoodjitterperformanceENC shouldhavefast
+
0.1µF
+
ENC
0.1µF
0.1µF
+
T1
ENC
LTM9011-14
PECL OR
LTM9011-14
LVDS
50Ω
50Ω
CLOCK
100Ω
0.1µF
–
ENC
9009101114 F13
–
0.1µF
ENC
Figure 13. PECL or LVDS Encode Drive
9009101114 F12
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
9009101114p
24
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
DIGITAL OUTPUTS
resistors should be located as close as possible to the
LVDS receiver.
The digital outputs of the LTM9011-14/LTM9010-14/
LTM9009-14 are serialized LVDS signals. Each channel
outputstwobitsatatime(2-lanemode).Atlowersampling
rates there is a one bit per channel option (1-lane mode).
The data can be serialized with 16, 14, or 12-bit serializa-
tion(seetimingdiagramsfordetails). Notethatwith12-bit
serialization the two LSBs are not available—this mode
is included for compatibility with the 12-bit versions of
these parts.
The outputs are powered by OV and OGND which are
DD
isolated from the A/D core power and ground.
Programmable LVDS Output Current
Thedefaultoutputdrivercurrentis3.5mA.Thiscurrentcan
be adjusted by control register A2 in the serial program-
ming mode. Available current levels are 1.75mA, 2.1mA,
2.5mA, 3mA, 3.5mA, 4mA and 4.5mA. In the parallel
programming mode the SCK pin can select either 3.5mA
or 1.75mA.
The output data should be latched on the rising and falling
edges of the data clock out (DCO). A data frame output
(FR) can be used to determine when the data from a new
conversionresultbegins. Inthe2-lane, 14-bitserialization
mode, the frequency of the FR output is halved.
Optional LVDS Driver Internal Termination
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
be enabled by serially programming mode control register
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current is
doubled to maintain the same output voltage swing. In the
parallel programming mode the SDO pin enables internal
termination. Internal termination should only be used with
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will de-
pend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for all
serialization modes is 5Msps.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTM9011-14. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 105MHz (LTM9010-14) or 80MHz (LTM9009-14).
MAXIMUM SAMPLING
SERIALIZATION MODE
FREQUENCY, f (MHz)
DCO FREQUENCY
4 • f
FR FREQUENCY
SERIAL DATA RATE
S
2-Lane
2-Lane
2-Lane
1-Lane
1-Lane
1-Lane
16-Bit Serialization
125
125
125
62.5
71.4
83.3
f
8 • f
7 • f
6 • f
S
S
S
S
S
14-Bit Serialization
12-Bit Serialization
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
3.5 • f
0.5 • f
S
S
3 • f
8 • f
7 • f
6 • f
f
S
f
S
f
S
f
S
S
16 • f
14 • f
12 • f
S
S
S
S
S
S
9009101114p
25
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
DATA FORMAT
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D13-D0)ofallchannelstoknownvalues.Thedigitaloutput
test patterns are enabled by serially programming mode
control registers A3 and A4. When enabled, the test pat-
ternsoverrideallotherformattingmodes:2’scomplement
and randomizer.
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
Table 2. Output Codes vs Input Voltage
+
–
A
– A
D13-D0
D13-D0
IN
IN
(2V RANGE)
>1.000000V
+0.999878V
+0.999756V
+0.000122V
+0.000000V
–0.000122V
–0.000244V
–0.999878V
–1.000000V
<–1.000000V
(OFFSET BINARY)
(2’s COMPLEMENT)
Output Disable
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
The digital outputs may be disabled by serially program-
ming mode control register A2. The current drive for all
digital outputs including DCO and FR are disabled to save
powerorenablein-circuittesting.Whendisabledthecom-
mon mode of each output pair becomes high impedance,
but the differential impedance may remain low.
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 2mW power consumption. Sleep mode is
enabled by mode control register A1 (serial programming
mode), or by SDI (parallel programming mode). The time
required to recover from sleep mode is about 2ms.
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
In nap mode any combination of A/D channels can be
powereddownwhiletheinternalreferencecircuitsandthe
PLL stay active, allowing faster wakeup than from sleep
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands very accurate DC
settling then an additional 50µs should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
leaves nap mode. Nap mode is enabled by mode control
register A1 in the serial programming mode.
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied
—an exclusive-OR operation is applied between the LSB
andallotherbits.TheFRandDCOoutputsarenotaffected.
Theoutputrandomizerisenabledbyseriallyprogramming
mode control register A1.
9009101114p
26
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
DEVICE PROGRAMMING MODES
Serial Programming Mode
The operating modes of the LTM9011-14/LTM9010-14/
LTM9009-14 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more flexibility and can program all available modes.
Theparallelinterfaceismorelimitedandcanonlyprogram
some of the more commonly used modes.
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V . The CS, SCK, SDI and SDO pins are binary
DD
logic inputs that set certain operating modes. These pins
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
can be tied to V or ground, or driven by 1.8V, 2.5V, or
DD
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 3 shows the
modes set by CS, SCK, SDI and SDO.
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams sections). During a read back command the
register is not updated and data on SDI is ignored.
Table 3. Parallel Programming Mode Control Bits
(PAR/SER = VDD
)
Pin
DESCRIPTION
CS
2-Lane / 1-Lane Selection Bit
0 = 2-Lane, 16-Bit Serialization Output Mode
1 = 1-Lane, 14-Bit Serialization Output Mode
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Power Down Control Bit
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and read back is not needed,
then SDO can be left floating and no pull-up resistor
is needed. Table 4 shows a map of the mode control
registers.
SCK
SDI
0 = Normal Operation
1 = Sleep Mode
Software Reset
SDO
Internal Termination Selection Bit
0 = Internal Termination Disabled
1 = Internal Termination Enabled
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
9009101114p
27
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
RESET
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7
RESET
Software Reset Bit
0 = Not Used
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC Is Momentarily Placed in SLEEP Mode.
This Bit Is Automatically Set Back to Zero After the Reset Is Complete
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1 (CSA): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSA = GND)
D7
D6
D5
D4
D3
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_8
NAP_5
NAP_4
NAP_1
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended.
Bit 6
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
Bit 5
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Bits 4-0
SLEEP: NAP_X Sleep/Nap Mode Control Bits
00000 = Normal Operation
0XXX1 = Channel 1 in Nap Mode
0XX1X = Channel 4 in Nap Mode
0X1XX = Channel 5 in Nap Mode
01XXX = Channel 8 in Nap Mode
1XXXX = Sleep Mode. Channels 1, 4, 5 and 8 Are Disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
REGISTER A1 (CSB): FORMAT AND POWER-DOWN REGISTER (ADDRESS 01h with CSB = GND)
D7
D6
D5
D4
D3
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_7
NAP_6
NAP_3
NAP_2
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7
Bit 6
Bit 5
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This Is Not Recommended.
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
9009101114p
28
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
Bits 4-0
SLEEP: NAP_4:NAP_1 Sleep/Nap Mode Control Bits
00000 = Normal Operation
0XXX1 = Channel 2 in Nap Mode
0XX1X = Channel 3 in Nap Mode
0X1XX = Channel 6 in Nap Mode
01XXX = Channel 7 in Nap Mode
1XXXX = Sleep Mode. Channels 2, 3, 6 and 7 Are Disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE2
OUTMODE1
OUTMODE0
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bits 7-5
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 4
TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current Is 2x the Current Set by ILVDS2:ILVDS0. Internal Termination Should Only Be
Used with 1.75mA, 2.1mA or 2.5mA LVDS Output Current Modes.
Bit 3
OUTOFF Output Disable Bit
0 = Digital Outputs Are Enabled.
1 = Digital Outputs Are Disabled.
Bits 2-0
OUTMODE2:OUTMODE0 Digital Output Mode Control Bits
000 = 2-Lanes, 16-Bit Serialization
001 = 2-Lanes, 14-Bit Serialization
010 = 2-Lanes, 12-Bit Serialization
011 = Not Used
100 = Not Used
101 = 1-Lane, 14-Bit Serialization
110 = 1-Lane, 12-Bit Serialization
111 = 1-Lane, 16-Bit Serialization
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
X
D5
D4
D3
D2
D1
D0
OUTTEST
TP13
TP12
TP11
TP10
TP9
TP8
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bit 6
Unused, Don’t Care Bit.
Bit 5-0
TP13:TP8
Test Pattern Data Bits (MSB)
TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
D2
D1
D0
TP7
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Note That CSA Controls Channels 1, 4, 5 and 8, CSB Controls Channels 2, 3, 6 and 7.
Bit 7-0 TP7:TP0 Test Pattern Data Bits (LSB)
TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
9009101114p
29
LTM9011-14/
LTM9010-14/LTM9009-14
applicaTions inForMaTion
GROUNDING AND BYPASSING
module has similar layout rules to other BGA packages.
The layout can be implemented with 6mil blind vias and
5mil traces. The pinout has been designed to minimize the
space required to route the analog and digital traces. The
analog and digital traces can essentially be routed within
the width of the package. This allows multiple packages
to be located close together for high channel count ap-
plications. Trace lengths for the analog inputs and digital
outputs should be matched as well as possible. Table 5
lists the trace lengths for the analog inputs and digital
outputs inside the package from the die pad to the pack-
age pad. These should be added to the PCB trace lengths
for best matching.
The LTM9011-14/LTM9010-14/LTM9009-14 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
Bypass capacitors are integrated inside the package; ad-
ditional capacitance is optional.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
MostoftheheatgeneratedbytheLTM9011-14/LTM9010-14/
LTM9009-14 is transferred from the die through the bot-
tom of the package onto the printed circuit board. The
ground pins should be connected to the internal ground
planes by multiple vias.
The pin assignments of the LTM9011-14/LTM9010-14/
LTM9009-14 allow a flow-through layout that makes it
possible to use multiple parts in a small area when a
large number of ADC channels are required. The LTM9011
Table 5. Internal Trace Lengths
LENGTH
(mm)
LENGTH
(mm)
LENGTH
(mm)
LENGTH
(mm)
PIN
E7
NAME
PIN
K8
K7
K9
NAME
PIN
E1
NAME
PIN
F10
F9
NAME
–
–
–
–
01A
1.775
1.947
1.847
1.850
3.233
3.246
0.179
1.127
2.126
2.177
1.811
1.812
3.199
3.196
0.706
0.639
0.392
0.436
05B
0.379
0.528
1.866
1.865
2.268
2.267
1.089
0.179
3.281
3.149
1.862
1.847
4.021
4.016
4.689
4.709
4.724
4.769
A
A
A
A
A
A
A
A
A
A
A
A
2.491
2.505
3.376
3.372
3.301
3.346
2.506
2.533
3.198
3.214
4.726
4.691
4.106
4.106
0.919
1.162
1.157
1.088
DCOB
1.811
1.812
1.117
1.038
1.644
1.643
IN3
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
–
+
+
–
+
–
+
–
+
–
+
–
+
–
+
+
+
E8
01A
01B
01B
02A
02A
02B
02B
03A
03A
03B
03B
04A
04A
04B
04B
05A
05A
05B
06A
E2
DCOB
IN3
–
–
C8
D8
B8
A8
D7
C7
D10
D9
E10
E9
G1
G2
H2
H1
K2
K1
M2
M1
N2
N1
P6
P5
L5
H7
H8
J9
FRA
IN4
+
+
K10 06A
L9 06B
L10 06B
FRA
IN4
–
–
FRB
IN5
+
+
J10
A7
L6
FRB
IN5
–
M7
L7
07A
07A
07B
07B
08A
08A
PAR/SER 3.838
IN6
+
SCK
0.240
0.453
0.274
1.069
3.914
0.123
0.079
3.915
IN6
–
P8
N8
L8
E6
SDOA
SDOB
SDI
IN7
+
D6
M6
B3
F3
IN7
–
IN8
+
M8
V
V
V
V
IN8
CM12
CM34
CM56
CM78
–
C9
C10
F7
M10 08B
CLK
CLK
+
M9
B1
B2
C1
C2
08B
J3
–
A
A
A
A
CSA
N3
IN1
IN1
IN2
IN2
+
–
+
F8
M5
G8
G7
CSB
–
+
J8
DCOA
DCOA
J7
9009101114p
30
LTM9011-14/
LTM9010-14/LTM9009-14
Typical applicaTions
Top Side
Silkscreen Top
9009101114p
31
LTM9011-14/
LTM9010-14/LTM9009-14
Typical applicaTions
Inner Layer 2 GND
Inner Layer 3
Inner Layer 4
Inner Layer 5 Power
9009101114p
32
LTM9011-14/
LTM9010-14/LTM9009-14
Typical applicaTions
Bottom Side
Silkscreen Bottom
9009101114p
33
LTM9011-14/
LTM9010-14/LTM9009-14
Typical applicaTions
LTM9009-14 Schematic
9009101114p
34
LTM9011-14/
LTM9010-14/LTM9009-14
package DescripTion
/ / b b b
Z
3 . 6 0 0
2 . 8 0 0
2 . 0 0 0
1 . 2 0 0
0 . 4 0 0
0 . 0 0 0
0 . 4 0 0
1 . 2 0 0
2 . 0 0 0
2 . 8 0 0
3 . 6 0 0
a a a
Z
9009101114p
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However,noresponsibilityisassumedforitsuse.LinearTechnologyCorporationmakesnorepresenta-
tionthattheinterconnectionofitscircuitsasdescribedhereinwillnotinfringeonexistingpatentrights.
35
LTM9011-14/
LTM9010-14/LTM9009-14
Typical applicaTion
Single-Ended to Differential Conversion Using LTC6409 and 50MHz Lowpass Filter (Only One Channel Shown)
3.3V
0.8pF
1.8V
0.1µF
1.8V
150Ω
474Ω
C5
B6
180nH
68pF
180nH
150pF
37.4Ω
+
66.9Ω
V
+
–
IN
OUT
75Ω
75Ω
+
–
+
+
–
+
–
+
–
A
A
B2
B1
E8
E7
G7
G8
H8
H7
O1A
O1A
DCO
DCO
FR
IN1
33pF
IN1
–
IN
68pF
150pF
180nH
–
+
OUT
180nH
37.4Ω
V
OCM
B3
C2
C1
F2
F1
F3
G2
G1
150Ω
474Ω
V
A
A
A
A
V
A
A
SHDN
CM12
+
IN2
LTM9011-14
FR
0.8pF
46.9Ω 66.9Ω
–
IN2
+
IN3
GND
–
IN3
CM34
+
IN4
–
IN4
N1
N2
+
A
A
IN8
–
IN8
P5 P6
9009101114 TA02
relaTeD parTs
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2170-14/LTC2171-14/ 14-Bit, 25Msps/40Msps/65Msps
LTC2172-14 1.8V Quad ADCs, Ultralow Power
178mW/234mW/360mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC2170-12/LTC2171-12/ 12-Bit, 25Msps/40Msps/65Msps
LTC2172-12 1.8V Quad ADCs, Ultralow Power
178mW/234mW/360mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC2173-12/LTC2174-12/ 12-Bit, 80Msps/105Msps/125Msps
LTC2175-12 1.8V Quad ADCs, Ultralow Power
412mW/481mW/567mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC2173-14/LTC2174-14/ 14-Bit, 80Msps/105Msps/125Msps
412mW/481mW/567mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC2175-14
Amplifiers/Filters
LTC6412
1.8V Quad ADCs, Ultralow Power
800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise
Variable Gain Amplifier
Figure, 4mm × 4mm QFN-24
LTC6420-20
LTC6421-20
1.8GHz Dual Low Noise, Low Distortion
Differential ADC Drivers for 300MHz IF
1.3GHz Dual Low Noise, Low Distortion
Differential ADC Drivers
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per Amplifier,
3mm × 4mm QFN-20
Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 40mA Supply Current per Amplifier,
3mm × 4mm QFN-20
LTC6605-7/ LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz Filters Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
LTC6605-14
LTM9002
with ADC Drivers
Pin-Programmable Gain, 6mm × 3mm DFN-22
14-Bit Dual Channel IF/Baseband Receiver Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
Subsystem
9009101114p
LT 0410 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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