LTC2170CUKG-14#PBF [Linear]
LTC2170-14 - 14-Bit, 25Msps Low Power Quad ADCs; Package: QFN; Pins: 52; Temperature Range: 0°C to 70°C;
| 型号： | LTC2170CUKG-14#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2170-14 - 14-Bit, 25Msps Low Power Quad ADCs; Package: QFN; Pins: 52; Temperature Range: 0°C to 70°C 转换器 |
| 文件： | 总34页 (文件大小：1511K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2172-14/
LTC2171-14/LTC2170-14
14-Bit, 65Msps/40Msps/
25Msps Low Power Quad ADCs
FeaTures
DescripTion
n
4-Channel Simultaneous Sampling ADC
TheLTC®2172-14/LTC2171-14/LTC2170-14are4-channel,
simultaneoussampling14-bitA/Dconvertersdesignedfor
digitizinghighfrequency,widedynamicrangesignals.They
are perfect for demanding communications applications
with AC performance that includes 73.7dB SNR and 90dB
spurious free dynamic range (SFDR). An ultralow jitter of
n
73.7dB SNR
n
90dB SFDR
n
Low Power: 311mW/202mW/162mW Total,
78mW/51mW/41mW per Channel
Single 1.8V Supply
n
n
Serial LVDS Outputs: One or Two Bits per Channel
0.15ps
allows undersampling of IF frequencies with
RMS
n
n
n
n
n
n
Selectable Input Ranges: 1V to 2V
excellent noise performance.
P-P
P-P
800MHz Full Power Bandwidth Sample-and-Hold
DC specifications include 1LSB INL (typ), 0.3LSB DNL
(typ) and no missing codes over temperature. The transi-
tion noise is a low 1.2LSB
Shutdown and Nap Modes
Serial SPI Port for Configuration
.
RMS
Pin-Compatible 14-Bit and 12-Bit Versions
52-Pin (7mm × 8mm) QFN Package
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lanemode)oronebitatatime(1-lanemode).TheLVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
applicaTions
n
Communications
n
Cellular Base Stations
+
–
n
Software Defined Radios
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n
Portable Medical Imaging
n
Multichannel Data Acquisition
n
Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
1.8V
V
1.8V
OV
LTC2172-14, 65Msps,
DD
DD
2-Tone FFT, fIN = 70MHz and 75MHz
CHANNEL 1
ANALOG
INPUT
14-BIT
OUT1A
OUT1B
0
–10
–20
–30
–40
S/H
S/H
S/H
S/H
ADC CORE
CHANNEL 2
ANALOG
INPUT
OUT2A
OUT2B
14-BIT
ADC CORE
DATA
SERIALIZER
–50
SERIALIZED
CHANNEL 3
ANALOG
INPUT
OUT3A
OUT3B
14-BIT
ADC CORE
LVDS
–60
–70
OUTPUTS
–80
–90
CHANNEL 4
ANALOG
INPUT
OUT4A
OUT4B
14-BIT
ADC CORE
–100
–110
–120
DATA
CLOCK
OUT
ENCODE
INPUT
PLL
0
20
10
FREQUENCY (MHz)
30
FRAME
217214 TA01b
GND
OGND
217214 TA01
21721014fb
1
LTC2172-14/
LTC2171-14/LTC2170-14
absoluTe MaxiMuM raTings
pin conFiguraTion
(Notes 1 and 2)
TOP VIEW
Supply Voltages
V
, OV ............................................... –0.3V to 2V
DD
DD
+
–
Analog Input Voltage (A , A
,
IN
IN
52 51 50 49 48 47 46 45 44 43 42 41
PAR/SER, SENSE) (Note 3).......... –0.3V to (V + 0.2V)
DD
+
–
+
–
+
–
+
–
A
A
1
2
40 OUT2A
39 OUT2A
IN1
Digital Input Voltage (ENC , ENC , CS,
IN1
SDI, SCK) (Note 4).................................... –0.3V to 3.9V
SDO (Note 4)............................................. –0.3V to 3.9V
V
OUT2B
3
38
37
CM12
+
A
OUT2B
+
4
IN2
IN2
–
Digital Output Voltage................ –0.3V to (OV + 0.3V)
Operating Temperature Range
LTC2172C, LTC2171C, LTC2170C............. 0°C to 70°C
LTC2172I, LTC2171I, LTC2170I ............–40°C to 85°C
Storage Temperature Range .................. –65°C to 150°C
DD
A
5
36 DCO
–
REFH
REFH
REFL
DCO
6
35
7
34 OV
53
GND
DD
8
33 OGND
+
REFL
+
9
32 FR
–
A
A
10
11
12
13
14
31 FR
IN3
–
+
–
+
–
30 OUT3A
29 OUT3A
28 OUT3B
27 OUT3B
IN3
V
CM34
+
A
IN4
IN4
–
A
15 16 17 18 19 20 21 22 23 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
T
= 150°C,
θ
= 28°C/W
JMAX
JA
EXPOSED PAD (PIN 53) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTC2172UKG-14
LTC2172UKG-14
LTC2171UKG-14
LTC2171UKG-14
LTC2170UKG-14
LTC2170UKG-14
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2172CUKG-14#PBF
LTC2172IUKG-14#PBF
LTC2171CUKG-14#PBF
LTC2171IUKG-14#PBF
LTC2170CUKG-14#PBF
LTC2170IUKG-14#PBF
LTC2172CUKG-14#TRPBF
LTC2172IUKG-14#TRPBF
LTC2171CUKG-14#TRPBF
LTC2171IUKG-14#TRPBF
LTC2170CUKG-14#TRPBF
LTC2170IUKG-14#TRPBF
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
21721014fb
2
LTC2172-14/
LTC2171-14/LTC2170-14
converTer characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2172-14
TYP
LTC2171-14
LTC2170-14
MIN TYP MAX
14
2.75 –2.75
PARAMETER
CONDITIONS
MIN
MAX
MIN
TYP
MAX
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
14
14
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
–3.25
–0.8
–12
1
0.3
3
3.25 –2.75
1
0.3
3
1
0.3
3
2.75
0.8
12
LSB
LSB
mV
0.8
12
–0.8
–12
0.8
12
–0.8
–12
Gain Error
Internal Reference
External Reference
–1
–1
–1
–1
–1
–1
%FS
%FS
l
–2.5
0.5
–2.5
0.5
–2.5
0.5
Offset Drift
20
20
20
µV/°C
Full-Scale Drift
Internal Reference
External Reference
35
25
35
25
35
25
ppm/°C
ppm/°C
Gain Matching
Offset Matching
Transition Noise
External Reference
0.2
3
0.2
3
0.2
3
%FS
mV
External Reference
1.2
1.2
1.2
LSB
RMS
analog inpuT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
l
l
l
V
V
V
Analog Input Range (A – A
)
1.7V < V < 1.9V
1 to 2
V
P-P
IN
IN
IN
DD
+
–
Analog Input Common Mode (A + A )/2
Differential Analog Input (Note 8)
External Reference Mode
V
– 100mV
0.625
V
CM
V
+ 100mV
1.300
V
IN(CM)
SENSE
IN(CM)
IN
IN
CM
CM
External Voltage Reference Applied to SENSE
Analog Input Common Mode Current
1.250
V
I
Per Pin, 65Msps
Per Pin, 40Msps
Per Pin, 25Msps
81
50
31
µA
µA
µA
+
–
l
l
l
I
I
I
t
t
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
0 < A , A < V
DD
–1
–3
–6
1
3
6
µA
µA
µA
ns
IN1
IN
IN
0 < PAR/SER < V
IN2
DD
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
IN3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
0
AP
0.15
80
ps
RMS
JITTER
CMRR
dB
BW-3B Full-Power Bandwidth
Figure 6 Test Circuit
800
MHz
21721014fb
3
LTC2172-14/
LTC2171-14/LTC2170-14
DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2172-14
TYP
LTC2171-14
TYP MAX
LTC2170-14
MIN TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
SNR
Signal-to-Noise Ratio
5MHz Input
73.7
73.7
73.5
73
73.5
73.4
73.4
72.8
72.9
72.9
72.8
72.3
dBFS
dBFS
dBFS
dBFS
l
l
l
l
30MHz Input
70MHz Input
140MHz Input
72.0
71.7
71.1
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or 3rd Harmonic
90
90
89
84
90
90
89
84
90
90
89
84
dBFS
dBFS
dBFS
dBFS
30MHz Input
70MHz Input
140MHz Input
77
85
80
85
80
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
90
90
90
90
90
90
90
90
90
90
90
90
dBFS
dBFS
dBFS
dBFS
30MHz Input
70MHz Input
140MHz Input
85
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
73.6
73.5
73.2
72.5
73.3
73.2
73.1
72.3
72.8
72.7
72.5
71.9
dBFS
dBFS
dBFS
dBFS
30MHz Input
70MHz Input
140MHz Input
71.2
71.3
70.8
Crosstalk, Near Channel
Crosstalk, Far Channel
10MHz Input (Note 12)
10MHz Input (Note 12)
–90
–90
–90
dBc
dBc
–105
–105
–105
inTernal reFerence characTerisTics The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
PARAMETER
CONDITIONS
= 0
MIN
TYP
0.5 • V
25
MAX
UNITS
V
V
CM
V
CM
V
CM
V
REF
V
REF
V
REF
V
REF
Output Voltage
I
0.5 • V – 25mV
0.5 • V + 25mV
OUT
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
ppm/°C
Ω
–600µA < I
< 1mA
< 1mA
4
OUT
I
= 0
1.225
1.250
25
1.275
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400µA < I
7
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
21721014fb
4
LTC2172-14/
LTC2171-14/LTC2170-14
DigiTal inpuTs anD ouTpuTs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
–
Differential Encode Mode (ENC Not Tied to GND)
l
V
V
Differential Input Voltage
(Note 8)
0.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
1.2
V
V
ICM
l
l
1.1
0.2
1.6
3.6
+
–
V
IN
Input Voltage Range
Input Resistance
ENC , ENC to GND
(See Figure 10)
V
kΩ
pF
R
10
IN
IN
C
Input Capacitance
3.5
–
Single-Ended Encode Mode (ENC Tied to GND)
l
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
V
V
= 1.8V
= 1.8V
1.2
0
V
V
IH
IL
IN
DD
DD
0.6
3.6
+
ENC to GND
V
R
(See Figure 11)
30
kΩ
pF
IN
IN
C
Input Capacitance
3.5
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 1.8V
1.3
V
V
IH
IL
DD
DD
IN
l
l
= 1.8V
0.6
10
I
IN
= 0V to 3.6V
–10
µA
pF
C
IN
Input Capacitance
3
200
3
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
= 1.8V, SDO = 0V
DD
Ω
µA
pF
OL
l
I
SDO = 0V to 3.6V
–10
10
OH
C
OUT
DIGITAL DATA OUTPUTS
l
l
V
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
125
350
175
454
250
mV
mV
OD
l
l
V
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.125
1.250
1.250
1.375
1.375
V
V
OS
R
Termination Enabled, OV = 1.8V
100
Ω
TERM
DD
21721014fb
5
LTC2172-14/
LTC2171-14/LTC2170-14
power requireMenTs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2172-14
LTC2171-14
LTC2170-14
MIN TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
1.7
TYP
1.8
MAX
1.9
MIN
1.7
TYP
1.8
1.8
96
MAX
1.9
l
l
l
V
Analog Supply Voltage (Note 10)
1.7
1.7
1.8
1.8
75
1.9
1.9
85
V
V
DD
OV
DD
Output Supply Voltage (Note 10)
1.7
1.8
1.9
1.7
1.9
I
I
Analog Supply Current Sine Wave Input
157
181
112
mA
VDD
OVDD
Digital Supply Current 1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
16
30
25
47
16
29
24
46
15
28
24
45
mA
mA
mA
mA
l
l
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
29
52
27
51
27
50
P
DISS
Power Dissipation
1-Lane Mode, 1.75mA Mode
1-Lane Mode, 3.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, 3.5mA Mode
311
337
328
367
202
225
216
256
162
185
178
216
mW
mW
mW
mW
l
l
378
419
250
293
202
243
P
P
P
Sleep Mode Power
Nap Mode Power
1
1
1
mW
mW
mW
SLEEP
75
20
75
20
75
20
NAP
Power Increase with Differential Encode Mode Enabled
(No Increase for Sleep Mode)
DIFFCLK
TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2172-14
TYP
LTC2171-14
TYP
LTC2170-14
MIN TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
l
f
t
Sampling Frequency
(Notes 10, 11)
5
65
5
40
5
25
MHz
S
l
l
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.3
2
7.69
7.69
100 11.88 12.5
100 12.5
100
100
19
2
20
20
100
100
ns
ns
ENCL
2
l
l
t
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.3
2
7.69
7.69
100 11.88 12.5
100
100
19
2
20
20
100
100
ns
ns
ENCH
AP
100
2
12.5
t
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
21721014fb
6
LTC2172-14/
LTC2171-14/LTC2170-14
TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
Digital Data Outputs (R
CONDITIONS
= 100Ω Differential, C = 2pF to GND on Each Output)
MIN
TYP
MAX
UNITS
TERM
L
t
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1 / (8 • f )
s
s
s
s
s
s
SER
S
1 / (7 • f )
S
1 / (6 • f )
S
1 / (16 • f )
S
1 / (14 • f )
S
1 / (12 • f )
S
l
l
l
t
t
t
t
t
FR to DCO Delay
(Note 8)
0.35 • t
0.35 • t
0.5 • t
0.5 • t
0.65 • t
0.65 • t
s
s
FRAME
DATA
PD
SER
SER
SER
SER
DATA to DCO Delay
Propagation Delay
Output Rise Time
Output Fall Time
(Note 8)
SER
SER
(Note 8)
0.7n + 2 • t
1.1n + 2 • t
1.5n + 2 • t
SER
s
SER
SER
Data, DCO, FR, 20% to 80%
Data, DCO, FR, 20% to 80%
0.17
0.17
60
ns
ns
R
F
DCO Cycle-to-Cycle Jitter
Pipeline Latency
t
= 1ns
ps
P-P
SER
6
Cycles
SPI Port Timing (Note 8)
l
l
t
SCK Period
Write Mode
Readback Mode, C
40
250
ns
ns
SCK
= 20pF, R
= 2k
SDO
PULLUP
l
l
l
l
l
t
t
t
t
t
CS to SCK Set-Up Time
SCK to CS Set-Up Time
SDI Set-Up Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO Valid Readback Mode
125
C
= 20pF, R
= 2k
SDO
PULLUP
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 00 0000 0000 0000 and 11 1111 1111
1111 in 2’s complement output mode.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 8: Guaranteed by design, not subject to test.
Note 3: When these pin voltages are taken below GND or above V , they
DD
will be clamped by internal diodes. This product can handle input currents
Note 9: V = OV = 1.8V, f
(LTC2171), or 25MHz (LTC2170), 2-lane output mode, ENC = single-
ended 1.8V square wave, ENC = 0V, input range = 2V with differential
= 65MHz (LTC2172), 40MHz
DD
DD
SAMPLE
+
of greater than 100mA below GND or above V without latchup.
DD
–
Note 4: When these pin voltages are taken below GND they will be
P-P
drive, unless otherwise noted. The supply current and power dissipation
specifications are totals for the entire chip, not per channel.
Note 10: Recommended operating conditions.
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
DD
Note 5: V = OV = 1.8V, f
= 65MHz (LTC2172),
DD
DD
SAMPLE
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
40MHz (LTC2171), or 25MHz (LTC2170), 2-lane output mode, differential
+
–
ENC /ENC = 2V sine wave, input range = 2V with differential drive,
P-P
P-P
data rate is 1000Mbps, so t
must be greater than or equal to 1ns.
SER
unless otherwise noted.
Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.3 to Ch.4.
Far-channel crosstalk refers to Ch.1 to Ch.3, Ch.1 to Ch.4, Ch.2 to Ch.3, and
Ch.2 to Ch.4.
21721014fb
7
LTC2172-14/
LTC2171-14/LTC2170-14
TiMing DiagraMs
2-Lane Output Mode, 16-Bit Serialization*
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
SER
DATA
t
FRAME
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D5
D4
D3
D2
D1
D0
0
0
D13 D11 D9
D7
D6
D5
D4
D3
D2
D1
0
D13 D11 D9
D12 D10 D8
+
OUT#A
–
OUT#B
D12 D10 D8
SAMPLE N-5
D0
0
+
OUT#B
217214 TD01
SAMPLE N-6
*SEE THE DIGITAL OUTPUTS SECTION
SAMPLE N-4
2-Lane Output Mode, 14-Bit Serialization
t
AP
ANALOG
INPUT
N + 2
N + 1
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
SER
DATA
t
FRAME
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D7
D6
D5
D4
D3
D2
D1 D13 D11 D9
D7
D6
D5
D4
D3
D2
D1 D13 D11 D9
D7
D6
D5
D3
D2
D1 D13 D11 D9
+
OUT#A
–
OUT#B
D0 D12 D10 D8
D0 D12 D10 D8
D4
D0 D12 D10 D8
SAMPLE N-3
+
OUT#B
217214 TD02
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
–
+
–
+
NOTE THAT IN THIS MODE, FR /FR HAS TWO TIMES THE PERIOD OF ENC /ENC
21721014fb
8
LTC2172-14/
LTC2171-14/LTC2170-14
TiMing DiagraMs
2-Lane Output Mode, 12-Bit Serialization
t
N + 1
AP
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
SER
DATA
t
FRAME
+
FR
–
FR
t
PD
t
SER
–
OUT#A
D9
D7
D6
D5
D4
D3 D13 D11 D9
D7
D5
D4
D3 D13 D11 D9
+
–
OUT#A
OUT#B
D8
D2 D12 D10 D8
SAMPLE N-5
D6
D2 D12 D10 D8
SAMPLE N-4
+
OUT#B
217214 TD03
SAMPLE N-6
1-Lane Output Mode, 16-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D1
D0
0
0
D13 D12 D11 D10 D9
SAMPLE N-5
D8
D7
D6
D5
D4
D3
D2
D1
D0
0
0
D13 D12 D11 D10
+
OUT#A
217214 TD04
SAMPLE N-6
–
SAMPLE N-4
+
OUT#B , OUT#B ARE DISABLED
21721014fb
9
LTC2172-14/
LTC2171-14/LTC2170-14
TiMing DiagraMs
1-Lane Output Mode, 14-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D3
D2
D1
D0 D13 D12 D11 D10 D9
SAMPLE N-5
D8
D7
D6
D5
D4
D3
D2
D1
D0 D13 D12 D11 D10
+
OUT#A
217214 TD05
SAMPLE N-6
–
SAMPLE N-4
+
OUT#B , OUT#B ARE DISABLED
1-Lane Output Mode, 12-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D5
D4
D3
D2 D13 D12 D11 D10 D9
SAMPLE N-5
D8
D7
D6
D5
D4
D3
D2 D13 D12 D11
+
OUT#A
217214 TD06
SAMPLE N-6
–
SAMPLE N-4
+
OUT#B , OUT#B ARE DISABLED
21721014fb
10
LTC2172-14/
LTC2171-14/LTC2170-14
TiMing DiagraMs
SPI Port Timing (Readback Mode)
t
S
t
DS
t
DH
t
t
H
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
A3
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SDO
217214 TD07
HIGH IMPEDANCE
21721014fb
11
LTC2172-14/
LTC2171-14/LTC2170-14
Typical perForMance characTerisTics
LTC2172-14: Integral
Nonlinearity (INL)
LTC2172-14: Differential
Nonlinearity (DNL)
LTC2172-14: 8k Point FFT,
IN = 5MHz, –1dBFS, 65Msps
f
2.0
1.5
0
–10
–20
–30
–40
–50
–60
–70
1.0
0.8
0.6
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
0
8192
12288
16384
0
20
10
FREQUENCY (MHz)
30
4096
0
8192
12288
16384
4096
OUTPUT CODE
OUTPUT CODE
217214 G01
217214 G03
217214 G02
LTC2172-14: 8k Point FFT,
fIN = 30MHz, –1dBFS, 65Msps
LTC2172-14: 8k Point FFT,
fIN = 70MHz, –1dBFS, 65Msps
LTC2172-14: 8k Point FFT,
fIN = 140MHz, –1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10
20
30
0
20
10
FREQUENCY (MHz)
30
0
20
10
FREQUENCY (MHz)
30
FREQUENCY (MHz)
217214 G05
217214 G04
217214 G06
LTC2172-14: 8k Point 2-Tone FFT,
IN = 68MHz, 69MHz, –1dBFS,
65Msps
LTC2172-14: SNR vs Input
Frequency, –1dBFS, 2V Range,
65Msps
LTC2172-14: Shorted Input
Histogram
f
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
74
73
72
71
70
69
68
67
66
–80
–90
–100
–110
–120
2000
1000
0
0
20
10
FREQUENCY (MHz)
30
8197
8201
OUTPUT CODE
8203
8205
8199
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
217214 G07
217214 G08
217214 G09
21721014fb
12
LTC2172-14/
LTC2171-14/LTC2170-14
Typical perForMance characTerisTics
LTC2172-14: SFDR vs Input
Frequency, –1dBFS, 2V Range,
65Msps
LTC2172-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 65Msps
LTC2172-14: SNR vs Input Level,
fIN = 70MHz, 2V Range, 65Msps
95
90
85
80
75
70
65
80
70
60
50
40
30
20
10
0
110
100
90
dBFS
dBFS
80
dBc
70
60
dBc
50
40
30
20
10
0
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
–60
–50
–40
–30
–20
–10
0
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
INPUT LEVEL (dBFS)
217214 G10
217214 G50
217214 G11
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dBFS
LTC2172-14: SNR vs SENSE,
IN = 5MHz, –1dBFS
LTC2172-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
f
160
155
50
40
30
75
74
73
72
71
70
2-LANE, 3.5mA
1-LANE, 3.5mA
150
145
140
135
130
125
120
115
110
2-LANE, 1.75mA
1-LANE, 1.75mA
20
10
0
69
68
67
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
10
20
30
40
50
60
0
20
40
60
SENSE PIN (V)
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
217214 G14
217214 G53
217214 G51
LTC2171-14: Integral Nonlinearity
(INL)
LTC2171-14: Differential
Nonlinearity (DNL)
LTC2171-14: 8k Point FFT,
fIN = 5MHz –1dBFS, 40Msps
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
2.0
1.5
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
–80
–90
–100
–110
–120
0
8192
12288
16384
4096
0
20
0
8192
12288
16384
10
4096
OUTPUT CODE
FREQUENCY (MHz)
OUTPUT CODE
217214 G16
217214 G17
217214 G15
21721014fb
13
LTC2172-14/
LTC2171-14/LTC2170-14
Typical perForMance characTerisTics
LTC2171-14: 8k Point FFT,
fIN = 29MHz, –1dBFS, 40Msps
LTC2171-14: 8k Point FFT,
fIN = 69MHz, –1dBFS, 40Msps
LTC2171-14: 8k Point FFT,
fIN = 139MHz, –1dBFS, 40Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
0
20
10
10
0
20
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
217214 G18
217214 G20
217214 G19
LTC2171-14: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
40Msps
LTC2171-14: SNR vs Input
Frequency, –1dBFS,
2V Range, 40Msps
LTC2171-14: Shorted Input
Histogram
0
–10
–20
–30
–40
–50
–60
–70
74
73
72
71
70
6000
5000
4000
3000
69
68
67
66
–80
–90
–100
–110
–120
2000
1000
0
0
20
10
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
8198
8202
OUTPUT CODE
8204
8206
8200
FREQUENCY (MHz)
217214 G21
217214 G23
217214 G22
LTC2171-14: SFDR vs Input
Frequency, –1dBFS, 2V Range,
40Msps
LTC2171-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 40Msps
LTC2171-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
100
95
90
85
80
75
70
95
90
85
80
75
70
65
110
100
90
dBFS
80
70
60
dBc
50
40
30
20
10
0
0
10
20
30
40
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
SAMPLE RATE (Msps)
217214 G54
217214 G24
217214 G25
21721014fb
14
LTC2172-14/
LTC2171-14/LTC2170-14
Typical perForMance characTerisTics
LTC2171-14: SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2170-14: Integral Nonlinearity
(INL)
LTC2170-14: Differential
Nonlinearity (DNL)
1.0
0.8
0.6
74
73
72
71
70
69
2.0
1.5
1.0
0.4
0.2
0
0.5
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.5
–1.0
–1.5
–2.0
68
67
66
0
8192
12288
16384
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
4096
0
8192
12288
16384
4096
OUTPUT CODE
SENSE PIN (V)
OUTPUT CODE
217214 G29
217214 G27
217214 G28
LTC2170-14: 8k Point FFT,
fIN = 5MHz –1dBFS, 25Msps
LTC2170-14: 8k Point FFT,
fIN = 30MHz –1dBFS, 25Msps
LTC2170-14: 8k Point FFT,
fIN = 70MHz –1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10
0
10
5
5
0
10
5
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
217214 G30
217214 G32
217214 G31
LTC2170-14: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
25Msps
LTC2170-14: 8k Point FFT,
LTC2170-14: Shorted Input
Histogram
f
IN = 140MHz –1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
6000
5000
4000
3000
–80
–90
–100
–110
–120
–80
–90
–100
–110
–120
2000
1000
0
0
10
0
10
5
5
8198
8202
8204
8206
8200
FREQUENCY (MHz)
FREQUENCY (MHz)
OUTPUT CODE
217214 G33
217214 G34
217214 G35
21721014fb
15
LTC2172-14/
LTC2171-14/LTC2170-14
Typical perForMance characTerisTics
LTC2170-14: SFDR vs Input
Frequency, –1dBFS, 2V Range,
25Msps
LTC2170-14: SNR vs Input
Frequency, –1dBFS, 2V Range,
25Msps
LTC2170-14: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 25Msps
110
100
90
95
90
85
80
75
70
65
74
73
72
71
70
dBFS
80
70
dBc
60
50
40
30
20
10
0
69
68
67
66
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
50
217214 G38
217214 G37
217214 G36
LTC2170-14: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
LTC2170-14: SNR vs SENSE,
IN = 5MHz, –1dBFS
DCO Cycle-Cycle Jitter vs Serial
Data Rate
f
350
300
250
200
150
80
75
70
65
74
73
72
71
70
69
100
50
0
68
67
66
60
0
5
10
15
20
25
0
200
400
600
800
1000
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
SAMPLE RATE (Msps)
SERIAL DATA RATE (Mbps)
SENSE PIN (V)
217214 G55
217214 G52
217214 G40
21721014fb
16
LTC2172-14/
LTC2171-14/LTC2170-14
pin FuncTions
+
A
(Pin 1): Channel 1 Positive Differential Analog
(Pin 2): Channel 1 Negative Differential Analog
(Pin 3): Common Mode Bias Output, Nominally
CS(Pin19):Inserialprogrammingmode(PAR/SER=0V),
CS is the serial interface chip select input. When CS is low,
SCK is enabled for shifting data on SDI into the mode
controlregisters.Inparallelprogrammingmode(PAR/SER
IN1
Input.
–
A
IN1
Input.
= V ), CS selects two-lane or one-lane output mode. CS
DD
V
CM12
can be driven with 1.8V to 3.3V logic.
Equal to V /2. V should be used to bias the common
DD
CM
SCK (Pin 20): In serial programming mode (PAR/SER
= 0V), SCK is the serial interface clock input. In parallel
mode of the analog inputs of channels 1 and 2. Bypass
to ground with a 0.1µF ceramic capacitor.
programmingmode(PAR/SER=V ),SCKselects3.5mA
DD
+
A
(Pin 4): Channel 2 Positive Differential Analog
(Pin 5): Channel 2 Negative Differential Analog
IN2
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to 3.3V logic.
Input.
–
A
IN2
SDI (Pin 21): In serial programming mode (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In parallel programming mode (PAR/SER =
Input.
REFH (Pins 6, 7): ADC High Reference. Bypass to Pin 8
and Pin 9 with a 2.2µF ceramic capacitor, and to ground
with a 0.1µF ceramic capacitor.
V ), SDI can be used to power down the part. SDI can
DD
be driven with 1.8V to 3.3V logic.
REFL (Pins 8, 9): ADC Low Reference. Bypass to Pin 6
and Pin 7 with a 2.2µF ceramic capacitor, and to ground
with a 0.1µF ceramic capacitor.
GND (Pins 22, 45, 49, Exposed Pad Pin 53): ADC Power
Ground. The exposed pad must be soldered to the PCB
ground.
+
A
(Pin 10): Channel 3 Positive Differential Analog
(Pin 11): Channel 3 Negative Differential Analog
(Pin 12): Common Mode Bias Output, Nominally
IN3
Input.
OGND (Pin 33): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
–
A
IN3
Input.
OV (Pin 34): Output Driver Supply. Bypass to ground
DD
V
CM34
with a 0.1µF ceramic capacitor.
Equal to V /2. V should be used to bias the common
DD
CM
mode of the analog inputs of channels 3 and 4. Bypass
SDO (Pin 46): In serial programming mode (PAR/SER
= 0V), SDO is the optional serial interface data output.
DataonSDOisreadbackfromthemodecontrolregisters
and can be latched on the falling edge of SCK. SDO is
an open-drain N-channel MOSFET output that requires
an external 2k pull-up resistor of 1.8V to 3.3V. If read-
back from the mode control registers is not needed,
the pull-up resistor is not necessary and SDO can be
left unconnected. In parallel programming mode (PAR/
to ground with a 0.1µF ceramic capacitor.
+
A
(Pin 13): Channel 4 Positive Differential Analog
(Pin 14): Channel 4 Negative Differential Analog
IN4
Input.
–
A
IN4
Input.
V
(Pins 15, 16, 51, 52): 1.8V Analog Power Supply.
DD
Bypasstogroundwith0.1µFceramiccapacitors. Adjacent
pins can share a bypass capacitor.
SER = V ), SDO is an input that enables internal 100Ω
DD
+
termination resistors on the digital outputs. When used
as an input, SDO can be driven with 1.8V to 3.3V logic
through a 1k series resistor.
ENC (Pin 17): Encode Input. Conversion starts on the
rising edge.
–
ENC (Pin 18): Encode Complement Input. Conversion
starts on the falling edge.
21721014fb
17
LTC2172-14/
LTC2171-14/LTC2170-14
pin FuncTions
PAR/SER (Pin 47): Programming Mode Selection Pin.
Connect to ground to enable serial programming mode.
CS, SCK, SDI and SDO become a serial interface that con-
LVDS OUTPUTS
The following pins are differential LVDS outputs. The
output current level is programmable. There is an op-
tional internal 100Ω termination resistor between the
pins of each LVDS output pair.
trols the A/D operating modes. Connect to V to enable
DD
parallel programming mode where CS, SCK, SDI and SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the V of the part and not be driven
by a logic signal.
–
+
–
+
OUT4B /OUT4B , OUT4A /OUT4A (Pins 23/24,
Pins 25/ 26): Serial Data Outputs for Channel 4. In 1-lane
DD
–
+
output mode, only OUT4A /OUT4A are used.
–
+
–
+
OUT3B /OUT3B , OUT3A /OUT3A (Pins 27/28,
V
(Pin48):ReferenceVoltageOutput.Bypasstoground
REF
Pins 29/30): Serial Data Outputs for Channel 3. In
with a 1µF ceramic capacitor, nominally 1.25V.
–
+
1-lane output mode, only OUT3A /OUT3A are used.
SENSE (Pin 50): Reference Programming Pin. Connect-
–
+
FR /FR (Pin 31/Pin 32): Frame Start Output.
ing SENSE to V selects the internal reference and a
DD
–
+
DCO /DCO (Pin 35/Pin 36): Data Clock Output.
1V input range. Connecting SENSE to ground selects
the internal reference and a 0.5V input range. An external
reference between 0.625V and 1.3V applied to SENSE
–
+
–
+
OUT2B /OUT2B , OUT2A /OUT2A (Pins 37/38,
Pins 39/40): Serial Data Outputs for Channel 2. In
–
+
selects an input range of ±0.8 • V
.
1-lane output mode, only OUT2A /OUT2A are used.
SENSE
–
+
–
+
OUT1B /OUT1B , OUT1A /OUT1A (Pins 41/42,
Pins 43/44): Serial Data Outputs for Channel 1. In
1-lane output mode, only OUT1A /OUT1A are used.
–
+
21721014fb
18
LTC2172-14/
LTC2171-14/LTC2170-14
FuncTional block DiagraM
+
–
1.8V
ENC ENC
1.8V
OV
V
DD
DD
OUT1A
OUT1B
CHANNEL 1
ANALOG
INPUT
14-BIT
ADC CORE
SAMPLE-
AND-HOLD
PLL
OUT2A
OUT2B
CHANNEL 2
ANALOG
INPUT
14-BIT
ADC CORE
SAMPLE-
AND-HOLD
DATA
SERIALIZER
OUT3A
OUT3B
CHANNEL 3
ANALOG
INPUT
SAMPLE-
AND-HOLD
14-BIT
ADC CORE
OUT4A
OUT4B
CHANNEL 4
ANALOG
INPUT
SAMPLE-
AND-HOLD
14-BIT
ADC CORE
DATA
CLOCKOUT
V
REF
1.25V
REFERENCE
FRAME
1µF
RANGE
SELECT
OGND
REFH
REFL
REF
BUF
SENSE
V
/2
DD
DIFF
REF
AMP
MODE
CONTROL
REGISTERS
217214 F01
GND
REFH
REFL
VCM12
0.1µF
VCM34
0.1µF
0.1µF
2.2µF
0.1µF
PAR/SER CS SCK SDI SDO
0.1µF
Figure 1. Functional Block Diagram
21721014fb
19
LTC2172-14/
LTC2171-14/LTC2170-14
applicaTions inForMaTion
CONVERTER OPERATION
or V output pins, which are nominally V /2. For the
CM34 DD
2V input range, the inputs should swing from V – 0.5V
CM
TheLTC2172-14/LTC2171-14/LTC2170-14arelowpower,
4-channel, 14-bit, 65Msps/40Msps/25Msps A/D convert-
ers that are powered by a single 1.8V supply. The analog
inputs should be driven differentially. The encode input
can be driven differentially for optimal jitter performance,
or single-ended for lower power consumption. The digital
outputs are serial LVDS to minimize the number of data
lines. Each channel outputs two bits at a time (2-lane
mode) or one bit at a time (1-lane mode). Many additional
features can be chosen by programming the mode control
registers through a serial SPI port.
to V + 0.5V. There should be a 180° phase difference
CM
between the inputs.
The four channels are simultaneously sampled by a
shared encode circuit (Figure 2).
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right
at the analog inputs. This lowpass filter isolates the
drive circuitry from the A/D sample-and-hold switch-
ing and limits wideband noise from the drive circuitry.
Figure 3 shows an example of an input RC filter. The RC
component values should be chosen based on the ap-
plication’s input frequency.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differen-
tially around a common mode voltage set by the V
CM12
50Ω
V
LTC2172-14
CM
V
V
DD
C
C
0.1µF
SAMPLE
3.5pF
R
ON
0.1µF
T1
1:1
10Ω
10Ω
25Ω
+
25Ω
+
–
A
IN
A
A
ANALOG
INPUT
IN
C
PARASITIC
LTC2172-14
0.1µF
25Ω
25Ω
1.8pF
DD
12pF
SAMPLE
3.5pF
R
25Ω
ON
–
25Ω
A
IN
IN
C
1.8pF
PARASITIC
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
217214 F03
V
DD
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
1.2V
10k
+
–
ENC
ENC
10k
1.2V
217214 F02
Figure 2. Equivalent Input Circuit. Only One of
the Four Analog Channels Is Shown.
21721014fb
20
LTC2172-14/
LTC2171-14/LTC2170-14
applicaTions inForMaTion
Transformer Coupled Circuits
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with V , setting the A/D input at its opti-
CM
mal DC level. At higher input frequencies a transmission
line balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
4 to 6) should convert the signal to differential before
driving the A/D.
50Ω
50Ω
V
V
CM
CM
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
0.1µF
+
+
A
A
IN
ANALOG
INPUT
IN
ANALOG
INPUT
T2
T2
LTC2172-14
LTC2172-14
T1
T1
0.1µF
0.1µF
25Ω
25Ω
25Ω
25Ω
4.7pF
1.8pF
–
–
A
A
IN
IN
217214 F04
217214 F05
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 70MHz to 170MHz
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 170MHz to 300MHz
V
CM
50Ω
V
CM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
200Ω 200Ω
25Ω
0.1µF
A
0.1µF
0.1µF
+
–
0.1µF
0.1µF
A
IN
2.7nH
0.1µF
+
–
IN
ANALOG
INPUT
LTC2172-14
ANALOG
INPUT
LTC2172-14
+
+
25Ω
25Ω
T1
12pF
A
–
–
2.7nH
A
25Ω
IN
IN
217214 F06
217214 F07
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 300MHz
21721014fb
21
LTC2172-14/
LTC2171-14/LTC2170-14
applicaTions inForMaTion
Reference
Encode Input
TheLTC2172-14/LTC2171-14/LTC2170-14hasaninternal
1.25V voltage reference. For a 2V input range using the
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
internal reference, connect SENSE to V . For a 1V input
DD
range using the internal reference, connect SENSE to
ground. For a 2V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 9).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
V
REF
will then be 1.6 • V
.
SENSE
1µF
LTC2172-14
The reference is shared by all four ADC channels, so it is
not possible to independently adjust the input range of
individual channels.
1.25V
EXTERNAL
REFERENCE
SENSE
1µF
217214 F09
The V , REFH and REFL pins should be bypassed, as
REF
shown in Figure 8. The 0.1µF capacitor between REFH and
REFL should be as close to the pins as possible (not on
the backside of the circuit board).
Figure 9. Using an External 1.25V Reference
LTC2172-14
LTC2172-14
V
DD
5Ω
V
REF
1.25V BANDGAP
REFERENCE
DIFFERENTIAL
COMPARATOR
1.25V
V
DD
1µF
0.625V
15k
30k
RANGE
DETECT
AND
+
–
ENC
CONTROL
ENC
TIE TO V FOR 2V RANGE;
DD
SENSE
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • V
FOR
SENSE
BUFFER
0.625V < V
< 1.300V
SENSE
INTERNAL ADC
HIGH REFERENCE
217214 F10
0.1µF
REFH
0.1µF
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
2.2µF
0.8x
DIFF AMP
0.1µF
REFL
LTC2172-14
+
INTERNAL ADC
LOW REFERENCE
1.8V TO 3.3V
0V
ENC
–
217214 F08
30k
ENC
CMOS LOGIC
BUFFER
Figure 8. Reference Circuit
217214 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
21721014fb
22
LTC2172-14/
LTC2171-14/LTC2170-14
applicaTions inForMaTion
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12 and 13).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
above V (up to 3.6V), and the common mode range
DD
DIGITAL OUTPUTS
is from 1.1V to 1.6V. In the differential encode mode,
–
The digital outputs of the LTC2172-14/LTC2171-14/
LTC2170-14 are serialized LVDS signals. Each chan-
nel outputs two bits at a time (2-lane mode) or one
bit at a time (1-lane mode). The data can be serialized
with 16-, 14-, or 12-bit serialization (see the Timing
Diagrams section for details). Note that with 12-bit
serialization the two LSBs are not available—this mode
is included for compatibility with the 12-bit versions
of these parts.
ENC should stay at least 200mV above ground to avoid
falsely triggering the single-ended encode mode. For
+
good jitter performance ENC should have fast rise and
fall times.
The single-ended encode mode should be used with
–
CMOS encode inputs. To select this mode, ENC is con-
+
nected to ground and ENC is driven with a square wave
+
encode input. ENC can be taken above V (up to 3.6V)
DD
so 1.8V to 3.3V CMOS logic levels can be used. The
+
+
ENC threshold is 0.9V. For good jitter performance
The output data should be latched on the rising and
falling edges of the data clockout (DCO). A data frame
output (FR) can be used to determine when the data
from a new conversion result begins. In the 2-lane, 14-
bit serialization mode, the frequency of the FR output
is halved.
ENC should have fast rise and fall times.
Clock PLL and Duty Cycle Stabilizer
Theencodeclockismultipliedbyaninternalphase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25µs to lock onto the input clock.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will de-
pend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for
all serialization modes is 5Msps.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from 30% to 70%.
In the serial programming mode it is possible to disable
0.1µF
+
ENC
0.1µF
+
T1
ENC
LTC2172-14
PECL OR
LTC2172-14
LVDS
50Ω
50Ω
100Ω
CLOCK
0.1µF
–
ENC
0.1µF
217214 F13
–
0.1µF
ENC
217214 F12
Figure 13. PECL or LVDS Encode Drive
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
21721014fb
23
LTC2172-14/
LTC2171-14/LTC2170-14
applicaTions inForMaTion
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2172-14. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2171-14) or 25MHz (LTC2170-14).
MAXIMUM SAMPLING
SERIALIZATION MODE
2-Lane
FREQUENCY, f (MHz)
DCO FREQUENCY
4 • f
FR FREQUENCY
SERIAL DATA RATE
S
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
65
65
f
8 • f
7 • f
6 • f
S
S
S
S
S
2-Lane
3.5 • f
0.5 • f
S
S
2-Lane
65
3 • f
8 • f
7 • f
6 • f
f
S
f
S
f
S
f
S
S
1-Lane
62.5
65
16 • f
14 • f
12 • f
S
S
S
S
S
S
1-Lane
1-Lane
65
By default the outputs are standard LVDS levels: a 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
The outputs are powered by OV and OGND which are
DD
Table 2. Output Codes vs Input Voltage
isolated from the A/D core power and ground.
+
–
A
– A
D13-D0
D13-D0
IN
IN
(2V RANGE)
>1.000000V
+0.999878V
+0.999756V
+0.000122V
+0.000000V
–0.000122V
–0.000244V
–0.999878V
–1.000000V
≤–1.000000V
(OFFSET BINARY)
(2’s COMPLEMENT)
Programmable LVDS Output Current
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
Thedefaultoutputdrivercurrentis3.5mA.Thiscurrentcan
be adjusted by control register A2 in serial programming
mode.Availablecurrentlevelsare1.75mA,2.1mA,2.5mA,
3mA, 3.5mA, 4mA and 4.5mA. In parallel programming
mode the SCK pin can select either 3.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
beenabledbyseriallyprogrammingmodecontrolregister
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing. In
parallel programming mode the SDO pin enables internal
termination. Internalterminationshouldonly beusedwith
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Digital Output Randomizer
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones in
the ADC output spectrum. These unwanted tones can be
randomized by randomizing the digital output before it is
transmitted off chip, which reduces the unwanted tone
amplitude.
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
21721014fb
24
LTC2172-14/
LTC2171-14/LTC2170-14
applicaTions inForMaTion
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The FR and DCO outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A1.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2172-14/LTC2171-14/
LTC2170-14 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more flexibility and can program all available modes.
Theparallelinterfaceismorelimitedandcanonlyprogram
some of the more commonly used modes.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
(D13-D0) of all channels to known values. The digital
output test patterns are enabled by serially programming
mode control registers A3 and A4. When enabled, the test
patterns override all other formatting modes: 2’s comple-
ment and randomizer.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V . The CS, SCK, SDI and SDO pins are binary
DD
logic inputs that set certain operating modes. These pins
can be tied to V or ground, or driven by 1.8V, 2.5V or
DD
3.3V CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table 3 shows the
modes set by CS, SCK, SDI and SDO.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A2. The current drive for all
digitaloutputs, includingDCOandFR, aredisabledtosave
powerorenablein-circuittesting.Whendisabled,thecom-
mon mode of each output pair becomes high impedance,
but the differential impedance may remain low.
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD
)
PIN
DESCRIPTION
CS
2-Lane/1-Lane Selection Bit
0 = 2-Lane, 16-Bit Serialization Output Mode
1 = 1-Lane, 14-Bit Serialization Output Mode
LVDS Current Selection Bit
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Power Down Control Bit
SCK
SDI
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire chip is powered down,
resulting in 1mW power consumption. Sleep mode is
enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
depends on the size of the bypass capacitors on V
REFH and REFL. For the suggested values in Figure 8, the
A/D will stabilize after 2ms.
0 = Normal Operation
1 = Sleep Mode
SDO
Internal 100Ω Termination Selection Bit
0 = Internal Termination Disabled
1 = Internal Termination Enabled
,
REF
Serial Programming Mode
In nap mode any combination of A/D channels can be
powereddownwhiletheinternalreferencecircuitsandthe
PLL stay active, allowing a faster wake-up than from sleep
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands very accurate DC
settling, then an additional 50µs should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
leavesnapmode.Napmodeisenabledbythemodecontrol
register A1 in the serial programming mode.
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
21721014fb
25
LTC2172-14/
LTC2171-14/LTC2170-14
applicaTions inForMaTion
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed.Table4showsamapofthemodecontrolregisters.
If the R/W bit is low, the serial data (D7:D0) will be
written to the register set by the address bits (A6:A0).
If the R/W bit is high, data in the register set by the
address bits (A6:A0) will be read back on the SDO pin
(see the Timing Diagrams section). During a readback
command the register is not updated and data on SDI
is ignored.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
D5
D4
X
D3
X
D2
X
D1
X
D0
X
RESET
X
Bit 7
RESET
0 = Not Used
Software Reset Bit
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode. This bit is
automatically set back to zero after the reset is complete at the end of the SPI write command. The reset register is write only.
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
D3
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_4
NAP_3
NAP_2
NAP_1
Bit 7
Bit 6
Bit 5
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended.
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Two’s Complement Mode Control Bit
Bits 4-0
SLEEP:NAP_4:NAP_1
00000 = Normal Operation
Sleep/Nap Mode Control Bits
0XXX1 = Channel 1 in Nap Mode
0XX1X = Channel 2 in Nap Mode
0X1XX = Channel 3 in Nap Mode
01XXX = Channel 4 in Nap Mode
1XXXX = Sleep Mode. All Channels Are Disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
21721014fb
26
LTC2172-14/
LTC2171-14/LTC2170-14
applicaTions inForMaTion
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7
D6
D5
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE2
OUTMODE1
OUTMODE0
Bits 7-5
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 4
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0. Internal termination should only be
used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Bit 3
OUTOFF
Output Disable Bit
0 = Digital Outputs are enabled.
1 = Digital Outputs are disabled.
Bits 2-0
OUTMODE2:OUTMODE0 Digital Output Mode Control Bits
000 = 2-Lanes, 16-Bit Serialization
001 = 2-Lanes, 14-Bit Serialization
010 = 2-Lanes, 12-Bit Serialization
011 = Not Used
100 = Not Used
101 = 1-Lane, 14-Bit Serialization
110 = 1-Lane, 12-Bit Serialization
111 = 1-Lane, 16-Bit Serialization
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
X
D5
D4
D3
D2
D1
D0
OUTTEST
TP13
TP12
TP11
TP10
TP9
TP8
Bit 7
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bit 6
Unused, Don’t Care Bit.
Bits 5-0
TP13:TP8
Test Pattern Data Bits (MSB)
TP13:TP8 Set the Test Pattern for Data Bit 13 (MSB) Through Data Bit 8.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
D2
D1
D0
TP7
TP6
TP5
TP4
TP3
TP2
TP1
TP0
Bits 7-0
TP7:TP0
Test Pattern Data Bits (LSB)
TP7:TP0 Set the Test Pattern for Data Bit 7 Through Data Bit 0 (LSB).
21721014fb
27
LTC2172-14/
LTC2171-14/LTC2170-14
applicaTions inForMaTion
GROUNDING AND BYPASSING
between REFH and REFL can be somewhat further away.
Thetracesconnectingthepinsandbypasscapacitorsmust
be kept short and should be made as wide as possible.
The LTC2172-14/LTC2171-14/LTC2170-14 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
The analog inputs, encode signals and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
High quality ceramic bypass capacitors should be used at
MostoftheheatgeneratedbytheLTC2172-14/LTC2171-14/
LTC2170-14istransferredfromthediethroughthebottom-
sideexposedpadandpackageleadsontotheprintedcircuit
board. For good electrical and thermal performance, the
exposed pad must be soldered to a large grounded pad
on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
the V , OV , V , V , REFH and REFL pins. Bypass
DD
DD CM REF
capacitorsmustbelocatedasclosetothepinsaspossible.
Of particular importance is the 0.1µF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2µF capacitor
21721014fb
28
LTC2172-14/
LTC2171-14/LTC2170-14
Typical applicaTions
Silkscreen Top
Top Side
Inner Layer 2 GND
Inner Layer 3
21721014fb
29
LTC2172-14/
LTC2171-14/LTC2170-14
Typical applicaTions
Inner Layer 4
Inner Layer 5 Power
Bottom Side
Silkscreen Bottom
21721014fb
30
LTC2172-14/
LTC2171-14/LTC2170-14
Typical applicaTions
LTC2172 Schematic
SENSE
PAR/SER
C4
1µF
R14
1k
SDO
C17
1µF
V
DD
C5
1µF
52 51 50 49 48 47 46 45 44 43 42 41
A
IN1
DIGITAL
OUTPUTS
1
2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
+
–
+
–
+
–
+
C29
0.1µF
OUT2A
A
A
V
A
A
A
A
A
IN1
IN1
IN2
IN2
–
OUT2A
OUT2B
OUT2B
DCO
IN1
3
CM12
4
+
IN2
5
–
IN2
6
DCO
REFH
REFH
REFL
LTC2172
7
OV
OV
DD
DD
C1
2.2µF
C30
0.1µF
8
C16
0.1µF
C2
0.1µF
OGND
9
+
FR
REFL
+
C3
0.1µF
10
11
12
13
14
–
FR
A
IN3
+
–
OUT3A
A
A
A
IN3
IN3
IN3
–
OUT3A
V
CM34
+
+
OUT3B
A
A
IN4
IN4
C59
–
–
OUT3B
0.1µF
DIGITAL
OUTPUTS
A
A
IN4
IN4
15 16 17 18 19 20 21 22 23 24 25 26
V
DD
C7
0.1µF
SPI BUS
C47
0.1µF
C46
0.1µF
217214 TA02
ENCODE
CLOCK
ENCODE
CLOCK
21721014fb
31
LTC2172-14/
LTC2171-14/LTC2170-14
package DescripTion
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.50 0.05
6.10 0.05
5.50 REF
(2 SIDES)
0.70 0.05
6.45 0.05
6.50 REF
(2 SIDES)
7.10 0.05 8.50 0.05
5.41 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.50 REF
(2 SIDES)
0.75 0.05
7.00 0.10
(2 SIDES)
R = 0.115
TYP
0.00 – 0.05
51
52
0.40 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
6.45 0.10
8.00 0.10
(2 SIDES)
6.50 REF
(2 SIDES)
5.41 0.10
(UKG52) QFN REV
Ø 0306
R = 0.10
TYP
0.25 0.05
0.50 BSC
TOP VIEW
SIDE VIEW
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
0.75 0.05
NOTE:
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
21721014fb
32
LTC2172-14/
LTC2171-14/LTC2170-14
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
03/10 Changed Sampling Frequency Max for LTC2171-14 from 45MHz to 40MHz in the Timing Characteristics section.
Added full part numbers to Grounding and Bypassing and Heat Transfer sections in Applications Information.
Revised Descriptions and Comments in the Related Parts section.
6
28
34
18
26
B
07/11 Corrected pin names for Pins 41-44 in the Pin Functions section.
Revised Software Reset paragraph and Table 4 in the Applications Information section.
21721014fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC2172-14/
LTC2171-14/LTC2170-14
relaTeD parTs
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2170-12/LTC2171-
12/LTC2172-12
12-Bit, 25Msps/40Msps/65Msps
1.8V Quad ADCs, Ultralow Power
160mW/198mW/306mW, 71dB SNR, 90dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC2173-12/LTC2174-
12/LTC2175-12
12-Bit, 80Msps/105Msps/125Msps
1.8V Quad ADCs, Ultralow Power
369mW/439mW/545mW, 70.6dB SNR, 88dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC2256-14/LTC2257-
14/LTC2258-14
14-Bit, 25Msps/40Msps/65Msps
1.8V ADCs, Ultralow Power
35mW/49mW/81mW, 74dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS
Outputs, 6mm × 6mm QFN-40
LTC2259-14/LTC2260-
14/LTC2261-14
14-Bit, 80Msps/105Msps/125Msps
1.8V ADCs, Ultralow Power
89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS
Outputs, 6mm × 6mm QFN-40
LTC2262-14
14-Bit, 150Msps 1.8V ADC, Ultralow Power 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
6mm × 6mm QFN-40
LTC2263-14/LTC2264-
14/LTC2265-14
14-Bit, 25Msps/40Msps/65Msps
1.8V Dual ADCs, Ultralow Power
94mW/113mW/171mW, 73.7dB SNR, 90dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2263-12/LTC2264-
12/LTC2265-12
12-Bit, 25Msps/40Msps/65Msps
1.8V Dual ADCs, Ultralow Power
94mW/112mW/167mW, 71dB SNR, 90dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2266-14/LTC2267-
14/LTC2268-14
14-Bit, 80Msps/105Msps/125Msps
1.8V Dual ADCs, Ultralow Power
203mW/243mW/299mW, 73.1dB SNR, 88dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2266-12/LTC2267-
12/LTC2268-12
12-Bit, 80Msps/105Msps/125Msps
1.8V Dual ADCs, Ultralow Power
200mW/238mW/292mW, 70.6dB SNR, 88dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
RF Mixers/Demodulators
LTC5517
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5527
LTC5557
LTC5575
400MHz to 3.7GHz High Linearity
Downconverting Mixer
24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 1900MHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports, 5V Supply
400MHz to 3.8GHz High Linearity
Downconverting Mixer
24.7dBm IIP3 at 1950MHz, 23.7dBm IIP3 at 2.6GHz, NF = 13.2dB, 3.3V Supply
Operation, Integrated Transformer
800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF
and LO Transformer
Amplifiers/Filters
LTC6412
800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise
Variable Gain Amplifier
Figure, 4mm × 4mm QFN-24
LTC6420-20
LTC6421-20
Dual Low Noise, Low Distortion
Fixed Gain 10V/V, 2.2nV/√Hz Total Input Referred Noise, 80mA Supply Current per
Differential ADC Drivers for 300MHz IF
Amplifier, 46dBm OIP3 at 100MHz, 3mm × 4mm QFN-20
Dual Low Noise, Low Distortion
Differential ADC Drivers for 140MHz IF
Fixed Gain 10V/V, 2.2nV/√Hz Total Input Referred Noise, 40mA Supply Current per
Amplifier, 42dBm OIP3 at 100MHz, 3mm × 4mm QFN-20
LTC6605-7/ LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz Filters Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
LTC6605-14
with ADC Drivers
Pin-Programmable Gain, 6mm × 3mm DFN-22
Signal Chain Receivers
LTM9002
14-Bit Dual Channel IF/Baseband Receiver Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
Subsystem
21721014fb
LT 0711 REV B • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
34
●
●
LINEAR TECHNOLOGY CORPORATION 2010
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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