LTC2170CUKG-12TRPBF [Linear]
12-Bit, 65Msps/40Msps/25Msps Low Power Quad ADCs; 12位，支持65Msps / 40Msps的/ 25Msps时的低功耗四通道ADC
| 型号： | LTC2170CUKG-12TRPBF |
| 厂家： | 
Linear |
| 描述： | 12-Bit, 65Msps/40Msps/25Msps Low Power Quad ADCs |
| 文件： | 总34页 (文件大小：1586K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2172-12/
LTC2171-12/LTC2170-12
12-Bit, 65Msps/40Msps/
25Msps Low Power Quad ADCs
FEATURES
DESCRIPTION
TheLTC®2172-12/LTC2171-12/LTC2170-12are4-channel,
simultaneoussampling12-bitA/Dconvertersdesignedfor
digitizinghighfrequency,widedynamicrangesignals.They
are perfect for demanding communications applications
with AC performance that includes 71dB SNR and 90dB
spurious free dynamic range (SFDR). An ultralow jitter of
n
4-Channel Simultaneous Sampling ADC
n
71dB SNR
n
90dB SFDR
Low Power: ꢀ06mW/198mW/160mW Total,
77mW/50mW/40mW per Channel
Single 1.8V Supply
Serial LVDS Outputs: One or Two Bits per Channel
Selectable Input Ranges: 1V to 2V
n
n
n
0.15ps
allows undersampling of IF frequencies with
RMS
n
excellent noise performance.
P-P
P-P
n
n
n
n
n
800MHz Full Power Bandwidth Sample-and-Hold
Shutdown and Nap Modes
DC specifications include 0.ꢀLSB INL (typ), 0.1LSB
DNL (typ) and no missing codes over temperature. The
transition noise is a low 0.ꢀLSB
Serial SPI Port for Configuration
.
RMS
Pin-Compatible 14-Bit and 12-Bit Versions
52-Pin (7mm × 8mm) QFN Package
The digital outputs are serial LVDS to minimize the num-
ber of data lines. Each channel outputs two bits at a time
(2-lanemode)oronebitatatime(1-lanemode).TheLVDS
drivers have optional internal termination and adjustable
output levels to ensure clean signal integrity.
APPLICATIONS
n
Communications
n
Cellular Base Stations
+
–
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL or
CMOS inputs. An internal clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n
Software Defined Radios
n
Portable Medical Imaging
n
Multichannel Data Acquisition
n
Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
1.8V
V
1.8V
OV
DD
DD
LTC2172-12, 65Msps,
2-Tone FFT, fIN = 70MHz and 75MHz
CHANNEL 1
ANALOG
INPUT
12-BIT
ADC CORE
OUT1A
OUT1B
S/H
S/H
S/H
S/H
0
–10
–20
–30
CHANNEL 2
ANALOG
INPUT
OUT2A
OUT2B
12-BIT
ADC CORE
DATA
SERIALIZER
–40
SERIALIZED
CHANNEL ꢀ
ANALOG
INPUT
OUTꢀA
OUTꢀB
12-BIT
ADC CORE
–50
LVDS
OUTPUTS
–60
–70
CHANNEL 4
ANALOG
INPUT
OUT4A
OUT4B
12-BIT
ADC CORE
–80
–90
–100
–110
–120
DATA
CLOCK
OUT
ENCODE
INPUT
PLL
0
20
10
FREQUENCY (MHz)
30
FRAME
217212 TA01b
GND
OGND
217212 TA01
21721012fa
1
LTC2172-12/
LTC2171-12/LTC2170-12
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1 and 2)
TOP VIEW
Supply Voltages
V
, OV ............................................... –0.ꢀV to 2V
DD
DD
+
–
Analog Input Voltage (A , A
,
IN
IN
52 51 50 49 48 47 46 45 44 4ꢀ 42 41
PAR/SER, SENSE) (Note ꢀ)...........–0.ꢀV to (V + 0.2V)
DD
+
–
+
–
+
–
+
–
A
A
1
2
40 OUT2A
ꢀ9 OUT2A
IN1
IN1
Digital Input Voltage (ENC , ENC , CS,
SDI, SCK) (Note 4).................................... –0.ꢀV to ꢀ.9V
SDO (Note 4) ............................................ –0.ꢀV to ꢀ.9V
V
OUT2B
ꢀ
ꢀ8
ꢀ7
CM12
+
A
OUT2B
+
4
IN2
IN2
–
Digital Output Voltage ................ –0.ꢀV to (OV + 0.ꢀV)
Operating Temperature Range
LTC2172C, LTC2171C, LTC2170C............. 0°C to 70°C
LTC2172I, LTC2171I, LTC2170I............ –40°C to 85°C
Storage Temperature Range................... –65°C to 150°C
DD
A
5
ꢀ6 DCO
–
REFH
REFH
REFL
DCO
6
ꢀ5
7
ꢀ4 OV
DD
5ꢀ
GND
8
ꢀꢀ OGND
+
REFL
+
9
ꢀ2 FR
–
A
A
10
11
12
1ꢀ
14
ꢀ1 FR
INꢀ
–
+
–
+
–
ꢀ0 OUTꢀA
29 OUTꢀA
28 OUTꢀB
27 OUTꢀB
INꢀ
V
CMꢀ4
+
A
IN4
IN4
–
A
15 16 17 18 19 20 21 22 2ꢀ 24 25 26
UKG PACKAGE
52-LEAD (7mm × 8mm) PLASTIC QFN
T
= 150°C, θ = 28°C/W
JA
JMAX
EXPOSED PAD (PIN 5ꢀ) IS GND, MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTC2172UKG-12
LTC2172UKG-12
LTC2171UKG-12
LTC2171UKG-12
LTC2170UKG-12
LTC2170UKG-12
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2172CUKG-12#PBF
LTC2172IUKG-12#PBF
LTC2171CUKG-12#PBF
LTC2171IUKG-12#PBF
LTC2170CUKG-12#PBF
LTC2170IUKG-12#PBF
LTC2172CUKG-12#TRPBF
LTC2172IUKG-12#TRPBF
LTC2171CUKG-12#TRPBF
LTC2171IUKG-12#TRPBF
LTC2170CUKG-12#TRPBF
LTC2170IUKG-12#TRPBF
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
52-Lead (7mm × 8mm) Plastic QFN
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
21721012fa
2
LTC2172-12/
LTC2171-12/LTC2170-12
CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2172-12
TYP
LTC2171-12
TYP
LTC2170-12
TYP MAX
PARAMETER
CONDITIONS
MIN
12
MAX
MIN
12
MAX
MIN
12
UNITS
Bits
l
l
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Linearity Error
Offset Error
Differential Analog Input (Note 6)
Differential Analog Input
(Note 7)
–1
0.ꢀ
0.1
ꢀ
1
–1
0.ꢀ
0.1
ꢀ
1
–1
0.ꢀ
0.1
ꢀ
1
LSB
LSB
mV
–0.5
–12
0.5
12
–0.4
–12
0.4
12
–0.4
–12
0.4
12
Gain Error
Internal Reference
External Reference
–1
–1
–1
–1
–1
–1
%FS
%FS
l
–2.5
0.5
–2.5
0.5
–2.5
0.5
Offset Drift
20
20
20
μV/°C
Full-Scale Drift
Internal Reference
External Reference
ꢀ5
25
ꢀ5
25
ꢀ5
25
ppm/°C
ppm/°C
Gain Matching
Offset Matching
Transition Noise
External Reference
0.2
ꢀ
0.2
ꢀ
0.2
ꢀ
%FS
mV
External Reference
0.ꢀ2
0.ꢀ2
0.ꢀ2
LSB
RMS
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
l
l
l
V
V
V
Analog Input Range (A – A
)
1.7V < V < 1.9V
1 to 2
V
P-P
IN
IN
IN
DD
+
–
Analog Input Common Mode (A + A )/2
Differential Analog Input (Note 8)
External Reference Mode
V
– 100mV
0.625
V
V
+ 100mV
1.ꢀ00
V
IN(CM)
SENSE
IN(CM)
IN
IN
CM
CM
CM
External Voltage Reference Applied to SENSE
Analog Input Common Mode Current
1.250
V
I
Per Pin, 65Msps
Per Pin, 40Msps
Per Pin, 25Msps
81
50
ꢀ1
μA
μA
μA
+
–
l
l
l
I
I
I
t
t
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
0 < A , A < V
DD
–1
–ꢀ
–6
1
ꢀ
6
μA
μA
μA
ns
IN1
IN
IN
0 < PAR/SER < V
IN2
DD
SENSE Input Leakage Current
0.625 < SENSE < 1.ꢀV
INꢀ
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
Analog Input Common Mode Rejection Ratio
0
AP
0.15
80
ps
RMS
JITTER
CMRR
dB
BW-ꢀB Full-Power Bandwidth
Figure 6 Test Circuit
800
MHz
21721012fa
3
LTC2172-12/
LTC2171-12/LTC2170-12
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2172-12
TYP
LTC2171-12
TYP
LTC2170-12
TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
SNR
Signal-to-Noise Ratio
5MHz Input
71
71
70.9
70.8
70.8
70.5
70.5
70.5
70.5
70.2
dBFS
dBFS
dBFS
dBFS
l
l
l
l
ꢀ0MHz Input
70MHz Input
140MHz Input
69.7
69.5
69.ꢀ
70.9
70.6
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd or ꢀrd Harmonic
90
90
89
84
90
90
89
84
90
90
89
84
dBFS
dBFS
dBFS
dBFS
ꢀ0MHz Input
70MHz Input
140MHz Input
77
85
79
85
79
85
Spurious Free Dynamic Range 5MHz Input
4th Harmonic or Higher
90
90
90
90
90
90
90
90
90
90
90
90
dBFS
dBFS
dBFS
dBFS
ꢀ0MHz Input
70MHz Input
140MHz Input
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70.9
70.9
70.7
70.ꢀ
70.8
70.7
70.6
70.2
70.5
70.4
70.ꢀ
69.9
dBFS
dBFS
dBFS
dBFS
ꢀ0MHz Input
70MHz Input
140MHz Input
69.1
69.4
69.2
Crosstalk, Near Channel
Crosstalk, Far Channel
10MHz Input (Note 12)
10MHz Input (Note 12)
–90
–90
–90
dBc
dBc
–105
–105
–105
INTERNAL REFERENCE CHARACTERISTICS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
PARAMETER
CONDITIONS
= 0
MIN
TYP
0.5 • V
25
MAX
UNITS
V
V
CM
V
CM
V
CM
V
REF
V
REF
V
REF
V
REF
Output Voltage
I
0.5 • V – 25mV
0.5 • V + 25mV
OUT
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
ppm/°C
Ω
–600μA < I
< 1mA
< 1mA
4
OUT
I
= 0
1.225
1.250
25
1.275
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400μA < I
7
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
21721012fa
4
LTC2172-12/
LTC2171-12/LTC2170-12
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
ENCODE INPUTS (ENC , ENC )
–
Differential Encode Mode (ENC Not Tied to GND)
l
V
V
Differential Input Voltage
(Note 8)
0.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
1.2
V
V
ICM
l
l
1.1
0.2
1.6
ꢀ.6
+
–
V
IN
Input Voltage Range
Input Resistance
ENC , ENC to GND
(See Figure 10)
V
kΩ
pF
R
10
IN
IN
C
Input Capacitance
ꢀ.5
–
Single-Ended Encode Mode (ENC Tied to GND)
l
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
V
V
= 1.8V
= 1.8V
1.2
0
V
V
IH
IL
IN
DD
DD
0.6
ꢀ.6
+
ENC to GND
V
R
(See Figure 11)
ꢀ0
kΩ
pF
IN
IN
C
Input Capacitance
ꢀ.5
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 1.8V
1.ꢀ
V
V
IH
IL
DD
DD
IN
l
l
= 1.8V
0.6
10
I
= 0V to ꢀ.6V
–10
μA
pF
IN
C
Input Capacitance
ꢀ
200
ꢀ
IN
SDO OUTPUT (Serial Programming Mode. Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
= 1.8V, SDO = 0V
DD
Ω
μA
pF
OL
l
I
OH
SDO = 0V to ꢀ.6V
–10
10
C
OUT
DIGITAL DATA OUTPUTS
l
l
V
Differential Output Voltage
100Ω Differential Load, ꢀ.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
125
ꢀ50
175
454
250
mV
mV
OD
l
l
V
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, ꢀ.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.125
1.250
1.250
1.ꢀ75
1.ꢀ75
V
V
OS
R
Termination Enabled, OV = 1.8V
100
Ω
TERM
DD
21721012fa
5
LTC2172-12/
LTC2171-12/LTC2170-12
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2172-12
LTC2171-12
LTC2170-12
TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
1.7
TYP
1.8
MAX
1.9
MIN
1.7
TYP
1.8
1.8
94
MAX
1.9
MIN
1.7
l
l
l
V
DD
Analog Supply Voltage (Note 10)
1.8
1.8
74
1.9
1.9
8ꢀ
V
V
OV
DD
Output Supply Voltage (Note 10)
1.7
1.8
1.9
1.7
1.9
1.7
I
I
Analog Supply Current Sine Wave Input
154
177
111
mA
VDD
OVDD
Digital Supply Current 1-Lane Mode, 1.75mA Mode
1-Lane Mode, ꢀ.5mA Mode
16
ꢀ0
25
47
16
29
24
46
15
28
24
45
mA
mA
mA
mA
l
l
2-Lane Mode, 1.75mA Mode
2-Lane Mode, ꢀ.5mA Mode
28
50
27
50
26
49
P
Power Dissipation
1-Lane Mode, 1.75mA Mode
1-Lane Mode, ꢀ.5mA Mode
2-Lane Mode, 1.75mA Mode
2-Lane Mode, ꢀ.5mA Mode
ꢀ06
ꢀꢀ1
ꢀ22
ꢀ62
198
221
212
252
160
184
176
214
mW
mW
mW
mW
DISS
l
l
ꢀ69
409
248
290
196
2ꢀ8
P
P
P
Sleep Mode Power
Nap Mode Power
1
1
1
mW
mW
mW
SLEEP
75
20
75
20
75
20
NAP
Power Increase with Differential Encode Mode Enabled
(No Increase for Sleep Mode)
DIFFCLK
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2172-12
TYP
LTC2171-12
TYP
LTC2170-12
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
TYP MAX UNITS
l
f
t
Sampling Frequency
(Notes 10, 11)
5
65
5
40
5
25
MHz
S
l
l
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.ꢀ
2
7.69
7.69
100 11.88 12.5
100 12.5
100
100
19
2
20
20
100
100
ns
ns
ENCL
2
l
l
t
t
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
7.ꢀ
2
7.69
7.69
100 11.88 12.5
100
100
19
2
20
20
100
100
ns
ns
ENCH
AP
100
2
12.5
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
21721012fa
6
LTC2172-12/
LTC2171-12/LTC2170-12
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
Digital Data Outputs (R
CONDITIONS
= 100Ω Differential, C = 2pF to GND on Each Output)
MIN
TYP
MAX
UNITS
TERM
L
t
Serial Data Bit Period
2-Lanes, 16-Bit Serialization
2-Lanes, 14-Bit Serialization
2-Lanes, 12-Bit Serialization
1-Lane, 16-Bit Serialization
1-Lane, 14-Bit Serialization
1-Lane, 12-Bit Serialization
1 / (8 • f )
s
s
s
s
s
s
SER
S
1 / (7 • f )
S
1 / (6 • f )
S
1 / (16 • f )
S
1 / (14 • f )
S
1 / (12 • f )
S
l
l
l
t
t
t
t
t
FR to DCO Delay
(Note 8)
0.ꢀ5 • t
0.ꢀ5 • t
0.5 • t
0.65 • t
0.65 • t
s
s
FRAME
DATA
PD
SER
SER
SER
SER
SER
DATA to DCO Delay
Propagation Delay
Output Rise Time
Output Fall Time
(Note 8)
0.5 • t
SER
(Note 8)
0.7n + 2 • t
1.1n + 2 • t
1.5n + 2 • t
SER
s
SER
SER
Data, DCO, FR, 20% to 80%
Data, DCO, FR, 20% to 80%
0.17
0.17
60
ns
ns
R
F
DCO Cycle-to-Cycle Jitter
Pipeline Latency
t
= 1ns
ps
P-P
SER
6
Cycles
SPI Port Timing (Note 8)
l
l
t
SCK Period
Write Mode
Readback Mode, C
40
250
ns
ns
SCK
= 20pF, R
= 2k
SDO
PULLUP
l
l
l
l
l
t
t
t
t
t
CS to SCK Set-Up Time
SCK to CS Set-Up Time
SDI Set-Up Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO Valid Readback Mode
125
C
= 20pF, R
= 2k
SDO
PULLUP
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 and 1111 1111 1111 in
2’s complement output mode.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 8: Guaranteed by design, not subject to test.
Note 3: When these pin voltages are taken below GND or above V , they
DD
will be clamped by internal diodes. This product can handle input currents
Note 9: V = OV = 1.8V, f
(LTC2171), or 25MHz (LTC2170), 2-lane output mode, ENC = single-
ended 1.8V square wave, ENC = 0V, input range = 2V with differential
= 65MHz (LTC2172), 40MHz
DD
DD
SAMPLE
+
of greater than 100mA below GND or above V without latchup.
DD
–
Note 4: When these pin voltages are taken below GND they will be
P-P
drive, unless otherwise noted. The supply current and power dissipation
specifications are totals for the entire chip, not per channel.
Note 10: Recommended operating conditions.
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
DD
Note 5: V = OV = 1.8V, f
= 65MHz (LTC2172),
DD
DD
SAMPLE
Note 11: The maximum sampling frequency depends on the speed grade
of the part and also which serialization mode is used. The maximum serial
40MHz (LTC2171), or 25MHz (LTC2170), 2-lane output mode, differential
+
–
ENC /ENC = 2V sine wave, input range = 2V with differential drive,
P-P
P-P
data rate is 1000Mbps, so t
must be greater than or equal to 1ns.
SER
unless otherwise noted.
Note 12: Near-channel crosstalk refers to Ch. 1 to Ch.2, and Ch.ꢀ to Ch.4.
Far-channel crosstalk refers to Ch.1 to Ch.ꢀ, Ch.1 to Ch.4, Ch.2 to Ch.ꢀ, and
Ch.2 to Ch.4.
21721012fa
7
LTC2172-12/
LTC2171-12/LTC2170-12
TIMING DIAGRAMS
2-Lane Output Mode, 16-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
SER
DATA
t
FRAME
–
FR
+
FR
t
PD
t
SER
–
OUT#A
Dꢀ
D2
D1
D0
D *
0
0
D11 D9
D7
D6
D5
D4
Dꢀ
D2
D1
D0
D *
0
D11 D9
D10 D8
D7
X
X
+
OUT#A
–
OUT#B
D *
Y
D10 D8
D *
Y
0
D6
+
OUT#B
217212 TD01
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
*D AND D ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
X
Y
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D AND D ARE SET TO
X
Y
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
2-Lane Output Mode, 14-Bit Serialization
t
AP
ANALOG
INPUT
N + 2
N + 1
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
SER
DATA
t
FRAME
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D5
D4
Dꢀ
D2
D1 D * D11 D9
D7
D6
D5
D4
Dꢀ
D2
D1
D0
D * D11 D9
D7
D6
D5
D4
Dꢀ
D2
D1 D * D11 D9
D7
D6
X
X
X
+
OUT#A
–
OUT#B
D0 D * D10 D8
Y
D * D10 D8
Y
D0 D * D10 D8
Y
+
OUT#B
217212 TD02
SAMPLE N-6
SAMPLE N-5
SAMPLE N-4
–
SAMPLE N-ꢀ
+
–
+
NOTE THAT IN THIS MODE, FR /FR HAS TWO TIMES THE PERIOD OF ENC /ENC
*D AND D ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
X
Y
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D AND D ARE SET TO
X
Y
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
21721012fa
8
LTC2172-12/
LTC2171-12/LTC2170-12
TIMING DIAGRAMS
2-Lane Output Mode, 12-Bit Serialization
t
N + 1
AP
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
SER
DATA
t
FRAME
+
FR
–
FR
t
PD
t
SER
–
OUT#A
D7
D5
D4
Dꢀ
D2
D1 D11 D9
D7
D6
D5
Dꢀ
D2
D1 D11 D9
D7
D6
+
–
OUT#A
OUT#B
D6
D0 D10 D8
SAMPLE N-5
D4
D0 D10 D8
SAMPLE N-4
+
OUT#B
217212 TD0ꢀ
SAMPLE N-6
1-Lane Output Mode, 16-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D * D *
0
0
D11 D10 D9
SAMPLE N-5
D8
D7
D6
D5
D4
Dꢀ
D2
D1
D0
D * D *
0
0
D11 D10 D9
SAMPLE N-4
D8
X
Y
X
Y
+
OUT#A
217212 TD04
SAMPLE N-6
–
+
OUT#B , OUT#B ARE DISABLED
*D AND D ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
X
Y
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D AND D ARE SET TO
X
Y
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
21721012fa
9
LTC2172-12/
LTC2171-12/LTC2170-12
TIMING DIAGRAMS
1-Lane Output Mode, 14-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
D1
D0
D * D * D11 D10 D9
D8
D7
D6
D5
D4
Dꢀ
D2
D1
D0 D * D * D11 D10 D9
D8
X
Y
X
Y
+
OUT#A
217212 TD05
SAMPLE N-6
–
SAMPLE N-5
SAMPLE N-4
+
OUT#B , OUT#B ARE DISABLED
*D AND D ARE EXTRA NON-DATA BITS FOR COMPLETE SOFTWARE COMPATIBILITY WITH THE 14-BIT
X
Y
VERSIONS OF THESE A/Ds. DURING NORMAL NON-OVERRANGED OPERATION D AND D ARE SET TO
X
Y
LOGIC 0. SEE THE DATA FORMAT SECTION FOR MORE DETAILS.
1-Lane Output Mode, 12-Bit Serialization
t
AP
N + 1
ANALOG
INPUT
N
t
t
ENCL
ENCH
–
ENC
+
ENC
t
SER
–
DCO
+
DCO
t
t
t
SER
FRAME
DATA
–
FR
+
FR
t
PD
t
SER
–
OUT#A
Dꢀ
D2
D1
D0 D11 D10 D9
SAMPLE N-5
D8
D7
D6
D5
D4
Dꢀ
D2
D1
D0 D11 D10 D9
+
OUT#A
217212 TD06
SAMPLE N-6
–
SAMPLE N-4
+
OUT#B , OUT#B ARE DISABLED
21721012fa
10
LTC2172-12/
LTC2171-12/LTC2170-12
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
t
t
t
DH
t
t
H
S
DS
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
Aꢀ
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
Dꢀ
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
Aꢀ
A2
A1
A0
D7
D6
D5
D4
Dꢀ
D2
D1
D0
R/W
SDO
217212 TD07
HIGH IMPEDANCE
21721012fa
11
LTC2172-12/
LTC2171-12/LTC2170-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2172-12: Integral
Nonlinearity (INL)
LTC2172-12: Differential
Nonlinearity (DNL)
LTC2172-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 65Msps
1.0
0.8
1.0
0.8
0.6
0
–10
–20
–30
–40
–50
–60
–70
0.6
0.4
0.4
0.2
0
0.2
0
–0.2
–0.4
–0.6
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–90
–100
–110
–120
–0.8
–1.0
0
2048
3072
4096
0
2048
3072
4096
1024
1024
0
10
20
30
OUTPUT CODE
OUTPUT CODE
FREQUENCY (MHz)
217212 G01
217212 G02
217212 G03
LTC2172-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 65Msps
LTC2172-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 65Msps
LTC2172-12: 8k Point FFT, fIN = 140MHz
–1dBFS, 65Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
10
FREQUENCY (MHz)
30
0
20
10
FREQUENCY (MHz)
30
0
10
20
30
FREQUENCY (MHz)
217212 G05
217212 G06
217212 G04
LTC2172-12: 8k Point 2-Tone FFT,
LTC2172-12: SNR vs Input
Frequency, –1dBFS, 2V Range,
65Msps
LTC2172-12: Shorted Input
Histogram
f
IN = 68MHz, 69MHz, –1dBFS,
65Msps
18000
0
–10
–20
–30
–40
–50
–60
–70
72
16000
14000
12000
10000
8000
71
70
69
68
67
66
6000
4000
2000
0
–80
–90
–100
–110
–120
2049
2050
2051
OUTPUT CODE
2052
2053
0
20
10
FREQUENCY (MHz)
30
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
217212 G08
217212 G07
217212 G09
21721012fa
12
LTC2172-12/
LTC2171-12/LTC2170-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2172-12: SFDR vs Input
Frequency, –1dBFS, 2V Range,
65Msps
LTC2172-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 65Msps
LTC2172-12: SNR vs Input Level,
fIN = 70MHz, 2V Range, 65Msps
80
70
60
50
40
30
20
10
0
95
90
85
80
75
70
65
110
100
90
dBFS
dBc
dBFS
80
70
dBc
60
50
40
30
20
10
0
–60
–40
–30
–20
–10
0
–50
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
INPUT LEVEL(dBFS)
217212 G50
217212 G10
217212 G12
IOVDD vs Sample Rate, 5MHz Sine
Wave Input, –1dBFS
LTC2172-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2172-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
72
71
70
69
68
67
66
160
155
50
40
30
2-LANE, 3.5mA
150
145
140
135
130
125
120
115
110
1-LANE, 3.5mA
2-LANE, 1.75mA
20
10
0
1-LANE, 1.75mA
0.6 0.7 0.8 0.9
1
1.1 1.2 1.ꢀ
0
10
20
30
40
50
60
0
10
20
30
40
50
60
SENSE PIN (V)
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
217212 G15
217212 G53
217212 G51
LTC2171-12: Integral Nonlinearity
(INL)
LTC2171-12: Differential
Nonlinearity (DNL)
LTC2171-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 40Msps
1.0
0.8
0.6
0.4
0.2
0
0
–10
–20
–ꢀ0
–40
–50
–60
–70
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.2
–0.4
–0.6
–0.8
–1.0
–80
–90
–100
–110
–120
–0.4
–0.6
–0.8
–1.0
0
20
0
2048
ꢀ072
4096
10
0
2048
3072
4096
1024
1024
FREQUENCY (MHz)
OUTPUT CODE
OUTPUT CODE
217212 G2ꢀ
217212 G22
217212 G21
21721012fa
13
LTC2172-12/
LTC2171-12/LTC2170-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2171-12: 8k Point FFT, fIN = 29MHz
–1dBFS, 40Msps
LTC2171-12: 8k Point FFT, fIN = 69MHz
–1dBFS, 40Msps
LTC2171-12: 8k Point FFT, fIN = 139MHz
–1dBFS, 40Msps
0
–10
–20
–ꢀ0
–40
–50
–60
–70
0
–10
–20
–ꢀ0
–40
–50
–60
–70
0
–10
–20
–ꢀ0
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
0
20
10
0
20
10
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
217212 G24
217212 G26
217212 G25
LTC2171-12: SNR vs Input
Frequency, –1dBFS, 2V Range,
40Msps
LTC2171-12: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
40Msps
LTC2171-12: Shorted Input
Histogram
0
–10
–20
–ꢀ0
–40
–50
–60
–70
18000
16000
14000
12000
72
71
70
69
68
67
66
10000
8000
6000
4000
2000
0
–80
–90
–100
–110
–120
0
20
10
2049
2050
2051
2052
2053
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
FREQUENCY (MHz)
OUTPUT CODE
217212 G27
217212 G28
217212 G29
LTC2171-12: SFDR vs Input
Frequency, –1dBFS, 2V Range,
40Msps
LTC2171-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 40Msps
LTC2171-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
110
100
90
95
90
85
80
75
70
65
100
95
90
85
80
75
70
dBFS
80
70
60
dBc
50
40
30
20
10
0
–80
–70
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
100 150 200 250 ꢀ00 ꢀ50
INPUT FREQUENCY (MHz)
50
0
10
20
30
40
SAMPLE RATE (Msps)
217212 G32
217212 G24a
217212 G54
21721012fa
14
LTC2172-12/
LTC2171-12/LTC2170-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2171-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2170-12: Integral Nonlinearity
(INL)
LTC2170-12: Differential
Nonlinearity (DNL)
72
1.0
0.8
0.6
0.4
0.2
0
1.0
0.8
0.6
71
70
69
68
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
67
66
0
2048
3072
4096
0
2048
3072
4096
1024
0.6 0.7 0.8 0.9
1
1.1 1.2 1.ꢀ
1024
OUTPUT CODE
OUTPUT CODE
SENSE PIN (V)
217212 G42
217212 G41
217212 Gꢀ5
LTC2170-12: 8k Point FFT, fIN = 30MHz
–1dBFS, 25Msps
LTC2170-12: 8k Point FFT, fIN = 70MHz
–1dBFS, 25Msps
LTC2170-12: 8k Point FFT, fIN = 5MHz
–1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10
0
10
0
10
5
5
5
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
217212 G43
217212 G44
217212 G45
LTC2170-12: 8k Point 2-Tone FFT,
fIN = 68MHz, 69MHz, –1dBFS,
25Msps
LTC2170-12: Shorted Input
Histogram
LTC2170-12: 8k Point FFT,
fIN = 140MHz –1dBFS, 25Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
18000
16000
14000
12000
10000
8000
–80
–90
–100
–110
–120
–80
–90
–100
–110
–120
6000
4000
2000
0
0
5
10
0
5
10
2049
2050
2051
2052
2053
FREQUENCY (MHz)
FREQUENCY (MHz)
OUTPUT CODE
217212 G47
217212 G46
217212 G48
21721012fa
15
LTC2172-12/
LTC2171-12/LTC2170-12
TYPICAL PERFORMANCE CHARACTERISTICS
LTC2170-12: SFDR vs Input
Frequency, –1dBFS, 2V Range,
25Msps
LTC2170-12: SNR vs Input
Frequency, –1dBFS, 2V Range,
25Msps
LTC2170-12: SFDR vs Input Level,
fIN = 70MHz, 2V Range, 25Msps
110
100
90
95
90
85
80
75
70
65
72
71
70
69
68
67
dBFS
80
70
dBc
60
50
40
30
20
10
0
66
–80
–60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
–70
0
100 150 200 250 ꢀ00 ꢀ50
INPUT FREQUENCY (MHz)
50
0
100 150 200 250 300 350
INPUT FREQUENCY (MHz)
50
217212 G52
217212 Gꢀ7
217212 G49
LTC2170-12: IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
LTC2170-12: SNR vs SENSE,
fIN = 5MHz, –1dBFS
DCO Cycle-Cycle Jitter vs Serial
Data Rate
80
75
70
65
350
300
250
200
150
72
71
70
69
68
67
66
100
50
0
60
0
5
10
15
20
25
0
200
400
600
800
1000
0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.ꢀ
SENSE PIN (V)
SAMPLE RATE (Msps)
SERIAL DATA RATE (Mbps)
217212 G55
217212 G52
217212 G55a
21721012fa
16
LTC2172-12/
LTC2171-12/LTC2170-12
PIN FUNCTIONS
+
–
A
(Pin 1): Channel 1 Positive Differential Analog
(Pin 2): Channel 1 Negative Differential Analog
(Pin 3): Common Mode Bias Output, Nominally
ENC (Pin 18): Encode Complement Input. Conversion
IN1
Input.
starts on the falling edge.
–
A
CS(Pin19):Inserialprogrammingmode(PAR/SER=0V),
CS is the serial interface chip select input. When CS is low,
SCK is enabled for shifting data on SDI into the mode
controlregisters.Inparallelprogrammingmode(PAR/SER
IN1
Input.
V
CM12
Equal to V /2. V should be used to bias the common
DD
CM
= V ), CS selects two-lane or one-lane output mode. CS
DD
mode of the analog inputs of channels 1 and 2. Bypass
can be driven with 1.8V to ꢀ.ꢀV logic.
to ground with a 0.1μF ceramic capacitor.
+
SCK (Pin 20): In serial programming mode (PAR/SER
= 0V), SCK is the serial interface clock input. In parallel
A
(Pin 4): Channel 2 Positive Differential Analog
(Pin 5): Channel 2 Negative Differential Analog
IN2
Input.
programmingmode(PAR/SER=V ),SCKselectsꢀ.5mA
DD
–
A
IN2
or 1.75mA LVDS output currents. SCK can be driven with
1.8V to ꢀ.ꢀV logic.
Input.
REFH (Pins 6, 7): ADC High Reference. Bypass to Pin 8
and Pin 9 with a 2.2μF ceramic capacitor, and to ground
with a 0.1μF ceramic capacitor.
SDI (Pin 21): In serial programming mode (PAR/SER =
0V), SDI is the serial interface data input. Data on SDI
is clocked into the mode control registers on the rising
edge of SCK. In parallel programming mode (PAR/SER =
REFL (Pins 8, 9): ADC Low Reference. Bypass to Pin 6
and Pin 7 with a 2.2μF ceramic capacitor, and to ground
with a 0.1μF ceramic capacitor.
V ), SDI can be used to power down the part. SDI can
DD
be driven with 1.8V to ꢀ.ꢀV logic.
+
A
(Pin 10): Channel ꢀ Positive Differential Analog
(Pin 11): Channel ꢀ Negative Differential Analog
(Pin 12): Common Mode Bias Output, Nominally
GND (Pins 22, 45, 49, Exposed Pad Pin 53): ADC Power
Ground. The exposed pad must be soldered to the PCB
ground.
IN3
Input.
–
A
IN3
Input.
OGND (Pin 33): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
V
CM34
Equal to V /2. V should be used to bias the common
DD
CM
mode of the analog inputs of channels ꢀ and 4. Bypass
OV (Pin 34): Output Driver Supply, 1.7V to 1.9V. Bypass
DD
to ground with a 0.1μF ceramic capacitor.
to ground with a 0.1μF ceramic capacitor.
+
A
(Pin 13): Channel 4 Positive Differential Analog
(Pin 14): Channel 4 Negative Differential Analog
IN4
SDO (Pin 46): In serial programming mode (PAR/SER
= 0V), SDO is the optional serial interface data output.
Data on SDO is read back from the mode control reg-
isters and can be latched on the falling edge of SCK.
SDO is an open-drain N-channel MOSFET output that
requires an external 2k pull-up resistor of 1.8V to ꢀ.ꢀV.
If readback from the mode control registers is not
needed, the pull-up resistor is not necessary and SDO
can be left unconnected. In parallel programming mode
Input.
–
A
IN4
Input.
V
(Pins 15, 16, 51, 52): Analog Power Supply, 1.7V
DD
to 1.9V. Bypass to ground with 0.1μF ceramic capacitors.
Adjacent pins can share a bypass capacitor.
+
ENC (Pin 17): Encode Input. Conversion starts on the
rising edge.
(PAR/SER = V ), SDO is an input that enables internal
DD
100ꢁ termination resistors on the digital outputs. When
used as an input, SDO can be driven with 1.8V to ꢀ.ꢀV
logic through a 1k series resistor.
21721012fa
17
LTC2172-12/
LTC2171-12/LTC2170-12
PIN FUNCTIONS
PAR/SER (Pin 47): Programming Mode Selection Pin.
Connect to ground to enable serial programming mode.
CS, SCK, SDI and SDO become a serial interface that con-
LVDS OUTPUTS
The following pins are differential LVDS outputs. The
output current level is programmable. There is an op-
tional internal 100ꢀ termination resistor between the
pins of each LVDS output pair.
trols the A/D operating modes. Connect to V to enable
DD
parallel programming mode where CS, SCK, SDI and SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directly to ground or the V of the part and not be driven
by a logic signal.
–
+
–
+
OUT4B /OUT4B , OUT4A /OUT4A (Pins 23/24,
Pins 25/ 26): Serial Data Outputs for Channel 4. In 1-lane
DD
–
+
output mode, only OUT4A /OUT4A are used.
–
+
–
+
OUT3B /OUT3B , OUT3A /OUT3A (Pins 27/28,
V
(Pin48):ReferenceVoltageOutput.Bypasstoground
REF
Pins 29/30): Serial Data Outputs for Channel ꢀ. In
with a 1μF ceramic capacitor, nominally 1.25V.
–
+
1-lane output mode, only OUTꢀA /OUTꢀA are used.
SENSE (Pin 50): Reference Programming Pin. Connect-
–
+
FR /FR (Pin 31/Pin 32): Frame Start Output.
ing SENSE to V selects the internal reference and a
DD
–
+
DCO /DCO (Pin 35/Pin 36): Data Clock Output.
1V input range. Connecting SENSE to ground selects
the internal reference and a 0.5V input range. An external
reference between 0.625V and 1.ꢀV applied to SENSE
–
+
–
+
OUT2B /OUT2B , OUT2A /OUT2A (Pins 37/38,
Pins 39/40): Serial Data Outputs for Channel 2. In
–
+
selects an input range of 0.8 • V
.
1-lane output mode, only OUT2A /OUT2A are used.
SENSE
–
+
–
+
OUT1B /OUT1B , OUT1A /OUT1A (Pins 41/42,
Pins 43/44): Serial Data Outputs for Channel 1. In
1-lane output mode, only OUT1A /OUT1A are used.
–
+
21721012fa
18
LTC2172-12/
LTC2171-12/LTC2170-12
FUNCTIONAL BLOCK DIAGRAM
+
–
1.8V
ENC ENC
1.8V
OV
V
DD
DD
OUT1A
OUT1B
CHANNEL 1
ANALOG
INPUT
12-BIT
ADC CORE
SAMPLE-
AND-HOLD
PLL
OUT2A
OUT2B
CHANNEL 2
ANALOG
INPUT
12-BIT
ADC CORE
SAMPLE-
AND-HOLD
DATA
SERIALIZER
OUTꢀA
OUTꢀB
CHANNEL ꢀ
ANALOG
INPUT
SAMPLE-
AND-HOLD
12-BIT
ADC CORE
OUT4A
OUT4B
CHANNEL 4
ANALOG
INPUT
SAMPLE-
AND-HOLD
12-BIT
ADC CORE
DATA
CLOCK OUT
V
REF
1.25V
REFERENCE
FRAME
1μF
RANGE
SELECT
OGND
REFH
REFL
REF
BUF
SENSE
V
/2
DD
DIFF
REF
AMP
MODE
CONTROL
REGISTERS
217212 F01
GND
REFH
REFL
VCM12
0.1μF
VCMꢀ4
0.1μF
0.1μF
2.2μF
0.1μF
PAR/SER CS SCK SDI SDO
0.1μF
Figure 1. Functional Block Diagram
21721012fa
19
LTC2172-12/
LTC2171-12/LTC2170-12
APPLICATIONS INFORMATION
CONVERTER OPERATION
or V
output pins, which are nominally V /2. For the
CMꢀ4 DD
2V input range, the inputs should swing from V – 0.5V
CM
The LTC2172-12/LTC2171-12/LTC2170-12 are low power,
4-channel, 12-bit, 65Msps/40Msps/25Msps A/D convert-
ers that are powered by a single 1.8V supply. The analog
inputs should be driven differentially. The encode input
can be driven differentially for optimal jitter performance,
or single-ended for lower power consumption. The digital
outputs are serial LVDS to minimize the number of data
lines. Each channel outputs two bits at a time (2-lane
mode) or one bit at a time (1-lane mode). Many additional
features can be chosen by programming the mode control
registers through a serial SPI port.
to V + 0.5V. There should be a 180° phase difference
between the inputs.
CM
The four channels are simultaneously sampled by a
shared encode circuit (Figure 2).
INPUT DRIVE CIRCUITS
Input Filtering
If possible, there should be an RC lowpass filter right
at the analog inputs. This lowpass filter isolates the
drive circuitry from the A/D sample-and-hold switch-
ing and limits wideband noise from the drive circuitry.
Figure ꢀ shows an example of an input RC filter. The
RC component values should be chosen based on the
application’s input frequency.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits (Figure 2). The inputs should be driven differen-
tially around a common mode voltage set by the V
CM12
50Ω
V
LTC2172-12
CM
V
DD
C
C
0.1μF
SAMPLE
ꢀ.5pF
R
ON
0.1μF
T1
1:1
10Ω
10ꢁ
25Ω
+
25Ω
+
–
A
IN
A
A
ANALOG
INPUT
IN
C
PARASITIC
LTC2172-12
0.1μF
25Ω
25Ω
1.8pF
V
DD
12pF
SAMPLE
ꢀ.5pF
R
25Ω
ON
–
25Ω
A
IN
IN
C
PARASITIC
T1: MA/COM MABAES0060
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
1.8pF
217212 F0ꢀ
V
DD
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
1.2V
10k
+
–
ENC
ENC
10k
1.2V
217212 F02
Figure 2. Equivalent Input Circuit. Only One of
the Four Analog Channels Is Shown.
21721012fa
20
LTC2172-12/
LTC2171-12/LTC2170-12
APPLICATIONS INFORMATION
Transformer Coupled Circuits
Amplifier Circuits
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC-coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distor-
tion.
Figure ꢀ shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
tap is biased with V , setting the A/D input at its opti-
CM
mal DC level. At higher input frequencies a transmission
line balun transformer (Figures 4 to 6) has better balance,
resulting in lower A/D distortion.
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
block is single-ended, then a transformer circuit (Figures
4 to 6) should convert the signal to differential before
driving the A/D.
50Ω
50Ω
V
V
CM
CM
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
0.1μF
+
+
A
A
IN
ANALOG
INPUT
IN
ANALOG
INPUT
T2
T2
LTC2172-12
LTC2172-12
T1
T1
0.1μF
0.1μF
25Ω
25Ω
25Ω
25Ω
4.7pF
1.8pF
–
–
A
A
IN
IN
217212 F04
217212 F05
T1: MA/COM MABA-007159-000000
T2: MA/COM MABAES0060
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1LB
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 4. Recommended Front-End Circuit for Input
Frequencies from 70MHz to 170MHz
Figure 5. Recommended Front-End Circuit for Input
Frequencies from 170MHz to 300MHz
V
CM
50Ω
V
CM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1μF
200Ω 200Ω
25Ω
0.1μF
A
0.1μF
0.1μF
+
–
0.1μF
0.1μF
A
IN
2.7nH
0.1μF
+
–
IN
ANALOG
INPUT
LTC2172-12
ANALOG
INPUT
LTC2172-12
+
+
25Ω
25Ω
T1
12pF
A
–
–
2.7nH
A
25Ω
IN
IN
217212 F06
217212 F07
T1: MA/COM ETC1-1-1ꢀ
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 7. Front-End Circuit Using a High Speed
Differential Amplifier
Figure 6. Recommended Front-End Circuit for Input
Frequencies Above 300MHz
21721012fa
21
LTC2172-12/
LTC2171-12/LTC2170-12
APPLICATIONS INFORMATION
Reference
Encode Input
TheLTC2172-12/LTC2171-12/LTC2170-12hasaninternal
1.25V voltage reference. For a 2V input range using the
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
internal reference, connect SENSE to V . For a 1V input
DD
range using the internal reference, connect SENSE to
ground. For a 2V input range with an external reference,
apply a 1.25V reference voltage to SENSE (Figure 9).
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.ꢀ0V. The input range
V
REF
will then be 1.6 • V
.
SENSE
1μF
LTC2172-12
The reference is shared by all four ADC channels, so it is
not possible to independently adjust the input range of
individual channels.
1.25V
EXTERNAL
REFERENCE
SENSE
1μF
217212 F09
The V , REFH and REFL pins should be bypassed, as
REF
shown in Figure 8. The 0.1μF capacitor between REFH and
REFL should be as close to the pins as possible (not on
the backside of the circuit board).
Figure 9. Using an External 1.25V Reference
LTC2172-12
LTC2172-12
V
DD
5Ω
V
REF
1.25V BANDGAP
REFERENCE
DIFFERENTIAL
COMPARATOR
1.25V
V
DD
1μF
0.625V
15k
ꢀ0k
RANGE
DETECT
AND
+
–
ENC
ENC
CONTROL
TIE TO V FOR 2V RANGE;
DD
SENSE
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • V
FOR
SENSE
BUFFER
0.625V < V
< 1.ꢀ00V
SENSE
INTERNAL ADC
HIGH REFERENCE
217212 F10
0.1μF
REFH
0.1μF
Figure 10. Equivalent Encode Input Circuit
for Differential Encode Mode
2.2μF
0.8x
DIFF AMP
0.1μF
REFL
LTC2172-12
+
INTERNAL ADC
LOW REFERENCE
1.8V TO ꢀ.ꢀV
0V
ENC
ENC
–
217212 F08
ꢀ0k
CMOS LOGIC
BUFFER
Figure 8. Reference Circuit
217212 F11
Figure 11. Equivalent Encode Input Circuit
for Single-Ended Encode Mode
21721012fa
22
LTC2172-12/
LTC2171-12/LTC2170-12
APPLICATIONS INFORMATION
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12 and 1ꢀ).
The encode inputs are internally biased to 1.2V through
10k equivalent resistance. The encode inputs can be taken
In the serial programming mode it is possible to disable
the duty cycle stabilizer, but this is not recommended. In
the parallel programming mode the duty cycle stabilizer
is always enabled.
above V (up to ꢀ.6V), and the common mode range
DD
is from 1.1V to 1.6V. In the differential encode mode,
DIGITAL OUTPUTS
–
ENC should stay at least 200mV above ground to avoid
The digital outputs of the LTC2172-12/LTC2171-12/
LTC2170-12 are serialized LVDS signals. Each channel
outputs two bits at a time (2-lane mode) or one bit at a
time (1-lane mode). The data can be serialized with 16-,
14-, or 12-bit serialization (see the Timing Diagrams sec-
tion for details).
falsely triggering the single-ended encode mode. For
+
good jitter performance ENC should have fast rise and
fall times.
The single-ended encode mode should be used with
–
CMOS encode inputs. To select this mode, ENC is con-
+
nected to ground and ENC is driven with a square wave
+
The output data should be latched on the rising and
falling edges of the data clockout (DCO). A data frame
output (FR) can be used to determine when the data
from a new conversion result begins. In the 2-lane, 14-
bit serialization mode, the frequency of the FR output
is halved.
encode input. ENC can be taken above V (up to ꢀ.6V)
DD
so 1.8V to ꢀ.ꢀV CMOS logic levels can be used. The
+
+
ENC threshold is 0.9V. For good jitter performance
ENC should have fast rise and fall times.
Clock PLL and Duty Cycle Stabilizer
Theencodeclockismultipliedbyaninternalphase-locked
loop (PLL) to generate the serial digital output data. If the
encode signal changes frequency or is turned off, the PLL
requires 25μs to lock onto the input clock.
The maximum serial data rate for the data outputs is
1Gbps, so the maximum sample rate of the ADC will de-
pend on the serialization mode as well as the speed grade
of the ADC (see Table 1). The minimum sample rate for
all serialization modes is 5Msps.
A clock duty cycle stabilizer circuit allows the duty cycle
of the applied encode signal to vary from ꢀ0% to 70%.
0.1μF
+
ENC
0.1μF
0.1μF
+
T1
ENC
LTC2172-12
PECL OR
LTC2172-12
LVDS
50ꢁ
50ꢁ
CLOCK
100ꢁ
0.1μF
–
ENC
217212 F1ꢀ
–
0.1μF
ENC
Figure 13. PECL or LVDS Encode Drive
217212 F12
T1 = MA/COM ETC1-1-1ꢀ
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
Figure 12. Sinusoidal Encode Drive
21721012fa
23
LTC2172-12/
LTC2171-12/LTC2170-12
APPLICATIONS INFORMATION
Table 1. Maximum Sampling Frequency for All Serialization Modes. Note That These Limits Are for the LTC2172-12. The Sampling
Frequency for the Slower Speed Grades Cannot Exceed 40MHz (LTC2171-12) or 25MHz (LTC2170-12).
MAXIMUM SAMPLING
SERIALIZATION MODE
2-Lane
FREQUENCY, f (MHz)
DCO FREQUENCY
4 • f
FR FREQUENCY
SERIAL DATA RATE
S
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
16-Bit Serialization
14-Bit Serialization
12-Bit Serialization
65
65
f
8 • f
7 • f
6 • f
S
S
S
S
S
2-Lane
ꢀ.5 • f
0.5 • f
S
S
2-Lane
65
ꢀ • f
8 • f
7 • f
6 • f
f
f
f
f
S
S
S
S
S
1-Lane
62.5
65
16 • f
14 • f
12 • f
S
S
S
S
S
S
1-Lane
1-Lane
65
By default the outputs are standard LVDS levels: a ꢀ.5mA
output current and a 1.25V output common mode volt-
age. An external 100ꢁ differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
DATA FORMAT
Table 2 shows the relationship between the analog input
voltage and the digital data output bits. By default the
output data format is offset binary. The 2’s complement
format can be selected by serially programming mode
control register A1.
The outputs are powered by OV and OGND which are
DD
In addition to the 12 data bits (D11 - D0), two additional
bits (DX and DY) are sent out in the 14-bit and 16-bit
serialization modes. These extra bits are to ensure com-
plete software compatibility with the 14-bit versions of
these A/Ds. During normal operation when the analog
inputs are not overranged, DX and DY are always logic 0.
When the analog inputs are overranged positive, DX and
DYbecomelogic1.Whentheanaloginputsareoverranged
negative, DX and DY become logic 0. DX and DY can also
be controlled by the digital output test pattern. See the
Timing Diagrams section for more information.
isolated from the A/D core power and ground.
Programmable LVDS Output Current
Thedefaultoutputdrivercurrentisꢀ.5mA.Thiscurrentcan
be adjusted by control register A2 in serial programming
mode.Availablecurrentlevelsare1.75mA,2.1mA,2.5mA,
ꢀmA, ꢀ.5mA, 4mA and 4.5mA. In parallel programming
mode the SCK pin can select either ꢀ.5mA or 1.75mA.
Optional LVDS Driver Internal Termination
In most cases, using just an external 100ꢁ termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100ꢁ termination resistor can
beenabledbyseriallyprogrammingmodecontrolregister
A2. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing. In
parallel programming mode the SDO pin enables internal
termination. Internalterminationshouldonlybeusedwith
1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Table 2. Output Codes vs Input Voltage
+
–
A
– A
D11-D0
D11-D0
IN
IN
(2V RANGE)
>+1.000000V
+0.999512V
+0.999024V
+0.000488V
0.000000V
(OFFSET BINARY) (2’s COMPLEMENT)
D , D
X
Y
1111 1111 1111
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
0111 1111 1110
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0001
1000 0000 0000
1000 0000 0000
11
00
00
00
00
00
00
00
00
00
–0.000488V
–0.000976V
–0.999512V
–1.000000V
≤–1.000000V
21721012fa
24
LTC2172-12/
LTC2171-12/LTC2170-12
APPLICATIONS INFORMATION
Digital Output Randomizer
In nap mode any combination of A/D channels can be
powereddownwhiletheinternalreferencecircuitsandthe
PLL stay active, allowing a faster wake-up than from sleep
mode. Recovering from nap mode requires at least 100
clock cycles. If the application demands very accurate DC
settling, then an additional 50μs should be allowed so the
on-chip references can settle from the slight temperature
shift caused by the change in supply current as the A/D
leavesnapmode.Napmodeisenabledbythemodecontrol
register A1 in the serial programming mode.
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones in
the ADC output spectrum. These unwanted tones can be
randomized by randomizing the digital output before it is
transmitted off chip, which reduces the unwanted tone
amplitude.
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The FR and DCO outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A1.
DEVICE PROGRAMMING MODES
The operating modes of the LTC2172-12/LTC2171-12/
LTC2170-12 can be programmed by either a parallel
interface or a simple serial interface. The serial interface
has more flexibility and can program all available modes.
Theparallelinterfaceismorelimitedandcanonlyprogram
some of the more commonly used modes.
Digital Output Test Pattern
To allow in-circuit testing of the digital interface to the
A/D, there is a test mode that forces the A/D data outputs
Parallel Programming Mode
(D11-D0, D , D ) of all channels to known values. The
X
Y
To use the parallel programming mode, PAR/SER should
digitaloutputtestpatternsareenabledbyseriallyprogram-
ming mode control registers Aꢀ and A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement and randomizer.
be tied to V . The CS, SCK, SDI and SDO pins are binary
DD
logic inputs that set certain operating modes. These pins
can be tied to V or ground, or driven by 1.8V, 2.5V or
DD
ꢀ.ꢀV CMOS logic. When used as an input, SDO should
be driven through a 1k series resistor. Table ꢀ shows the
modes set by CS, SCK, SDI and SDO.
Output Disable
The digital outputs may be disabled by serially program-
ming mode control register A2. The current drive for all
digitaloutputs, includingDCOandFR, aredisabledtosave
powerorenablein-circuittesting.Whendisabled,thecom-
mon mode of each output pair becomes high impedance,
but the differential impedance may remain low.
Table 3. Parallel Programming Mode Control Bits (PAR/SER = VDD
)
PIN
DESCRIPTION
CS
2-Lane/1-Lane Selection Bit
0 = 2-Lane, 16-Bit Serialization Output Mode
1 = 1-Lane, 14-Bit Serialization Output Mode
LVDS Current Selection Bit
0 = ꢀ.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Power Down Control Bit
SCK
SDI
Sleep and Nap Modes
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire chip is powered down,
resulting in 1mW power consumption. Sleep mode is
enabled by mode control register A1 (serial program-
ming mode), or by SDI (parallel programming mode).
The amount of time required to recover from sleep mode
0 = Normal Operation
1 = Sleep Mode
SDO
Internal 100Ω Termination Selection Bit
0 = Internal Termination Disabled
1 = Internal Termination Enabled
depends on the size of the bypass capacitors on V
,
REF
REFH and REFL. For the suggested values in Figure 8, the
A/D will stabilize after 2ms.
21721012fa
25
LTC2172-12/
LTC2171-12/LTC2170-12
APPLICATIONS INFORMATION
Serial Programming Mode
A0) will be read back on the SDO pin (see the Timing Dia-
grams section). During a readback command the register
is not updated and data on SDI is ignored.
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D mode control
registers. Data is written to a register with a 16-bit serial
word. Data can also be read back from a register to verify
its contents.
The SDO pin is an open-drain output that pulls to ground
witha200ꢁimpedance.Ifregisterdataisreadbackthrough
SDO, an external 2k pull-up resistor is required. If serial
data is only written and readback is not needed, then SDO
can be left floating and no pull-up resistor is needed. Table
4 shows a map of the mode control registers.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset is
complete, bit D7 is automatically set back to zero.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be written
to the register set by the address bits (A6:A0). If the R/W
bit is high, data in the register set by the address bits (A6:
Table 4. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
D5
D4
X
Dꢀ
X
D2
X
D1
X
D0
X
RESET
X
Bit 7
RESET
0 = Not Used
Software Reset Bit
1 = Software Reset. All Mode Control Registers Are Reset to 00h. The ADC is momentarily placed in SLEEP mode. This Bit Is
Automatically Set Back to Zero After the Reset Is Complete
Bits 6-0
Unused, Don’t Care Bits.
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
D6
D5
D4
Dꢀ
D2
D1
D0
DCSOFF
RAND
TWOSCOMP
SLEEP
NAP_4
NAP_ꢀ
NAP_2
NAP_1
Bit 7
Bit 6
Bit 5
DCSOFF
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer On
1 = Clock Duty Cycle Stabilizer Off. This is Not Recommended.
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
Two’s Complement Mode Control Bit
Bits 4-0
SLEEP:NAP_4:NAP_1
00000 = Normal Operation
Sleep/Nap Mode Control Bits
0XXX1 = Channel 1 in Nap Mode
0XX1X = Channel 2 in Nap Mode
0X1XX = Channel ꢀ in Nap Mode
01XXX = Channel 4 in Nap Mode
1XXXX = Sleep Mode. All Channels Are Disabled
Note: Any Combination of Channels Can Be Placed in Nap Mode.
21721012fa
26
LTC2172-12/
LTC2171-12/LTC2170-12
APPLICATIONS INFORMATION
REGISTER A2: OUTPUT MODE REGISTER (ADDRESS 02h)
D7
D6
D5
D4
Dꢀ
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE2
OUTMODE1
OUTMODE0
Bits 7-5
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = ꢀ.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = ꢀ.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 4
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS Output Driver Current is 2x the Current Set by ILVDS2:ILVDS0. Internal termination should only be
used with 1.75mA, 2.1mA or 2.5mA LVDS output current modes.
Bit ꢀ
OUTOFF
Output Disable Bit
0 = Digital Outputs are enabled.
1 = Digital Outputs are disabled.
Bits 2-0
OUTMODE2:OUTMODE0 Digital Output Mode Control Bits
000 = 2-Lanes, 16-Bit Serialization
001 = 2-Lanes, 14-Bit Serialization
010 = 2-Lanes, 12-Bit Serialization
011 = Not Used
100 = Not Used
101 = 1-Lane, 14-Bit Serialization
110 = 1-Lane, 12-Bit Serialization
111 = 1-Lane, 16-Bit Serialization
REGISTER A3: TEST PATTERN MSB REGISTER (ADDRESS 03h)
D7
D6
X
D5
D4
Dꢀ
D2
D1
D0
OUTTEST
TP11
TP10
TP9
TP8
TP7
TP6
Bit 7
OUTTEST
Digital Output Test Pattern Control Bit
0 = Digital Output Test Pattern Off
1 = Digital Output Test Pattern On
Bit 6
Unused, Don’t Care Bit.
Bits 5-0
TP11:TP6
Test Pattern Data Bits (MSB)
TP11:TP6 Set the Test Pattern for Data Bit 11 (MSB) Through Data Bit 6.
REGISTER A4: TEST PATTERN LSB REGISTER (ADDRESS 04h)
D7
D6
D5
D4
Dꢀ
D2
D1
D0
TP5
TP4
TPꢀ
TP2
TP1
TP0
TPX
TPY
Bits 7-2
TP5:TP0
Test Pattern Data Bits (LSB)
TP5:TP0 Set the Test Pattern for Data Bit 5 Through Data Bit 0 (LSB).
Bits 1-0
TPX:TPY
Set the Test Pattern for Extra Bits D and D . These Bits are for Compatibility with the 14-Bit Version of the A/D.
X Y
21721012fa
27
LTC2172-12/
LTC2171-12/LTC2170-12
APPLICATIONS INFORMATION
GROUNDING AND BYPASSING
between REFH and REFL can be somewhat further away.
Thetracesconnectingthepinsandbypasscapacitorsmust
be kept short and should be made as wide as possible.
The LTC2172-12/LTC2171-12/LTC2170-12 requires a
printed circuit board with a clean unbroken ground plane.
A multilayer board with an internal ground plane in the
first layer beneath the ADC is recommended. Layout for
the printed circuit board should ensure that digital and
analog signal lines are separated as much as possible. In
particular, care should be taken not to run any digital track
alongside an analog signal track or underneath the ADC.
The analog inputs, encode signals and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
High quality ceramic bypass capacitors should be used at
MostoftheheatgeneratedbytheLTC2172-12/LTC2171-12/
LTC2170-12 is transferred from the die through the bot-
tom-side exposed pad and package leads onto the printed
circuitboard.Forgoodelectricalandthermalperformance,
the exposed pad must be soldered to a large grounded
pad on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
the V , OV , V , V , REFH and REFL pins. Bypass
DD
DD CM REF
capacitorsmustbelocatedasclosetothepinsaspossible.
Of particular importance is the 0.1μF capacitor between
REFH and REFL. This capacitor should be on the same
side of the circuit board as the A/D, and as close to the
device as possible (1.5mm or less). Size 0402 ceramic
capacitors are recommended. The larger 2.2μF capacitor
21721012fa
28
LTC2172-12/
LTC2171-12/LTC2170-12
TYPICAL APPLICATIONS
Silkscreen Top
Top Side
Inner Layer 2 GND
Inner Layer 3
21721012fa
29
LTC2172-12/
LTC2171-12/LTC2170-12
TYPICAL APPLICATIONS
Inner Layer 4
Inner Layer 5 Power
Bottom Side
Silkscreen Bottom
21721012fa
30
LTC2172-12/
LTC2171-12/LTC2170-12
TYPICAL APPLICATIONS
LTC2172 Schematic
SENSE
PAR/SER
C4
1μF
R14
1k
SDO
C17
1μF
V
DD
C5
1μF
52 51 50 49 48 47 46 45 44 4ꢀ 42 41
A
IN1
DIGITAL
OUTPUTS
1
2
40
ꢀ9
ꢀ8
ꢀ7
ꢀ6
ꢀ5
ꢀ4
ꢀꢀ
ꢀ2
ꢀ1
ꢀ0
29
28
27
+
–
+
–
+
–
+
C29
0.1μF
OUT2A
A
A
V
A
A
A
A
A
IN1
IN1
IN2
IN2
–
OUT2A
OUT2B
OUT2B
DCO
IN1
ꢀ
CM12
4
+
IN2
5
–
IN2
6
DCO
REFH
REFH
REFL
LTC2172
7
OV
OV
DD
DD
C1
2.2μF
Cꢀ0
0.1μF
8
C16
0.1μF
C2
0.1μF
OGND
9
+
FR
REFL
+
Cꢀ
0.1μF
10
11
12
1ꢀ
14
–
FR
A
INꢀ
+
–
OUTꢀA
A
A
A
INꢀ
INꢀ
INꢀ
–
OUTꢀA
V
CMꢀ4
+
+
OUTꢀB
A
A
IN4
IN4
C59
–
–
OUTꢀB
0.1μF
DIGITAL
OUTPUTS
A
A
IN4
IN4
15 16 17 18 19 20 21 22 2ꢀ 24 25 26
V
DD
C7
0.1μF
SPI BUS
C47
0.1μF
C46
0.1μF
217212 TA02
ENCODE
CLOCK
ENCODE
CLOCK
21721012fa
31
LTC2172-12/
LTC2171-12/LTC2170-12
PACKAGE DESCRIPTION
UKG Package
52-Lead Plastic QFN (7mm × 8mm)
(Reference LTC DWG # 05-08-1729 Rev Ø)
7.50 0.05
6.10 0.05
5.50 REF
(2 SIDES)
0.70 0.05
6.45 0.05
6.50 REF
(2 SIDES)
7.10 0.05 8.50 0.05
5.41 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.50 REF
(2 SIDES)
0.75 0.05
7.00 0.10
(2 SIDES)
R = 0.115
TYP
0.00 – 0.05
51
52
0.40 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 × 45°C
CHAMFER
6.45 0.10
8.00 0.10
(2 SIDES)
6.50 REF
(2 SIDES)
5.41 0.10
(UKG52) QFN REV
Ø 0306
R = 0.10
TYP
0.25 0.05
0.50 BSC
TOP VIEW
SIDE VIEW
0.200 REF
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
0.75 0.05
NOTE:
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
3. ALL DIMENSIONS ARE IN MILLIMETERS
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
21721012fa
32
LTC2172-12/
LTC2171-12/LTC2170-12
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
0ꢀ/10 Changed Sampling Frequency Max for LTC2171-12 from 45MHz to 40MHz in the Timing Characteristics section
Added full part numbers to Grounding and Bypassing and Heat Transfer sections in Applications Information
Revised Descriptions and Comments in the Related Parts section
6
28
ꢀ4
21721012fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
33
LTC2172-12/
LTC2171-12/LTC2170-12
RELATED PARTS
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2170-14/LTC2171-14/ 14-Bit, 25Msps/40Msps/65Msps 1.8V
LTC2172-14 Quad ADCs, Ultralow Power
162mW/202mW/ꢀ11mW, 7ꢀ.7dB SNR, 90dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
LTC217ꢀ-14/LTC2174-14/ 14-Bit, 80Msps/105Msps/125Msps 1.8V ꢀ76mW/450mW/558mW, 7ꢀ.4 dB SNR, 88dB SFDR, Serial LVDS Outputs,
LTC2175-14
LTC217ꢀ-12/LTC2174-12/ 12-Bit, 80Msps/105Msps/125Msps
LTC2175-12 1.8V Quad ADCs, Ultralow Power
LTC2256-14/LTC2257-14/ 14-Bit, 25Msps/40Msps/65Msps
LTC2258-14 1.8V ADCs, Ultralow Power
LTC2259-14/LTC2260-14/ 14-Bit, 80Msps/105Msps/125Msps
Quad ADCs, Ultralow Power
7mm × 8mm QFN-52
ꢀ69mW/4ꢀ9mW/545mW, 70.6dB SNR, 88dB SFDR, Serial LVDS Outputs,
7mm × 8mm QFN-52
ꢀ5mW/49mW/81mW, 74dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS
Outputs, 6mm × 6mm QFN-40
89mW/106mW/127mW, 7ꢀ.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS
Outputs, 6mm × 6mm QFN-40
LTC2261-14
1.8V ADCs, Ultralow Power
LTC2262-14
14-Bit, 150Msps 1.8V ADC, Ultralow Power 149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
6mm × 6mm QFN-40
LTC226ꢀ-14/LTC2264-14/ 14-Bit, 25Msps/40Msps/65Msps
LTC2265-14 1.8V Dual ADCs, Ultralow Power
94mW/11ꢀmW/171mW, 7ꢀ.7dB SNR, 90dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC226ꢀ-12/LTC2264-12/ 12-Bit, 25Msps/40Msps/65Msps
LTC2265-12 1.8V Dual ADCs, Ultralow Power
94mW/112mW/167mW, 71dB SNR, 90dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps
LTC2268-14 1.8V Dual ADCs, Ultralow Power
20ꢀmW/24ꢀmW/299mW, 7ꢀ.1dB SNR, 88dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps
200mW/2ꢀ8mW/292mW, 70.6dB SNR, 88dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2268-12
1.8V Dual ADCs, Ultralow Power
RF Mixers/Demodulators
LTC5517
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIPꢀ: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5527
LTC5557
LTC5575
400MHz to ꢀ.7GHz High Linearity
Downconverting Mixer
24.5dBm IIPꢀ at 900MHz, 2ꢀ.5dBm IIPꢀ at 1900MHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports, 5V Supply
400MHz to ꢀ.8GHz High Linearity
Downconverting Mixer
24dBm IIPꢀ at 1950MHz, 2ꢀ.7dBm IIPꢀ at 2.6GHz, NF = 1ꢀ.2dB, ꢀ.ꢀV Supply
Operation, Integrated Transformer
800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
High IIPꢀ: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF
and LO Transformer
Amplifiers/Filters
LTC6412
800MHz, ꢀ1dB Range, Analog-Controlled Continuously Adjustable Gain Control, ꢀ5dBm OIPꢀ at 240MHz, 10dB Noise
Variable Gain Amplifier
Figure, 4mm × 4mm QFN-24
LTC6420-20
LTC6421-20
Dual Low Noise, Low Distortion
Fixed Gain 10V/V, 2.2nV/√Hz Total Input Referred Noise, 80mA Supply Current per
Differential ADC Drivers for ꢀ00MHz IF
Amplifier, 46dBm OIPꢀ at 100MHz, ꢀmm × 4mm QFN-20
Dual Low Noise, Low Distortion
Differential ADC Drivers for 140MHz IF
Fixed Gain 10V/V, 2.2nV/√Hz Total Input Referred Noise, 40mA Supply Current per
Amplifier, 42dBm OIPꢀ at 100MHz, ꢀmm × 4mm QFN-20
LTC6605-7/ LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz Filters Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
LTC6605-14
with ADC Drivers
Pin-Programmable Gain, 6mm × ꢀmm DFN-22
Signal Chain Receivers
LTM9002
14-Bit Dual Channel IF/Baseband Receiver Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
Subsystem
21721012fa
LT 0310 REV A • PRINTED IN USA
LinearTechnology Corporation
16ꢀ0 McCarthy Blvd., Milpitas, CA 950ꢀ5-7417
34
●
●
© LINEAR TECHNOLOGY CORPORATION 2010
(408) 4ꢀ2-1900 FAX: (408) 4ꢀ4-0507 www.linear.com
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