LTC2164IUK#PBF [Linear]
LTC2164 - 16-Bit, 105Msps Low Power ADCs; Package: QFN; Pins: 48; Temperature Range: -40°C to 85°C;
| 型号： | LTC2164IUK#PBF |
| 厂家： | 
Linear |
| 描述： | LTC2164 - 16-Bit, 105Msps Low Power ADCs; Package: QFN; Pins: 48; Temperature Range: -40°C to 85°C 转换器 |
| 文件： | 总36页 (文件大小：713K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2165/LTC2164/LTC2163
16-Bit, 125/105/80Msps
Low Power ADCs
FeaTures
DescripTion
The LTC®2165/LTC2164/LTC2163 are sampling 16-bit A/D
converters designed for digitizing high frequency, wide
dynamic range signals. They are perfect for demanding
communications applications with AC performance that
includes 76.8dB SNR and 90dB spurious free dynamic
n
76.8dB SNR
n
90dB SFDR
n
Low Power: 194mW/163mW/108mW
n
Single 1.8V Supply
n
CMOS, DDR CMOS, or DDR LVDS Outputs
n
range (SFDR). Ultralow jitter of 0.07ps
amplingofIFfrequencieswithexcellentnoiseperformance.
allows unders-
Selectable Input Ranges: 1V to 2V
RMS
P-P
P-P
n
n
n
n
n
n
550MHz Full Power Bandwidth S/H
Optional Data Output Randomizer
Optional Clock Duty Cycle Stabilizer
Shutdown and Nap Modes
DC specs include 2LSB INL (typ), 0.5LSB DNL (typ)
and no missing codes over temperature. The transition
noise is 3.4LSB
.
RMS
Serial SPI Port for Configuration
48-Pin (7mm × 7mm) QFN Package
The digital outputs can be either full rate CMOS, double
data rate CMOS, or double data rate LVDS. A separate
output power supply allows the CMOS output swing to
range from 1.2V to 1.8V.
applicaTions
n
+
–
Communications
The ENC and ENC inputs may be driven differentially
or single-ended with a sine wave, PECL, LVDS, TTL, or
CMOS inputs. An optional clock duty cycle stabilizer al-
lows high performance at full speed for a wide range of
clock duty cycles.
n
Cellular Base Stations
n
Software Defined Radios
n
Portable Medical Imaging
n
Multichannel Data Acquisition
n
Nondestructive Testing
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Typical applicaTion
2-Tone FFT, fIN = 70MHz and 69MHz
1.8V
1.8V
OV
0
–10
–20
–30
–40
V
DD
DD
16-BIT
ADC CORE
ANALOG
INPUT
S/H
–50
–60
–70
D15
•
•
•
D0
CMOS, DDR
CMOS OR
DDR LVDS
OUTPUTS
OUTPUT
DRIVERS
–80
–90
125MHz
CLOCK
CLOCK
CONTROL
–100
–110
–120
0
20
30
40
50
60
10
FREQUENCY (MHz)
2165 TA01b
2165 TA01a
GND
OGND
216543f
1
LTC2165/LTC2164/LTC2163
absoluTe MaxiMuM raTings (Notes 1, 2)
Supply Voltages (V , O ) .......................–0.3V to 2V
Digital Output Voltage ................–0.3V to (OV + 0.3V)
DD VDD
DD
+
–
Analog Input Voltage (A , A , PAR/SER, SENSE)
Operating Temperature Range
IN
IN
(Note 3) ................................... –0.3V to (V + 0.2V)
LTC2165C, LTC2164C, LTC2163C............. 0°C to 70°C
LTC2165I, LTC2164I, LTC2163I............–40°C to 85°C
Storage Temperature Range...................–65°C to 150°C
DD
+
–
Digital Input Voltage (ENC , ENC , CS, SDI, SCK)
(Note 4) ................................................ –0.3V to 3.9V
SDO (Note 4) ............................................ –0.3V to 3.9V
pin conFiguraTion
FULL RATE CMOS OUTPUT MODE
DOUBLE DATA RATE CMOS OUTPUT MODE
TOP VIEW
TOP VIEW
V
1
2
3
36 D11
35 D10
34 D9
CM
V
1
2
3
36 D10_11
35 DNC
34 D8_9
33 DNC
CM
+
+
A
A
IN
–
A
A
IN
–
IN
IN
GND 4
REFH 5
REFL 6
REFH 7
REFL 8
33 D8
GND 4
REFH 5
REFL 6
REFH 7
REFL 8
32 OV
DD
32 OV
DD
31 OGND
30 CLKOUT
29 CLKOUT
28 D7
27 D6
26 D5
49
GND
31 OGND
30 CLKOUT
29 CLKOUT
28 D6_7
27 DNC
49
GND
+
–
+
–
PAR/SER 9
GND 10
GND 11
PAR/SER 9
GND 10
GND 11
26 D4_5
25 DNC
V
DD
12
25 D4
V
DD
12
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
T
= 150°C, θ = 29°C/W
JA
JMAX
T
= 150°C, θ = 29°C/W
JA
JMAX
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
216543f
2
LTC2165/LTC2164/LTC2163
pin conFiguraTion
DOUBLE DATA RATE LVDS OUTPUT MODE
TOP VIEW
+
V
1
2
3
36 D10_11
CM
+
–
A
A
35 D10_11
IN
–
+
34 D8_9
33 D8_9
IN
–
GND 4
REFH 5
32 OV
DD
REFL 6
REFH 7
REFL 8
31 OGND
49
GND
+
–
30 CLKOUT
29 CLKOUT
+
PAR/SER 9
GND 10
GND 11
28 D6_7
27 D6_7–
+
26 D4_5
V
DD
12
25 D4_5–
UK PACKAGE
48-LEAD (7mm × 7mm) PLASTIC QFN
T
= 150°C, θ = 29°C/W
JA
JMAX
EXPOSED PAD (PIN 49) IS GND, MUST BE SOLDERED TO PCB
orDer inForMaTion
LEAD FREE FINISH
LTC2165CUK#PBF
LTC2165IUK#PBF
LTC2164CUK#PBF
LTC2164IUK#PBF
LTC2163CUK#PBF
LTC2163IUK#PBF
TAPE AND REEL
PART MARKING*
LTC2165UK
LTC2165UK
LTC2164UK
LTC2164UK
LTC2163UK
LTC2163UK
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTC2165CUK#TRPBF
LTC2165IUK#TRPBF
LTC2164CUK#TRPBF
LTC2164IUK#TRPBF
LTC2163CUK#TRPBF
LTC2163IUK#TRPBF
48-Lead (7mm × 7mm) Plastic QFN
48-Lead (7mm × 7mm) Plastic QFN
48-Lead (7mm × 7mm) Plastic QFN
48-Lead (7mm × 7mm) Plastic QFN
48-Lead (7mm × 7mm) Plastic QFN
48-Lead (7mm × 7mm) Plastic QFN
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
0°C to 70°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
216543f
3
LTC2165/LTC2164/LTC2163
converTer characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C.
LTC2165
TYP
LTC2164
TYP
LTC2163
TYP
PARAMETER
CONDITIONS
MIN
16
MAX
MIN
16
MAX
MIN
16
MAX
UNITS
Bits
l
l
Resolution (No Missing Codes)
Integral Linearity Error
Differential Analog Input
(Note 6)
–6
2
6
–6
2
6
–6
2
6
LSB
l
l
Differential Linearity Error
Offset Error
Differential Analog Input
(Note 7)
–0.9
–7
0.5
1.5
0.9
7
–0.9
–7
0.5
1.5
0.9
7
–0.9
–7
0.5
1.5
0.9
7
LSB
mV
Gain Error
Internal Reference
External Reference
1.5
–0.5
1.5
–0.5
1.5
–0.5
%FS
%FS
l
–1.8
0.7
–1.8
0.7
–1.8
0.7
Offset Drift
10
10
10
µV/°C
Full-Scale Drift
Internal Reference
External Reference
30
10
30
10
30
10
ppm/°C
ppm/°C
Transition Noise
External Reference
3.4
3.5
3.2
LSB
RMS
analog inpuT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 5)
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
l
l
l
V
V
V
Analog Input Range (A – A
)
1.7V < V < 1.9V
1 to 2
V
P-P
IN
IN
IN
DD
+
–
Analog Input Common Mode (A + A )/2
Differential Analog Input (Note 8)
External Reference Mode
0.7
V
CM
1.25
V
IN(CM)
SENSE
INCM
IN
IN
External Voltage Reference Applied to SENSE
Analog Input Common Mode Current
0.625
1.250
1.300
V
I
Per Pin, 125Msps
Per Pin, 105Msps
Per Pin, 80Msps
200
170
130
µA
µA
µA
+
–
l
l
l
I
I
I
t
t
Analog Input Leakage Current (No Encode)
PAR/SER Input Leakage Current
0 < A , A < V
–1
–3
–6
1
3
6
µA
µA
µA
ns
IN1
IN
IN
DD
0 < PAR/SER < V
IN2
DD
SENSE Input Leakage Current
0.625 < SENSE < 1.3V
IN3
Sample-and-Hold Acquisition Delay Time
Sample-and-Hold Acquisition Delay Jitter
0
AP
Single-Ended Encode
Differential Encode
0.07
0.09
ps
ps
JITTER
RMS
RMS
CMRR
BW-3B
Analog Input Common Mode Rejection Ratio
Full Power Bandwidth
80
dB
Figure 6 Test Circuit
550
MHz
DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2165
TYP
LTC2164
TYP
LTC2163
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX UNITS
SNR
Signal-to-Noise Ratio
5MHz Input
76.8
76.6
76.3
76.7
76.5
76
77.1
76.9
76.4
dBFS
dBFS
dBFS
l
l
l
70MHz Input
140MHz Input
75
75
75.3
SFDR
SFDR
Spurious Free Dynamic Range 5MHz Input
2nd Harmonic
90
89
84
90
89
84
90
89
84
dBFS
dBFS
dBFS
70MHz Input
140MHz Input
80
82
80
81
82
82
Spurious Free Dynamic Range 5MHz Input
3rd Harmonic
90
89
84
90
89
84
90
89
84
dBFS
dBFS
dBFS
70MHz Input
140MHz Input
216543f
4
LTC2165/LTC2164/LTC2163
DynaMic accuracy The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 5)
LTC2165
TYP
LTC2164
TYP
LTC2163
TYP
SYMBOL PARAMETER
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX UNITS
SFDR Spurious Free Dynamic Range 5MHz Input
95
95
95
95
95
95
95
95
95
dBFS
dBFS
dBFS
l
l
4th Harmonic or Higher
70MHz Input
140MHz Input
88
89
90
S/(N+D) Signal-to-Noise Plus
Distortion Ratio
5MHz Input
70MHz Input
140MHz Input
76.6
76.2
75.1
76.5
76.1
75
76.9
76.5
75.3
dBFS
dBFS
dBFS
74
74.1
74.6
inTernal reFerence characTerisTics The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5)
PARAMETER
CONDITIONS
= 0
MIN
TYP
0.5•V
MAX
UNITS
V
V
V
V
V
V
V
V
Output Voltage
I
0.5•V – 25mV
0.5•V + 25mV
CM
CM
CM
REF
REF
REF
REF
OUT
DD
DD
DD
Output Temperature Drift
Output Resistance
Output Voltage
25
4
ppm/°C
Ω
–600µA < I
< 1mA
< 1mA
OUT
I
= 0
1.225
1.250
25
1.275
V
OUT
Output Temperature Drift
Output Resistance
Line Regulation
ppm/°C
Ω
–400µA < I
7
OUT
1.7V < V < 1.9V
0.6
mV/V
DD
DigiTal inpuTs anD ouTpuTs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
ENCODE INPUTS (ENC , ENC )
DIFFERENTIAL ENCODE MODE (ENC NOT TIED TO GND)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
+
–
–
l
V
V
Differential Input Voltage
(Note 8)
0.2
V
ID
Common Mode Input Voltage
Internally Set
Externally Set (Note 8)
1.2
V
V
ICM
l
l
1.1
0.2
1.6
3.6
+
–
V
Input Voltage Range
Input Resistance
ENC , ENC to GND
(See Figure 10)
(Note 8)
V
kΩ
pF
IN
R
10
IN
IN
C
Input Capacitance
3.5
–
SINGLE-ENDED ENCODE MODE (ENC TIED TO GND)
l
l
l
V
V
V
High Level Input Voltage
Low Level Input Voltage
Input Voltage Range
Input Resistance
V
V
= 1.8V
= 1.8V
1.2
0
V
V
IH
IL
IN
DD
0.6
3.6
DD
+
ENC to GND
(See Figure 11)
(Note 8)
V
R
30
kΩ
pF
IN
IN
C
Input Capacitance
3.5
DIGITAL INPUTS (CS, SDI, SCK in Serial or Parallel Programming Mode. SDO in Parallel Programming Mode)
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Current
V
DD
V
DD
V
IN
= 1.8V
1.3
V
V
IH
IL
l
l
= 1.8V
0.6
10
I
IN
= 0V to 3.6V
–10
µA
216543f
5
LTC2165/LTC2164/LTC2163
DigiTal inpuTs anD ouTpuTs The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
C
IN
Input Capacitance
(Note 8)
3
pF
SDO OUTPUT (Serial Programming Mode. Open Drain Output. Requires 2kΩ Pull-Up Resistor if SDO is Used)
R
Logic Low Output Resistance to GND
Logic High Output Leakage Current
Output Capacitance
V
= 1.8V, SDO = 0V
200
3
Ω
µA
pF
OL
DD
l
I
SDO = 0V to 3.6V
(Note 8)
–10
10
OH
C
OUT
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
OV = 1.8V
DD
l
l
V
V
High Level Output Voltage
Low Level Output Voltage
I = –500µA
1.750
1.790
0.010
V
V
OH
OL
O
I = 500µA
O
0.050
OV = 1.5V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –500µA
1.488
0.010
V
V
OH
OL
O
I = 500µA
O
OV = 1.2V
DD
V
V
High Level Output Voltage
Low Level Output Voltage
I = –500µA
1.185
0.010
V
V
OH
OL
O
I = 500µA
O
DIGITAL DATA OUTPUTS (LVDS MODE)
l
l
V
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
350
175
454
mV
mV
OD
V
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.250
1.250
1.375
V
V
OS
R
Termination Enabled, OV = 1.8V
100
Ω
TERM
DD
power requireMenTs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2165
TYP MAX MIN
LTC2164
TYP MAX MIN
LTC2163
TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
CMOS Output Modes: Full Data Rate and Double Data Rate
l
l
l
V
Analog Supply Voltage (Note 10)
Output Supply Voltage (Note 10)
Analog Supply Current DC Input
1.7
1.1
1.8
1.8
1.9
1.9
1.7
1.1
1.8
1.8
1.9
1.9
1.7
1.1
1.8
1.8
1.9
1.9
69
V
V
DD
OV
DD
I
108
110
123
91
92
103
60
61
mA
mA
VDD
Sine Wave Input
I
Digital Supply Current Sine Wave Input, OV =1.2V
5
4
3
mA
OVDD
DD
l
P
Power Dissipation
DC Input
Sine Wave Input, OV =1.2V
194
204
222
163
170
186
108
113
125
mW
mW
DISS
DD
LVDS Output Mode
Analog Supply Voltage (Note 10)
l
l
V
DD
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
1.7
1.7
1.8
1.8
1.9
1.9
V
V
OV
Output Supply Voltage (Note 10)
DD
I
Analog Supply Current Sine Wave Input 1.75mA Mode
3.5mA Mode
112
113
94
95
62
63
mA
mA
VDD
l
l
127
47
107
47
72
46
I
Digital Supply Current Sine Wave Input 1.75mA Mode
22
42
22
42
22
42
mA
mA
OVDD
(OV = 1.8V)
3.5mA Mode
DD
216543f
6
LTC2165/LTC2164/LTC2163
power requireMenTs The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 9)
LTC2165
MIN TYP MAX MIN
LTC2164
TYP MAX MIN
LTC2163
TYP MAX UNITS
SYMBOL PARAMETER
Power Dissipation
CONDITIONS
P
Sine Wave Input, 1.75mA Mode
Sine Wave Input, 3.5mA Mode
241
279
209
247
151
189
mW
mW
DISS
l
314
278
213
All Output Modes
P
P
P
Sleep Mode Power
Nap Mode Power
1
1
1
mW
mW
mW
SLEEP
NAP
10
20
10
20
10
20
Power Increase with Differential Encode Mode Enabled
(No Increase for Nap or Sleep Modes)
DIFFCLK
TiMing characTerisTics The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 5)
LTC2165
LTC2164
LTC2163
TYP MAX UNITS
SYMBOL PARAMETER
CONDITIONS
MIN
TYP MAX MIN TYP MAX MIN
l
f
Sampling Frequency
(Note 10)
1
125
1
105
1
80
MHz
S
L
l
l
t
ENC Low Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
3.8
2
4
4
500
500
4.52 4.76
4.76
500
500
5.93 6.25
6.25
500
500
ns
ns
2
2
l
l
t
t
ENC High Time (Note 8) Duty Cycle Stabilizer Off
Duty Cycle Stabilizer On
3.8
2
4
4
500
500
4.52 4.76
500
500
5.93 6.25
500
500
ns
ns
H
2
4.76
2
6.25
Sample-and-Hold
Acquisition Delay Time
0
0
0
ns
AP
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL DATA OUTPUTS (CMOS MODES: FULL DATA RATE AND DOUBLE DATA RATE)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.7
1.4
0.3
3.1
2.6
0.6
ns
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
SKEW
D
C
Full Data Rate Mode
Double Data Rate Mode
6
6.5
Cycles
Cycles
DIGITAL DATA OUTPUTS (LVDS MODE)
l
l
l
t
t
t
ENC to Data Delay
ENC to CLKOUT Delay
DATA to CLKOUT Skew
Pipeline Latency
C = 5pF (Note 8)
1.1
1
1.8
1.5
0.3
6.5
3.2
2.7
0.6
ns
ns
D
L
C = 5pF (Note 8)
L
C
t – t (Note 8)
0
ns
SKEW
D
C
Cycles
SPI PORT TIMING (Note 8)
l
l
t
SCK Period
Write Mode
40
ns
ns
SCK
Readback Mode, C
= 20pF, R
= 20pF, R
= 2k
= 2k
250
SDO
PULLUP
l
l
l
l
l
t
t
t
t
t
CS to SCK Setup Time
SCK to CS Setup Time
SDI Setup Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO Valid
Readback Mode, C
125
SDO
PULLUP
216543f
7
LTC2165/LTC2164/LTC2163
elecTrical characTerisTics
Note 6: Integral nonlinearity is defined as the deviation of a code from a
best fit straight line to the transfer curve. The deviation is measured from
the center of the quantization band.
Note 7: Offset error is the offset voltage measured from –0.5 LSB when
the output code flickers between 0000 0000 0000 0000 and 1111 1111
1111 1111 in 2’s complement output mode.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All voltage values are with respect to GND with GND and OGND
shorted (unless otherwise noted).
Note 8: Guaranteed by design, not subject to test.
Note 3: When these pin voltages are taken below GND or above V , they
DD
will be clamped by internal diodes. This product can handle input currents
Note 9: V = 1.8V, f
= 125MHz (LTC2165), 105MHz (LTC2164), or
DD
SAMPLE
+
of greater than 100mA below GND or above V without latchup.
DD
80MHz (LTC2163), CMOS outputs, ENC = single-ended 1.8V square wave,
–
ENC = 0V, input range = 2V with differential drive, 5pF load on each
Note 4: When these pin voltages are taken below GND they will be
P-P
digital output unless otherwise noted.
clamped by internal diodes. When these pin voltages are taken above V
DD
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
Note 10: Recommended operating conditions.
Note 5: V = OV = 1.8V, f
(LTC2164), or 80MHz (LTC2163), LVDS outputs, differential ENC /ENC
= 125MHz (LTC2165), 105MHz
DD
DD
SAMPLE
+
–
= 2V sine wave, input range = 2V with differential drive, unless
P-P
P-P
otherwise noted.
TiMing DiagraMs
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
D
N – 6
N – 5
N – 4
N – 3
N – 2
D0–D15, OF
t
C
+
CLKOUT
–
CLKOUT
2165 TD01
216543f
8
LTC2165/LTC2164/LTC2163
TiMing DiagraMs
Double Data Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
t
D
D
D0_1
D0
N-6
D1
N-6
D0
N-5
D1
N-5
D0
N-4
D1
N-4
D0
N-3
D1
N-3
•
•
•
D14_15
OF
D14
D15
D14
D15
D14
D15
D14
D15
N-3
N-6
N-6
N-5
N-5
N-4
N-4
N-3
OF
OF
OF
OF
N-3
N-6
N-5
N-4
t
t
C
C
+
CLKOUT
–
CLKOUT
2165 TD02
Double Data Rate LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels
t
AP
N + 4
N + 2
ANALOG
INPUT
N
N + 3
t
H
N + 1
t
L
–
ENC
+
ENC
t
t
D
D
+
D0_1
D0
N-6
D1
N-6
D0
N-5
D1
N-5
D0
N-4
D1
N-4
D0
N-3
D1
N-3
–
D0_1
•
•
•
+
D14_15
D14
D15
D14
D15
N-5
D14
D15
D14
D15
N-3
N-6
N-6
N-5
N-5
N-4
N-4
N-3
–
D14_15
+
OF
OF
OF
OF
OF
N-3
N-6
N-4
–
OF
t
t
C
C
+
CLKOUT
–
CLKOUT
2165 TD03
216543f
9
LTC2165/LTC2164/LTC2163
TiMing DiagraMs
SPI Port Timing (Readback Mode)
t
S
t
DS
t
DH
t
t
H
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
A3
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SDO
2165 TD04
HIGH IMPEDANCE
216543f
10
LTC2165/LTC2164/LTC2163
Typical perForMance characTerisTics
LTC2165 Integral
LTC2165 Differential
Non-Linearity (DNL)
LTC2165 64k Point FFT,
Non-Linearity (INL)
fIN = 5MHz, –1dBFS, 125Msps
4.0
3.0
1.0
0.8
0
–10
–20
–30
–40
–50
–60
–70
0.6
2.0
0.4
1.0
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
–2.0
–3.0
–4.0
–80
–90
–100
–110
–120
0
32768
49152
65536
0
20
30
40
50
60
16384
0
32768
49152
65536
10
16384
OUTPUT CODE
OUTPUT CODE
FREQUENCY (MHz)
2165 G01
2165 G02
2165 G03
LTC2165 64k Point FFT,
fIN = 30MHz, –1dBFS, 125Msps
LTC2165 64k Point FFT,
fIN = 70MHz, –1dBFS, 125Msps
LTC2165 64k Point FFT,
fIN = 140MHz, –1dBFS, 125Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
20
30
40
50
60
0
20
30
40
50
60
10
10
0
20
30
40
50
60
10
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2165 G04
2165 G06
2165 G05
LTC2165 64k Point 2-Tone FFT,
fIN = 70MHz, 69MHz, –7dBFS,
125Msps
LTC2165 SNR vs Input Frequency,
–1dBFS, 2V Range, 125Msps
LTC2165 Shorted Input Histogram
0
–10
–20
–30
–40
–50
–60
–70
78
77
76
75
74
73
72
71
70
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
–80
–90
–100
–110
–120
0
20
30
40
50
60
10
0
50
100
150
200
250
300
32750
32762 32768 32774
OUTPUT CODE
32756
FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
2165 G07
2165 G09
2165 G08
216543f
11
LTC2165/LTC2164/LTC2163
Typical perForMance characTerisTics
LTC2165 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
2V Range, 125Msps
LTC2165: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
125Msps, 1V Range
LTC2165 SFDR vs Input Level,
f
IN = 70MHz, 2V Range, 125Msps
130
120
110
100
90
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
dBFS
3RD
3RD
80
2ND
dBc
70
2ND
60
50
40
30
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
2165 G12
2165 G10
2165 G11
LTC2165 IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS,
5pF on Each Data Output
LTC2165 IVDD vs Sample Rate,
LTC2165 SNR vs SENSE,
fIN = 5MHz, –1dBFS
5MHz Sine Wave Input, –1dBFS
120
110
100
90
50
40
30
20
10
0
78
77
76
75
74
73
72
71
70
3.5mA LVDS
3.5mA LVDS OUTPUTS
CMOS OUTPUTS
1.75mA LVDS
1.8V CMOS
1.2V CMOS
80
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
25
50
75
100
125
0
25
50
75
100
125
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
SENSE PIN (V)
2165 G13
2165 G14
2165 G15
LTC2164 Differential
Non-Linearity (DNL)
LTC2164 64k Point FFT,
LTC2164 Integral Non-Linearity
(INL)
fIN = 5MHz, –1dBFS, 105Msps
4.0
3.0
0
–10
–20
–30
–40
–50
–60
–70
1.0
0.8
0.6
2.0
0.4
0.2
0
1.0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
–2.0
–3.0
–4.0
–80
–90
–100
–110
–120
0
32768
49152
65536
16384
0
10
20
30
40
50
0
32768
49152
65536
16384
OUTPUT CODE
FREQUENCY (MHz)
OUTPUT CODE
2165 G16
2165 G18
2165 G17
216543f
12
LTC2165/LTC2164/LTC2163
Typical perForMance characTerisTics
LTC2164 64k Point FFT,
fIN = 30MHz, –1dBFS, 105Msps
LTC2164 64k Point FFT,
fIN = 70MHz, –1dBFS, 105Msps
LTC2164 64k Point FFT,
fIN = 140MHz, –1dBFS, 105Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10
20
30
40
50
0
10
20
30
40
50
0
10
20
30
40
50
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2165 G20
2165 G19
2165 G21
LTC2164 64k Point 2-Tone FFT,
fIN = 70MHz, 69MHz, –7dBFS,
105Msps
LTC2164 SNR vs Input Frequency,
–1dBFS, 2V Range, 105Msps
LTC2164 Shorted Input Histogram
0
–10
–20
–30
–40
–50
–60
–70
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
78
77
76
75
74
73
72
71
70
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
–80
–90
–100
–110
–120
0
10
20
30
40
50
32790
32802 32808 32814
OUTPUT CODE
32796
0
50
100
150
200
250
300
FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
2165 G22
2165 G23
2165 G24
LTC2164 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
2V Range, 105Msps
LTC2164: 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
105Msps, 1V Range
LTC2164 SFDR vs Input Level,
fIN = 70MHz, 2V Range, 105Msps
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
130
120
110
100
90
dBFS
3RD
3RD
80
2ND
dBc
70
2ND
60
50
40
30
20
0
50
100
150
200
250
300
0
50
100
150
200
250
300
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
2165 G26
2165 G25
2165 G27
216543f
13
LTC2165/LTC2164/LTC2163
Typical perForMance characTerisTics
LTC2164 IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS,
5pF on Each Data Output
LTC2164 SNR vs SENSE,
fIN = 5MHz, –1dBFS
LTC2164 IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
100
90
80
70
60
50
40
30
20
10
0
78
77
76
75
74
73
72
71
70
3.5mA LVDS
3.5mA LVDS OUTPUTS
CMOS OUTPUTS
1.75mA LVDS
1.2V CMOS
1.8V CMOS
0
25
50
75
100
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
25
50
75
100
SAMPLE RATE (Msps)
SENSE PIN (V)
SAMPLE RATE (Msps)
2165 G28
2165 G30
2165 G29
LTC2163 64k Point FFT, fIN = 5MHz,
–1dBFS, 80Msps
LTC2163 Integral Non-Linearity
(INL)
LTC2163 Differential
Non-Linearity (DNL)
0
4.0
3.0
1.0
0.8
0.6
–10
–20
–30
–40
–50
–60
–70
2.0
0.4
0.2
0
1.0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.0
–2.0
–3.0
–4.0
–80
–90
–100
–110
–120
0
32768
49152
65536
0
32768
49152
65536
0
10
20
30
40
16384
16384
FREQUENCY (MHz)
OUTPUT CODE
OUTPUT CODE
2165 G33
2165 G31
2165 G32
LTC2163 64k Point FFT,
LTC2163 64k Point FFT,
fIN = 70MHz, –1dBFS, 80Msps
LTC2163 64k Point FFT,
fIN = 140MHz, –1dBFS, 80Msps
f
IN = 30MHz, –1dBFS, 80Msps
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–80
–90
–80
–90
–100
–110
–120
–100
–110
–120
–100
–110
–120
0
10
20
30
40
0
10
20
30
40
0
10
20
30
40
FREQUENCY (MHz)
FREQUENCY (MHz)
FREQUENCY (MHz)
2165 G34
2165 G36
2165 G35
216543f
14
LTC2165/LTC2164/LTC2163
Typical perForMance characTerisTics
LTC2163 64k Point 2-Tone FFT,
fIN = 70MHz, 69MHz, –7dBFS,
80Msps
LTC2163 SNR vs Input Frequency,
–1dBFS, 2V Range
LTC2163 Shorted Input Histogram
0
–10
–20
–30
–40
–50
–60
–70
78
77
76
75
74
73
72
71
70
10000
9000
8000
7000
6000
5000
4000
3000
2000
1000
0
SINGLE-ENDED
ENCODE
DIFFERENTIAL
ENCODE
–80
–90
–100
–110
–120
0
10
20
30
40
0
50
100
150
200
250
300
32817
32829
32835
32841
32823
FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
OUTPUT CODE
2165 G37
2165 G39
2165 G38
LTC2163 2nd or 3rd Harmonic
vs Input Frequency, –1dBFS,
2V Range, 80Msps
LTC2163 2nd, 3rd Harmonic
vs Input Frequency, –1dBFS,
80Msps, 1V Range
LTC2163 SFDR vs Input Level,
fIN = 70MHz, 2V Range, 80Msps
130
120
110
100
90
100
95
90
85
80
75
70
65
100
95
90
85
80
75
70
65
dBFS
3RD
3RD
80
2ND
dBc
70
2ND
60
50
40
30
20
–80 –70 –60 –50 –40 –30 –20 –10
INPUT LEVEL (dBFS)
0
0
50
100
150
200
250
300
0
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
2165 G27
2165 G40
2165 G41
LTC2163 IVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
LTC2163 IOVDD vs Sample Rate,
5MHz Sine Wave Input, –1dBFS
LTC2163 SNR vs SENSE,
fIN = 5MHz, –1dBFS
50
40
30
20
10
0
70
60
50
40
78
77
76
75
74
73
72
71
70
3.5mA LVDS
3.5mA LVDS OUTPUTS
CMOS OUTPUTS
1.75mA LVDS
1.2V CMOS
1.8V CMOS
0
20
40
60
80
0.6 0.7 0.8 0.9
1
1.1 1.2 1.3
0
20
40
60
80
SAMPLE RATE (Msps)
SAMPLE RATE (Msps)
SENSE PIN (V)
2165 G44
2165 G43
2165 G45
216543f
15
LTC2165/LTC2164/LTC2163
pin FuncTions
(Pins That Are the Same for All Digital Output Modes)
SCK (Pin 18): Serial Interface Clock Input. In serial
programming mode, (PAR/SER = 0V), SCK is the serial
interface clock input. In the parallel programming mode
V
(Pin 1): Common Mode Bias Output. Nominally
CM
equal to V /2. V should be used to bias the common
DD
CM
(PAR/SER = V ), SCK controls the digital output mode
DD
mode of the analog inputs. Bypass to ground with a 0.1µF
ceramic capacitor.
(see Table 2). SCK can be driven with 1.8V to 3.3V logic.
SDI(Pin19):SerialInterfaceDataInput.Inserialprogram-
ming mode, (PAR/SER = 0V), SDI is the serial interface
data input. Data on SDI is clocked into the mode control
registersontherisingedgeofSCK.Intheparallelprogram-
+
A
A
(Pin 2): Positive Differential Analog Input.
(Pin 3): Negative Differential Analog Input.
IN
–
IN
GND (Pins 4, 10, 11, 14, 20, 43, Exposed Pad Pin 49):
ADC Power Ground. The exposed pad must be soldered
to the PCB ground.
ming mode (PAR/SER = V ), SDI can be used together
DD
with SDO to power down the part (Table 2). SDI can be
driven with 1.8V to 3.3V logic.
REFH (Pins 5, 7): ADC High Reference. See the Applica-
tions Information section for recommended bypassing
circuits for REFH and REFL.
OGND (Pin 31): Output Driver Ground. Must be shorted
to the ground plane by a very low inductance path. Use
multiple vias close to the pin.
REFL(Pins6,8):ADCLowReference.SeetheApplications
Information section for recommended bypassing circuits
for REFH and REFL.
OV (Pin 32): Output Driver Supply. Bypass to ground
DD
with a 0.1µF ceramic capacitor.
SDO (Pin 44): Serial Interface Data Output. In serial pro-
gramming mode, (PAR/SER = 0V), SDO is the optional
serial interface data output. Data on SDO is read back
from the mode control registers and can be latched on
the falling edge of SCK. SDO is an open-drain NMOS
output that requires an external 2kΩ pull-up resistor to
1.8V – 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected. In the parallel programming
PAR/SER(Pin9):ProgrammingModeSelectionPin. Con-
nect to ground to enable the serial programming mode.
CS, SCK, SDI, SDO become a serial interface that control
the A/D operating modes. Connect to V to enable the
DD
parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the A/D operating modes. PAR/SER should be connected
directlytogroundorV andnotbedrivenbyalogicsignal.
DD
V
(Pins 12, 13, 47, 48): Analog Power Supply, 1.7V
DD
mode (PAR/SER = V ), SDO can be used together with
DD
to 1.9V. Bypass to ground with 0.1µF ceramic capacitors.
SDI to power down the part (Table 2). When used as an
input, SDO can be driven with 1.8V to 3.3V logic through
a 1kΩ series resistor.
Adjacent pins can share a bypass capacitor.
+
ENC (Pin 15): Encode Input. Conversion starts on the
rising edge.
V
(Pin 45): Reference Voltage Output. Bypass to
REF
–
ground with a 2.2µF ceramic capacitor. The output voltage
ENC (Pin 16): Encode Complement Input. Conversion
is nominally 1.25V.
starts on the falling edge. Tie to GND for single-ended
encode mode.
SENSE(Pin46): ReferenceProgrammingPin.Connecting
SENSEtoV selectstheinternalreferenceanda 1Vinput
CS (Pin 17): Serial Interface Chip Select Input. In serial
programming mode (PAR/SER = 0V), CS is the serial in-
terface chip select input. When CS is low, SCK is enabled
for shifting data on SDI into the mode control registers.
DD
range. Connecting SENSE to ground selects the internal
reference and a 0.5V input range. An external reference
between 0.625V and 1.3V applied to SENSE selects an
input range of ±0.8 • V
.
In the parallel programming mode (PAR/SER = V ),
SENSE
DD
CS controls the clock duty cycle stabilizer (see Table 2).
CS can be driven with 1.8V to 3.3V logic.
216543f
16
LTC2165/LTC2164/LTC2163
pin FuncTions
FULL RATE CMOS OUTPUT MODE
DOUBLE DATA RATE LVDS OUTPUT MODE
All Pins Below Have CMOS Output Levels (OGND to
VDD
All Pins Below Have LVDS Output Levels. The Output
Current Level is Programmable. There is an Optional
Internal 100Ω Termination Resistor Between the Pins
of Each LVDS Output Pair.
O
)
D0 to D15 (Pins 21-28, 33-40): Digital Outputs. D15 is
the MSB.
–
+
–
+
D0_1 /D0_1 to D14_15 /D14_15 (Pins 21/22, 23/24,
25/26, 27/28, 33/34, 35/36, 37/38, 39/40): Double Data
Rate Digital Outputs. Two data bits are multiplexed onto
each differential output pair. The even data bits (D0, D2,
–
+
CLKOUT (Pin 29): Inverted version of CLKOUT .
+
CLKOUT (Pin 30): Data Output Clock. The digital outputs
normally transition at the same time as the falling edge
+
+
+
of CLKOUT . The phase of CLKOUT can also be delayed
relative to the digital outputs by programming the mode
control registers.
D4, D6, D8, D10, D12, D14) appear when CLKOUT is low.
The odd data bits (D1, D3, D5, D7, D9, D11, D13, D15)
+
appear when CLKOUT is high.
–
+
DNC (Pin 41): Do not connect this pin.
CLKOUT /CLKOUT (Pins 39/40): Data Output Clock.
The digital outputs normally transition at the same time
OF(Pin42):Overflow/UnderflowDigitalOutput.OFishigh
when an overflow or underflow has occurred.
+
as the falling and rising edges of CLKOUT . The phase of
+
CLKOUT canalsobedelayedrelativetothedigitaloutputs
by programming the mode control registers.
DOUBLE DATA RATE CMOS OUTPUT MODE
–
+
OF /OF (Pins41/42):Overflow/UnderflowDigitalOutput.
OF is high when an overflow or underflow has occurred.
+
All Pins Below Have CMOS Output Levels (OGND to
O
VDD
)
D0_1 to D14_15 (Pins 22, 24, 26, 28, 34, 36, 38, 40):
Double Data Rate Digital Outputs. Two data bits are mul-
tiplexed onto each output pin. The even data bits (D0,
+
D2, D4, D6, D8, D10, D12, D14) appear when CLKOUT
is low. The odd data bits (D1, D3, D5, D7, D9, D11, D13,
+
D15) appear when CLKOUT is high.
DNC (Pins 21, 23, 25, 27, 33, 35, 37, 39, 41): Do not
connect these pins.
–
+
CLKOUT (Pin 29): Inverted version of CLKOUT .
+
CLKOUT (Pin 30): Data Output Clock. The digital outputs
normally transition at the same time as the falling and ris-
+
+
ing edges of CLKOUT . The phase of CLKOUT can also
be delayed relative to the digital outputs by programming
the mode control registers.
OF(Pin42):Overflow/UnderflowDigitalOutput.OFishigh
when an overflow or underflow has occurred.
216543f
17
LTC2165/LTC2164/LTC2163
FuncTional block DiagraM
V
DD
OV
OF
DD
ANALOG
INPUT
16-BIT
ADC CORE
CORRECTION
LOGIC
S/H
D15
•
•
•
OUTPUT
DRIVERS
D0
V
+
–
REF
1.25V
CLKOUT
REFERENCE
CLKOUT
2.2µF
RANGE
SELECT
OGND
REFH
REFL INTERNAL CLOCK SIGNALS
REF
BUF
SENSE
DIFF
REF
AMP
CLOCK/DUTY
CYCLE
CONTROL
MODE
V
CONTROL
CM
V
/2
DD
REGISTERS
0.1µF
2165 BD
REFH
REFL
GND
2.2µF
+
–
PAR/SER
SCK SDI
SDO
ENC
ENC
CS
0.1µF
0.1µF
Figure 1. Functional Block Diagram
216543f
18
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
CONVERTER OPERATION
the V bypass capacitor should be increased to 2.2µF.
With a single-ended input the harmonic distortion and INL
willdegrade,butthenoiseandDNLwillremainunchanged.
CM
The LTC2165/LTC2164/LTC2163 are low power, 16-bit,
125/105/80Msps A/D converters that are powered by a
single 1.8V supply. The analog inputs should be driven
differentially. The encode input can be driven differentially
or single-ended for lower power consumption. The digital
outputs can be CMOS, double data rate CMOS (to halve
the number of output lines), or double data rate LVDS
(to reduce digital noise in the system). Many additional
features can be chosen by programming the mode control
registers through a serial SPI port.
INPUT DRIVE CIRCUITS
Input filtering
If possible, there should be an RC lowpass filter right at
the analog inputs. This lowpass filter isolates the drive
circuitryfromtheA/Dsample-and-holdswitching,andalso
limits wideband noise from the drive circuitry. Figure 3
shows an example of an input RC filter. The RC component
values should be chosen based on the application’s input
frequency.
ANALOG INPUT
The analog inputs are differential CMOS sample-and-hold
circuits(Figure2).Theinputsshouldbedrivendifferentially
Transformer Coupled Circuits
around a common mode voltage set by the V output
CM
Figure 3 shows the analog input being driven by an RF
transformer with a center-tapped secondary. The center
pin, which is nominally V /2. For the 2V input range,
DD
the inputs should swing from V – 0.5V to V + 0.5V.
CM
CM
tap is biased with V , setting the A/D input at its optimal
CM
Thereshouldbe180°phasedifferencebetweentheinputs.
DC level. At higher input frequencies a transmission line
balun transformer (Figures 4 through 6) has better bal-
ance, resulting in lower A/D distortion.
Single-Ended Input
+
Forapplicationslesssensitivetoharmonicdistortion,theA
IN
inputcanbedrivensingle-endedwitha1V signalcentered
P-P
Amplifier Circuits
–
aroundV .TheA inputshouldbeconnectedtoV and
CM
IN
CM
Figure 7 shows the analog input being driven by a high
speed differential amplifier. The output of the amplifier is
AC coupled to the A/D so the amplifier’s output common
mode voltage can be optimally set to minimize distortion.
LTC2165
V
DD
C
C
SAMPLE
5pF
R
ON
10Ω
10Ω
15Ω
+
–
A
IN
IN
C
1.8pF
PARASITIC
At very high frequencies an RF gain block will often have
lower distortion than a differential amplifier. If the gain
blockissingle-ended,thenatransformercircuit(Figures4
through 6) should convert the signal to differential before
V
DD
SAMPLE
5pF
R
ON
15Ω
A
C
1.8pF
PARASITIC
driving the A/D.
V
50Ω
DD
V
CM
0.1µF
0.1µF
T1
1:1
+
25Ω
1.2V
A
IN
ANALOG
INPUT
LTC2165
10k
0.1µF
25Ω
25Ω
+
–
ENC
12pF
–
25Ω
A
IN
ENC
10k
T1: MA/COM MABAES0060 RESISTORS,
CAPACITORS ARE 0402 PACKAGE SIZE
2165 F03
1.2V
2165 F02
Figure 3. Analog Input Circuit Using a Transformer.
Recommended for Input Frequencies from 5MHz to 70MHz
Figure 2. Equivalent Input Circuit
216543f
19
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
50Ω
V
CM
0.1µF
0.1µF
+
12Ω
A
ANALOG
INPUT
IN
T2
LTC2165
T1
0.1µF
25Ω
25Ω
8.2pF
0.1µF
–
12Ω
A
IN
2165 F04
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 4. Recommended Front End Circuit for
Input Frequencies from 5MHz to 150MHz
50Ω
V
CM
0.1µF
0.1µF
0.1µF
+
A
ANALOG
INPUT
IN
T2
LTC2165
T1
0.1µF
25Ω
25Ω
1.8pF
–
A
IN
2165 F05
T1: MA/COM MABA-007159-000000
T2: COILCRAFT WBC1-1TL
RESISTORS, CAPACITORS ARE 0402 PACKAGE SIZE
Figure 5. Recommended Front End Circuit for
Input Frequencies from 150MHz to 250MHz
50Ω
V
V
CM
CM
HIGH SPEED
DIFFERENTIAL
AMPLIFIER
0.1µF
0.1µF
A
200Ω 200Ω
25Ω
0.1µF
0.1µF
0.1µF
0.1µF
+
–
4.7nH
+
A
IN
IN
ANALOG
INPUT
LTC2165
LTC2165
ANALOG
INPUT
T1
12pF
0.1µF
4.7nH
+
–
25Ω
25Ω
–
25Ω
A
IN
A
IN
12pF
T1: MA/COM ETC1-1-13
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
2165 F06
2165 F07
Figure 6. Recommended Front End Circuit for
Input Frequencies Above 250MHz
Figure 7. Front End Circuit Using a
High Speed Differential Amplifier
216543f
20
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
Reference
LTC2165
REFH
REFL
C3
0.1µF
The LTC2165/LTC2164/LTC2163 has an internal 1.25V
voltage reference. For a 2V input range using the internal
reference, connect SENSE to V . For a 1V input range
C1
2.2µF
DD
REFH
using the internal reference, connect SENSE to ground.
For a 2V input range with an external reference, apply a
1.25V reference voltage to SENSE (Figure 9).
C2
REFL
0.1µF
2165 F08b
CAPACITORS ARE 0402 PACKAGE SIZE
The input range can be adjusted by applying a voltage to
SENSE that is between 0.625V and 1.30V. The input range
Figure 8b. Alternative REFH/REFL Bypass Circuit
will then be 1.6 • V
.
SENSE
Figures 8c and 8d show the recommended circuit board
layout for the REFH/REFL bypass capacitors. Note that in
Figure 8c, every pin of the interdigitated capacitor (C1)
is connected since the pins are not internally connected
in some vendors’ capacitors. In Figure 8d, the REFH and
REFL pins are connected by short jumpers in an internal
layer. To minimize the inductance of these jumpers they
can be placed in a small hole in the GND plane on the
second board layer.
The V , REFH and REFL pins should be bypassed as
REF
shown in Figure 8a. A low inductance 2.2µF interdigitated
capacitor is recommended for the bypass between REFH
and REFL. This type of capacitor is available at a low cost
from multiple suppliers.
At sample rates below 110Msps an interdigitated capaci-
tor is not necessary for good performance and C1 can
be replaced by a standard 2.2µF capacitor between REFH
and REFL. The capacitor should be as close to the pins
as possible (not on the back side of the circuit board).
LTC2165
5Ω
V
REF
1.25V BANDGAP
REFERENCE
1.25V
2.2µF
0.625V
Figure 8c. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8a
RANGE
DETECT
AND
CONTROL
TIE TO V FOR 2V RANGE;
DD
SENSE
TIE TO GND FOR 1V RANGE;
RANGE = 1.6 • V
FOR
SENSE
BUFFER
0.625V < V
< 1.300V
SENSE
INTERNAL ADC
HIGH REFERENCE
REFH
REFL
C2
–
+
–
0.1µF
Figure 8d. Recommended Layout for the REFH/REFL
Bypass Circuit in Figure 8b
+
0.8x
C1
DIFF AMP
REFH
REFL
–
+
+
–
V
C3
0.1µF
REF
2.2µF
INTERNAL ADC
LOW REFERENCE
LTC2165
1.25V
EXTERNAL
REFERENCE
SENSE
1µF
C1: 2.2µF LOW INDUCTANCE
INTERDIGITATED CAPACITOR
TDK CLLE1AX7S0G225M
MURATA LLA219C70G225M
AVX W2L14Z225M
2165 F08
2165 F09
OR EQUIVALENT
Figure 8a. Reference Circuit
Figure 9. Using an External 1.25V Reference
216543f
21
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
Encode Input
0.1µF
0.1µF
+
ENC
LTC2165
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board. There are two modes
of operation for the encode inputs: the differential encode
mode (Figure 10), and the single-ended encode mode
(Figure 11).
T1
50Ω
50Ω
100Ω
–
ENC
0.1µF
2165 F12
T1 = MA/COM ETC1-1-13
RESISTORS AND CAPACITORS
ARE 0402 PACKAGE SIZE
LTC2165
V
DD
Figure 12. Sinusoidal Encode Drive
DIFFERENTIAL
COMPARATOR
V
DD
0.1µF
+
ENC
15k
30k
+
–
ENC
PECL OR
LTC2165
LVDS
CLOCK
ENC
0.1µF
–
ENC
2165 F13
2165 F10
Figure 13. PECL or LVDS Encode Drive
Figure 10. Equivalent Encode Input
Circuit for Differential Encode Mode
+
to ground and ENC is driven with a square wave encode
+
input. ENC can be taken above V (up to 3.6V) so 1.8V
DD
+
LTC2165
+
to3.3VCMOSlogiclevelscanbeused.TheENC threshold
+
is 0.9V. For good jitter performance ENC should have fast
1.8V TO 3.3V
0V
ENC
rise and fall times.
–
30k
ENC
CMOS LOGIC
BUFFER
If the encode signal is turned off or drops below approxi-
mately 500kHz, the A/D enters nap mode.
2165 F11
Figure 11. Equivalent Encode Input
Circuit for Single-Ended Encode Mode.
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50%( 5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintain a constant 50% internal duty cycle. If the encode
signal changes frequency, the duty cycle stabilizer circuit
requires one hundred clock cycles to lock onto the input
clock. The duty cycle stabilizer is enabled by mode control
register A2 (serial programming mode), or by CS (parallel
programming mode).
The differential encode mode is recommended for sinu-
soidal, PECL, or LVDS encode inputs (Figures 12, 13).
The encode inputs are internally biased to 1.2V through
10kΩ equivalent resistance. The encode inputs can be
taken above V (up to 3.6V), and the common mode
DD
range is from 1.1V to 1.6V. In the differential encode
–
mode, ENC should stay at least 200mV above ground to
avoid falsely triggering the single-ended encode mode.
+
–
For good jitter performance ENC and ENC should have
fast rise and fall times.
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. If
the duty cycle stabilizer is disabled, care should be taken
216543f
ThesingleendedencodemodeshouldbeusedwithCMOS
–
encode inputs. To select this mode, ENC is connected
22
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
to make the sampling clock have a 50%( 5%) duty cycle.
The duty cycle stabilizer should not be used below 5Msps.
When using double data rate CMOS at sample rates above
100Msps, the SNR may degrade slightly, about 0.2dB to
0.5dB depending on load capacitance and board layout.
DIGITAL OUTPUTS
Double Data Rate LVDS Mode
Digital Output Modes
In double data rate LVDS mode, two data bits are multi-
plexedandoutputoneachdifferentialoutputpair.Thereare
TheLTC2165/LTC2164/LTC2163canoperateinthreedigital
output modes: full rate CMOS, double data rate CMOS (to
halvethenumberofoutputlines),ordoubledatarateLVDS
(to reduce digital noise in the system.) The output mode
is set by mode control register A3 (serial programming
mode), orbySCK(parallelprogrammingmode). Notethat
double data rate CMOS cannot be selected in the parallel
programming mode.
+
–
+
eight LVDS output pairs (D0_1 /D0_1 through D14_15 /
–
+
–
D14_15 ) for the digital output data. Overflow (OF /OF )
+
–
and the data output clock (CLKOUT /CLKOUT ) each have
an LVDS output pair.
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
Full Rate CMOS Mode
In full rate CMOS mode the data outputs (D0 to D15),
+
overflow (OF), and the data output clocks (CLKOUT ,
The outputs are powered by OV and OGND which are
DD
–
CLKOUT ) have CMOS output levels. The outputs are
isolated from the A/D core power and ground. In LVDS
powered by OV and OGND which are isolated from the
DD
mode, OV must be 1.8V.
DD
A/D core power and ground. OV can range from 1.1V
DD
to 1.9V, allowing 1.2V through 1.8V CMOS logic outputs.
Programmable LVDS Output Current
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF, a digital buffer should be used.
In LVDS mode, the default output driver current is 3.5mA.
Thiscurrentcanbeadjustedbyseriallyprogrammingmode
control register A3. Available current levels are 1.75mA,
2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Double Data Rate CMOS Mode
Optional LVDS Driver Internal Termination
In double data rate CMOS mode, two data bits are mul-
tiplexed and output on each data pin. This reduces the
number of digital lines by eight, simplifying board routing
and reducing the number of input pins needed to receive
thedata.Thedataoutputs(D0_1,D2_3,D4_5,D6_7,D8_9,
D10_11, D12_13, D14_15), overflow (OF), and the data
In most cases using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
beenabledbyseriallyprogrammingmodecontrolregister
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
+
–
output clocks (CLKOUT , CLKOUT ) have CMOS output
levels. TheoutputsarepoweredbyOV andOGNDwhich
DD
are isolated from the A/D core power and ground. OV
DD
can range from 1.1V to 1.9V, allowing 1.2V through 1.8V
CMOS logic outputs.
Overflow Bit
For good performance, the digital outputs should drive
minimal capacitive loads. If the load capacitance is larger
than 10pF, a digital buffer should be used.
The overflow output bit outputs a logic high when the
analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
216543f
23
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
Phase-Shifting the Output Clock
The LTC2165/LTC2164/LTC2163 can also phase-shift the
+
–
CLKOUT /CLKOUT signalsbyseriallyprogrammingmode
control register A2. The output clock can be shifted by 0°,
45°, 90°, or 135°. To use the phase-shifting feature the
clock duty cycle stabilizer must be turned on. Another
In full rate CMOS mode the data output bits normally
+
change at the same time as the falling edge of CLKOUT ,
+
so the rising edge of CLKOUT can be used to latch the
output data. In double data rate CMOS and LVDS modes
the data output bits normally change at the same time as
+
control register bit can invert the polarity of CLKOUT and
–
CLKOUT ,independentlyofthephase-shift.Thecombina-
+
thefallingandrisingedgesofCLKOUT .Toallowadequate
tion of these two features enables phase-shifts of 45° up
to 315° (Figure 14).
+
setup and hold time when latching the data, the CLKOUT
signal may need to be phase-shifted relative to the data
outputbits. MostFPGAshavethisfeature;thisisgenerally
the best place to adjust the timing.
+
ENC
D0-D13, OF
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
0
CLKPHASE1 CLKPHASE0
0°
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
45°
90°
0
0
0
1
1
1
1
135°
180°
225°
270°
315°
+
CLKOUT
2165 F14
Figure 14. Phase-Shifting CLKOUT
Table 1. Output Codes vs Input Voltage
+
–
A
– A
D15 – D0
(OFFSET BINARY)
D15 – D0
(2’S COMPLEMENT)
IN
IN
(2V RANGE)
OF
>1.000000V
+0.999970V
+0.999939V
1
0
0
1111 1111 1111 1111
1111 1111 1111 1111
1111 1111 1111 1110
0111 1111 1111 1111
0111 1111 1111 1111
0111 1111 1111 1110
+0.000030V
+0.000000V
–0.000030V
–0.000061V
0
0
0
0
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0111 1111 1111 1110
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
–0.999939V
–1.000000V
< –1.000000V
0
0
1
0000 0000 0000 0001
0000 0000 0000 0000
0000 0000 0000 0000
1000 0000 0000 0001
1000 0000 0000 0000
1000 0000 0000 0000
216543f
24
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
DATA FORMAT
PC BOARD
FPGA
CLKOUT
Table 1 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
OF
D13/D0
D13
D12
D12/D0
Digital Output Randomizer
LTC2165
•
•
•
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
D2/D0
D1/D0
D2
D1
D0
D0
2165 F16
The digital output is randomized by applying an exclusive-
OR logic operation between the LSB and all other data
output bits. To decode, the reverse operation is applied
—an exclusive-OR operation is applied between the LSB
and all other bits. The LSB, OF and CLKOUT outputs are
not affected. The output randomizer is enabled by serially
programming mode control register A4.
Figure 16. Unrandomizing a Randomized Digital Output Signal
Alternate Bit Polarity
Anotherfeaturethatreducesdigitalfeedbackonthecircuit
board is the alternate bit polarity mode. When this mode is
enabled, all of the odd bits (D1, D3, D5, D7, D9, D11, D13,
D15) are inverted before the output buffers. The even bits
(D0, D2, D4, D6, D8, D10, D12, D14), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
CLKOUT
CLKOUT
OF
OF
When there is a very small signal at the input of the A/D
thatiscenteredaroundmid-scale,thedigitaloutputstoggle
between mostly 1’s and mostly 0’s. This simultaneous
switchingofmostofthebitswillcauselargecurrentsinthe
ground plane. By inverting every other bit, the alternate bit
polarity mode makes half of the bits transition high while
half of the bits transition low. This cancels current flow in
the ground plane, reducing the digital noise.
D15
D15/D0
D14/D0
D14
D2
•
•
•
D2/D0
D1/D0
RANDOMIZER
ON
D1
D0
D0
2165 F15
Figure 15. Functional Equivalent of Digital Output Randomizer
216543f
25
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13, D15.) The
alternate bit polarity mode is independent of the digital
output randomizer—either, both or neither function can
be on at the same time. The alternate bit polarity mode is
enabledbyseriallyprogrammingmodecontrolregisterA4.
InnapmodetheA/Dcoreispowereddownwhiletheinternal
referencecircuitsstayactive,allowingfasterwake-upthan
from sleep mode. Recovering from nap mode requires at
least 100 clock cycles. If the application demands very
accurate DC settling then an additional 50µs should be
allowed so the on-chip references can settle from the
slight temperature shift caused by the change in supply
current as the A/D leaves nap mode.
Digital Output Test Patterns
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D15 to D0) to known values:
Sleep mode and nap mode are enabled by mode control
register A1 (serial programming mode), or by SDI and
SDO (parallel programming mode).
All 1s: all outputs are 1
All 0s: all outputs are 0
DEVICE PROGRAMMING MODES
The operating modes of the LTC2165/LTC2164/LTC2163
can be programmed by either a parallel interface or a
simple serial interface. The serial interface has more flex-
ibility and can program all available modes. The parallel
interface is more limited and can only program some of
the more commonly used modes.
Alternating: outputs change from all 1s to all 0s on
alternating samples.
Checkerboard: outputs change from
10101010101010101 to 01010101010101010
on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes: 2’s
complement, randomizer, alternate bit polarity.
Parallel Programming Mode
To use the parallel programming mode, PAR/SER should
be tied to V . The CS, SCK, SDI and SDO pins are binary
DD
logic inputs that set certain operating modes. These pins
Output Disable
can be tied to V or ground, or driven by 1.8V, 2.5V, or
DD
3.3V CMOS logic. When used as an input, SDO should be
driven through a 1kΩ series resistor. Table 2 shows the
modes set by CS, SCK, SDI and SDO.
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs includ-
ing OF and CLKOUT are disabled. The high-impedance
disabled state is intended for in-circuit testing or long
periods of inactivity—it is too slow to multiplex a data
bus between multiple converters at full speed. When the
outputs are disabled the ADC should be put into either
sleep or nap mode.
Table 2. Parallel Programming Mode Control Bits (PAR/SER = VDD
)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
Digital Output Mode Control Bit
0 = Full Rate CMOS Output Mode
Sleep and Nap Modes
1 = Double Data Rate LVDS Output Mode
(3.5mA LVDS Current, Internal Termination Off)
The A/D may be placed in sleep or nap modes to conserve
power. In sleep mode the entire device is powered down,
resulting in 1mW power consumption. The amount of
time required to recover from sleep mode depends on
SDI/SDO
Power-Down Control Bits
00 = Normal Operation
01 = Not Used
10 = Nap Mode
11 = Sleep Mode (Entire Device Powered Down)
the size of the bypass capacitors on V , REFH, and
REF
REFL. For the suggested values in Figure 8, the A/D will
stabilize after 2ms.
216543f
26
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
Serial Programming Mode
Diagrams). During a read back command the register is
not updated and data on SDI is ignored.
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become a
serialinterfacethatprogramtheA/Dmodecontrolregisters.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
The SDO pin is an open drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required. If
serialdataisonlywrittenandreadbackisnotneeded, then
SDO can be left floating and no pull-up resistor is needed.
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first 16 rising edges of
SCK. Any SCK rising edges after the first 16 are ignored.
The data transfer ends when CS is taken high again.
Table 3 shows a map of the mode control registers.
Software Reset
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset, bit D7 in the
reset register is written with a logic 1. After the reset SPI
write command is complete, bit D7 is automatically set
back to zero.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Table 3. Serial Programming Mode Register Map (PAR/SER = GND)
REGISTER A0: RESET REGISTER (ADDRESS 00h)
D7
D6
X
D5
X
D4
X
D3
X
D2
X
D1
X
D0
X
RESET
Bits 7
RESET
0 = Not Used
Software Reset Bit
1 = Software Reset. All Mode Control Registers are reset to 00h. The ADC is momentarily placed in sleep mode.
This bit is automatically set back to zero at the end of the SPI write command.
The reset register is write only. Data read back from the reset register will be random.
Bits 6-0
Unused, Don’t Care Bits
REGISTER A1: POWER DOWN REGISTER (ADDRESS 01h)
D7
X
D6
X
D5
X
D4
X
D3
X
D2
X
D1
D0
PWROFF1
PWROFF0
Bits 7-2
Unused, Don’t Care Bits
Bits 1-0
PWROFF1: PWROFF0
00 = Normal Operation
01 = Not Used
Power Down Control Bits
10 = Nap Mode
11 = Sleep Mode
216543f
27
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
X
D6
X
D5
X
D4
X
D3
D2
D1
D0
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, Don’t Care Bits
Bit 3
CLKINV
Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1: CLKPHASE0
Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
+
–
01 = CLKOUT /CLKOUT Delayed by 45° (Clock Period × 1/8)
+
–
10 = CLKOUT /CLKOUT Delayed by 90° (Clock Period × 1/4)
+
–
11 = CLKOUT /CLKOUT Delayed by 135° (Clock Period × 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS
Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
D5
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
OUTMODE1
OUTMODE0
Bit 7
Unused, Don’t Care Bit
Bits 6-4
ILVDS2: ILVDS0
LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 3
TERMON
LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2x the current set by ILVDS2:ILVDS0.
216543f
28
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
Bit 2
OUTOFF
Output Disable Bit
0 = Digital outputs are enabled.
1 = Digital outputs are disabled and have high output impedance.
Note: If the digital outputs are disabled the part should also be put in sleep mode or nap mode.
Bits 1-0
OUTMODE1: OUTMODE0
Digital Output Mode Control Bits
00 = Full Rate CMOS Output Mode
01 = Double Data Rate LVDS Output Mode
10 = Double Data Rate CMOS Output Mode
11 = Not Used
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
X
D6
X
D5
D4
D3
D2
D1
D0
OUTTEST2
OUTTEST1
OUTTEST0
ABP
RAND
TWOSCOMP
Bits 7-6
Unused, Don’t Care Bits
Bits 5-3
OUTTEST2: OUTTEST0
Digital Output Test Pattern Bits
000 = Digital Output Test Patterns Off
001 = All Digital Outputs = 0
011 = All Digital Outputs = 1
101 = Checkerboard Output Pattern. OF, D15-D0 alternate between 1 0101 0101 0101 0101 and 0 1010 1010 1010 1010.
111 = Alternating Output Pattern. OF, D15-D0 alternate between 0 0000 0000 0000 0000 and 1 1111 1111 1111 1111.
Note: Other bit combinations are not used.
Bit 2
Bit 1
Bits 0
ABP
Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On. Forces the output format to be Offset Binary.
RAND
Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP
Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
216543f
29
LTC2165/LTC2164/LTC2163
applicaTions inForMaTion
GROUNDING AND BYPASSING
the circuit board as the A/D, and as close to the device
as possible. A low inductance interdigitated capacitor is
suggested for REFH/REFL if the sampling frequency is
greater than 110Msps.
The LTC2165/LTC2164/LTC2163 requires a printed circuit
board with a clean unbroken ground plane in the first
layer beneath the ADC. A multilayer board with an internal
ground plane is recommended. Layout for the printed
circuit board should ensure that digital and analog signal
lines are separated as much as possible. In particular, care
should be taken not to run any digital track alongside an
analog signal track or underneath the ADC.
The analog inputs, encode signals, and digital outputs
should not be routed next to each other. Ground fill and
grounded vias should be used as barriers to isolate these
signals from each other.
HEAT TRANSFER
High quality ceramic bypass capacitors should be used at
the V , OV , V , V , REFH and REFL pins. Bypass
DD
DD CM REF
Most of the heat generated by the LTC2165/LTC2164/
LTC2163 is transferred from the die through the bottom-
sideexposedpadandpackageleadsontotheprintedcircuit
board. For good electrical and thermal performance, the
exposed pad must be soldered to a large grounded pad
on the PC board. This pad should be connected to the
internal ground planes by an array of vias.
capacitors must be located as close to the pins as pos-
sible.Size0402ceramiccapacitorsarerecommended.The
traces connecting the pins and bypass capacitors must
be kept short and should be made as wide as possible.
Of particular importance is the capacitor between REFH
and REFL. This capacitor should be on the same side of
216543f
30
LTC2165/LTC2164/LTC2163
Typical applicaTions
Silkscreen Top
Top Side
216543f
31
LTC2165/LTC2164/LTC2163
Typical applicaTions
Inner Layer 2
Inner Layer 3
216543f
32
LTC2165/LTC2164/LTC2163
Typical applicaTions
Inner Layer 4
Inner Layer 5
Bottom Side
216543f
33
LTC2165/LTC2164/LTC2163
Typical applicaTions
C23
2.2µF
SDO
SENSE
V
DD
C19
0.1µF
48 47 46 45 44 43 42 41 40 39 38 37
SENSE V SDO GND OF DNC D15 D14 D13 D12
C51
0.1µF
V
V
DD DD
REF
36
35
34
33
32
31
30
29
28
27
26
25
1
2
V
D11
CM
+
A
A
D10
D9
A
A
+
–
IN
IN
3
–
IN
IN
4
GND
D8
C15
0.1µF
5
REFH
REFL
REFH
REFL
PAR/SER
GND
OV
DD
–
+
–
+
+
–
6
OGND
0V
DIGITAL
OUTPUTS
DD
LTC2165
CN1
7
+
C37
CLKOUT
+
–
0.1µF
8
–
CLKOUT
C21
0.1µF
9
D7
D6
D5
D4
PAR/SER
10
11
12
GND
V
DD
V
DD
+
–
V
GND ENC ENC CS SCK SDI GND D0 D1 D2 D3
DD
C18
0.1µF
13 14 15
16
17 18
19 20 21
22
23 24
2165 TA02
C28
0.1µF
C32
0.1µF
R51
100Ω
ENCODE
CLOCK
216543f
34
LTC2165/LTC2164/LTC2163
package DescripTion
UK Package
48-Lead Plastic QFN (7mm × 7mm)
(Reference LTC DWG # 05-08-1704 Rev C)
0.70 0.05
5.15 0.05
5.50 REF
6.10 0.05 7.50 0.05
(4 SIDES)
5.15 0.05
PACKAGE OUTLINE
0.25 0.05
0.50 BSC
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.10
R = 0.115
TYP
7.00 0.10
(4 SIDES)
TYP
47 48
0.40 0.10
PIN 1 TOP MARK
(SEE NOTE 6)
1
2
PIN 1
CHAMFER
C = 0.35
5.15 0.10
5.50 REF
(4-SIDES)
5.15 0.10
(UK48) QFN 0406 REV C
0.200 REF
0.25 0.05
0.50 BSC
BOTTOM VIEW—EXPOSED PAD
0.00 – 0.05
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION (WKKD-2)
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
216543f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTC2165/LTC2164/LTC2163
Typical applicaTion
1.8V
V
1.8V
OV
2-Tone FFT, fIN = 70MHz and 69MHz
DD
DD
0
–10
–20
–30
–40
–50
–60
–70
16-BIT
ANALOG
INPUT
S/H
ADC CORE
D15
•
•
•
D0
CMOS, DDR
CMOS OR
DDR LVDS
OUTPUTS
OUTPUT
DRIVERS
–80
–90
–100
–110
–120
125MHz
CLOCK
CLOCK
CONTROL
0
20
30
40
50
60
10
FREQUENCY (MHz)
2165 TA03a
GND
OGND
2165 TA03
relaTeD parTs
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2259-14/LTC2260-14/ 14-Bit, 80Msps/105Msps/125Msps
89mW/106mW/127mW, 73.4dB SNR, 85dB SFDR, DDR LVDS/DDR CMOS/CMOS
Outputs, 6mm × 6mm QFN-40
LTC2261-14
1.8V ADCs, Ultralow Power
LTC2262-14
14-Bit, 150Msps 1.8V ADC, Ultralow
Power
149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,
6mm × 6mm QFN-40
LTC2266-14/LTC2267-14/ 14-Bit, 80Msps/105Msps/125Msps
LTC2268-14 1.8V Dual ADCs, Ultralow Power
216mW/250mW/293mW, 73.4dB SNR, 85dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2266-12/LTC2267-12/ 12-Bit, 80Msps/105Msps/125Msps
216mW/250mW/293mW, 70.5dB SNR, 85dB SFDR, Serial LVDS Outputs,
6mm × 6mm QFN-40
LTC2268-12
1.8V Dual ADCs, Ultralow Power
RF Mixers/Demodulators
LTC5517
40MHz to 900MHz Direct Conversion
Quadrature Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LTC5557
LTC5575
400MHz to 3.8GHz High Linearity
Downconverting Mixer
23.7dBm IIP3 at 2.6GHz, 23.5dBm IIP3 at 3.5GHz, NF = 13.2dB, 3.3V Supply
Operation, Integrated Transformer
800MHz to 2.7GHz Direct Conversion
Quadrature Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated RF
and LO Transformer
Amplifiers/Filters
LTC6412
800MHz, 31dB Range, Analog-Controlled Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise Figure,
Variable Gain Amplifier
4mm × 4mm QFN-24
LTC6605-7/LTC6605-10/ Dual Matched 7MHz/10MHz/14MHz
Dual Matched 2nd Order Lowpass Filters with Differential Drivers,
Pin-Programmable Gain, 6mm × 3mm DFN-22
LTC6605-14
Filters with ADC Drivers
Signal Chain Receivers
LTM9002
14-Bit Dual Channel IF/Baseband
Receiver Subsystem
Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers
216543f
LT 0611 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
●
●
LINEAR TECHNOLOGY CORPORATION 2011
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
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