LTC2150-12_15_技术文档

LTC2152-12/

LTC2151-12/LTC2150-12

Single 12-Bit 250Msps/

210Msps/170Msps ADCs

FEATURES

DESCRIPTION

The LTC^®2152-12/LTC2151-12/LTC2150-12 are a family

of 250Msps/210Msps/170Msps 12-bit A/D converters

designedfordigitizinghighfrequency,widedynamicrange

signals. They are perfect for demanding communications

applications with AC performance that includes 68.5dB

SNR and 90dB spurious free dynamic range (SFDR). The

1.25GHz input bandwidth allows the ADC to undersample

highinputfrequencieswithgoodperformance.Thelatency

is only six clock cycles.

n

68.5dB SNR

n

90dB SFDR

Low Power: 347mW/333mW/306mW Total

Single 1.8V Supply

DDR LVDS Outputs

n

Easy-to-Drive 1.5V Input Range

P-P

n

1.25GHz Full Power Bandwidth S/H

Optional Clock Duty Cycle Stabilizer

Low Power Sleep and Nap Modes

Serial SPI Port for Conﬁguration

Pin-Compatible 14-Bit Versions

40-Lead (6mm × 6mm) QFN Package

DCspecsinclude 0.26LSBINL(typ), 0.16LSBDNL(typ)

and no missing codes over temperature. The transition

noise is 0.54LSB

.

RMS

The digital outputs are double-data rate (DDR) LVDS.

APPLICATIONS

+

–

n

The ENC and ENC inputs can be driven differentially with

asinewave,PECL,LVDS,TTL,orCMOSinputs.Anoptional

clock duty cycle stabilizer allows high performance at full

speed for a wide range of clock duty cycles.

Communications

Cellular Basestations

Software Deﬁned Radios

Medical Imaging

High Deﬁnition Video

Testing and Measurement Instruments

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

LTC2152-12: 32K Point 2-Tone FFT,

f_IN= 71MHz and 69MHz, 250Msps

V

DD

OV

0

–20

DD

D10_11

12-BIT

PIPELINED

ADC

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

DDR

LVDS

S/H

•

–40

D0_1

–60

OGND

CLOCK/DUTY

CYCLE

CONTROL

–80

CLOCK

–100

–120

21521012 TA01a

GND

0

40

60

80

100 120

20

FREQUENCY (MHz)

21521012 TA01b

21521012fa

1

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION

(Notes 1, 2)

TOP VIEW

Supply Voltage

V , OV ................................................ –0.3V to 2V

DD

Analog Input Voltage

+

–

A

, A , PAR/SER,

40 39 38 37 36 35 34 33 32 31

IN

SENSE (Note 3)........................ –0.3V to (V + 0.2V)

V

1

2

3

4

5

6

7

8

9

30

29

28

OV

DD

+

DD

D6_7

Digital Input Voltage

DD

–

+

–

GND

+

ENC , ENC (Note 3)................ –0.3V to (V + 0.3V)

DD

+

–

A

27 CLKOUT

IN

CS, SDI, SCK (Note 4)........................... –0.3V to 3.9V

–

A

26 CLKOUT

+

IN

GND

41

SDO (Note 4)............................................. –0.3V to 3.9V

GND

SENSE

VREF

25

D4_5

Digital Output Voltage................ –0.3V to (OV + 0.3V)

–

+

–

DD

24 D4_5

23

Operating Temperature Range

D2_3

22 D2_3

LTC2152C, LTC2151C, LTC2150C............. 0°C to 70°C

LTC2152I, LTC2151I, LTC2150I ............–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

VCM

GND 10

21

OGND

11 12 13 14 15 16 17 18 19 20

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

T

JMAX

= 150°C, θ = 33°C/W

JA

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC2152CUJ-12#PBF

LTC2152IUJ-12#PBF

LTC2151CUJ-12#PBF

LTC2151IUJ-12#PBF

LTC2150CUJ-12#PBF

LTC2150IUJ-12#PBF

TAPE AND REEL

LTC2152CUJ-12#TRPBF LTC2152UJ-12

LTC2152IUJ-12#TRPBF LTC2152UJ-12

LTC2151CUJ-12#TRPBF LTC2151UJ-12

LTC2151IUJ-12#TRPBF LTC2151UJ-12

LTC2150CUJ-12#TRPBF LTC2150UJ-12

LTC2150IUJ-12#TRPBF LTC2150UJ-12

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

40-Lead (6mm × 6mm) Plastic QFN

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping

container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

21521012fa

2

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

CONVERTER CHARACTERISTICS _{The l denotes the specifications which apply over the full operating}

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

LTC2152-12

TYP

LTC2151-12

TYP

LTC2150-12

PARAMETER

CONDITIONS

MIN

12

MAX

MIN

12

MAX

MIN

TYP MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

12

–1.2

–0.6

–13

–4

Differential Analog Input (Note 6)

Differential Analog Input

(Note 7)

–1.2

–0.6

–13

–4

0.26

0.16

5

1.2

0.6

13

3

–1.2

–0.6

–13

–4

0.30

0.16

5

1.2

0.6

13

3

0.30 1.2

0.16 0.6

LSB

5

1

13

3

mV

Gain Error

External Reference

1

%FS

µV/°C

Offset Drift

20

Full-Scale Drift

Internal Reference

External Reference

30

10

30

10

30

10

ppm/°C

Transition Noise

0.54

LSB

RMS

ANALOG INPUT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

1.7V < V < 1.9V

MIN

TYP

MAX

UNITS

+

–

l

V

Analog Input Range (A – A

)

1.5

V

P-P

IN

DD

+

–

Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)

V

– 20mV

V

CM

V + 20mV

CM

V

IN(CM)

SENSE

IN

CM

External Reference Mode

1.200

–1

1.250

1.300

V

µA

ns

+

–

I

t

Analog Input Leakage Current

SENSE Input Leakage Current

0 < A , A < V , No Encode

1

IN1

IN

DD

1.2V < SENSE < 1.3V

0 < PAR/SER < V

–1

IN2

PAR/SER Input Leakage Current

–1

IN3

DD

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Jitter

Analog Input Common Mode Rejection Ratio

Full-Power Bandwidth

1

AP

0.15

75

ps

RMS

JITTER

CMRR

BW-3B

dB

1250

MHz

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. A_IN= –1dBFS. (Note 5)

LTC2152-12

TYP

LTC2151-12

TYP

LTC2150-12

TYP MAX UNITS

SYMBOL

PARAMETER

CONDITIONS

MIN

67.1

72

MAX

MIN

67.1

74

MAX

MIN

67.3

76

SNR

Signal-to-Noise Ratio

15MHz Input

70MHz Input

140MHz Input

68.5

68.4

68.0

68.5

68.3

67.9

68.5

68.3

67.8

dBFS

l

SFDR

Spurious Free Dynamic Range 15MHz Input

2nd or 3rd Harmonic

90.6

88

80

90.1

89

81

90

88

80

dBFS

70MHz Input

140MHz Input

Spurious Free Dynamic Range 15MHz Input

4th Harmonic or Higher

98

95

85

98

95

85

98

95

84

dBFS

70MHz Input

140MHz Input

81

82

83

S/(N+D)

Signal-to-Noise Plus

Distortion Ratio

15MHz Input

70MHz Input

140MHz Input

68.5

68.4

67.7

68.4

68.3

67.7

68.4

68.3

67.7

dBFS

66.5

66.6

66.7

Crosstalk

Crosstalk Between Channels

Up to 315MHz Input

–95

dB

21521012fa

3

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

PARAMETER

CONDITIONS

= 0

MIN

TYP

MAX

UNITS

V

CM

Output Voltage

I

0.439 •

– 18mV

0.439 •

V

OUT

V

DD

V

+ 18mV

DD

V

Output Temperature Drift

Output Resistance

Output Voltage

37

4

ppm/°C

Ω

CM

–1mA < I

< 1mA

CM

OUT

I

= 0

1.225

1.250

30

1.275

V

REF

OUT

Output Temperature Drift

Output Resistance

Line Regulation

ppm/°C

Ω

–400µA < I

< 1mA

7

OUT

1.7V < V < 1.9V

0.6

mV/V

DD

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

LTC2152-12

TYP

LTC2151-12

TYP

LTC2150-12

MIN TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

(Note 9)

MIN

1.7

MAX

1.9

MIN

1.7

MAX

1.9

l

V

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Digital Supply Current

1.8

1.7

1.8

1.9

V

DD

OV

LVDS Mode (Note 9)

1.7

1.9

1.7

1.9

DD

I

166

185

158

175

145

159

mA

VDD

OVDD

1.75mA LVDS Mode

3.5mA LVDS Mode

27

45

32

50

27

44

31

50

25

43

30

48

mA

l

P

DISS

Power Dissipation

1.75mA LVDS Mode

3.5mA LVDS Mode

347

380

391

423

333

364

371

405

306

338

340

373

mW

P

Nap Mode Power

Sleep Mode Power

Clocked at f

105

<2

99

<2

93

<2

mW

NAP

S(MAX)

SLEEP

DIGITAL INPUTS AND OUTPUTS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

ENCODE INPUTS (ENC , ENC )

l

V

Differential Input Voltage

(Note 8)

0.2

1

1.9

V

ID

Common Mode Input Voltage

Internally Set

Externally Set (Note 8)

1.2

V

ICM

l

1.1

0.2

1.5

1.9

+

–

V

IN

Input Voltage Range

Input Resistance

Input Capacitance

ENC , ENC to GND

(See Figure 2)

(Note 8)

V

kΩ

pF

R

10

2

IN

C

DIGITAL INPUTS (CS, SDI, SCK)

l

V

High Level Input Voltage

Low Level Input Voltage

Input Current

V

= 1.8V

1.3

V

IH

IL

DD

IN

= 1.8V

0.6

10

I

IN

= 0V to 1.8V

–10

µA

pF

C

IN

Input Capacitance

(Note 8)

3

200

4

SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)

R

Logic Low Output Resistance to GND

Logic High Output Leakage Current

Output Capacitance

V

= 1.8V, SDO = 0V

DD

Ω

µA

OL

l

I

SDO = 0V to 3.6V

(Note 8)

–10

10

OH

C

OUT

pF

21521012fa

4

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

DIGITAL INPUTS AND OUTPUTS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

DIGITAL DATA OUTPUTS

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Differential Output Voltage

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

125

350

175

454

250

mV

OD

l

V

Common Mode Output Voltage

On-Chip Termination Resistance

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

100

1.375

V

Ω

OS

R

Termination Enabled, OV = 1.8V

TERM

DD

TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

LTC2152-12

TYP

LTC2151-12

TYP

LTC2150-12

MIN TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

l

f

S

t

L

Sampling Frequency

(Note 9)

10

250

10

210

10

170

MHz

l

ENC Low Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

1.9

1.5

2

50

2.26

1.5

2.38

50

2.79

1.5

2.94

50

ns

l

t

H

ENC High Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

1.9

1.5

2

50

2.26

1.5

2.38

50

2.79

1.5

2.94

50

ns

DIGITAL DATA OUTPUTS

SYMBOL PARAMETER

LTC215X-12

TYP

CONDITIONS

C = 5pF

MIN

1.7

1.3

0.3

6

MAX

UNITS

ns

l

t

ENC to Data Delay

ENC to CLKOUT Delay

DATA to CLKOUT Skew

Pipeline Latency

2

2.3

2

D

L

C = 5pF

L

1.6

0.4

ns

C

t – t

D C

0.55

6

ns

SKEW

Cycles

SPI Port Timing (Note 8)

t

SCK Period

Write Mode, C

= 20pF

SDO

40

ns

SCK

Readback Mode R

= 2k, C

= 20pF

250

PULLUP

SDO

l

t

CS to SCK Set-Up Time

SCK to CS Hold Time

SDI Set-Up Time

5

ns

S

H

DS

DH

DO

SDI Hold Time

SCK Falling to SDO Valid

Readback Mode R

125

PULLUP

SDO

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: V = OV = 1.8V, f

= 250MHz (LTC2152),

DD

SAMPLE

210MHz (LTC2151), or 170MHz (LTC2150), LVDS outputs, differential

+

–

ENC /ENC = 2V sine wave, input range = 1.5V with differential

P-P

drive, unless otherwise noted.

Note 2: All voltage values are with respect to GND with GND and OGND

Note 6: Integral nonlinearity is defined as the deviation of a code from a

best fit straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 7: Offset error is the offset voltage measured from –0.5LSB when the

output code flickers between 0000 0000 0000 and 1111 1111 1111 in 2’s

complement output mode.

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V , they

DD

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above V without latchup.

DD

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above V

DD

Note 8: Guaranteed by design, not subject to test.

Note 9: Recommended operating conditions.

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

21521012fa

5

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2152-12: Integral Nonlinearity

(INL)

LTC2152-12: Differential

Nonlinearity (DNL)

LTC2152-12: 32K Point FFT,

f_IN= 15MHz, –1dBFS, 250Msps

0

–20

2.0

1.5

0.50

0.25

0

1.0

–40

0.5

0

–60

–0.5

–1.0

–1.5

–2.0

–80

–0.25

–0.50

–100

–120

0

40

60

80

100 120

0

4095

20

0

4095

FREQUENCY (MHz)

OUTPUT CODE

21521012 G01

21521012 G02

21521012 G03

LTC2152-12: 32K Point FFT,

f_IN= 70MHz, –1dBFS, 250Msps

LTC2152-12: 32K Point FFT,

f_IN= 122MHz, –1dBFS, 250Msps

LTC2152-12: 32K Point FFT,

f_IN= 171MHz, –1dBFS, 250Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

40

60

80

100 120

0

40

60

80

100 120

0

40

60

80

100 120

20

FREQUENCY (MHz)

21521012 G04

21521012 G05

21521012 G06

LTC2152-12: 32K Point FFT,

f_IN= 380MHz, –1dBFS, 250Msps

LTC2152-12: 32K Point FFT,

f_IN= 420MHz, –1dBFS, 250Msps

f

_IN= 229MHz, –1dBFS, 250Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

40

60

80

100 120

21521012 G09

0

40

60

80

100 120

0

40

60

80

100 120

20

FREQUENCY (MHz)

21521012 G07

21521012 G08

21521012fa

6

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2152-12: 32K Point FFT,

f_IN= 907MHz, –1dBFS, 250Msps

LTC2152-12: 32K Point 2-Tone FFT,

f_IN= 71MHz and 69MHz, 250Msps

LTC2152-12: 32K Point FFT,

f_IN= 567MHz, –1dBFS, 250Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

40

60

80

100 120

0

40

60

80

100 120

0

40

60

80

100 120

20

FREQUENCY (MHz)

215210 G10

21521012 G11

21521012 G12

LTC2152-12: Shorted Input

Histogram

LTC2152-12: I_OVDDvs Sample Rate,

15MHz Sine Wave Input, –1dBFS

LTC2152-12: I_VDDvs Sample Rate,

15MHz Sine Wave Input, –1dBFS

20000

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

50

45

40

35

30

25

20

15

170

160

150

140

130

120

110

LVDS CURRENT 3.5mA

LVDS CURRENT 1.75mA

2048

2052

2056

0

50

100

150

200

250

0

50

100

150

200

250

OUTPUT CODE

SAMPLE RATE (Msps)

21521012 G13

21521012 G14

21521012 G15

LTC2152-12: SFDR vs Input

Frequency, –1dBFS, 1.5V Range,

250Msps

LTC2152-12: SNR vs Input Level,

f_IN= 70MHz, 1.5V Range, 250Msps

LTC2152-12: SFDR vs Input Level,

f_IN= 70MHz, 1.5V Range, 250Msps

90

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

120

100

80

60

40

20

0

dBFS

dBc

0

100 200 300 400 500 600 700 800 9001000

INPUT FREQUENCY (MHz)

21521012 G18

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–70

–90 –80 –70 –60 –50 –40 –30 –20 –10

AMPLITUDE (dBFS)

0

21521012 G17

21521012 G16

21521012fa

7

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2152-12: SNR vs Input

Frequency, –1dBFS, 1.5V Range,

250Msps

LTC2152-12: Frequency Response

75

70

65

60

55

50

45

40

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

0

100 200 300 400 500 600 700 800 9001000

INPUT FREQUENCY (MHz)

100

1000

INPUT FREQUENCY (MHz)

21521012 G19

21521012 G20

LTC2151-12: Integral Nonlinearity

INL

LTC2151-12: Differential Nonlinearity

DNL

LTC2151-12: 32K Point FFT,

f_IN= 15MHz, –1dBFS, 210Msps

0.50

0.25

0

2.0

1.5

0

–20

1.0

–40

0.5

0

–60

–0.5

–1.0

–1.5

–2.0

–80

–0.25

–0.50

–100

–120

0

4095

0

40

60

80

100

20

OUTPUT CODE

FREQUENCY (MHz)

21521012 G22

21521012 G21

21521012 G23

LTC2151-12: 32K Point FFT,

f_IN= 171MHz, –1dBFS, 210Msps

LTC2151-12: 32K Point FFT,

f

_IN= 71MHz, –1dBFS, 210Msps

f

_IN= 101MHz, –1dBFS, 210Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

40

60

80

100

0

40

60

80

100

0

40

60

80

100

20

FREQUENCY (MHz)

21521012 G24

21521012 G25

21521012 G26

21521012fa

8

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2151-12: 32K Point FFT,

f_IN= 227MHz, –1dBFS, 210Msps

LTC2151-12: 32K Point FFT,

f_IN= 379MHz, –1dBFS, 210Msps

LTC2151-12: 32K Point FFT,

f

_IN= 417MHz, –1dBFS, 210Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

40

60

80

100

20

0

40

60

80

100

0

40

60

80

100

20

FREQUENCY (MHz)

21521012 G28

21521012 G27

21521012 G29

LTC2151-12: 32K Point FFT,

f_IN= 567MHz, –1dBFS, 210Msps

LTC2151-12: 32K Point FFT,

f_IN= 907MHz, –1dBFS, 210Msps

LTC2151-12: 32K Point 2-Tone FFT,

_IN= 71MHz and 69MHz, 210Msps

f

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

40

60

80

100

0

40

60

80

100

0

40

60

80

100

20

FREQUENCY (MHz)

21521012 G30

21521012 G31

21521012 G32

LTC2151-12: I_OVDDvs Sample Rate,

15MHz Sine Wave Input, –1dBFS

LTC2151-12: I_VDDvs Sample Rate,

15MHz Sine Wave Input, –1dBFS

LTC2151-12: Shorted Input

Histogram

20000

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

50

45

40

35

30

25

20

15

160

150

140

130

120

110

LVDS CURRENT 3.5mA

LVDS CURRENT 1.75mA

2044

2048

2052

2056

0

42

84

126

168

210

0

42

84

128

168

210

OUTPUT CODE

SAMPLE RATE (Msps)

21521012 G33

21521012 G35

21521012 G34

21521012fa

9

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LTC2152-12/

LTC2151-12/LTC2150-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2151-12: SFDR vs Input

Level, –1dBFS, 1.5V Range,

210Msps

LTC2151-12: SFDR vs Input Level,

f_IN= 70MHz, 1.5V Range, 210Msps

LTC2151-12: SNR vs Input Level,

f

_IN= 70MHz, 1.5V Range, 210Msps

90

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

120

100

80

60

40

20

0

dBFS

dBc

0

100 200 300 400 500 600 700 800 9001000

INPUT FREQUENCY (MHz)

21521012 G38

–80 –70 –60 –50 –40 –30 –20 –10

AMPLITUDE (dBFS)

0

10

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–70

21521012 G37

21521012 G36

LTC2151-12: SNR vs Input Level,

–1dBFS, 1.5V Range, 210Msps

LTC2151-12: Frequency Response

75

70

65

60

55

50

45

40

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

0

100 200 300 400 500 600 700 800 9001000

INPUT FREQUENCY (MHz)

21521012 G39

100

1000

INPUT FREQUENCY (MHz)

21521012 G40

LTC2150-12: Differential

Nonlinearity DNL

LTC2150-12: 32K Point FFT,

f_IN= 15MHz, –1dBFS, 170Msps

LTC2150-12: Integral Nonlinearity INL

2.0

1.5

0

–20

0.50

0.25

0

1.0

–40

0.5

0

–60

–0.5

–1.0

–1.5

–2.0

–80

–0.25

–100

–120

–0.50

0

30 40 50 60 70 80

FREQUENCY (MHz)

10 20

0

4095

0

4095

OUTPUT CODE

21521012 G41

21521012 G42

21521012 G43

21521012fa

10

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2150-12: 32K Point FFT,

f_IN= 70MHz, –1dBFS, 170Msps

LTC2150-12: 32K Point FFT,

f_IN= 121MHz, –1dBFS, 170Msps

LTC2150-12: 32K Point FFT,

f

_IN= 176MHz, –1dBFS, 170Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

30 40 50 60 70 80

FREQUENCY (MHz)

0

30 40 50 60 70 80

FREQUENCY (MHz)

0

30 40 50 60 70 80

FREQUENCY (MHz)

10 20

21521012 G44

21521012 G45

21521012 G46

LTC2150-12: 32K Point FFT,

f_IN= 225MHz, –1dBFS, 170Msps

LTC2150-12: 32K Point FFT,

f_IN= 380MHz, –1dBFS, 170Msps

LTC2150-12: 32K Point FFT,

_IN= 420MHz, –1dBFS, 170Msps

f

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

30 40 50 60 70 80

FREQUENCY (MHz)

0

30 40 50 60 70 80

FREQUENCY (MHz)

10 20

0

30 40 50 60 70 80

FREQUENCY (MHz)

10 20

21521012 G47

21521012 G49

21521012 G48

LTC2150-12: 32K Point FFT,

f_IN= 907MHz, –1dBFS, 170Msps

LTC2150-12: 32K Point 2-Tone FFT,

f_IN= 71MHz and 69MHz, 170Msps

f

_IN= 567MHz, –1dBFS, 170Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

30 40 50 60 70 80

FREQUENCY (MHz)

0

30 40 50 60 70 80

FREQUENCY (MHz)

0

40 50 60 70 80

10 20 30

FREQUENCY (MHz)

10 20

21521012 G50

21521012 G51

21521012 G52

21521012fa

11

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2150-12: I_OVDDvs Sample

Rate, 15MHz Sine Wave Input,

–1dBFS

LTC2150-12: Shorted Input

Histogram

LTC2150-12: I_VDDvs Sample Rate,

15MHz Sine Wave Input, –1dBFS

60

55

50

45

40

35

30

25

20

140

135

130

125

120

115

110

105

100

20000

18000

16000

14000

12000

10000

8000

6000

4000

2000

0

LVDS CURRENT 3.5mA

LVDS CURRENT 1.75mA

15

2056

2060

2064

0

34

68

102

136

170

0

136

170

34

68

102

OUTPUT CODE

SAMPLE RATE (Msps)

21521012 G53

21521012 G55

21521012 G54

LTC2150-12: SFDR vs Input

Frequency, –1dBFS, 1.5V Range,

170Msps

LTC2150-12: SFDR vs Input Level,

LTC2150-12: SNR vs Input Level,

f_IN= 70MHz, 1.5V Range, 170Msps

f

_IN= 70MHz, 1.5V Range, 170Msps

90

80

70

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

120

100

80

60

40

20

0

dBFS

dBc

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

100 200 300 400 500 600 700 800 9001000

INPUT FREQUENCY (MHz)

21521012 G58

–70

–80 –70 –60 –50 –40 –30 –20 –10

AMPLITUDE (dBFS)

0

10

21521012 G57

21521012 G56

LTC2150-12: SNR vs Input

Frequency, –1dBFS, 1.5V Range,

170Msps

LTC2150-12: Frequency Response

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

75

70

65

60

55

50

45

40

–5.0

100

1000

0

100 200 300 400 500 600 700 800 9001000

INPUT FREQUENCY (MHz)

21521012 G59

INPUT FREQUENCY (MHz)

21521012 G60

21521012fa

12

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

PIN FUNCTIONS

SDO (Pin 36): In serial programming mode, (PAR/SER =

0V), SDO is the optional serial interface data output. Data

on SDO is read back from the mode control registers and

can be latched on the falling edge of SCK. SDO is an open-

drain N-channel MOSFET output that requires an external

2k pull-up resistor from 1.8V to 3.3V. If readback from the

mode control registers is not needed, the pull-up resistor

is not necessary and SDO can be left unconnected.

V

(Pins 1, 2): 1.8V Analog Power Supply. Bypass to

DD

ground with 0.1µF ceramic capacitor. Pins 1, 2 can share

a bypass capacitor.

GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC

Power Ground. The exposed pad must be soldered to the

PCB ground.

+

A

IN

A

IN

(Pin 4): Positive Differential Analog Input.

(Pin 5): Negative Differential Analog Input.

–

SDI (Pin 37): In serial programming mode, (PAR/SER

= 0V), SDI is the serial interface data input. Data on SDI

is clocked into the mode control registers on the rising

edge of SCK. In parallel programming mode (PAR/SER =

SENSE (Pin 7): Reference Programming Pin. Connecting

SENSE to V selects the internal reference and a 0.75V

DD

input range. An external reference between 1.2V and 1.3V

V ), SDI selects 3.5mA or 1.75mA LVDS output current

DD

applied to SENSE selects an input range of 0.6 • V

.

SENSE

(see Table 2).

V

(Pin 8): Reference Voltage Output. Bypass to ground

REF

SCK (Pin 38): In serial programming mode, (PAR/SER

with a 2.2µF ceramic capacitor. Nominally 1.25V.

= 0V), SCK is the serial interface clock input. In parallel

V

(Pin 9): Common Mode Bias Output; nominally equal

CM

programming mode (PAR/SER = V ), SCK controls the

DD

to 0.439 • V . V should be used to bias the common

DD CM

sleep mode (see Table 2).

mode of the analog inputs. Bypass to ground with a 0.1µF

ceramic capacitor.

CS (Pin 39): In serial programming mode, (PAR/SER =

0V), CS is the serial interface chip select input. When CS

is low, SCK is enabled for shifting data on SDI into the

mode control registers. In parallel programming mode

+

ENC (Pin 11): Encode Input. Conversion starts on the

rising edge.

–

(PAR/SER = V ), CS controls the clock duty cycle stabi-

ENC (Pin 12): Encode Complement Input. Conversion

DD

lizer (see Table 2).

starts on the falling edge.

PAR/SER (Pin 40): Programming Mode Selection Pin.

Connect to ground to enable the serial programming

mode. CS, SCK, SDI and SDO become a serial interface

NC (Pins 16, 17): No Connection.

OV (Pins 20, 30): 1.8V Output Driver Supply. Bypass

DD

eachpintogroundwithseparate0.1µFceramiccapacitors.

that control the A/D operating modes. Connect to V to

DD

enabletheparallelprogrammingmodewhereCS,SCKand

SDI become parallel logic inputs that control a reduced

set of the A/D operating modes. PAR/SER should be con-

OGND (Pin 21): LVDS Driver Ground.

nected directly to ground or the V of the part and not

DD

be driven by a logic signal.

21521012fa

13

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LTC2152-12/

LTC2151-12/LTC2150-12

PIN FUNCTIONS

LVDS Outputs (DDR LVDS)

–

+

CLKOUT /CLKOUT (Pins 26/27): Data Output Clock.

The digital outputs normally transition at the same time

The following pins are differential LVDS outputs. The

output current level is programmable. There is an optional

internal 100Ω termination resistor between the pins of

each LVDS output pair.

+

as the falling and rising edges of CLKOUT . The phase of

+

CLKOUT canalsobedelayedrelativetothedigitaloutputs

by programming the mode control registers.

–

+

–

+

–

+

OF /OF (Pins 14/15): Over/Underflow Digital Output.

D

0_1

/D

0_1

toD

/D

10_11

(Pins18/19,22/23,24/25,

10_11

OF is high when an overflow or underflow has occurred.

28/29, 31/32, 33/34): Double-Data Rate Digital Outputs.

Two data bits are multiplexed onto each differential output

pair. The even data bits (D0, D2, D4, D6, D8, D10) appear

+

This underflow is valid only when CLKOUT is low. In the

second half clock cycle, the overflow is set to 0.

+

when CLKOUT is low. The odd data bits (D1, D3, D5, D7,

+

D9, D11) appear when CLKOUT is high.

FUNCTIONAL BLOCK DIAGRAM

V

DD

OV

DD

D10_11

12-BIT

PIPELINED

ADC

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

DDR

LVDS

S/H

•

D0_1

V

CM

V

CM

0.1µF

OGND

BUFFER

GND

CLOCK

CS

CLOCK/DUTY

CYCLE CONTROL

SCK

SDI

SPI

SDO

PAR/SER

V

REF

2.2µF

1.25V

REFERENCE

GND

RANGE

SELECT

SENSE

21521012 F01

Figure 1. Functional Block Diagram

21521012fa

14

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LTC2152-12/

LTC2151-12/LTC2150-12

TIMING DIAGRAMS

Double-Data Rate Output Timing, All Outputs Are Differential LVDS

t

AP

N

N + 3

N + 2

N + 1

t

L

H

–

+

ENC

+

–

CLKOUT

t

C

–

+

D0_1

D0

N-6

D1

N-6

D0

N-5

D1

D0

D1

N-4

N-5

N-4

t

D

–

+

D10_11

D10

D11

D10

D11

D10

D11

N-4

N-6

N-5

N-4

–

+

OF

N-6

INVALID OF

INVALID

N-5

21521012 TD01

t

SKEW

SPI Port Timing (Readback Mode)

t

S

t

DS

t

DH

t

H

SCK

CS

SCK

t

DO

SDI

A6

A5

A4

A3

A2

A1

A0

XX

D6

XX

D5

XX

D4

XX

D3

XX

D2

XX

D1

XX

R/W

SDO

D7

D0

HIGH IMPEDANCE

SPI Port Timing (Write Mode)

CS

SCK

SDI

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

SDO

21521012 TD02

21521012fa

15

HIGH IMPEDANCE

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

CONVERTER OPERATION

INPUT DRIVE CIRCUITS

Input Filtering

The LTC2152-12/LTC2151-12/LTC2150-12 are 12-

bit 250Msps/210Msps/170Msps A/D converters that

are powered by a single 1.8V supply. The analog

inputs must be driven differentially. The encode in-

puts should be driven differentially for optimal per-

formance. The digital outputs are double-data rate

LVDS. Additional features can be chosen by programming

the mode control registers through a serial SPI port.

If possible, there should be an RC lowpass filter right at

the analog inputs. This lowpass filter isolates the drive

circuitryfromtheA/Dsample-and-holdswitching,andalso

limits wide band noise from the drive circuitry. Figure 3

shows an example of an input RC filter. The RC compo-

nent values should be chosen based on the application’s

input frequency.

ANALOG INPUT

Transformer-Coupled Circuits

The analog input is a differential CMOS sample-and-hold

circuit (Figure 2). It must be driven differentially around a

Figure 3 shows the analog input being driven by an RF

transformer with the common mode supplied through a

common mode voltage set by the V output pin, which

CM

pair of resistors via the V pin.

CM

is nominally 0.439 • V . The inputs should swing from

DD

At higher input frequencies a transmission line balun

transformer(Figures4and5)hasbetterbalance,resulting

in lower A/D distortion.

V

– 0.375V to V + 0.375V. There should be a 180°

phase difference between the inputs.

CM

LTC2152-12

V

DD

10Ω

R

ON

V

CM

2pF

20Ω

5Ω

0.1µF

10pF

+

–

A

IN

LTC2152-12

+

0.1µF

T1

1:1

2pF

4.7Ω

IN

V

A

DD

IN

R

20Ω

25Ω

ON

A

0.1µF

4.7Ω

–

V

DD

T1: MACOM ETC1-1T

21521012 F03

1.2V

Figure 3. Analog Input Circuit Using a Transformer.

Recommended for Input Frequencies from 5MHz to 70MHz

10k

+

–

ENC

10Ω

V

CM

ENC

0.1µF

LTC2152-12

0.1µF

T2

WBC1-1L

4.7Ω

T1

+

IN

A

IN

MABA

007159-

000000

45Ω

21521012 F02

100Ω

0.1µF

4.7Ω

Figure 2. Equivalent Input Circuit for Differential Input Clock

–

A

IN

21521012 F04

Figure 4. Recommended Front-End Circuit for

Input Frequencies from 15MHz to 150MHz

21521012fa

16

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

Amplifier Circuits

V

CM

Figure 6 shows the analog input being driven by a high

speed differential amplifier. The output of the amplifier is

AC-coupled to the A/D so the amplifier’s output common

mode voltage can be optimally set to minimize distortion.

0.1µF

10Ω

4.7Ω

LTC2152-12

0.1µF

MABA

007159-

000000

+

IN

A

IN

45Ω

T1

100Ω

At very high frequencies an RF gain block will often have

lower distortion than a differential amplifier. If the gain

block is single-ended, then a transformer circuit (Figures

3 and 5) should convert the signal to differential before

driving the A/D. The A/D cannot be driven single-ended.

0.1µF

4.7Ω

0.1µF

–

A

IN

21521012 F05

T1: MACOM ETC1-1-13

Figure 5. Recommended Front-End Circuit for

Input Frequencies from 150MHz Up to 900MHz

Reference

TheLTC2152-12/LTC2151-12/LTC2150-12hasaninternal

1.25V voltage reference. For a 1.5V input range with in-

ternal reference, connect SENSE to V . For a 1.5V input

DD

range with an external reference, apply a 1.25V reference

voltage to SENSE (Figure 7).

V

CM

0.1µF

50Ω

LTC2152-12

3pF

Encode Input

0.1µF

4.7Ω

+

INPUT

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board.

A

IN

3pF

0.1µF

4.7Ω

–

IN

21521012 F06

The encode inputs are internally biased to 1.2V through

10k equivalent resistance (Figure 8). If the common mode

of the driver is within 1.1V to 1.5V, it is possible to drive

Figure 6. Front-End Circuit Using a High

Speed Differential Amplifier

LTC2152-12

V

DD

5Ω

1.25V

2.2µF

1.2V

V

REF

10k

+

–

ENC

SCALER/

BUFFER

ADC

REFERENCE

SENSE

DETECTOR

ENC

21521012 F07

21521012 F08

Figure 8. Equivalent Encode Input Circuit

Figure 7. Reference Circuit

21521012fa

17

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LTC2152-12/

LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

the encode inputs directly. Otherwise, a transformer or

coupling capacitors are needed (Figures 9 and 10). The

maximum (peak) voltage of the input signal should never

Forapplicationswherethesamplerateneedstobechanged

quickly, the clock duty cycle stabilizer can be disabled. If

the duty cycle stabilizer is disabled, care should be taken

to make the sampling clock have a 50% ( 5%) duty cycle.

exceed V + 0.1V or go below –0.1V.

DD

Clock Duty Cycle Stabilizer

DIGITAL OUTPUTS

For good performance the encode signal should have a

50% ( 5%) duty cycle. If the optional clock duty cycle

stabilizer circuit is enabled, the encode duty cycle can

vary from 30% to 70% and the duty cycle stabilizer will

maintain a constant 50% internal duty cycle. If the encode

signal changes frequency or is turned off, the duty cycle

stabilizer circuit requires one hundred clock cycles to lock

onto the input clock. The duty cycle stabilizer is enabled

via SPI Register A2 (see SPI Control Register) or by CS

in parallel programming mode.

Thedigitaloutputsaredouble-datarateLVDSsignals.Two

data bits are multiplexed and output on each differential

+

output pair. There are six LVDS output pairs (D0_1 /

–

+

–

D0_1 through D10_11 /D10_11 ). Overflow (OF /OF )

–

and the data output clock (CLKOUT /CLKOUT ) each have

an LVDS output pair.

By default the outputs are standard LVDS levels: 3.5mA

outputcurrentanda1.25Voutputcommonmodevoltage.

LTC2152-12

V

DD

1.2V

10k 10k

0.1µF

50Ω

T1

100Ω

0.1µF

21521012 F09

T1: MACOM ETC1-1-13

Figure 9. Sinusoidal Encode Drive

LTC2152-12

V

DD

1.2V

10k 10k

0.1µF

+

–

ENC

PECL OR

LVDS INPUT

100Ω

0.1µF

ENC

21521012 F10

Figure 10. PECL or LVDS Encode Drive

21521012fa

18

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LTC2152-12/

LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

An external 100Ω differential termination resistor is re-

quiredforeachLVDSoutputpair.Theterminationresistors

shouldbelocatedascloseaspossibletotheLVDSreceiver.

Overflow Bit

The overflow output bit (OF) outputs a logic high when

the analog input is either overranged or underranged.

The overflow bit has the same pipeline latency as the

data bits.

The outputs are powered by OV and OGND, which are

DD

isolated from the A/D core power and ground.

When CLKINV is set to 0 in the SPI register A2, OF signal

Programmable LVDS Output Current

+

is valid when CLKOUT is low as shown in the Timing

The default output driver current is 3.5mA. This current

can be adjusted by serially programming mode control

register A3 (see Table 3). Available current levels are

1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.

Diagram.

Phase Shifting the Output Clock

To allow adequate setup and hold time when latching the

+

output data, the CLKOUT signal may need to be phase

Optional LVDS Driver Internal Termination

shiftedrelativetothedataoutputbits.MostFPGAshavethis

feature; this is generally the best place to adjust the timing.

In most cases, using just an external 100Ω termination

resistor will give excellent LVDS signal integrity. In ad-

dition, an optional internal 100Ω termination resistor

can be enabled by serially programming mode control

register A3. The internal termination helps absorb any

reflections caused by imperfect termination at the re-

ceiver. When the internal termination is enabled, the

output driver current is doubled to maintain the same

output voltage swing.

+

Alternatively, the ADC can also phase shift the CLKOUT /

–

CLKOUT signals by serially programming mode control

register A2. The output clock can be shifted by 0°, 45°,

90°, or 135°. To use the phase shifting feature, the clock

duty cycle stabilizer must be turned on. Another con-

+

trol register bit can invert the polarity of CLKOUT and

–

CLKOUT , independently of the phase shift. The combina-

tion of these two features enables phase shifts of 45° up

to 315° (Figure 11).

21521012fa

19

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LTC2152-12/

LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

+

ENC

D0-D11, OF

MODE CONTROL BITS

CLKINV CLKPHASE1 CLKPHASE0

PHASE

SHIFT

0°

0

1

0

1

0

1

0

1

0

1

0

1

0

1

45°

90°

135°

180°

225°

270°

+

CLKOUT

315°

21521012 F11

Figure 11. Phase-Shifting CLKOUT

21521012fa

20

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LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

DATA FORMAT

CLKOUT

OF

Table 1 shows the relationship between the analog input

voltage, the digital data output bits and the overflow bit.

By default the output data format is offset binary. The 2’s

complement format can be selected by serially program-

ming mode control register A4.

OF

D11

D11/D0

D10/D0

Table 1. Output Codes vs Input Voltage

D10

+

–

A

– A

D11-D0

IN

•

(1.5V Range)

OF

1

(OFFSET BINARY)

(2’s COMPLEMENT)

RANDOMIZER

ON

>0.75V

1111 1111 1111

1111 1111 1110

1000 0000 0001

1000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

0111 1111 1111

0111 1111 1110

0000 0000 0001

0000 0000 0000

1111 1111 1111

1111 1111 1110

1000 0000 0001

1000 0000 0000

D1

D1/D0

+0.75V

0

+0.7496337V

+0.0003662V

+0.000000V

–0.0003662V

–0.0007324V

–0.74963378V

–0.75V

0

D0

0

21521012 F12

0

Figure 12. Functional Equivalent of Digital Output Randomizer

0

< –0.75V

1

PC BOARD

Digital Output Randomizer

FPGA

CLKOUT

Interference from the A/D digital outputs is sometimes

unavoidable.Digitalinterferencemaybefromcapacitiveor

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off-chip, these unwanted

tones can be randomized, which reduces the unwanted

tone amplitude.

OF

D11/D0

LTC215X-12

D11

D10

D10/D0

D1/D0

D0

•

The digital output is randomized by applying an exclu-

sive-OR logic operation between the LSB and all other

data output bits. To decode, the reverse operation is

applied—an exclusive-OR operation is applied between

the LSB and all other bits. The LSB, OF and CLKOUT out-

puts are not affected. The output randomizer is enabled

by serially programming mode control register A4.

D1

D0

21521012 F13

Figure 13. Unrandomizing for Randomized

Digital Output Signal

21521012fa

21

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LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

Alternate Bit Polarity

Sleep Mode

TheA/Dmaybeplacedinapower-downmodetoconserve

power. In sleep mode, the entire A/D converter is powered

down, resulting in < 2mW power consumption. If the en-

code input signal is not disabled, the power consumption

will be higher (up to 2mW at 250Msps). Sleep mode is

enabled by mode control register A1 (serial programming

mode), or by SCK (parallel programming mode).

Another feature that may reduce digital feedback on the

circuit board is the alternate bit polarity mode. When this

mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,

D11) are inverted before the output buffers. The even

bits (D0, D2, D4, D6, D8, D10), OF and CLKOUT are not

affected. This can reduce digital currents in the circuit

board ground plane and reduce digital noise, particularly

for very small analog input signals.

The amount of time required to recover from sleep mode

depends on the size of the bypass capacitors on V

.

REF

The digital output is decoded at the receiver by inverting

the odd bits (D1, D3, D5, D7, D9, D11). The alternate bit

polaritymodeisindependentofthedigitaloutputrandom-

izer—either both or neither function can be on at the same

time. The alternate bit polarity mode is enabled by serially

programming mode control register A4.

For the suggested values in Figure 1, the A/D will stabi-

lize after 0.1ms + 2500 • t where t is the period of the

p

sampling clock.

Nap Mode

In nap mode the A/D core is powered down while the

internal reference circuits stay active, allowing faster

wakeup. Recovering from nap mode requires at least 100

clock cycles. Wake-up time from nap mode is guaranteed

only if the clock is kept running, otherwise sleep mode,

wake-up time conditions apply. Nap mode is enabled by

setting register A1 in the serial programming mode.

Digital Output Test Patterns

To allow in-circuit testing of the digital interface to the

A/D, there are several test modes (activate by setting

DTESTON) that force the A/D data outputs (OF, D11 to

D0) to known values:

All 1s: All outputs are 1

All 0s: All outputs are 0

DEVICE PROGRAMMING MODES

The operating modes of the LTC215X-12 can be pro-

grammed by either a parallel interface or a simple serial

interface. The serial interface has more flexibility and

can program all available modes. The parallel interface

is more limited and can only program some of the more

commonly used modes.

Alternating: Outputs change from all 1s to all 0s on

alternating samples

Checkerboard: Outputs change from 1010101010101

to 0101010101010 on alternating samples.

The digital output test patterns are enabled by serially

programming mode control register A4. When enabled,

the test patterns override all other formatting modes:

2’s complement, randomizer, alternate-bit polarity.

Parallel Programming Mode

To use the parallel programming mode, PAR/SER should

be tied to V . The CS, SCK and SDI pins are binary logic

DD

Output Disable

inputs that set certain operating modes. These pins can

be tied to V or ground, or driven by 1.8V, 2.5V, or 3.3V

The digital outputs may be disabled by serially program-

ming mode control register A3. All digital outputs, includ-

ing OF and CLKOUT, are disabled. The high impedance

disabled state is intended for long periods of inactivity,

it is not designed for multiplexing the data bus between

multiple converters.

DD

CMOS logic. Table 2 shows the modes set by CS, SCK

and SDI.

21521012fa

22

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LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

Table 2. Parallel Programming Mode Control Bits)

Software Reset

DESCRIPTION

If serial programming is used, the mode control registers

shouldbeprogrammedassoonaspossibleafterthepower

supplies turn on and are stable. The first serial command

must be a software reset which will reset all register data

bits to logic 0. To perform a software reset it is neces-

sary to write 1 in register A0 (Bit D7). After the reset is

complete, Bit D7 is automatically set back to zero. This

register is WRITE-ONLY.

CS

Clock Duty Cycle Stabilizer Control Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

Power-Down Control Bit

SCK

SDI

0 = Normal Operation

1 = Sleep Mode (entire ADC is powered down)

LVDS Current Selection Bit

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

GROUNDING AND BYPASSING

Serial Programming Mode

The LTC215X-12 requires a printed circuit board with a

clean unbroken ground plane in the first layer beneath the

ADC. A multilayer board with an internal ground plane is

recommended. Layoutforthe printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track

or underneath the ADC.

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become

a serial interface that program the A/D control registers.

Data is written to a register with a 16-bit serial word. Data

can also be read back from a register to verify its contents.

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the first sixteen rising edges

of SCK. Any SCK rising edges after the first sixteen are

ignored.ThedatatransferendswhenCSistakenhighagain.

High quality ceramic bypass capacitors should be used

at the V , OV , V and V

pins. Bypass capacitors

DD

DD CM

REF

must be located as close to the pins as possible. Size

0402 ceramic capacitors are recommended. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

The first bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The final eight bits are the register data (D7:D0).

If the R/W bit is low, the serial data (D7:D0) will be writ-

ten to the register set by the address bits (A6:A0). If the

R/W bit is high, data in the register set by the address bits

(A6:A0) will be read back on the SDO pin (see the Timing

Diagrams). During a readback command the register is

not updated and data on SDI is ignored.

The analog inputs, encode signals and digital outputs

should not be routed next to each other. Ground fill and

grounded vias should be used as barriers to isolate these

signals from each other.

HEAT TRANSFER

The SDO pin is an open-drain output that pulls to ground

with a 200Ω impedance. If register data is read back

through SDO, an external 2k pull-up resistor is required.

If serial data is only written and readback is not needed,

then SDO can be left floating and no pull-up resistor is

needed.Table 3showsamapofthemodecontrolregisters.

Most of the heat generated by the LTC215X-12 is trans-

ferred from the die through the bottom-side exposed pad

and package leads onto the printed circuit board. For good

electricalandthermalperformance,theexposedpadmust

be soldered to a large grounded pad on the PC board. This

pad should be connected to the internal ground planes by

an array of vias.

21521012fa

23

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LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

Table 3. Serial Programming Mode Register Map (PAR/SER = GND). An “X” indicates an unused bit.

REGISTER A0: RESET REGISTER (ADDRESS 00h) WRITE-ONLY

D7

D6

X

D5

D4

X

D3

X

D2

X

D1

X

D0

X

RESET

X

Bit 7

RESET

0 = Not Used

Software Reset Bit

1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.

Bits 6-0

Unused bit.

REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)

D7

X

D6

X

D5

X

D4

X

D3

D2

D1

0

D0

0

SLEEP

NAP

Bits 7-4

Unused, these bits are read back as 0.

Bit 3

SLEEP

0 = Normal Operation

1 = Power Down Entire ADC

Bit 2

NAP

0 = Normal Mode

1 = Low Power Mode

Must be set to 0.

Bit 1-0

REGISTER A2: TIMING REGISTER (ADDRESS 02h)

D7

X

D6

X

D5

X

D4

X

D3

D2

D1

D0

CLKINV

CLKPHASE1

CLKPHASE0

DCS

Bits 7-4

Unused, these bits are read back as 0.

CLKINV Output Clock Invert Bit

Bit 3

0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)

1 = Inverted CLKOUT Polarity

Bits 2-1

CLKPHASE1:CLKPHASE0

Output Clock Phase Delay Bits

00 = No CLKOUT Delay (as shown in the Timing Diagrams)

+

–

01 = CLKOUT /CLKOUT delayed by 45° (Clock Period • 1/8)

10 = CLKOUT /CLKOUT delayed by 90° (Clock Period • 1/4)

11 = CLKOUT /CLKOUT delayed by 135° (Clock Period • 3/8)

Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.

Bit 0

DCS

Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

21521012fa

24

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LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)

D7

X

D6

X

D5

X

D4

D3

D2

D1

D0

ILVDS2

ILVDS1

ILVDS0

TERMON

OUTOFF

Bits 7-5

Unused, these bits are read back as 0.

Bits 4-2

ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 1

Bit 0

TERMON

0 = Internal Termination Off

1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0

LVDS Internal Termination Bit

OUTOFF

0 = LVDS DDR

Digital Output Mode Control Bits

1 = LVDS Tristate (High Impedance)

REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)

D7

D6

D5

D4

D3

0

D2

D1

D0

OUTTEST2

OUTTEST1

OUTTEST0

ABP

DTESTON

RAND

TWOSCOMP

Bits 7-5

OUTTEST2:OUTTEST0

000 = All Digital Outputs = 0

001 = All Digital Outputs = 1

Digital Output Test Pattern Bits

010 = Alternating Output Pattern. OF, D11-D0 alternate between 00000 0000 0000 and 11111 1111 1111

100 = Checkerboard Output Pattern. OF, D11-D0 alternate between 01010 1010 1010 and 10101 0101 0101

Bit 4

ABP

Alternate Bit Polarity Mode Control Bit

0 = Alternate Bit Polarity Mode Off

1 = Alternate Bit Polarity Mode On

Bit 3

Bit 2

Must be set to 0.

DTESTON

0 = Normal Mode

1 = Enable the Digital Output Test Patterns

Enable digital patterns (Bits 7-5)

Bit 1

Bit 0

RAND

Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

TWOSCOMP Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

21521012fa

25

For more information www.linear.com/LTC2152-12

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LTC2151-12/LTC2150-12

APPLICATIONS INFORMATION

215210 F15

215210 F16

215210 F14

Silkscreen Top

Inner Layer 1

Inner Layer 2

215210 F17

215210 F18

Inner Layer 3

Inner Layer 4

215210 F19

215210 F20

Inner Layer 5

Bottom Layer

21521012fa

26

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LTC2152-12/

LTC2151-12/LTC2150-12

TYPICAL APPLICATIONS

LTC2152-12 Schematic

SDO

SDI

SCK

CS

PAR/SER

V

DD

0.2µF

0.1µF

TP3

R9, 1k

SENSE

C13

1

V

30

DD

2.2µF

OV

DD

+

2

V

29

28

27

26

25

24

23

22

21

DD

+

–

D6_7

R14

10Ω

3

GND

–

+

–

+

–

+

–

4

5

+

A

INA

+

–

CLKOUT

D4_5

CLKOUT

–

R16

100Ω

LTC2152-12

6

GND

R19

10Ω

+

SENSE

D4_5

7

SENSE

–

D4_5

A

8

INA

V

REF

+

D2_3

9

C16

2.2µF

V

CM

–

D2_3

10

41

GND

10Ω

OGND

VCM

C21

0.1µF

21521012 TA02

0.1µF

100Ω

0.1µF

+

–

CLK

21521012fa

27

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LTC2152-12/

LTC2151-12/LTC2150-12

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

0.70 0.05

6.50 0.05

5.10 0.05

4.42 0.05

4.50 0.05

(4 SIDES)

4.42 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.115

TYP

6.00 0.10

(4 SIDES)

R = 0.10

TYP

39 40

0.40 0.10

PIN 1 TOP MARK

(SEE NOTE 6)

1

2

PIN 1 NOTCH

R = 0.45 OR

0.35 ¥ 45

CHAMFER

4.42 0.10

4.50 REF

(4-SIDES)

4.42 0.10

(UJ40) QFN REV Ø 0406

0.200 REF

0.25 0.05

0.50 BSC

0.00 – 0.05

NOTE:

BOTTOM VIEW—EXPOSED PAD

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

21521012fa

28

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LTC2152-12/

LTC2151-12/LTC2150-12

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

5 and 15

A

12/14 Changed pipeline latency to 6

Updated G17, G37 and G57

7, 10 and 12

21521012fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

29

For more information www.linear.com/LTC2152-12

LTC2152-12/

LTC2151-12/LTC2150-12

TYPICAL APPLICATION

LTC2152-12: 32K Point 2-Tone FFT,

f_IN= 71MHz and 69MHz, 250Msps

V

DD

OV

DD

0

D10_11

–20

12-BIT

PIPELINED

ADC

•

CORRECTION

LOGIC

DDR

LVDS

ANALOG

INPUT

OUTPUT

DRIVERS

S/H

•

–40

–60

D0_1

OGND

CLOCK/DUTY

CYCLE

CONTROL

–80

CLOCK

–100

–120

21521012 TA03a

GND

0

40

60

80

100 120

20

FREQUENCY (MHz)

21521012 TA03b

RELATED PARTS

PART NUMBER

ADCs

DESCRIPTION

COMMENTS

1250mW, 77.7dB SNR, 100dB SFDR, 64-Lead QFN Package

LTC2208

16-Bit, 130Msps, 3.3V ADC, LVDS Outputs

LTC2157-14/LTC2156-14/

LTC2155-14

14-Bit, 250Msps/210Msps/170Msps,

1.8V Dual ADC, DDR LVDS Outputs

650mW/616mW/567mW, 70dB SNR, 90dB SFDR, 64-Lead QFN Package

LTC2152-14/LTC2151-14/

LTC2150-14

14-Bit, 250Msps/210Msps/170Msps,

1.8V Dual ADC, DDR LVDS Outputs

356mW/338mW/313mW, 70dB SNR, 90dB SFDR, 40-Lead QFN Package

LTC2262-14

14-Bit, 150Msps 1.8V ADC, Ultralow Power

149mW, 72.8dB SNR, 88dB SFDR, DDR LVDS/DDR CMOS/CMOS Outputs,

40-Lead QFN Package

RF Mixers/Demodulators

LT^®5517

40MHz to 900MHz Direct Conversion

Quadrature Demodulator

High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LT5527

LT5575

400MHz to 3.7GHz High Linearity

Downconverting Mixer

24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,

50Ω Single-Ended RF and LO Ports

800MHz to 2.7GHz Direct Conversion

Quadrature Demodulator

High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator,

Integrated RF and LO Transformer

Amplifiers/Filters

LTC6409

10GHz GBW, 1.1nV/√Hz Differential Amplifier/ 88dB SFDR at 100MHz, Input Range Includes Ground 52mA Supply

ADC Driver

Current, 3mm × 2mm QFN Package

LTC6412

800MHz, 31dB Range, Analog-Controlled

Variable Gain Amplifier

Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz,

10dB Noise Figure, 4mm × 4mm QFN-24 Package

LTC6420-20

1.8GHz Dual Low Noise, Low Distortion

Differential ADC Drivers for 300MHz IF

Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per

Amplifier, 3mm × 4mm QFN-20 Package

Receiver Subsystems

LTM^®9002

14-Bit Dual Channel IF/Baseband Receiver

Subsystem

Integrated High Speed ADC, Passive Filters and Fixed Gain Differential

Amplifiers

LTM9003

12-Bit Digital Pre-Distortion Receiver

Integrated 12-Bit ADC Down-Converter Mixer with 0.4GHz to 3.8GHz Input

Frequency Range

21521012fa

LT1214 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

30

For more information www.linear.com/LTC2152-12

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2152-12

●

 LINEAR TECHNOLOGY CORPORATION 2011


型号：	LTC2150-12_15
厂家：	Linear
描述：	Single 12-Bit 250Msps/ 210Msps/170Msps ADCs
文件：	总30页 (文件大小：677K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2150-12_15 [Linear]

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