LTC2150-14 [Linear]
300MHz Digital Predistortion Receiver; 300MHz的数字预失真接收器型号: | LTC2150-14 |
厂家: | Linear |
描述: | 300MHz Digital Predistortion Receiver |
文件: | 总36页 (文件大小:1000K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
LTM9013
300MHz Digital
Predistortion Receiver
FEATURES
DESCRIPTION
The LTM®9013 is a 300MHz digital predistortion receiver.
Utilizing an integrated system in a package (SiP) technol-
ogy, itisaμModule® (micromodule)receiverthatincludes
a dual high speed 14-bit A/D converter, lowpass filter,
differential gain stages and a quadrature demodulator.
n
Integrated I/Q Demodulator, IF Amplifier, and Dual
14-Bit, 310Msps High Speed ADC
n
External Highpass Filter Allows Bandwidth
Adjustment
n
300MHz Lowpass Filter for Each Channel
n
RF Input Frequency Range: 0.7GHz to 4GHz
The LTM9013 is perfect for digital predistortion applica-
tions, with AC performance that includes 59dB SNR and
1.3dB frequency flatness from DC to 300MHz. A highpass
filter or simple AC coupling are used external to the device
for design flexiblity. The integrated on-chip broadband
transformers provide a 50Ω single-ended interface at
the RF input.
n
50Ω Single-Ended RF Port
50Ω Differential LO Port
n
n
Frequency Flatness: 1.3dB Typical
n
66dBc IM3 Level at –7dBFS
n
59dB SNR at –1dBFS
n
Parallel DDR LVDS Outputs
n
Clock Duty Cycle Stabilizer
n
A 5V supply powers the demodulator and a 3.3V supply
powers the IF amplifiers for minimal distortion. A 1.8V
supplyallowslowpowerADCoperation.Aseparateoutput
supply allows the DDR LVDS outputs to drive 1.8V logic.
An optional multiplexer allows both channels to share a
digital output bus. An optional clock duty cycle stabilizer
allows high performance at full speed for a wide range of
clock duty cycles.
Low Power: 2.6W
n
Shutdown and Nap Modes
n
15mm × 15mm BGA Package
APPLICATIONS
n
Telecommunications
n
Wideband, Low IF Receivers
n
Digital Predistortion Receivers
Cellular Base Stations
n
L, LT, LTC, LTM, µModule, Linear Technology and the Linear logo are registered trademarks of
Linear Technology Corporation.
TYPICAL APPLICATION
15nH
100Ω
5V
0.01µF
64k Point FFT
6.8pF
15nH
0.01µF
fIN = 1950MHz, –1dBFS
100Ω
V
CC1
5V
V
CC2
3.3V
V
DD
1.8V
0
–10
LTM9013
GAIN_Q GAIN_I
OV
DD
1.8V
–20
–30
–40
ADC
–50
CLKOUT
–60
0°
ADC CLK
OF
LNA
–70
90°
–80
–90
ADC
GND
–100
–110
–120
PAR/SER
GND
SCK CS SDI SDO
9013 TA01
LO IN
0
16 32 48
96 112 128 144 160
FREQUENCY (MHz)
64 80
15nH
100Ω
0.01µF
9013 TA01b
6.8pF
5V
0.01µF
15nH
100Ω
9013f
1
For more information www.linear.com/LTM9013
LTM9013
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2)
Supply Voltage
TOP VIEW
1
2
3
4
5
6
7
8
9
10 11 12 13 14
V
V
...................................................... –0.3V to 5.5V
...................................................... –0.3V to 3.8V
CC1
CC2
A
B
C
D
E
V , OV ............................................. –0.3V to 2.0V
DD
DD
Analog Input Voltage
EN, EIP2, REF, IP2I, IP2Q...........–0.3V to V
+ 0.3V
CC1
DD
PAR/SER, SENSE..................... –0.3V to (V + 0.2V)
F
Digital Input Voltage (Note 3)
+
–
G
H
J
CLK , CLK ............................. –0.3V to (V + 0.3V)
DD
Digital Input Voltage (Note 4)
CS, SDI, SCK......................................... –0.3V to 3.9V
RF Input DC Voltage............................................... 0.1V
K
L
+
–
LO , LO Input DC Voltage.............–0.3V to V
Analog Input Current
+ 0.3V
CC1
M
N
P
+IN_I, –IN_I, +IN_Q, –IN_Q............................ 20mA
GAIN_I, GAIN_Q, EN_I, EN_Q, SHDN_I,
BGA PACKAGE
196-LEAD (15mm × 15mm × 2.82mm)
SHDN_Q........................................................... 10mA
+
–
LO , LO Input Power ........................................ +10dBm
RF Input Power ..................................................+20dBm
Analog Input Power, Continuous
T
= 125°C, θ = 20°C/W, θ
= 6°C/W, θ
=19°C/W, θ =9°C/W
JCtop JB
JMAX
JA
JCbottom
θ VALUES DEFINED PER JESD 51-12
WEIGHT = 1.35g
+IN_I, –IN_I, +IN_Q, –IN_Q........................... +15dBm
Analog Input Power, 100μs Pulse
+IN_I, –IN_I, +IN_Q, –IN_Q...........................+20dBm
Analog Output Voltage
+OUT_I, –OUT_I,
+OUT_Q, –OUT_Q .........................2.5V to V
Digital Output Voltage
+ 0.3V
CC1
SDO ..................................................... –0.3V to 3.9V
Except SDO............................ –0.3V to (OV + 0.3V)
DD
Operating Temperature Range
LTM9013C ............................................... 0°C to 70°C
LTM9013I.............................................–40°C to 85°C
Storage Temperature Range .................. –55°C to 125°C
CAUTION: This part is sensitive to electrostatic discharge
(ESD). It is very important that proper ESD precautions
be observed when handling the RF and LO inputs of the
LTM9013.
9013f
2
For more information www.linear.com/LTM9013
LTM9013
ORDER INFORMATION
LEAD FREE FINISH
LTM9013CY-AA#PBF
LTM9013IY-AA#PBF
TRAY
PART MARKING*
LTM9013Y-AA
LTM9013Y-AA
PACKAGE DESCRIPTION
TEMPERATURE RANGE
0°C to 70°C
LTM9013CY-AA#PBF
LTM9013IY-AA#PBF
196-Lead (15mm × 15mm × 2.8mm) BGA
196-Lead (15mm × 15mm × 2.8mm) BGA
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
This product is only offered in trays. For more information go to: http://www.linear.com/packaging/
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. PRF = –5dBm, PLO = 0dBm (Notes 5, 7) unless otherwise noted.
SYMBOL PARAMETER
RF Input Frequency Range
CONDITIONS
MIN
TYP
MAX
UNITS
No External Matching (Mid Band)
with External Matching (Low Band, High Band)
1.5 to 2.7
0.7 to 4.0
GHz
GHz
LO Input Frequency Range
No External Matching (Mid Band)
With External Matching (Low Band, High Band)
1.5 to 2.7
0.7 to 4.0
GHz
GHz
IF Frequency Range
0.5 to 300
>10
MHz
dB
RF Input Return Loss
LO Input Return Loss
RF Input Power for –1dBFS
LO Input Power
Z = 50Ω, 1.5GHz to 2.7GHz, Internally Matched
O
Z = 50Ω, 1.5GHz to 2.7GHz, Internally Matched
O
>10
dB
RF = 2140MHz, LO = 1990MHz (Figure 14)
–5
dBm
dBm
dB
–6 to +6
0.15
1
I/Q Gain Mismatch
RF = 2140MHz, LO = 1990MHz (Figure 14)
RF = 2140MHz, LO = 1990MHz (Figure 14)
LO = 1990MHz
I/Q Phase Mismatch
Deg
dBm
dBm
dB
LO to RF Leakage
–55
RF to LO Isolation
RF = 2140MHz
58
Gain Flatness (Notes 5, 6)
Lowpass Filter Cutoff Frequency
Resolution (No Missing Codes)
Integral Linearity Error (Note 8)
Differential Linearity Error
Offset Error (Note 9)
f
= 500kHz to 300MHz (Figure 14)
0.5
IF
0.5dB Point
300
MHz
Bits
LSB
LSB
LSB
l
14
Differential Analog Input
Differential Analog Input
4.5
0.35
62
–1
1
–186
186
9013f
3
For more information www.linear.com/LTM9013
LTM9013
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. PRF = –5dBm, PLO = 0dBm (Notes 5, 7) unless otherwise noted.
SYMBOL
IIP3
PARAMETER
CONDITIONS
MIN
TYP
30
MAX
UNITS
dBm
Input 3rd Order Intercept, 1 Tone
Input 2nd Order Intercept, 1 Tone
Signal-to-Noise Ratio at –1dBFS
RF = 2140MHz, LO = 1990MHz
RF = 2140MHz, LO = 1990MHz
RF = 2140MHz, LO = 1990MHz (Figure 14)
IIP2
56
dBm
SNR
59
62
dBFS
dBFS
l
l
f
IF
= 150MHz (Note 6)
59
60
SFDR
Spurious Free Dynamic Range
2nd or 3rd Harmonic
RF = 2140MHz, LO = 1990MHz (Figure 14)
= 150MHz (Note 6)
65
70
dB
dB
f
IF
Spurious Free Dynamic Range
4th or Higher
RF = 2140MHz, LO = 1990MHz (Figure 14)
= 150MHz (Note 6)
75
80
dB
dB
f
IF
S/(N+D)
IMD3
Signal-to-Noise Plus Distortion Ratio
RF = 2140MHz, LO = 1990MHz (Figure 14)
= 150MHz (Note 6)
58
61
dBFS
dBFS
l
f
IF
58
Intermodulation Distortion at –7dBFS per
Tone
RF = 2140MHz and 2141MHz, LO = 1990MHz
(Figure 14)
66
dB
ANALOG INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Demodulator Adjust Inputs (IP2I, IP2Q)
Input Voltage
0
1.3
V
kΩ||pF
μs
Input Impedance
2||1
2
Settling Time
For Step Input; Output with 90% of Final Value
Demodulator Adjust Input (REF)
Input Voltage
0.4
49
0.5
0.7
65
V
Input Impedance
8||1
MΩ||pF
Amplifier Analog Inputs (+IN_I, –IN_I, +IN_Q, –IN_Q)
Differential Input Resistance
Input Common Mode Voltage
Minimum Input Frequency (3dB Corner)
Amplifier Gain Control Analog Inputs (GAIN_I, GAIN_Q)
V
= 100mV
57
Ω
mV
kHz
IN(DIFF)
640
500
R
Input Resistance
Input Low Current
Gain Control Range
GAIN_I, GAIN_Q = 1.0V, R = 1V/∆I
7.8
7.2
9.2
–5
10.6
12.8
kΩ
kΩ
IN
IN
IL
l
I
GAIN_I, GAIN_Q = 0V
–9
–10
–1
–1
µA
µA
IL
l
l
V
= 0.2V to 1.2V
27.5
29
30.5
dB
GAIN
Temperature Coefficient of Gain at Fixed
Gain Control Voltage
–0.007
dB/°C
l
Gain Control Slope
Gain Control Voltage = 0.2V to 1V, Slope of the
Least-Square Fit Line
30.6
32.6
0.12
0.2
34.7
dB/V
dB
Average Conformance Error to Gain
Slope Line
Gain Control Voltage = 0.2V to 1V, Standard
Error to the Least-Square Fit Line
Maximum Conformance Error to Gain
Slope Line
Gain Control Voltage = 0.2V to 1V, Maximum
Error to the Least-Square Fit Line
dB
9013f
4
For more information www.linear.com/LTM9013
LTM9013
ANALOG INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
ADC Analog Inputs (SENSE)
Input Leakage Current
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
1.1V < SENSE < 1.2V
–1
1
μA
Demodulator Analog Outputs (+OUT_I, –OUT_I, +OUT_Q, –OUT_Q)
Common Mode Voltage
V
CC1
– 1.5V
V
Differential Output Impedance
50||6
Ω||pF
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Demodulator Logic Inputs (EN, EIP2)
l
l
V
V
High Level Input Voltage
Low Level Input Voltage
Input Pull-Up Resistance
EIP2 Input Current
Turn-On Time
V
V
V
= 5V
= 5V
2
V
V
IH
CC
CC
CC
0.3
IL
= 5V, V = 4.4V to 2.6V
100
40
kΩ
μA
µs
µs
EN
EIP2 = 5V
0.2
0.8
Turn-Off Time
I and Q Channel Logic Inputs (EN_I, EN_Q, SHDN_I, SHDN_Q)
l
l
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
Input Pull-Up Resistance
Input High Current
V
V
V
= 3.3V
2.2
V
V
CC
CC
CC
= 3.3V
0.8
= 3.3V, V
= 0V to 0.5V
100
–15
–30
kΩ
µA
µA
EN_I,EN_Q
EN_I, EN_Q = 2.2V, SHDN_I, SHDN_Q = 2.2V
EN_I, EN_Q = 0.8V, SHDN_I, SHDN_Q = 0.8V
–30
–60
–1
–1
Input Low Current
+
–
ADC Encode Clock Inputs (CLK , CLK )
Differential Input Voltage
l
l
V
= 1.8V
0.2
1.1
V
DD
Common Mode Input Voltage
Internally Set
Externally Set
1.2
V
V
1.5
Input Resistance
Input Capacitance
10
2
kΩ
pF
(Note 10)
ADC Logic Inputs (SDI, SCK, CS)
l
l
l
V
IH
V
IL
High Level Input Voltage
Low Level Input Voltage
Input Current
V
V
V
= 1.8V
1.3
V
V
DD
DD
IN
= 1.8V
0.6
10
= 0V to 3.6V
–10
μA
pF
Input Capacitance
(Note 10)
3
ADC Logic Inputs (PAR/SER)
Input Leakage Current
ADC Logic Output (SDO)
Logic Low Output Resistance to GND
0 < PAR/SER < V
–1
1
μA
DD
V
DD
= 1.8V, SDO = 0V
200
4
Ω
µA
pF
l
Logic High Output Leakage Current
Output Capacitance
SDO = 0V to 3.6V
(Note 10)
–10
10
9013f
5
For more information www.linear.com/LTM9013
LTM9013
DIGITAL INPUTS AND OUTPUTS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Data Outputs (OV = 1.8V)
DD
l
l
Differential Output Voltage
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
247
125
350
175
454
250
mV
mV
l
l
Common Mode Output Voltage
On-Chip Termination Resistance
100Ω Differential Load, 3.5mA Mode
100Ω Differential Load, 1.75mA Mode
1.125
1.125
1.250
1.250
1.375
1.375
V
V
Termination Enabled, OV = 1.8V
100
Ω
DD
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
4.75
2.7
TYP
MAX
5.25
3.6
UNITS
l
l
l
l
l
l
V
V
V
Demodulator and Amplifier Supply Voltage
Amplifier Analog Supply Voltage
ADC Analog Supply Voltage
V
V
CC1
CC2
DD
3.3
1.8
1.8
285
16
1.74
1.74
1.9
V
OV
ADC Digital Output Supply Voltage
Demodulator and Amplifier Supply Current
1.9
V
DD
I
I
330
20
mA
mA
CC1
Demodulator and Amplifier Shutdown
Current
EN = 0V, EN_I, EN_Q = 3.3V, SHDN_I,
SHDN_Q = 0V
CC1(SHDN)
l
l
I
I
I
Amplifier Supply Current
ADC Supply Current
Digital Supply Current
ADC Sleep Power
132
335
80
160
385
90
mA
mA
mA
mW
W
CC2
DD
3.5mA Mode
OVDD
ADC Programmed for Sleep Mode, No CLK
5
Total Power Dissipation
2.6
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
f
t
Sampling Frequency
CLK Low Time
1
310
MHz
S
L
l
l
Duty Cycle Stabilizer Off (Note 10)
Duty Cycle Stabilizer On (Note 10)
1.5
1.2
1.6
1.6
50
50
ns
ns
l
l
t
t
t
CLK High Time
Duty Cycle Stabilizer Off (Note 10)
Duty Cycle Stabilizer On (Note 10)
1.5
1.2
1.6
1.6
50
50
ns
ns
H
Sample-and-Hold Acquisition Delay Time
Jitter
0.15
ps
RMS
JITTER
Sample-and-Hold Acquisition Delay Time
1
ns
AP
DATA Outputs (Note 10)
l
l
l
t
t
t
CLK to DATA Delay
C = 5pF
1.7
1.3
0.3
2
2.3
2
ns
ns
ns
D
L
CLK to CLKOUT Delay
DATA to CLKOUT Skew
C = 5pF
L
1.6
0.4
C
t – t
D C
0.55
SKEW
9013f
6
For more information www.linear.com/LTM9013
LTM9013
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Notes 5, 7)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
SPI Port Timing (Note 10)
l
l
t
SCK Period
Write Mode
40
ns
ns
SCK
Readback Mode C
= 20pF, R
= 20pF, R
= 2kΩ
= 2kΩ
250
SDO
SDO
PULLUP
t
t
t
t
t
CS to SCK Set-up Time
SCK to CS Hold Time
SDI Set-Up Time
5
5
5
5
ns
ns
ns
ns
ns
S
H
DS
DH
DO
SDI Hold Time
SCK Falling to SDO Valid
Readback Mode C
125
PULLUP
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 5: Using test circuit 1 (see Figure 14 Design Example in Applications
Information section).
Note 6: Signal applied to the INn pins and measures only the amplifier
and ADC.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 7: V
= 5V, V
= 3.3V, V = 1.8V, EN = 5V, EN_I, EN_Q = 0V,
CC1
CC2 DD
GAIN_I, GAIN_Q = 1.2V, SHDN_I, SHDN_Q = 3.3V, SENSE = 1.15V,
Note 3: When these pin voltages are taken below GND or above V , they
f = 310MHz, unless otherwise noted.
S
DD
will be clamped by internal diodes. This product can handle input currents
Note 8: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
of greater than 100mA below GND or above V without latchup.
DD
Note 4: When these pin voltages are taken below GND they will be
clamped by internal diodes. When these pin voltages are taken above V
they will not be clamped by internal diodes. This product can handle input
currents of greater than 100mA below GND without latchup.
,
DD
Note 9: DC offset is the ADC output code with no RF or LO input signal
applied the module.
Note 10: Guaranteed by design, not subject to test
9013f
7
For more information www.linear.com/LTM9013
LTM9013
TYPICAL PERFORMANCE CHARACTERISTICS
64k Point FFT, fIN = 1950MHz,
–1dBFS
64K Point FFT, fIN = 1925MHz,
1975MHz, –7dBFS per Tone
Baseband Frequency Response
0
0
–10
0
–10
–1
–20
–20
–30
–30
–40
–40
–2
–3
–50
–50
–60
–60
–70
–70
–4
–5
–6
–80
–80
–90
–90
–100
–110
–120
–100
–110
–120
0
50 100 150 200 250 300 350 400 450 500
BASEBAND FREQUENCY (MHz)
0
16 32 48 64 80 96 112 128 144 160
FREQUENCY (MHz)
0
16 32 48 64 80 96 112 128 144 160
FREQUENCY (MHz)
9013 G01
9013 G02
9013 G03
SNR at 150MHz IF vs RF Drive
HD2 at 150MHz IF vs LO Power
HD2 at 150MHz IF vs RF Drive
–45
–50
–55
–60
–65
–70
–75
–80
–40
–45
61.0
60.5
–50
–55
60.0
59.5
HD2, Q CHANNEL
HD2, I CHANNEL
HD2, Q CHANNEL
–60
–65
–70
59.0
58.5
58.0
HD2, I CHANNEL
–5
0
5
10
15
–5
0
5
10
15
–22 –18 –14 –10 –6 –2
LO POWER (dBm)
2
6
10
RF DRIVE (dBm)
RF DRIVE (dBm)
9013 G06
9013 G04
9013 G05
HD3 at 150MHz IF vs RF Drive
IM3 at 150MHz vs RF Drive
LO to RF Isolation
–40
–45
–50
–40
–45
–50
–55
–60
–65
–70
–75
–80
0
–10
–20
–30
–40
–50
–60
–70
–80
–55
–60
–65
–70
–75
0
5
15
–5
10
–4 –2
0
–12 –10 –8 –6
2
4
6
8
10
1.9 2.0
1.5 1.6 1.7 1.8
2.1 2.2 2.3 2.4 2.5
RF DRIVE (dBm)
RF DRIVE PER TONE (dBm)
LO FREQUENCY (GHz)
9013 G07
9013 G08
9013 G09
9013f
8
For more information www.linear.com/LTM9013
LTM9013
PIN FUNCTIONS
Supply Pins
GAIN_I (Pin C12): I Channel Gain Control Input. This is
an input that controls the gain of the amplifier. This pin is
internally pulled low with 10kΩ to GND. The gain control
slope is approximately 32dB/V with a gain control range
of 0.1V to 1.1V.
V
(Pin B7): Analog 5V Supply for Demodulator and
CC1
Amplifiers.Thespecifiedoperatingrangeis4.75Vto5.25V.
Thevoltageonthispinprovidespowerforthedemodulator
andamplifierstagesonlyandisinternallybypassedtoGND.
GAIN_Q (Pin C1): Q Channel Gain Control Input. This is
an input that controls the gain of the amplifier. This pin is
internally pulled low with 10kΩ to GND. The gain control
slope is approximately 32dB/V with a gain control range
of 0.1V to 1.1V.
V
(Pins A2, A3, A12, A13, D1, D12): Analog 3.3V Sup-
CC2
ply for Amplifiers. The specified operating range is 2.7V to
3.6V. V is internally bypassed to GND.
CC2
V
(Pins J6, J9): Analog 1.8V Supply for ADC. The
DD
specifiedoperatingrangeis1.74Vto1.9V.V isinternally
DD
+
–
CLK , CLK (Pins J5, K5): ADC Clock Input. Conversion
bypassed to GND.
+
starts on the rising edge of CLK .
OV (Pins N5, N10): Positive 1.8V Supply for the Digital
DD
IP2_I (Pin C10): IP2 Adjustment Pin for I Channel.
IP2_Q (Pin D10): IP2 Adjustment Pin for Q Channel.
Output Drivers. The specified operating range is 1.74V to
1.9V. OV is internally bypassed to GND.
DD
GND: Analog Ground. See Pin Configuration table for pin
locations.
REF (Pin D8): Voltage Reference Input for Analog Control
Voltage Pins.
SENSE (Pin J8): ADC Reference Programming Pin. Con-
Analog Inputs
necting SENSE to V selects the internal reference and
DD
RF (Pin A10): RF Input Pin. This is a single-ended 50Ω
terminatedinput.Noexternalmatchingnetworkisrequired
forthe1.5GHzto2.7GHzband. Anexternalseriesinductor
(and/or shunt capacitor) may be required for impedance
transformationto50Ωinthebandfrom700MHzto1.5GHz,
or for the band from 2.7GHz to 4GHz (see Figure 2). If the
RF source is not DC blocked, a series blocking capacitor
should be used. Otherwise, damage to the IC may result.
a 1.32V input range.
Analog Outputs
+OUT_I,–OUT_I(PinsF10,F11):ChannelISignalOutput.
This is a differential output from the demodulator. The DC
bias point is V
– 1.5V for each pin. These pins must
CC1
have an external 100Ω or inductor pull-up to V . Series
CC1
blocking capacitors are required between these pins and
+IN_I, –IN_I.
+
–
LO ,LO (PinsA6,A5):LocalOscillatorInputPins.Thisisa
differential50Ωterminatedinput.Anexternalseriesinduc-
tor(and/orshuntcapacitor)mayberequiredforimpedance
transformationto50Ωinthebandfrom700MHzto1.5GHz,
or for the band from 2.7GHz to 4GHz (see Figure 4). If the
LO source is not DC blocked, a series blocking capacitor
must be used. Otherwise, damage to the IC may result.
+OUT_Q,–OUT_Q(PinsF4,F5):ChannelQSignalOutput.
This is a differential output from the demodulator. The DC
bias point is V
– 1.5V for each pin. These pins must
CC1
have an external 100Ω or inductor pull-up to V . Series
CC1
blocking capacitors are required between these pins and
+IN_Q, –IN_Q.
+IN_I, –IN_I (Pins E10, E11): Channel I Signal Input. This
is a differential input that drives the amplifier. It has an
internally generated DC bias. Series blocking capacitors
are required between these pins and +OUT_I, –OUT_I.
Control Pins
EN (Pin B8): Demodulator Enable Pin. If EN = high (the
input voltage is higher than 2.0V), the demodulator is en-
abled. If EN = low (the input voltage is less than 1.0V), it
is disabled. If the enable function is not needed, then this
+IN_Q, –IN_Q (Pins E4, E5): Channel Q Signal Input. This
is a differential input that drives the Amplifier. It has an
internally generated DC bias. Series blocking capacitors
are required between these pins and +OUT_Q, –OUT_Q.
pin should be tied to V
.
CC1
EIP2 (Pin D6): Demodulator IP2 Adjust Enable Pin. Pin is
internally pulled low with 200kΩ to GND. If EIP2 = high
9013f
9
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LTM9013
PIN FUNCTIONS
(the input voltage is higher than 2.0V), the IP2 adjust
circuit is enabled. If EIP2 = low (the input voltage is less
than 1.0V), it is disabled.
controls the clock duty stabilizer (see Table 4). CS can be
driven with 1.8V to 3.3V logic.
PAR/SER (Pin J10): Programming Mode Selection Pin.
Connect to GND to enable the serial programming mode
where CS, SCK, SDI, SDO become a serial interface that
NC1, NC2, NC3 (Pins C6, C9, D9): Do Not Connect.
EN_I (Pin C14): First Amplifier I Channel Enable Pin. Pin
is internally pulled high with 100kΩ to V . Assert pin to
a low voltage to enable the amplifier. Connect pin to GND
if enable function is not used.
controlstheADCoperatingmodes.ConnecttoV toenable
DD
CC2
the parallel programming mode where CS, SCK, SDI, SDO
become parallel logic inputs that control a reduced set of
the ADC operating modes. PAR/SER should be connected
EN_Q (Pin C3): First Amplifier Q Channel Enable Pin. Pin
is internally pulled high with 100kΩ to V . Assert pin to
directly to GND or V and not be driven by a logic signal.
DD
CC2
a low voltage to enable the amplifier. Connect pin to GND
if enable function is not used.
Digital Outputs
SDO (Pin L11): Serial Interface Data Output. In serial pro-
gramming mode (PAR/SER = GND), SDO is the optional
serialinter-facedataoutput.DataonSDOisreadbackfrom
themodecontrolregistersandcanbelatchedonthefalling
edge of SCK. SDO is an open-drain N-channel MOSFET
output that requires an external 2kΩ pull-up resistor from
1.8V to 3.3V. If readback from the mode control registers
is not needed, the pull-up resistor is not necessary and
SDO can be left unconnected.
SHDN_I (Pin D14): Amplifier I Channel Shutdown Pin.
Pin is internally pulled high with 100kΩ to V . Assert
CC2
pin to a low voltage to shut down the amplifier. Proper
sequencing of the EN_I and SHDN_I pins is required to
avoid non-monotonic output signal behavior. Connect pin
to V
if shutdown function is not used.
CC2
SHDN_Q (Pin D3): Amplifier Q Channel Shutdown Pin.
Pin is internally pulled high with 100kΩ to V . Assert
CC2
pin to a low voltage to shut down the amplifier. Proper
sequencing of the EN_Q and SHDN_Q pins is required to
avoid non-monotonic output signal behavior. Connect pin
LVDS Digital Outputs
ThefollowingpinsaredifferentialLVDSoutputs.Theoutput
currentlevelisprogrammable.Thereisanoptionalinternal
100Ω termination resistor between the pins of each LVDS
output pair.
to V if shutdown function is not used.
CC2
SDI (Pin K11): Serial Interface Data Input. In serial pro-
gramming mode, (PAR/SER = GND), SDI is the serial
interface data input. Data on SDI is clocked into the mode
control registers on the rising edge of SCK. In the parallel
+
–
CLKOUT ,CLKOUT (PinsP8,P7):ADCDataOutputClock.
–
+
–
+
DB0_1 /DB0_1 to DB12_13 /DB12_13 (See Pin Con-
figurationtableforpinlocations):QChannelADCDouble
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DB0,
programming mode (PAR/SER = V ), SDI selects 3.5mA
DD
or a 7.5mA LVDS output current (see Table 4). SDI can be
driven with 1.8V to 3.3V logic.
+
DB2,DB4,DB6,DB8,DB10,DB12)appearwhenCLKOUT
SCK (Pin J11): Serial Interface Clock Input. In serial
programming mode (PAR/SER = GND), SCK is the serial
interface clock input. In the parallel programming mode
islow.Theodddatabits(DB1,DB3,DB5,DB7,DB9,DB11,
+
DB13) appear when CLKOUT is high.
–
+
–
+
(PAR/SER = V ), SCK can be used to place the part in the
DD
DA0_1 /DA0_1 to DA12_13 /DA12_13 (See Pin Con-
figurationtableforpinlocations):QChannelADCDouble
Data Rate Digital Outputs. Two data bits are multiplexed
onto each differential output pair. The even data bits (DA0,
low power sleep mode (see Table 4). SCK can be driven
with 1.8V to 3.3V logic.
CS (Pin K10): Serial Interface Chip Select Input. In serial
programming mode (PAR/SER = GND), CS is the serial
interface chip selectinput. WhenCS is low, SCK isenabled
for shifting data on SDI into the mode control registers.
+
DA2,DA4,DA6,DA8,DA10,DA12)appearwhenCLKOUT
islow.Theodddatabits(DA1,DA3,DA5,DA7,DA9,DA11,
+
DA13) appear when CLKOUT is high.
+
–
+
In the parallel programming mode (PAR/SER = V ), CS
DD
OF ,OF (PinsK2,K1):Overflow/UnderflowOutputs.OF
is high when an overflow/underflow has occurred.
9013f
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For more information www.linear.com/LTM9013
LTM9013
PIN FUNCTIONS
Pin Configuration
1
2
3
4
5
6
7
8
9
10
RF
11
GND
GND
GND
GND
–IN_I
–OUT_I
GND
GND
SCK
12
13
14
GND
GND
EN_I
SHDN_I
GND
GND
GND
GND
GND
GND
–
+
A
B
C
D
E
GND
V
V
GND
GND
GND
GND
+IN_Q
LO
LO
GND
GND
EN
GND
GND
NC2
NC3
GND
GND
GND
GND
V
CC2
V
CC2
CC2
CC2
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
EN_Q
SHDN_Q
GND
GND
GND
GND
NC1
EIP2
GND
GND
GND
GND
V
GND
GND
GND
CC1
GAIN_Q
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
REF
IP2_I
IP2_Q
+IN_I
+OUT_I
GND
GAIN_I
GND
GND
GND
GND
GND
GND
GND
GND
V
GND
V
CC2
CC2
GND
GND
GND
GND
GND
–IN_Q
GND
GND
GND
GND
SENSE
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
F
GND
+OUT_Q –OUT_Q
G
H
J
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
+
GND
CLK
V
V
DD
PAR/SER
CS
DD
–
+
–
K
L
OF
OF
GND
CLK
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
SDI
–
–
+
DB01
DB23
DB67
DB01+
GND
GND
GND
GND
SDO
DA1213 DA1213
–
–
+
–
+
–
+
–
+
M
N
P
DB23
DB45
DB45
DB89
GND
DA89
DA89
DA45
DA01
DA1011 DA1011
+
–
+
–
+
+
–
+
DB67
DB89
OV
DD
OV
DD
DA45
DA67
DA01
DA67
GND
+
–
+
–
–
+
+
–
–
GND
DB1213 DB1213 DB1011 DB1011
CLKOUT CLKOUT
DA23
DA23
Top View of BGA Package (Looking Through Component)
BLOCK DIAGRAM
DA12_13
DA0_1
•
•
•
RF
+
CLKOUT
CLKOUT
–
+
OF
0°
–
IP2
ADC
CONTROL
RANGE
SELECT
CLOCK DUTY
CYCLE CONTROL
OF
CONTROL
90°
DB12_13
DB0_1
•
•
•
9013 F01
Figure 1. Functional Block Diagram
9013f
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LTM9013
TIMING DIAGRAMS
Double-Data Rate Output Timing, All Data Are Differential LVDS
N
t
AP
N + 3
N + 2
N + 1
t
t
L
H
–
+
CLK
CLK
+
–
CLKOUT
CLKOUT
t
C
–
+
DA0_1
DA0_1
DA0
DA1
DA0
DA1
DA0
DA1
N-3
N-5
N-5
N-4
N-4
N-3
t
D
–
+
DA12_13
DA12_13
DA12
DA13
DA12
DA13
DA12
DA13
N-5
N-5
N-5
N-4
N-4
N-4
N-3
N-3
–
+
DB0_1
DB0_1
DB0
DB1
DB0
DB1
DB0
DB1
N-5
N-4
N-3
N-3
–
+
DB12_13
DB12_13
DB12
DB13
DB12
DB13
DB12
DB13
N-5
N-5
N-5
N-4
N-4
N-4
N-4
N-3
N-3
N-3
N-3
–
+
OF
OF_A
OF_B
t
OF_A
OF_B
OF_A
OF_B
N-5
OF
9013 TD01
SKEW
9013f
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LTM9013
TIMING DIAGRAMS
SPI Port Timing (Readback Mode)
t
S
t
DS
t
DH
t
t
H
SCK
CS
SCK
t
DO
SDI
A6
A5
A4
A3
A2
A1
A0
XX
XX
D6
XX
D5
XX
D4
XX
D3
XX
D2
XX
D1
XX
R/W
SDO
D7
D0
HIGH IMPEDANCE
SPI Port Timing (Write Mode)
CS
SCK
SDI
A6
A5
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
R/W
SDO
9013 TD02
HIGH IMPEDANCE
9013f
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LTM9013
OPERATION
Description
The LTM9013 variable gain amplifier employs an interpo-
lated, tapped attenuator circuit architecture to generate
the variable-gain characteristic. The tapped attenuator
is fed to a buffer and output amplifier to complete the
differential signal path. This circuit architecture provides
good RF input power handling capability along with a
constant output noise and output IP3 characteristic that
are desirable for most IF signal chain applications. The
internal control circuitry takes the gain control signal from
the GAIN terminals and converts this to an appropriate set
of control signals to the attenuator ladder. The attenuator
control circuit ensures that the linear-in-dB gain response
is continuous and monotonic over the gain range for both
slow and fast moving input control signals while exhibit-
ing very little input impedance variation over gain. These
TheLTM9013isalowIFreceivertargetingdigitalpredistor-
tion receiver applications, such as wireless infrastructure
with RF input frequencies up to 4GHz. It is an integrated
μModule receiver utilizing system in a package (SiP) tech-
nologytocombineadual, highspeed14-bitA/Dconverter,
300MHzlowpassfilters,onelownoise,differentialamplifier
per channel with adjustable gain and an I/Q demodulator
with IP2 adjustment.
Thefollowingsectionsdescribeinfurtherdetailtheopera-
tion of each section.
Demodulator Operation
The RF signal is applied to the inputs of the RF trans-
conductance amplifiers and is then demodulated into I/Q
baseband signals using quadrature LO signals which are
internally generated from an external LO source by preci-
sion 90° phase shifters.
characteristic
designconsiderationsresultinagain-vs-V
G
with a 0.1dB ripple and a 0.5µs gain response time that
is slower than a similar digital step attenuator design.
Anoftenoverlookedcharacteristicofananalog-controlled
VGA is upconverted amplitude modulation (AM) noise
from the gain control terminals. The VGA behaves as a
2-quadrant multiplier, so some minimal care is required
to avoid excessive AM sideband noise generation. The
following table demonstrates the effect of the baseline
20nV/√HzequivalentinputcontrolnoisefromtheLTM9013
circuit along with the effect of a higher combined input
noise due to a noisy external control circuit.
Broadband transformers are integrated at the RF input to
enable a single-ended RF interface. In the mid frequency
band (1.5GHz to 2.7GHz), both RF and LO ports are inter-
nally matched to 50Ω. No external matching components
are needed. For the low (700MHz to 1.5GHz), and high
(2.7GHz to 4GHz) frequency bands a simple network with
series inductors and/or shunt capacitors can be used as
the impedance matching network.
Amplifier Operation
CONTROL INPUT TOTAL NOISE
PEAK AM NOISE AT 10kHz OFFSET
NEAR MAXIMUM GAIN (dBc/Hz)
VOLTAGE (nV/√Hz)
Each channel of the LTM9013 consists of a single stage of
AC-coupled,lownoiseandlowdistortionfullydifferentialop
amp/ADCdriver.Eachstageisfollowedbya4-polelowpass
filter using a high speed, high performance operational
amplifier and precision passive components. The stage
is designed to provide maximum gain and phase flatness.
20
40
–142
–136
–131
–128
–122
70
100
200
9013f
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LTM9013
OPERATION
The baseline equivalent 20nV/√Hz input noise is seen to
produceworst-caseAMsidebandsof–142dBc/Hzwhichis
near the –147dBm/Hz output noise floor at maximum gain
for a nominal 0dBm output signal. An input control noise
voltage less than 80nV/√Hz is generally recommended to
avoidmeasurableAMsidebandnoise.Whileopampcontrol
circuit output noise voltage is usually below 80nV/√Hz,
some low power DAC outputs exceed 150nV/√Hz. DACs
withoutputnoiseintherangeof100nV/√Hzto150nV/√Hz
can usually be accommodated with a suitable 2:1 or 3:1
resistordividernetworkontheDACoutputtosuppressthe
noise amplitude by the same ratio. Noisy DACs in excess
of 150nV/√Hz should be avoided if minimal AM noise is
important in the application.
ADC Input Network
The passive network between the amplifier output and
the ADC input stages provides a 0.1dB ripple, 4th order
Chebyshev lowpass filter response.
Converter Operation
The LTM9013 includes a 2-channel, 14-bit 310Msps A/D
converter powered by a single 1.8V supply. The converter
has five pipelined ADC stages; a sampled input will result
in a digitized value five cycles later. The analog inputs
are driven differentially by the VGA. The encode inputs
should be driven differentially for optimal performance.
The digital outputs are double data rate LVDS. Additional
features can be chosen by programming the mode control
registers through a serial SPI port.
9013f
15
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LTM9013
APPLICATIONS INFORMATION
RF Input
0
–5
Figure 2 shows the mixer’s RF input which consists of an
integrated transformer and high linearity transconduc-
tance amplifiers. The primary side of the transformer is
connected to the RF input pin. The secondary side of the
transformer is connected to the differential inputs of the
transconductance amplifiers. Under no circumstances
should an external DC voltage be applied to the RF input
pin. DC current flowing into the primary side of the trans-
former may cause damage to the integrated transformer.
A series blocking capacitor should be used to AC-couple
the RF input port to the RF signal source.
–10
–15
–20
–25
–30
NO MATCHING
ELEMENTS
1.95GHz MATCH
(3.3nH + 1.5pF)
100
1000
10000
FREQUENCY (MHz)
9013 F03
Figure 3. RF Input Return Loss with External Matching
Table 1. RF Input Impedance
EXTERNAL
MATCHING
LTM9013
NETWORK FOR
LOW BAND AND
MID BAND
FREQUENCY MAGNITUDE
PHASE
R
X
RF
INPUT
TO I-MIXER
C19
500MHz
600MHz
0.96
0.93
0.90
0.81
0.70
0.74
0.78
0.82
0.81
0.83
0.83
0.83
0.84
0.83
0.84
0.81
0.81
0.78
0.75
0.73
0.68
0.66
0.63
0.62
0.61
0.59
41.2
92.3Ω
85.3Ω
76.0Ω
66.9Ω
49.4Ω
34.8Ω
25.9Ω
20.4Ω
16.8Ω
13.2Ω
11.0Ω
7.9Ω
–95.4Ω
–62.0Ω
–36.0Ω
–17.6Ω
0.4Ω
L5
RF
50.6
C20
C21
700MHz
61.3
TO Q-MIXER
800MHz
71.3
900MHz
90.7
1000MHz
1100MHz
1200MHz
1300MHz
1400MHz
1500MHz
1600MHz
1700MHz
1800MHz
1900MHz
2000MHz
2100MHz
2200MHz
2300MHz
2400MHz
2500MHz
2600MHz
2700MHz
2800MHz
2900MHz
3000MHz
109.6
122.1
130.2
136.9
143.6
149.0
157.2
165.3
175.9
–173.1
–161.6
–150.2
–141.5
–132.7
–129.9
–126.8
–128.6
–129.1
–126.9
–124.9
–117.7
8.5Ω
9013 F02
11.2Ω
12.1Ω
11.6Ω
10.9Ω
9.7Ω
Figure 2. RF Input Interface
The RF input port is internally matched over a wide fre-
quency range from 1.5GHz to 2.7GHz with input return
loss typically better than 10dB. No external matching
network is needed for this frequency range. When the
part is operated at lower frequencies, however, the input
return loss can be improved with the matching network
shown in Figure 2. Shunt capacitors C20, C21 and series
inductor L5 can be selected for optimum input impedance
matchingatthedesiredfrequencyasillustratedinFigure3.
C19 serves as a series DC blocking capacitor.
7.7Ω
5.8Ω
5.2Ω
4.7Ω
1.5Ω
4.8Ω
–2.5Ω
–6.2Ω
–9.2Ω
–10.5Ω
–10.9Ω
–10.6Ω
–9.7Ω
–9.4Ω
–8.8Ω
–8.6Ω
–8.5Ω
–7.6Ω
7.3Ω
10.9Ω
15.2Ω
20.2Ω
22.2Ω
24.9Ω
24.3Ω
24.8Ω
26.0Ω
27.2Ω
31.5Ω
The RF input impedance and S11 parameters (without
external matching components) are listed in Table 1.
9013f
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LTM9013
APPLICATIONS INFORMATION
LO Input Port
0
–5
The mixer’s LO input interface is shown in Figure 4. The
input consists of a precision quadrature phase shifter
which generates 0° and 90° phase-shifted LO signals for
the LO buffer amplifiers driving the I/Q mixers. Under no
circumstances should an external DC voltage be applied
to the input pin. DC current flowing into the primary side
of the transformer may damage the transformer.
–10
–15
–20
–25
–30
NO MATCHING
ELEMENTS
1.8GHz MATCH
(0.5pF + 6.8nH)
LTM9013
LO
INPUT
100
1000
FREQUENCY (MHz)
10000
T1
C22
LO–
LO+
9013 F05
LO QUADRATURE
GENERATOR AND
BUFFER AMPLIFIERS
C24
Figure 5. LO Input Return Loss with External Matching
Table 2. LO Input Impedance
FREQUENCY MAGNITUDE
PHASE
–70.3
–83.9
–97.1
–119.8
–144.9
–177.8
146.5
115.0
87.9
R
X
9013 F04
500MHz
600MHz
0.71
0.66
0.66
0.62
0.55
0.51
0.48
0.52
0.57
0.62
0.66
0.67
0.69
0.67
0.66
0.61
0.55
0.46
0.34
0.30
0.33
0.42
0.51
0.53
0.52
0.33
67.7Ω
55.0Ω
44.5Ω
29.8Ω
20.2Ω
16.1Ω
22.2Ω
34.3Ω
51.6Ω
66.9Ω
84.7Ω
101.4Ω
123.7Ω
154.8Ω
193.5Ω
206.9Ω
163.1Ω
101.7Ω
65.5Ω
40.0Ω
25.8Ω
21.4Ω
23.1Ω
31.4Ω
42.2Ω
45.9Ω
15.5Ω
3.6Ω
Figure 4. LO Input Interface
700MHz
–3.3Ω
–8.3Ω
–6.5Ω
–0.4Ω
5.3Ω
The LO input port is internally matched over a wide fre-
quency range from 1.5GHz to 2.7GHz with input return
loss typically better than 10dB. No external matching
network is needed for this frequency range. The LO input
impedanceandS11parameters(withoutexternalmatching
components) are listed in Table 2. Outside this frequency
range, theimpedancematchcanbeimprovedusingseries
capacitor C22 and shunt capacitor C24.
800MHz
900MHz
1000MHz
1100MHz
1200MHz
1300MHz
1400MHz
1500MHz
1600MHz
1700MHz
1800MHz
1900MHz
2000MHz
2100MHz
2200MHz
2300MHz
2400MHz
2500MHz
2600MHz
2700MHz
2800MHz
2900MHz
3000MHz
6.1Ω
–0.9Ω
–12.4Ω
–30.5Ω
–46.6Ω
–67.4Ω
–75.6Ω
–70.8Ω
–10.8Ω
24.2Ω
21.3Ω
5.5Ω
70.5
55.0
44.0
34.1
24.3
15.5
2.5
–10.2
–34.3
–63.8
–113.3
–164.3
164.8
140.5
120.3
101.7
98.1
–2.5Ω
–1.6Ω
2.2Ω
6.3Ω
6.7Ω
3.6Ω
1.3Ω
9013f
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LTM9013
APPLICATIONS INFORMATION
IM2 Adjustment Circuitry
IF Input Port Characteristics
The LTM9013 also contains circuitry for the independent
adjustment of IM2 levels on the I and Q channels. When
the EIP2 pin is a logic high, this circuitry is enabled and
the IP2I and IP2Q analog control voltage inputs are able
to adjust the IM2 level. The IM2 level can be effectively
minimized over a large range of the baseband bandwidth.
The circuitry has an effective baseband frequency upper
limit of about 200MHz. Any IM2 component that falls in
this frequency range can be minimized.
The amplifier inputs provide a nominal 50Ω differential
input impedance over the operating frequency range.
The input impedance characteristic derives from the dif-
ferential attenuator ladder. The internal circuit controls the
IF connections to this attenuator ladder and generates the
appropriate common mode DC voltage.
Enable/Shutdown
through
BoththeENandSHDNpinsareself-biasedtoV
CC2
their respective 100k pull-up resistors, so the default
open-pin state is powered on with the output amplifier
signal path disabled. Pulling the EN pin low completes the
signal path from the attenuator ladder through the output
amplifier. The EN pin essentially provides a fast muting
function while the SHDN pin provides slower power on/
off function.
Variable Gain Amplifier
The LTM9013 includes a high linearity, fully-differential
analog-controlled variable-gain amplifier (VGA) opti-
mized for application frequencies in the range of 1MHz to
500MHz. The VGA architecture provides a constant OIP3
and constant output noise level (NF + Gain) over the 31dB
gain-control range and thus exhibits a uniform spurious-
free dynamic range (SFDR) over gain. This constant SFDR
characteristic is ideal for use in receiver IF chains.
For applications requiring the SHDN function, it is recom-
mended that the output amplifier signal path be disabled
with a high EN voltage before transitioning the SHDN
signal. When enabling the amplifier, allow at least 5ms
dwell time between the rising SHDN transition and the
falling EN transition to avoid non-monotonic output signal
behavior though the VGA. The opposite delay sequence
is recommended for the falling SHDN transition, but this
is less critical as the output signal amplitude will drop
abruptly regardless of the EN pin.
Gain Characteristics
The LTM9013 provides a continuously adjustable gain of
31dB that is linear-in-dB with respect to the control volt-
ages appliedto GAIN_IandGAIN_Q. Inthisway, apositive
gain-control slope is easily achieved:
Apply gain control voltage to the GAIN_I/GAIN_Q pins.
Gain increases with increasing GAIN_I/GAIN_Q voltage.
SHDN
Whenconnectedinthistypicalsingle-endedconfiguration,
the active control input range extends from 0.1V to 1.1V.
This control input range can be extended using a resistor
divider with a suitably low output resistance. For example,
two series resistors of 1k each would extend the control
input range from 0.2V to 2.2V while providing an effective
500Ω Thevinin equivalent source resistance, a relatively
small loading effect compared to the 10k input resistance
of the GAIN_I/GAIN_Q terminals.
t
t
DWELL
DWELL
9013 F06
EN
Figure 6
9013f
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LTM9013
APPLICATIONS INFORMATION
ESD
Encode Input
The signal quality of the encode inputs strongly affects
the A/D noise performance. The encode inputs should
be treated as analog signals—do not route them next to
digital traces on the circuit board.
The amplifier inputs are protected with reverse-biased
ESD diodes on all pins. If any pin is forced one diode drop
above the positive supply or one diode drop below the
negative supply, then large currents may flow through the
diodes. No damage to the devices will occur if the current
is kept below 10mA.
The encode inputs are internally biased to 1.2V through
10k equivalent resistance (Figure 8). If the common mode
of the driver is within 1.1V to 1.5V, it is possible to drive
the encode inputs directly. Otherwise a transformer or
coupling capacitors are needed (Figures 9 and 10). The
maximum (peak) voltage of the input signal should never
Reference
The LTM9013 has an internal 1.25V voltage reference for
the ADC. For a 1.32V input range with internal reference,
connect SENSE to V . For a 1.32V input range with an
exceed V + 0.1V or go below –0.1V.
DD
DD
external reference, apply a 1.25V reference voltage to
SENSE (Figure 7). Apply a 1.15V reference voltage to
SENSE to achieve specified performance.
LTM9013
5Ω
V
REF
1.25V
0.1µF
SCALER/
BUFFER
ADC
REFERENCE
SENSE
SENSE
DETECTOR
9013 F07
Figure 7. Reference Circuit
LTM9013
V
DD
1.2V
10k
+
–
CLK
CLK
9013 F08
Figure 8. Equivalent Encode Input Circuit
9013f
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LTM9013
APPLICATIONS INFORMATION
LTM9013
V
DD
1.2V
10k
0.1µF
50Ω
100Ω
0.1µF
50Ω
T1: MACOM
ETC1-1-13
9013 F09
Figure 9. Sinusoidal Encode Circuit
DIGITAL OUTPUTS
LTM9013
V
DD
The digital outputs are double data rate LVDS signals. Two
data bits are multiplexed and output on each differential
output pair. There are seven LVDS output pairs for chan-
1.2V
+
–
–
+
nel A (DA0_1 /DA0_1 through DA12_13 /DA12_13 )
0.1µF
0.1µF
10k
+
–
+
–
CLK
and seven pairs for channel B (DB0_1 /DB0_1 through
–
+
+
–
DB12_13 /DB12_13 ). Overflow (OF /OF ) and the data
output clock (CLKOUT /CLKOUT ) each have an LVDS
output pair. Note that overflow for both channels is mul-
+
–
PECL OR
LVDS INPUT
100Ω
CLK
+
–
tiplexed onto the OF /OF output pair.
9013 F10
By default the outputs are standard LVDS levels: 3.5mA
output current and a 1.25V output common mode volt-
age. An external 100Ω differential termination resistor
is required for each LVDS output pair. The termination
resistors should be located as close as possible to the
LVDS receiver.
Figure 10. PECL or LVDS Encode Drive
Clock Duty Cycle Stabilizer
For good performance the encode signal should have a
50% ( 5%) duty cycle. If the optional clock duty cycle
stabilizer circuit is enabled, the encode duty cycle can
vary from 30% to 70% and the duty cycle stabilizer will
maintainaconstant50%internaldutycycle.Thedutycycle
stabilizer is enabled via SPI Register A2 (see Table 5) or
by CS in parallel programming mode.
Programmable LVDS Output Current
The default output driver current is 3.5mA. This current
can be adjusted by serially programming mode control
register A3 (see Table 5). Available current levels are
1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.
Forapplicationswherethesamplerateneedstobechanged
quickly, the clock duty cycle stabilizer can be disabled. In
this cases care should be taken to make the clock a 50%
( 5%) duty cycle.
9013f
20
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LTM9013
APPLICATIONS INFORMATION
Optional LVDS Driver Internal Termination
Phase Shifting the Output Clock
In most cases, using just an external 100Ω termination
resistor will give excellent LVDS signal integrity. In addi-
tion, an optional internal 100Ω termination resistor can
beenabledbyseriallyprogrammingmodecontrolregister
A3. The internal termination helps absorb any reflections
caused by imperfect termination at the receiver. When the
internal termination is enabled, the output driver current
is doubled to maintain the same output voltage swing.
To allow adequate set-up and hold time when latching the
+
output data, the CLKOUT signal may need to be phase
shifted relative to the data output bits. Most FPGAs have
this feature; this is generally the best place to adjust the
timing.
+
Alternatively, the ADC can also phase shift the CLKOUT /
–
CLKOUT signals by serially programming mode control
register A2. The output clock can be shifted by 0°, 45°,
90°, or 135°. To use the phase shifting feature the clock
duty cycle stabilizer must be turned on. Another con-
Overflow Bit
+
The overflow output bit (OF) outputs a logic high when
the analog input is either overranged or underranged. The
overflow bit has the same pipeline latency as the data bits.
trol register bit can invert the polarity of CLKOUT and
–
CLKOUT , independently of the phase shift. The combina-
tion of these two features enables phase shifts of 45° up
to 315° (Figure 11).
+
+
The OF output is double data rate; when CLKOUT is low,
channel A’s overflow is available; when CLKOUT is high,
channel B’s overflow is available.
+
CLK
D0-D13, OF
MODE CONTROL BITS
PHASE
SHIFT
CLKINV
0
CLKPHASE1 CLKPHASE0
0°
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
45°
90°
0
0
0
1
1
1
1
135°
180°
225°
270°
315°
+
CLKOUT
9013 F11
Figure 11. Phase Shifting CLKOUT
9013f
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LTM9013
APPLICATIONS INFORMATION
DATA FORMAT
CLKOUT
CLKOUT
OF
Table 3 shows the relationship between the analog input
voltage, the digital data output bits and the overflow bit.
By default the output data format is offset binary. The 2’s
complement format can be selected by serially program-
ming mode control register A4.
OF
D13
D13/D0
D12/D0
D12
Table 3. Output Codes vs Input Level
•
•
•
D13-D0
D13-D0
RANDOMIZER
ON
+IN – –IN
+Overflow
+Full Scale
OF
1
(OFFSET BINARY)
(2’s COMPLEMENT)
D1
11 1111 1111 1111
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
01 1111 1111 1110
00 0000 0000 0001
00 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1110
10 0000 0000 0001
10 0000 0000 0000
10 0000 0000 0000
D1/D0
D0
0
0
D0
0
9013 F12
Mid-Scale
0
0
Figure 12. Functional Equivalent of Digital Output Randomizer
0
–Full Scale
–Overflow
0
PC BOARD
0
FPGA
CLKOUT
1
OF
Digital Output Randomizer
D13/D0
Interference from the A/D digital outputs is sometimes
unavoidable.Digitalinterferencemaybefromcapacitiveor
inductive coupling or coupling through the ground plane.
Even a tiny coupling factor can cause unwanted tones
in the ADC output spectrum. By randomizing the digital
output before it is transmitted off chip, these unwanted
tones can be randomized which reduces the unwanted
tone amplitude.
LTM9013
D13
D12
D12/D0
D1/D0
D0
•
•
•
D1
D0
The digital output is randomized by applying an exclu-
sive-OR logic operation between the LSB and all other
data output bits. To decode, the reverse operation is
applied—an exclusive-OR operation is applied between
the LSB and all other bits. The LSB, OF and CLKOUT out-
puts are not affected. The output randomizer is enabled
by serially programming mode control register A4.
9013 F13
Figure 13. Decoding a Randomized Digital Output Signal
9013f
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LTM9013
APPLICATIONS INFORMATION
Alternate Bit Polarity
Output Disable
Another feature that may reduce digital feedback on the
circuit board is the alternate bit polarity mode. When this
mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,
D11, D13)areinvertedbeforetheoutputbuffers. Theeven
bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are
not affected. This can reduce digital currents in the circuit
board ground plane and reduce digital noise, particularly
for very small analog input signals.
The digital outputs may be disabled by serially program-
ming mode control register A3. All digital outputs includ-
ing OF and CLKOUT are disabled. The high impedance
disabled state is intended for long periods of inactivity,
it is not designed for multiplexing the data bus between
multiple converters.
Sleep Mode
The A/D may be placed in sleep mode to conserve power.
In sleep mode the entire A/D converter is powered down,
resulting in <5mW power consumption. If the encode
input signal is not disabled the power consumption will be
higher (up to 5mW at 250Msps). Sleep mode is enabled
by mode control register A1 (serial programming mode),
or by SCK (parallel programming mode).
The digital output is decoded at the receiver by inverting
the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate
bit polarity mode is independent of the digital output ran-
domizer—either both or neither function can be on at the
same time. The alternate bit polarity mode is enabled by
serially programming mode control register A4.
Digital Output Test Patterns
In the serial programming mode it is also possible to dis-
ablechannelBwhileleavingchannelAinnormaloperation.
To allow in-circuit testing of the digital interface to the
A/D, there are several test modes that force the A/D data
outputs (OF, D13 to D0) to known values:
The amount of time required to recover from sleep mode
. With
depends on the size of the bypass capacitor on V
REF
the 2.2µF value used internally, the A/D will stabilize after
All 1s: All outputs are 1
All 0s: All outputs are 0
0.1ms + 2500 • t where t is the period of the sampling
p
p
clock.
Alternating: Outputs change from all 1s to all 0s on
alternating samples
Nap Mode
In nap mode the A/D core is powered down while the inter-
nal reference circuits stay active, allowing faster wakeup.
Recovering from nap mode requires at least 100 clock
cycles. Nap mode is enabled by power-down register A1
in the serial programming mode.
Checkerboard:Outputschangefrom101010101010101
to 010101010101010 on alternating samples.
The digital output test patterns are enabled by serially
programming mode control register A4. When enabled,
the test patterns override all other formatting modes:
2’s complement, randomizer, alternate-bit polarity.
Wake-up time from nap mode is guaranteed only if the
clock is kept running, otherwise Power-Down Wake-up
conditions apply.
9013f
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LTM9013
APPLICATIONS INFORMATION
DEVICE PROGRAMMING MODES
Serial data transfer starts when CS is taken low. The data
on the SDI pin is latched at the first sixteen rising edges
of SCK. Any SCK rising edges after the first sixteen are
ignored.ThedatatransferendswhenCSistakenhighagain.
The operating modes of the A/D can be programmed by
either a parallel interface or a simple serial interface. The
serial interface has more flexibility and can program all
available modes. The parallel interface is more limited and
canonlyprogramsomeofthemorecommonlyusedmodes.
The first bit of the 16-bit input word is the R/W bit. The
next seven bits are the address of the register (A6:A0).
The final eight bits are the register data (D7:D0).
Parallel Programming Mode
If the R/W bit is low, the serial data (D7:D0) will be writ-
ten to the register set by the address bits (A6:A0). If the
R/W bit is high, data in the register set by the address bits
(A6:A0) will be read back on the SDO pin (see the Timing
Diagrams). During a readback command the register is
not updated and data on SDI is ignored.
To use the parallel programming mode, PAR/SER should
be tied to V . The CS, SCK and SDI pins are binary logic
DD
inputs that set certain operating modes. These pins can
be tied to V or ground, or driven by 1.8V, 2.5V, or 3.3V
DD
CMOS logic. Table 4 shows the modes set by CS, SCK
and SDI.
The SDO pin is an open-drain output that pulls to ground
with a 200Ω impedance. If register data is read back
through SDO, an external 2k pull-up resistor is required.
If serial data is only written and readback is not needed,
then SDO can be left floating and no pull-up resistor is
needed.Table 5showsamapofthemodecontrolregisters.
Table 4. Parallel Programming Mode Control Bits (PAR/SER = VDD
)
PIN
DESCRIPTION
CS
Clock Duty Cycle Stabilizer Control Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
SCK
SDI
Power Down Control Bit
0 = Normal Operation
1 = Sleep Mode (entire ADC is powered down)
Software Reset
LVDS Current Selection Bit
If serial programming is used, the mode control registers
shouldbeprogrammedassoonaspossibleafterthepower
supplies turn on and are stable. The first serial command
must be a software reset which will reset all register data
bits to logic 0. To perform a software reset it is neces-
sary to write 1 in register A0 (Bit D7). After the reset is
complete, Bit D7 is automatically set back to zero. This
register is write-only.
0 = 3.5mA LVDS Current Mode
1 = 1.75mA LVDS Current Mode
Serial Programming Mode
To use the serial programming mode, PAR/SER should be
tied to ground. The CS, SCK, SDI and SDO pins become
a serial interface that program the A/D control registers.
Data is written to a register with a 16-bit serial word. Data
can also be read back from a register to verify its contents.
9013f
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LTM9013
APPLICATIONS INFORMATION
Table 5. Serial Programming Mode Register Map (PAR/SER = GND). X Indicates Unused Bit
REGISTER A0: RESET REGISTER (ADDRESS 00h) Write Only
D7
D6
X
D5
D4
X
D3
X
D2
X
D1
X
D0
X
RESET
X
Bit 7
RESET
0 = Reset Disabled
Software Reset Bit
1 = Software Reset. All mode control registers are reset to 00h. This bit is automatically set back to zero after the reset is complete.
Bits 6-0
Unused Bits
REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)
D7
X
D6
X
D5
X
D4
X
D3
D2
D1
D0
0
SLEEP
NAP
PDB
Bits 7-4
Unused, this bit read back as 0
Bit 3
SLEEP
0 = Normal Operation
1 = Power Down Entire ADC
Bit 2
NAP
0 = Normal Mode
1 = Low Power Mode for Both Channels
PDB
Bit 1
Bit 0
0 = Normal Operation
1 = Power Down Channel B. Channel A operates normally.
Must be set to 0
REGISTER A2: TIMING REGISTER (ADDRESS 02h)
D7
X
D6
X
D5
X
D4
X
D3
D2
D1
D0
CLKINV
CLKPHASE1
CLKPHASE0
DCS
Bits 7-4
Unused, This Bit Read Back as 0
Bit 3
CLKINV Output Clock Invert Bit
0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)
1 = Inverted CLKOUT Polarity
Bits 2-1
CLKPHASE1:CLKPHASE0 Output Clock Phase Delay Bits
00 = No CLKOUT Delay (as shown in the Timing Diagrams)
+
+
+
–
–
–
01 = CLKOUT /CLKOUT delayed by 45° (Clock Period • 1/8)
10 = CLKOUT /CLKOUT delayed by 90° (Clock Period • 1/4)
11 = CLKOUT /CLKOUT delayed by 135° (Clock Period • 3/8)
Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.
Bit 0
DCS Clock Duty Cycle Stabilizer Bit
0 = Clock Duty Cycle Stabilizer Off
1 = Clock Duty Cycle Stabilizer On
9013f
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LTM9013
APPLICATIONS INFORMATION
REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)
D7
X
D6
X
D5
X
D4
D3
D2
D1
D0
ILVDS2
ILVDS1
ILVDS0
TERMON
OUTOFF
Bits 7-5
Unused, This Bit Read Back as 0
Bits 4-2
ILVDS2:ILVDS0 LVDS Output Current Bits
000 = 3.5mA LVDS Output Driver Current
001 = 4.0mA LVDS Output Driver Current
010 = 4.5mA LVDS Output Driver Current
011 = Not Used
100 = 3.0mA LVDS Output Driver Current
101 = 2.5mA LVDS Output Driver Current
110 = 2.1mA LVDS Output Driver Current
111 = 1.75mA LVDS Output Driver Current
Bit 1
Bit 0
TERMON LVDS Internal Termination Bit
0 = Internal Termination Off
1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0
OUTOFF Digital Output Mode Control Bits
0 = Digital Outputs Are Enabled
1 = Digital Outputs Are Disabled (High Impedance)
REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)
D7
D6
D5
D4
D3
0
D2
D1
D0
OUTTEST2
OUTTEST1
OUTTEST0
ABP
DTESTON
RAND
TWOSCOMP
Bits 7-5
OUTTEST2:OUTTEST0 Digital Output Test Pattern Bits
000 = All Digital Outputs = 0
001 = All Digital Outputs = 1
010 = Alternating Output Pattern. OF, D13-D0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111
100 = Checkerboard Output Pattern. OF, D13-D0 alternate between 101 0101 0101 0101 and 010 1010 1010 1010
Note 1: Other bit combinations are not used.
Note 2: Patterns from channel A and channel B may not be synchronous.
Bit 4
ABP Alternate Bit Polarity Mode Control Bit
0 = Alternate Bit Polarity Mode Off
1 = Alternate Bit Polarity Mode On
Bit 3
Bit 2
Must Be Set to 0
DTESTON
0 = Normal Mode
1 = Enable the Digital Output Test Patterns
Enable the digital output test patterns (set by Bits 7-5)
Bit 1
Bit 0
RAND Data Output Randomizer Mode Control Bit
0 = Data Output Randomizer Mode Off
1 = Data Output Randomizer Mode On
TWOSCOMP Two’s Complement Mode Control Bit
0 = Offset Binary Data Format
1 = Two’s Complement Data Format
9013f
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LTM9013
APPLICATIONS INFORMATION
Design Examples
0
The LTM9013 allows the user to tailor the highpass corner
frequencytosuittheapplication.The0.5dBlowpasscorner
is set by the internal network at 300MHz. By cascading
the external highpass and internal lowpass networks a
bandpass characteristic is realized. An example of a very
low frequency highpass corner is shown in Figure 14.
–1
–2
–3
–4
–5
–6
The typical performance for the overall module is shown
below:
0
50 100 150 200 250 300 350 400 450 500
BASEBAND FREQUENCY (MHz)
IF passband (1.5dB): 1MHz to 300MHz
RF input for –1dBFS: –5dBm at maximum gain
SNR at –1dBFS: 59.1dB
9013 F15
Figure 15. Baseband Frequency Response
HD2 at –1dBFS: 74dBc
IMD3 at –7dBFS per tone: –72dBc
The frequency response is shown in Figure 15:
15nH
100Ω
0.01µF
0.01µF
5V
6.8pF
100Ω
V
V
V
15nH
CC1
CC2
DD
5V
3.3V
1.8V
LTM9013
GAIN_Q GAIN_I
OV
DD
1.8V
ADC
ADC
CLKOUT
0°
ADC CLK
OF
LNA
90°
PAR/SER
GND
SCK CS SDI SDO
GND
9013 F14
LO IN
15nH
100Ω
0.01µF
0.01µF
6.8pF
15nH
5V
100Ω
Figure 14. Highpass Filter Set for 1MHz
9013f
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LTM9013
APPLICATIONS INFORMATION
For those applications that require a higher frequency
corner at the highpass point, the network can be tailored,
for example, as shown in Figure 16.
0
–0.5
–1.0
–1.5
The typical performance for the overall module is shown
below:
IF passband (1.0dB): 55MHz to 315MHz
RF input for –1dBFS: –5dBm at maximum gain
SNR at –1dBFS: 59.1dB
–2.0
–2.5
–3.0
0
50 100 150 200 250 300 350 400 450 500
BASEBAND FREQUENCY (MHz)
HD2 at –1dBFS: 74dBc
9013 F17
IMD3 at –7dBFS per tone: –72dBc
The frequency response is shown in Figure 17:
Figure 17. Baseband Frequency Response
56pF
100Ω
5V
0.01µF
180nH 150nH
56pF
0.01µF
100Ω
V
V
V
DD
1.8V
CC1
CC2
5V
3.3V
LTM9013
GAIN_Q GAIN_I
OV
DD
1.8V
ADC
CLKOUT
0°
ADC CLK
OF
LNA
90°
ADC
GND
PAR/SER
GND
SCK CS SDI SDO
9013 F16
LO IN
100Ω
56pF
180nH 150nH
56pF
0.01µF
0.01µF
5V
100Ω
Figure 16. Highpass Filter Set for 55MHz
9013f
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LTM9013
APPLICATIONS INFORMATION
Supply Sequencing
Recommended Layout
The V
CC2
pins supply voltage to the demodulator. The
The high integration of the LTM9013 makes the PCB
board layout simple. However, to optimize its electrical
and thermal performance, some layout considerations
are still necessary.
CC1
V
pins supply voltage to the amplifiers. The amplifier
output stages are also fed by the V
pins, so careful
CC1
power supply sequencing is important. Power must be
applied to the V pins before power is applied to the
CC2
• Use large PCB copper areas for ground. This helps to
dissipate heat in the package through the board and
also helps to shield sensitive on-board analog signals.
V
pins to avoid damage to the amplifiers. Note also that
CC1
the amplifiers must be enabled before voltage is applied
to the V pins for the same reason.
CC1
• Use multiple ground vias. Using as many vias as pos-
sible helps to improve the thermal performance of the
boardandcreatesnecessarybarriersseparatinganalog
and digital traces on the board at high frequencies.
Grounding and Bypassing
The LTM9013 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an
internal ground plane is recommended. The pinout of the
LTM9013 has been optimized for a flowthrough layout so
that the interaction between inputs and digital outputs is
minimized. A continuous row of ground pads facilitate a
layout that ensures that digital and analog signal lines are
separated as much as possible.
• Separate analog and digital traces as much as possible,
using vias to create high frequency barriers. This will
reduce digital feedback that can reduce the signal-to-
noise ratio (SNR) and dynamic range of the LTM9013.
Figures 18 through 25 give a good example of the recom-
mended layout.
The LTM9013 is internally bypassed with the ADC (V ),
mixer, amplifier (V ) digital (OV ) supplies returning to
a common ground (GND). Additional bypass capacitance
is optional and may be required if power supply noise is
significant.
DD
The quality of the paste print is an important factor in
producing high yield assemblies. It is recommended to
useatype3or4printingno-cleansolderpaste. Thesolder
stencildesignshouldfollowtheguidelinesoutlinedinPCB
Assembly and Manufacturing Guidelines
CC
DD
Heat Transfer
BGA Packages: Assembly Considerations for Linear Tech-
nology µModule BGA Packages.
Most of the heat generated by the LTM9013 is transferred
through the bottom-side ground pins. For good electrical
and thermal performance, it is critical that all ground pins
are connected to a ground plane of sufficient area with as
many vias as possible.
9013f
29
For more information www.linear.com/LTM9013
LTM9013
TYPICAL APPLICATIONS
3
1
3
1
O V D D
O V D D
K 1 3
E 1 3
G N D
1 1
M
G N D
1 0
M
G N D
9
M
G N D
8
M
G N D
7
M
V D D
V D D
G N D
6
J 9
F 9
M
G N D
5
M
G N D
2
M
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
L 8
L 7
L 4
L 3
L 2
L 1
K 1 2
K 1 1
K 8
K 7
K 2
J 1 4
J 1 3
J 1 2
J 1 1
J 1 0
J 8
V C C 2
1 N
V C C 2
V C C 2
V C C 2
V C C 2
V C C 2
4
1
M
M
1 C
B 1
A 4
3
1
V C C 1
S D O
G 2
J 7
1
0
L 1
J 6
S D I
S C K
S # C
3
1
L 1
J 5
L 9
J 2
K 1 0
K 9
J 1
P A R _ S E R #
G N D
3
H 1
H 1
H 1
H 1
G N D
2
G N D
1
G N D
0
I N + _ Q
N I - _
G N D
5 D
8 H
G N D
7 H
G N D
6 H
G N D
5 H
G N D
3 H
G N D
1 H
Q
E 5
I N + _ I
N I - _
K 5
L 5
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G N D
G 1 3
G 1 2
G 1 1
G 1 0
G 9
G 8
G 7
G 6
G 5
G 4
G 3
G 1
F 1 4
F 1 3
F 1 2
F 1 1
F 1 0
F 8
I
F 7
F 6
F 5
F 2
E 1 2
E 1 1
E 8
C N
C N
C N
J 4
J 3
F 3
E 7
E 4
E 3
E 2
G N D
1
D 1
I
_ T U O -
G N D
0
L 6
K 6
D 1
G N D
9 D
O + U T _ I
G N D
8 D
G N D
7 D
G N D
4 D
G N D
3 D
G N D
2 D
Q _ T U O -
E 6
O + U T _ Q
6 D
4
6
3
1
3
1
3
1
3
1
9013f
30
For more information www.linear.com/LTM9013
LTM9013
TYPICAL APPLICATIONS
G N D
G N D
G N D
G N D
V C C
V S S
8
4
3
1
S E T
S E T
4
4
4
3
1
6
9013f
31
For more information www.linear.com/LTM9013
LTM9013
TYPICAL APPLICATIONS
Figure 20. Layer 1
Figure 21. Layer 2
9013f
32
For more information www.linear.com/LTM9013
LTM9013
TYPICAL APPLICATIONS
Figure 22. Layer 3
Figure 23. Layer 4
9013f
33
For more information www.linear.com/LTM9013
LTM9013
TYPICAL APPLICATIONS
Figure 24. Layer 5
Figure 25. Layer 6
9013f
34
For more information www.linear.com/LTM9013
LTM9013
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
Z
/ / b b b
Z
6 . 5 0
5 . 5 0
4 . 5 0
3 . 5 0
2 . 5 0
1 . 5 0
0 . 5 0
0 . 5 0
1 . 5 0
2 . 5 0
3 . 5 0
4 . 5 0
5 . 5 0
6 . 5 0
0 . 0 0
6 . 2 0
6 . 8 0
9013f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
35
LTM9013
TYPICAL APPLICATION
Block Diagram for IM2 Adjustment. Only the I-Channel Is Shown
DSP
1-D
MINIMIZATION
ALGORITHM
DAC
ADC
IP2I
LTM9013
1MHz BPF
LNA
RMS
DETECTION
f
LO
= 1990MHz
LOOPBACK
LTC5588-1
f1 = 20MHz
f2 = 21MHz
+
DAC
PA
9013 TA02
RELATED PARTS
PART NUMBER
ADCs
DESCRIPTION
COMMENTS
LTC2208
16-Bit, 130Msps, 3.3V ADC, LVDS Outputs
1250mW, 77.7dB SNR, 100dB SFDR, 64-Lead QFN Package
LTC2157-14/ LTC2156-14/ 14-Bit, 250Msps/210Msps/170Msps,
LTC2155-14 1.8V Dual ADC, DDR LVDS Outputs
605mW/565mW/511mW, 70dB SNR, 90dB SFDR, 9mm × 9mm
64-Lead QFN Package
LTC2152-14/LTC2151-14/ 14-Bit, 250Msps/210Msps/170Msps,
338mW/316mW/290mW, 70dB SNR, 90dB SFDR, 6mm × 6mm
40-Lead QFN Package
LTC2150-14
1.8V Single ADC, DDR LVDS Outputs
LTC2158-14
14-Bit, 310Msps 1.8V Dual ADC, DDR LVDS Outputs,
Low Power
724mW, 68.8dB SNR, 88dB SFDR, 9mm × 9mm 64-Lead
QFN Package
RF Mixers/Demodulators
LT5517
40MHz to 900MHz Direct Conversion Quadrature
Demodulator
High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator
LT5527
LT5575
400MHz to 3.7GHz High Linearity Downconverting Mixer 24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,
50Ω Single-Ended RF and LO Ports
800MHz to 2.7GHz Direct Conversion Quadrature
Demodulator
High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator,
Integrated RF and LO Transformer
Amplifiers/Filters
LTC6409
10GHz GBW, 1.1nV/√Hz Differential Amplifier/ADC Driver 88dB SFDR at 100MHz, Input Range Includes Ground 52mA
Supply Current, 3mm × 2mm QFN Package
LTC6412
800MHz, 31dB Range, Analog-Controlled Variable
Gain Amplifier
Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz,
10dB Noise Figure, 4mm × 4mm QFN-24 Package
LTC6420-20
1.8GHz Dual Low Noise, Low Distortion Differential ADC Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply
Drivers for 300MHz IF
Current per Amplifier, 3mm × 4mm QFN-20 Package
Receiver Subsystems
LTM9002
14-Bit Dual Channel IF/Baseband Receiver Subsystem
12-Bit Digital Pre-Distortion Receiver
Integrated High Speed ADC, Passive Filters and Fixed Gain
Differential Amplifiers
LTM9003
Integrated 12-Bit ADC Down-Converter Mixer with 0.4GHz to
3.8GHz Input Frequency Range
9013f
LT 0313 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
36
(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTM9013
●
●
LINEAR TECHNOLOGY CORPORATION 2013
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