LTC2150-14_15_技术文档

LTC2152-14/

LTC2151-14/LTC2150-14

14-Bit 250Msps/

210Msps/170Msps ADCs

FEATURES

DESCRIPTION

n

70dB SNR

TheLTC^®2152-14/LTC2151-14/LTC2150-14are250Msps/

210Msps/170Msps 14-bit A/D converters designed for

digitizing high frequency, wide dynamic range signals.

They are perfect for demanding communications applica-

tions with AC performance that includes 70dB SNR and

90dB spurious free dynamic range (SFDR). The 1.25GHz

input bandwidth allows the ADC to undersample high

frequencies with good performance. The latency is only

six clock cycles.

n

90dB SFDR

Low Power: 356mW/338mW/313mW Total

Single 1.8V Supply

DDR LVDS Outputs

n

Easy-to-Drive 1.5V Input Range

P-P

1.25GHz Full Power Bandwidth S/H

Optional Clock Duty Cycle Stabilizer

Low Power Sleep and Nap Modes

Serial SPI Port for Conﬁguration

Pin Compatible 12-Bit Versions

40-Pin (6mm × 6mm) QFN Package

DCspecsinclude 0.85LSBINL(typ), 0.25LSBDNL(typ)

and no missing codes over temperature. The transition

noise is 1.82LSB

.

RMS

The digital outputs are double-data rate (DDR) LVDS.

APPLICATIONS

+

–

n

The ENC and ENC inputs can be driven differentially with

asinewave,PECL,LVDS,TTL,orCMOSinputs.Anoptional

clock duty cycle stabilizer allows high performance at full

speed for a wide range of clock duty cycles.

Communications

Cellular Basestations

Software Deﬁned Radios

Medical Imaging

High Deﬁnition Video

Testing and Measurement Instruments

L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION

LTC2152-14: 32K Point FFT,

f_IN= 15MHz, –1dBFS, 250Msps

V

DD

0

OV

DD

–20

–40

D12_13

14-BIT

PIPELINED

ADC

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

DDR

LVDS

S/H

•

D0_1

–60

–80

OGND

CLOCK/DUTY

CYCLE

CONTROL

CLOCK

–100

–120

21521014 TA01a

0

40

60

80

100 120

20

FREQUENCY (MHz)

21521014 TA01b

21521014fa

1

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION

(Notes 1, 2)

TOP VIEW

Supply Voltage

V , OV ................................................ –0.3V to 2V

DD

Analog Input Voltage

+

–

A

, A , PAR/SER,

40 39 38 37 36 35 34 33 32 31

IN

SENSE (Note 3)........................ –0.3V to (V + 0.2V)

V

1

2

3

4

5

6

7

8

9

30

29

28

OV

DD

+

DD

D8_9

Digital Input Voltage

DD

–

+

–

GND

+

ENC , ENC (Note 3)................ –0.3V to (V + 0.3V)

DD

+

–

A

27 CLKOUT

IN

CS, SDI, SCK (Note 4)........................... –0.3V to 3.9V

–

A

26 CLKOUT

+

IN

GND

41

SDO (Note 4)............................................. –0.3V to 3.9V

GND

SENSE

VREF

25

D6_7

Digital Output Voltage................ –0.3V to (OV + 0.3V)

–

+

–

DD

24 D6_7

23

Operating Temperature Range

D4_5

22 D4_5

LTC2152C, LTC2151C, LTC2150C............. 0°C to 70°C

LTC2152I, LTC2151I, LTC2150I ............–40°C to 85°C

Storage Temperature Range .................. –65°C to 150°C

VCM

GND 10

21

OGND

11 12 13 14 15 16 17 18 19 20

UJ PACKAGE

40-LEAD (6mm × 6mm) PLASTIC QFN

T

JMAX

= 150°C, θ = 34.1°C/W

JA

EXPOSED PAD (PIN 41) IS GND, MUST BE SOLDERED TO PCB

ORDER INFORMATION

LEAD FREE FINISH

LTC2152CUJ-14#PBF

LTC2152IUJ-14#PBF

LTC2151CUJ-14#PBF

LTC2151IUJ-14#PBF

LTC2150CUJ-14#PBF

LTC2150IUJ-14#PBF

TAPE AND REEL

LTC2152CUJ-14#TRPBF LTC2152UJ-14

LTC2152IUJ-14#TRPBF LTC2152UJ-14

LTC2151CUJ-14#TRPBF LTC2151UJ-14

LTC2151IUJ-14#TRPBF LTC2151UJ-14

LTC2150CUJ-14#TRPBF LTC2150UJ-14

LTC2150IUJ-14#TRPBF LTC2150UJ-14

PART MARKING*

PACKAGE DESCRIPTION

TEMPERATURE RANGE

0°C to 70°C

40-Lead (6mm × 6mm) Plastic QFN

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

0°C to 70°C

–40°C to 85°C

Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping

container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

21521014fa

2

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

CONVERTER CHARACTERISTICS _{The l denotes the specifications which apply over the full operating}

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

LTC2152-14

TYP

LTC2151-14

TYP

LTC2150-14

MIN TYP MAX

PARAMETER

CONDITIONS

MIN

14

MAX

MIN

14

MAX

UNITS

Bits

l

Resolution (No Missing Codes)

Integral Linearity Error

Differential Linearity Error

Offset Error

14

–5.1

–0.9

–13

–4

Differential Analog Input (Note 6)

Differential Analog Input

(Note 7)

–5.5

–0.9

–13

–4

0.85

0.25

5

5.5

0.9

13

3

–5.1

–0.9

–13

–4

1

0.25

5

5.1

0.9

13

3

1

5.1

LSB

0.25 0.9

LSB

3

1

13

3

mV

Gain Error

External Reference

1

%FS

µV/°C

Offset Drift

20

Full-Scale Drift

Internal Reference

External Reference

30

10

30

10

30

10

ppm/°C

Transition Noise

External Reference

1.82

LSB

RMS

ANALOG INPUT ^Thel denotes the specifications which apply over the full operating temperature range, otherwise

specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

1.7V < V < 1.9V

MIN

TYP

MAX

UNITS

+

–

l

V

Analog Input Range (A – A

)

1.5

V

P-P

IN

DD

+

–

Analog Input Common Mode (A + A )/2 Differential Analog Input (Note 8)

V

– 20mV

V

CM

V + 20mV

CM

V

IN(CM)

SENSE

IN

CM

External Reference Mode

1.200

–1

1.250

1.300

V

µA

ns

+

–

I

t

Analog Input Leakage Current

SENSE Input Leakage Current

0 < A , A < V No Encode

1

IN1

IN

DD

1.2V < SENSE < 1.3V

0 < PAR/SER < V

–1

IN2

PAR/SER Input Leakage Current

–1

IN3

DD

Sample-and-Hold Acquisition Delay Time

Sample-and-Hold Acquisition Delay Jitter

Analog Input Common Mode Rejection Ratio

Full-Power Bandwidth

1

AP

0.15

75

ps

RMS

JITTER

CMRR

BW-3B

dB

1250

MHz

DYNAMIC ACCURACY ^Thel denotes the specifications which apply over the full operating temperature range,

otherwise specifications are at T_A= 25°C. A_IN= –1dBFS. (Note 5)

LTC2152-14

TYP

LTC2151-14

TYP

LTC2150-14

TYP MAX UNITS

SYMBOL

PARAMETER

CONDITIONS

MIN

67.3

72

MAX

MIN

67.4

75

MAX

MIN

67.5

76

SNR

Signal-to-Noise Ratio

15MHz Input

70MHz Input

140MHz Input

70

69.7

69.3

70

69.8

69.4

70

69.8

69.5

dBFS

l

SFDR

Spurious Free Dynamic Range 15MHz Input

2nd or 3rd Harmonic

90

85

82

90

85

82

90

85

83

dBFS

70MHz Input

140MHz Input

Spurious Free Dynamic Range 15MHz Input

4th Harmonic or Higher

95

85

95

88

98

95

88

dBFS

70MHz Input

140MHz Input

81

82

83

S/(N+D)

Signal-to-Noise Plus

Distortion Ratio

15MHz Input

70MHz Input

140MHz Input

69.9

69.4

68.8

69.9

69.4

68.8

69.9

69.4

68.8

dBFS

66.7

66.8

66.9

Cross Talk Cross-Talk Between Channels Up to 315MHz Input

–95

dB

21521014fa

3

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

INTERNAL REFERENCE CHARACTERISTICS ^Thel denotes the specifications which apply over the

full operating temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

PARAMETER

CONDITIONS

= 0

MIN

TYP

MAX

UNITS

V

CM

Output Voltage

I

0.439 •

– 18mV

0.439 •

V

OUT

V

DD

V

+ 18mV

DD

V

Output Temperature Drift

Output Resistance

Output Voltage

37

4

ppm/°C

Ω

CM

–1mA < I

< 1mA

CM

OUT

I

= 0

1.225

1.250

30

1.275

V

REF

OUT

Output Temperature Drift

Output Resistance

Line Regulation

ppm/°C

Ω

–400µA < I

< 1mA

7

OUT

1.7V < V < 1.9V

0.6

mV/V

DD

POWER REQUIREMENTS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

LTC2152-14

TYP

LTC2151-14

TYP

LTC2150-14

MIN TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

(Note 9)

MIN

1.7

MAX

1.9

MIN

1.7

MAX

1.9

l

V

Analog Supply Voltage

Output Supply Voltage

Analog Supply Current

Digital Supply Current

1.8

1.7

1.8

1.9

V

DD

OV

LVDS Mode (Note 9)

1.7

1.9

1.7

1.9

DD

I

169

186

160

176

147

162

mA

VDD

OVDD

1.75mA LVDS Mode

3.5mA LVDS Mode

29

49

34.5

54.5

28

48

33.5

54

27

47

32.5

52

mA

l

P

DISS

Power Dissipation

1.75mA LVDS Mode

3.5mA LVDS Mode

356

392

397

433

338

374

377

414

313

349

350

385

mW

P

Nap Mode Power

Sleep Mode Power

Clocked at f

105

<2

98

<2

93

<2

mW

SLEEP

S(MAX)

NAP

DIGITAL INPUTS AND OUTPUTS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

CONDITIONS

MIN

TYP

MAX

UNITS

+

–

ENCODE INPUTS (ENC , ENC )

l

V

Differential Input Voltage

(Note 8)

0.2

1

1.9

V

ID

Common Mode Input Voltage

Internally Set

Externally Set (Note 8)

1.2

V

ICM

l

1.1

0.2

1.5

1.9

+

–

V

IN

Input Voltage Range

Input Resistance

Input Capacitance

ENC , ENC to GND

(See Figure 2)

(Note 8)

V

kΩ

pF

R

10

2

IN

C

DIGITAL INPUTS (CS, SDI, SCK)

l

V

High Level Input Voltage

Low Level Input Voltage

Input Current

V

= 1.8V

1.3

V

IH

IL

DD

IN

= 1.8V

0.6

10

I

IN

= 0V to 1.8V

–10

µA

pF

C

IN

Input Capacitance

(Note 8)

3

200

4

SDO OUTPUT (Open-Drain Output. Requires 2k Pull-Up Resistor if SDO Is Used)

R

Logic Low Output Resistance to GND

Logic High Output Leakage Current

Output Capacitance

V

= 1.8V, SDO = 0V

DD

Ω

µA

OL

l

I

SDO = 0V to 3.6V

(Note 8)

–10

10

OH

C

OUT

pF

21521014fa

4

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

DIGITAL INPUTS AND OUTPUTS ^Thel denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at T_A= 25°C. (Note 5)

SYMBOL PARAMETER

DIGITAL DATA OUTPUTS

CONDITIONS

MIN

TYP

MAX

UNITS

l

V

Differential Output Voltage

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

247

125

350

175

454

250

mV

OD

l

V

Common Mode Output Voltage

On-Chip Termination Resistance

100Ω Differential Load, 3.5mA Mode

100Ω Differential Load, 1.75mA Mode

1.125

1.250

100

1.375

V

Ω

OS

R

Termination Enabled, OV = 1.8V

TERM

DD

TIMING CHARACTERISTICS ^Thel denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at T_A= 25°C. (Note 5)

LTC2152-14

TYP

LTC2151-14

TYP

LTC2150-14

MIN TYP MAX UNITS

SYMBOL PARAMETER

CONDITIONS

MIN

MAX

MIN

MAX

l

f

t

Sampling Frequency

ENC Low Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

(Note 9)

10

1.9

1.5

250

50

10

2.26

1.5

210

50

10

2.79

1.5

170

50

MHz

ns

S

l

2

2.38

2.94

L

l

t

H

ENC High Time (Note 8) Duty Cycle Stabilizer Off

Duty Cycle Stabilizer On

1.9

1.5

2

50

2.26

1.5

2.38

50

2.79

1.5

2.94

50

ns

MIN

TYP

MAX

UNITS

SYMBOL PARAMETER

DIGITAL DATA OUTPUTS

CONDITIONS

l

t

ENC to Data Delay

ENC to CLKOUT Delay

DATA to CLKOUT Skew

Pipeline Latency

C = 5pF (Note 8)

1.7

1.3

0.3

6

2

2.3

2

ns

D

L

C = 5pF (Note 8)

L

1.6

0.4

C

t – t (Note 8)

0.55

6

ns

SKEW

D

C

Cycles

SPI Port Timing (Note 8)

t

SCK Period

Write Mode, C

= 20pF

SDO

40

ns

SCK

Readback Mode R

= 2k, C

= 20pF

250

PULLUP

SDO

l

t

CS to SCK Set-Up Time

SCK to CS Hold Time

SDI Set-Up Time

5

ns

S

H

DS

DH

DO

SDI Hold Time

SCK Falling to SDO Valid

Readback Mode R

125

PULLUP

SDO

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 5: V = OV = 1.8V, f

= 250MHz (LTC2152),

DD

SAMPLE

210MHz (LTC2151), or 170MHz (LTC2150), LVDS outputs, differential

+

–

ENC /ENC = 2V sine wave, input range = 1.5V with differential

P-P

drive, unless otherwise noted.

Note 2: All voltage values are with respect to GND with GND and OGND

Note 6: Integral nonlinearity is defined as the deviation of a code from a

best fit straight line to the transfer curve. The deviation is measured from

the center of the quantization band.

Note 7: Offset error is the offset voltage measured from –0.5LSB when the

output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111

in 2’s complement output mode.

shorted (unless otherwise noted).

Note 3: When these pin voltages are taken below GND or above V , they

DD

will be clamped by internal diodes. This product can handle input currents

of greater than 100mA below GND or above V without latchup.

DD

Note 4: When these pin voltages are taken below GND they will be

clamped by internal diodes. When these pin voltages are taken above V

they will not be clamped by internal diodes. This product can handle input

currents of greater than 100mA below GND without latchup.

DD

Note 8: Guaranteed by design, not subject to test.

Note 9: Recommended operating conditions.

21521014fa

5

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2152-14: Integral Nonlinearity

(INL)

LTC2152-14: Differential

Nonlinearity (DNL)

LTC2152-14: 32K Point FFT,

f_IN= 15MHz, –1dBFS, 250Msps

2.0

1.5

0

–20

0.4

0.2

1.0

–40

0.5

0

–60

–0.5

–1.0

–1.5

–2.0

–80

–0.2

–0.4

–100

–120

0

8192

12288

16383

0

8192

12288

16383

4096

0

40

60

80

100 120

20

OUTPUT CODE

FREQUENCY (MHz)

21521014 G02

21521014 G01

21521014 G03

LTC2152-14: 32K Point FFT,

f_IN= 70MHz, –1dBFS, 250Msps

LTC2152-14: 32K Point FFT,

f_IN= 122MHz, –1dBFS, 250Msps

LTC2152-14: 32K Point FFT,

f_IN= 171MHz, –1dBFS, 250Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

40

60

80

100 120

0

40

60

80

100 120

20

0

40

60

80

100 120

20

FREQUENCY (MHz)

21521014 G05

21521014 G04

21521014 G06

LTC2152-14: 32K Point FFT,

_IN= 229MHz, –1dBFS, 250Msps

LTC2152-14: 32K Point FFT,

f_IN= 381MHz, –1dBFS, 250Msps

f

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

0

40

60

80

100 120

0

40

60

80

100 120

20

FREQUENCY (MHz)

21521014 G07

21521014 G08

21521014fa

6

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2152-14: 32K Point FFT, f_IN

907MHz, –1dBFS, 250Msps

=

LTC2152-14: 32K Point FFT, f_IN

421MHz, –1dBFS, 250MHz

=

LTC2152-14: 32K Point FFT, f_IN

571MHz, –1dBFS, 250MHz

=

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

20

40

60

80

100 120

0

40

60

80

100 120

0

40

60

80

100 120

20

INPUT FREQUENCY (MHz)

21521014 G10

21521014 G09

21521014 G11

LTC2152-14: 32K Point 2-Tone

FFT, f_IN= 70.5MHz and 69.5MHz,

250Msps

LTC2152-14: I_OVDDvs Sample

Rate, 15MHz Sine Wave Input,

–1dBFS

LTC2152-14: Shorted Input

Histogram

50

45

40

35

30

25

20

15

0

–20

4000

3500

3000

2500

2000

1500

1000

500

LVDS CURRENT

3.5mA

–40

–60

LVDS CURRENT

1.75mA

–80

–100

–120

0

100

150

200

250

50

0

40

60

80

100 120

8196

8200

8208

8204

OUTPUT CODE

8212

8216

20

SAMPLE RATE (Msps)

INPUT FREQUENCY (MHz)

21521014 G12

215210 G13

21521014 G14

LTC2152-14: I_VDDvs Sample

Rate, 15MHz Sine Wave Input,

–1dBFS

LTC2152-14: SFDR vs Input

Level, f_IN= 70MHz, 1.5V Range,

250Msps

170

160

150

140

130

120

110

120

100

80

dBFS

dBc

60

40

20

0

–80

–50 –40 –30 –20 –10

AMPLITUDE (dBFS)

0

–70 –60

0

100

150

200

250

50

SAMPLE RATE (Msps)

21521014 G16

21521014 G15

21521014fa

7

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2152-14: SFDR vs Input

Frequency, –1dBFS, 1.5V Range,

250Msps

LTC2152-14: SNR vs Input Level,

f_IN= 70MHz, 1.5V Range, 250Msps

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

dBFS

dBc

200 300 400 500 600

1000

0

100

700 800 900

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–70

INPUT FREQUENCY (MHz)

21521014 G18

21521014 G17

LTC2152-14: SNR vs Input

Frequency, –1dBFS, 1.5V Range,

250Msps

LTC2152-14: Frequency Response

75

70

65

60

55

50

45

40

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–6.0

200 300 400 500 600

1000

100

1000

0

100

700 800 900

INPUT FREQUENCY (MHz)

21521014 G20

21521014 G19

21521014fa

8

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2151-14: Integral Nonlinearity

INL

LTC2151-14: Differential Nonlinearity

DNL

LTC2151-14: 32K Point FFT,

f_IN= 15MHz, –1dBFS, 210Msps

2.0

1.5

0

–20

0.4

0.2

1.0

–40

0.5

0

–60

–0.5

–1.0

–1.5

–2.0

–80

–0.2

–0.4

–100

–120

0

8192

12288

16383

4096

0

8192

12288

16383

0

40

60

80

100

4096

20

OUTPUT CODE

FREQUENCY (MHz)

21521014 G22

21521014 G21

21521014 G23

LTC2151-14: 32K Point FFT,

f_IN= 171MHz, –1dBFS, 210Msps

LTC2151-14: 32K Point FFT,

f_IN= 101MHz, –1dBFS, 210Msps

LTC2151-14: 32K Point FFT,

f_IN= 71MHz, –1dBFS, 210Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

40

60

80

100

0

40

60

80

100

20

0

40

60

80

100

20

FREQUENCY (MHz)

21521014 G24

21521014 G25

21521014 G26

LTC2151-14: 32K Point FFT,

f_IN= 227MHz, –1dBFS, 210Msps

LTC2151-14: 32K Point FFT,

f_IN= 379MHz, –1dBFS, 210Msps

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

0

40

60

80

100

20

0

40

60

80

100

20

FREQUENCY (MHz)

21521014 G27

21521014 G28

21521014fa

9

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2151-14: 32K Point FFT,

f_IN= 571MHz, –1dBFS, 210Msps

LTC2151-14: 32K Point FFT,

f_IN= 907MHz, –1dBFS, 210Msps

LTC2151-14: 32K Point FFT,

f

_IN= 417MHz, –1dBFS, 210Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

40

60

80

100

20

0

40

60

80

100

20

0

40

60

80

100

20

FREQUENCY (MHz)

21521014 G29

21521014 G30

21521014 G31

LTC2151-14: I_OVDDvs Sample

Rate, 15MHz Sine Wave Input,

–1dBFS

LTC2151-14: 32K Point 2-Tone FFT,

f_IN= 70.5MHz and 69.5MHz, 210Msps

LTC2151-14: Shorted Input

Histogram

50

45

40

35

30

25

20

15

0

–20

4000

3500

3000

2500

2000

1500

1000

500

LVDS CURRENT

3.5mA

–40

–60

LVDS CURRENT

1.75mA

–80

–100

–120

0

100

150

200

250

50

0

40

60

80

100

20

8196

8200

8208

8204

OUTPUT CODE

8212

8216

SAMPLE RATE (Msps)

FREQUENCY (MHz)

21521014 G34

215210 G33

21521014 G32

LTC2151-14: I_VDDvs Sample Rate,

15MHz Sine Wave Input, –1dBFS

LTC2151-14: SFDR vs Input Level,

f_IN= 71MHz, 1.5V Range, 210Msps

170

160

150

140

130

120

110

120

100

80

60

40

20

0

dBFS

dBc

–90 –80

–50 –40 –30 –20 –10

0

100

150

200

250

–70 –60

50

AMPLITUDE (dBFS)

SAMPLE RATE (Msps)

21521014 G36

21521014 G35

21521014fa

10

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2151-14: SFDR vs Input

Frequency, –1dBFS, 1.5V Range,

210Msps

LTC2151-14: SNR vs Input

Level, f_IN= 71MHz, 1.5V Range,

210Msps

80

90

dBFS

70

80

60

50

40

30

20

10

0

70

60

50

40

30

20

10

0

dBc

200 300 400 500 600

1000

0

100

700 800 900

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–70

INPUT FREQUENCY (MHz)

21521014 G38

21521014 G37

LTC2151-14: SNR vs Input Frequency,

–1dBFS, 1.5V Range, 210Msps

LTC2151-14: Frequency Response

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–6.0

75

70

65

60

55

50

45

40

100

1000

200 300 400 500 600

1000

0

100

700 800 900

INPUT FREQUENCY (MHz)

21521014 G40

21521014 G39

21521014fa

11

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2150-14: 32K Point FFT,

f_IN= 15MHz, –1dBFS, 170Msps

LTC2150-14: Differential

Nonlinearity DNL

LTC2150-14: Integral Nonlinearity INL

0

–20

2.0

1.5

0.4

0.2

1.0

–40

0.5

0

–60

0

–0.5

–1.0

–1.5

–2.0

–80

–0.2

–0.4

–100

–120

0

8192

12288

16383

4096

0

10 20 30 40 50 60 70 80

0

8192

12288

16383

4096

FREQUENCY (MHz)

OUTPUT CODE

21521014 G42

21521014 G43

21521014 G41

LTC2150-14: 32K Point FFT,

_IN= 70MHz, –1dBFS, 170Msps

LTC2150-14: 32K Point FFT,

f_IN= 121MHz, –1dBFS, 170Msps

f

0

–20

–40

–60

–80

0

–20

–40

–60

–80

–100

–120

–100

–120

0

10 20 30 40 50 60 70 80

FREQUENCY (MHz)

0

10 20 30 40 50 60 70 80

FREQUENCY (MHz)

21521014 G44

21521014 G45

LTC2150-14: 32K Point FFT,

f_IN= 176MHz, –1dBFS, 170Msps

f

_IN= 225MHz, –1dBFS, 170Msps

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

0

10 20 30 40 50 60 70 80

FREQUENCY (MHz)

0

10 20 30 40 50 60 70 80

FREQUENCY (MHz)

21521014 G46

21521014 G47

21521014fa

12

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2150-14: 32K Point FFT,

f_IN= 571MHz, –1dBFS, 170Msps

LTC2150-14: 32K Point FFT,

f_IN= 380MHz, –1dBFS, 170Msps

f

_IN= 420MHz, –1dBFS, 170Msps

0

–20

0

–20

0

–20

–40

–60

–80

–100

–120

–100

–120

–100

–120

0

10 20 30 40 50 60 70 80

FREQUENCY (MHz)

0

10 20 30 40 50 60 70 80

FREQUENCY (MHz)

0

10 20 30 40 50 60 70 80

FREQUENCY (MHz)

21521014 G48

21521014 G49

21521014 G50

LTC2150-14: 32K Point 2-Tone FFT,

_IN= 70.5MHz and 69.5MHz,

170Msps

f

LTC2150-14: 32K Point FFT,

LTC2150-14: Shorted Input

Histogram

f_IN= 907MHz, –1dBFS, 170Msps

0

–20

0

–20

4000

3500

3000

2500

2000

1500

1000

500

–40

–60

–80

–100

–120

–100

–120

0

10 20 30 40 50 60 70 80

FREQUENCY (MHz)

0

10 20 30 40 50 60 70 80

8196

8200

8208

8204

OUTPUT CODE

8212

8216

INPUT FREQUENCY (MHz)

21521014 G51

21521014 G52

215210 G53

LTC2150-14: I_OVDDvs Sample

Rate, 15MHz Sine Wave Input,

–1dBFS

LTC2150-14: I_VDDvs Sample Rate,

15MHz Sine Wave Input, –1dBFS

50

45

40

35

30

25

20

15

160

150

140

130

120

LVDS CURRENT

3.5mA

LVDS CURRENT

1.75mA

110

0

100

150

200

250

50

100

150

200

250

50

SAMPLE RATE (Msps)

21521014 G54

21521014 G55

21521014fa

13

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL PERFORMANCE CHARACTERISTICS

LTC2150-14: SFDR vs Input

Frequency, –1dBFS, 1.5V Range,

170Msps

LTC2150-14: SFDR vs Input Level,

LTC2150-14: SNR vs Input Level,

f_IN= 70MHz, 1.5V Range, 170Msps

80

70

60

50

40

30

20

10

0

90

80

70

60

50

40

30

20

10

0

120

100

80

60

40

20

0

dBFS

dBc

–60 –50 –40 –30 –20 –10

INPUT LEVEL (dBFS)

0

–70

–90 –80

–50 –40 –30 –20 –10

AMPLITUDE (dBFS)

0

200 300 400 500 600

1000

–70 –60

0

100

700 800 900

INPUT FREQUENCY (MHz)

21521014 G57

21521014 G56

21521014 G58

LTC2150-14: SNR vs Input

Frequency, –1dBFS, 1.5V Range,

170Msps

LTC2150-14: Frequency Response

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–6.0

75

70

65

60

55

50

45

40

100

1000

200 300 400 500 600

1000

0

100

700 800 900

INPUT FREQUENCY (MHz)

21521014 G60

21521014 G59

21521014fa

14

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

PIN FUNCTIONS

mode control registers and can be latched on the falling

edge of SCK. SDO is an open-drain N-channel MOSFET

output that requires an external 2k pull-up resistor from

1.8V to 3.3V. If readback from the mode control registers

is not needed, the pull-up resistor is not necessary and

SDO can be left unconnected.

V

(Pins 1, 2): 1.8V Analog Power Supply. Bypass to

DD

ground with 0.1µF ceramic capacitor. Pins 1, 2 can share

a bypass capacitor.

GND (Pins 3, 6, 10, 13, 35, Exposed Pad Pin 41): ADC

Power Ground. The exposed pad must be soldered to the

PCB ground.

SDI(Pin37):SerialInterfaceDataInput.Inserialprogram-

ming mode, (PAR/SER = 0V), SDI is the serial interface

data input. Data on SDI is clocked into the mode control

registersontherisingedgeofSCK.Inparallelprogramming

+

A

(Pin 4): Positive Differential Analog Input.

(Pin 5): Negative Differential Analog Input.

IN

–

SENSE (Pin 7): Reference Programming Pin. Connecting

mode (PAR/SER = V ), SDI selects 3.5mA or 1.75mA

DD

SENSE to V selects the internal reference and a 0.75V

DD

LVDS output current (see Table 2).

input range. An external reference between 1.2V and 1.3V

applied to SENSE selects an input range of 0.6 × V

.

SCK (Pin 38): Serial Interface Clock Input. In serial

programming mode, (PAR/SER = 0V), SCK is the serial

interfaceclockinput.Inparallelprogrammingmode(PAR/

SENSE

V

(Pin 8): Reference Voltage Output. Bypass to ground

REF

with a 2.2µF ceramic capacitor. Nominally 1.25V.

SER = V ), SCK controls the sleep mode (see Table 2).

DD

V

(Pin 9): Common Mode Bias Output; nominally equal

CM

CS (Pin 39): Serial Interface Chip Select Input. In serial

programming mode, (PAR/SER = 0V), CS is the serial in-

terface chip select input. When CS is low, SCK is enabled

for shifting data on SDI into the mode control registers. In

to 0.439 • V . V should be used to bias the common

DD CM

mode of the analog inputs. Bypass to ground with a 0.1µF

ceramic capacitor.

+

ENC (Pin 11): Encode Input. Conversion starts on the

parallelprogrammingmode(PAR/SER=V ),CScontrols

DD

rising edge.

the clock duty cycle stabilizer (see Table 2).

–

ENC (Pin 12): Encode Complement Input. Conversion

PAR/SER (Pin 40): Programming Mode Selection Pin.

Connect to ground to enable the serial programming

mode. CS, SCK, SDI and SDO become a serial interface

starts on the falling edge.

OV (Pins 20, 30): 1.8V Output Driver Supply. Bypass

DD

that control the A/D operating modes. Connect to V to

to ground with a 0.1µF ceramic capacitor.

DD

enabletheparallelprogrammingmodewhereCS,SCKand

SDI become parallel logic inputs that control a reduced

set of the A/D operating modes. PAR/SER should be con-

OGND (Pin 21): LVDS Driver Ground.

SDO (Pin 36): Serial Interface Data Output. In serial pro-

grammingmode,(PAR/SER=0V),SDOistheoptionalserial

interface data output. Data on SDO is read back from the

nected directly to ground or the V of the part and not

DD

be driven by a logic signal.

21521014fa

15

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

PIN FUNCTIONS

LVDS Outputs (DDR LVDS)

–

+

CLKOUT /CLKOUT (Pins 26/27): Data Output Clock.

The digital outputs normally transition at the same time

The following pins are differential LVDS outputs. The

output current level is programmable. There is an optional

internal 100Ω termination resistor between the pins of

each LVDS output pair.

+

as the falling and rising edges of CLKOUT . The phase of

+

CLKOUT canalsobedelayedrelativetothedigitaloutputs

by programming the mode control registers.

–

+

–

+

–

+

OF /OF (Pins 14/15): Over/Underflow Digital Output.

D

/D

to D

/D

12_13

(Pins 16/17, 18/19,

0_1

12_13

OF is high when an overflow or underflow has occurred.

22/23, 24/25, 28/29, 31/32, 33/34): Double-Data Rate

Digital Outputs. Two data bits are multiplexed onto each

differential output pair. The even data bits (D0, D2, D4,

+

This underflow is valid only when CLKOUT is low. In the

second half clock cycle, the overflow is set to 0.

+

D6, D8, D10, D12) appear when CLKOUT is low. The odd

data bits (D1, D3, D5, D7, D9, D11, D13) appear when

+

CLKOUT is high.

FUNCTIONAL BLOCK DIAGRAM

V

DD

OV

DD

D12_13

14-BIT

PIPELINED

ADC

•

CORRECTION

LOGIC

ANALOG

INPUT

OUTPUT

DRIVERS

DDR

LVDS

S/H

•

D0_1

V

CM

V

CM

0.1µF

OGND

BUFFER

GND

CLOCK

CS

CLOCK/DUTY

CYCLE CONTROL

SCK

SDI

SPI

SDO

PAR/SER

V

REF

2.2µF

1.25V

REFERENCE

GND

RANGE

SELECT

SENSE

21521014 F01

Figure 1. Functional Block Diagram

21521014fa

16

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TIMING DIAGRAMS

Double-Data Rate Output Timing, All Outputs Are Differential LVDS

t

AP

N

N + 3

N + 2

N + 1

t

L

H

–

+

ENC

+

–

CLKOUT

t

C

–

+

D0_1

D0

N-6

D1

N-6

D0

N-5

D1

D0

D1

N-4

N-5

N-4

t

D

–

+

D12_13

D12

D13

D12

D13

D12

D13

N-4

N-6

N-5

N-4

D12_13

–

+

OF

N-6

INVALID OF

INVALID

N-5

21521014 TD01

t

SKEW

SPI Port Timing (Readback Mode)

t

S

t

DS

t

DH

t

H

SCK

CS

SCK

t

DO

SDI

A6

A5

A4

A3

A2

A1

A0

XX

D6

XX

D5

XX

D4

XX

D3

XX

D2

XX

D1

XX

R/W

SDO

D7

D0

HIGH IMPEDANCE

SPI Port Timing (Write Mode)

CS

SCK

SDI

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D0

R/W

SDO

21521014 TD02

21521014fa

17

HIGH IMPEDANCE

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

CONVERTER OPERATION

INPUT DRIVE CIRCUITS

Input Filtering

The LTC2152-14/LTC2151-14/LTC2150-14 are 14-

bit 250Msps/210Msps/170Msps A/D converters that

are powered by a single 1.8V supply. The analog

inputs must be driven differentially. The encode in-

puts should be driven differentially for optimal per-

formance. The digital outputs are double-data rate

LVDS. Additional features can be chosen by programming

the mode control registers through a serial SPI port.

If possible, there should be an RC lowpass filter right at

the analog inputs. This lowpass filter isolates the drive

circuitryfromtheA/Dsample-and-holdswitching,andalso

limits wide band noise from the drive circuitry. Figure 3

shows an example of an input RC filter. The RC compo-

nent values should be chosen based on the application’s

input frequency.

ANALOG INPUT

Transformer-Coupled Circuits

The analog input is a differential CMOS sample-and-hold

circuit (Figure 2). It must be driven differentially around a

Figure 3 shows the analog input being driven by an RF

transformer with the common mode supplied through a

common mode voltage set by the V output pin, which

CM

pair of resistors via the V pin.

CM

is nominally 0.8V. The inputs should swing from V

0.375V to V + 0.375V. There should be a 180° phase

–

CM

At higher input frequencies a transmission line balun

transformer(Figures4and5)hasbetterbalance,resulting

in lower A/D distortion.

CM

difference between the inputs.

LTC2152-14

V

DD

10Ω

R

V

CM

ON

2pF

20Ω

5Ω

0.1µF

+

–

A

IN

LTC2152-14

0.1µF

T1

1:1

4.7Ω

2pF

+

–

IN

A

V

DD

IN

25Ω

R

20Ω

ON

10pF

A

0.1µF

4.7Ω

IN

V

DD

T1: MACOM ETC1-1T

21521014 F03

Figure 3. Analog Input Circuit Using a Transformer.

Recommended for Input Frequencies from 5MHz to 70MHz

1.2V

10k

+

–

10Ω

ENC

V

CM

0.1µF

T2

WBC1-1L

1:1

LTC2152-14

0.1µF

4.7Ω

T1

+

IN

A

IN

MABA

007159-

000000

45Ω

21521014 F02

100Ω

0.1µF

4.7Ω

Figure 2. Equivalent Input Circuit for Differential Input Clock

–

A

IN

21521014 F04

Figure 4. Recommended Front-End Circuit for

Input Frequencies from 15MHz to 150MHz

21521014fa

18

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

Amplifier Circuits

V

CM

Figure 6 shows the analog input being driven by a high

speed differential amplifier. The output of the amplifier is

AC-coupled to the A/D so the amplifier’s output common

mode voltage can be optimally set to minimize distortion.

0.1µF

10Ω

4.7Ω

LTC2152-14

0.1µF

MABA

007159-

000000

+

IN

A

IN

45Ω

T1

100Ω

At very high frequencies an RF gain block will often have

lower distortion than a differential amplifier. If the gain

block is single-ended, then a transformer circuit (Figures

3 and 5) should convert the signal to differential before

driving the A/D. The A/D cannot be driven single-ended.

0.1µF

4.7Ω

0.1µF

–

A

IN

21521014 F05

Figure 5. Recommended Front-End Circuit for

Input Frequencies from 150MHz Up to 900MHz

Reference

TheLTC2152-14/LTC2151-14/LTC2150-14hasaninternal

1.25V voltage reference. For a 1.5V input range with in-

ternal reference, connect SENSE to V . For a 1.5V input

DD

range with an external reference, apply a 1.25V reference

voltage to SENSE (Figure 7).

V

CM

0.1µF

50Ω

LTC2152-14

Encode Input

3pF

0.1µF

4.7Ω

The signal quality of the encode inputs strongly affects

the A/D noise performance. The encode inputs should

be treated as analog signals—do not route them next to

digital traces on the circuit board.

+

INPUT

A

IN

3pF

0.1µF

4.7Ω

–

IN

21521014 F06

The encode inputs are internally biased to 1.2V through

10k equivalent resistance (Figure 8). If the common mode

of the driver is within 1.1V to 1.5V, it is possible to drive

Figure 6. Front-End Circuit Using a High

Speed Differential Amplifier

LTC2152-14

V

DD

5Ω

1.25V

2.2µF

V

REF

1.2V

10k

+

–

ENC

SCALER/

BUFFER

ADC

REFERENCE

SENSE

DETECTOR

21521014 F07

21521014 F08

Figure 8. Equivalent Encode Input Circuit

Figure 7. Reference Circuit

21521014fa

19

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

the encode inputs directly. Otherwise, a transformer or

coupling capacitors are needed (Figures 9 and 10). The

maximum (peak) voltage of the input signal should never

Forapplicationswherethesamplerateneedstobechanged

quickly, the clock duty cycle stabilizer can be disabled. If

the duty cycle stabilizer is disabled, care should be taken

to make the sampling clock have a 50% ( 5%) duty cycle.

exceed V +0.1V or go below –0.1V.

DD

Clock Duty Cycle Stabilizer

DIGITAL OUTPUTS

For good performance the encode signal should have a

50% ( 5%) duty cycle. If the optional clock duty cycle

stabilizer circuit is enabled, the encode duty cycle can

vary from 30% to 70% and the duty cycle stabilizer will

maintain a constant 50% internal duty cycle. If the encode

signal changes frequency or is turned off, the duty cycle

stabilizer circuit requires one hundred clock cycles to lock

onto the input clock. The duty cycle stabilizer is enabled

via SPI Register A2 (see SPI Control Register) or by CS

in parallel programming mode.

Thedigitaloutputsaredouble-datarateLVDSsignals.Two

data bits are multiplexed and output on each differential

+

output pair. There are seven LVDS output pairs (D0_1 /

–

+

–

D0_1 through D12_13 /D12_13 ). Overflow (OF /OF )

–

and the data output clock (CLKOUT /CLKOUT ) each have

an LVDS output pair.

By default the outputs are standard LVDS levels: 3.5mA

outputcurrentanda1.25Voutputcommonmodevoltage.

LTC2152-14

V

DD

1.2V

10k

0.1µF

50Ω

T1

100Ω

0.1µF

21521014 F09

T1: MACOM ETC1-1-13

Figure 9. Sinusoidal Encode Drive

LTC2152-14

V

DD

1.2V

10k

0.1µF

+

–

ENC

PECL OR

LVDS INPUT

100Ω

0.1µF

ENC

21521014 F10

Figure 10. PECL or LVDS Encode Drive

21521014fa

20

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

An external 100Ω differential termination resistor is re-

quiredforeachLVDSoutputpair.Theterminationresistors

shouldbelocatedascloseaspossibletotheLVDSreceiver.

Overflow Bit

The overflow output bit (OF) outputs a logic high when

the analog input is either overranged or underranged.

The overflow bit has the same pipeline latency as the

data bits.

The outputs are powered by OV and OGND, which are

DD

isolated from the A/D core power and ground.

+

The OF is valid when CLKOUT is low.

Programmable LVDS Output Current

The default output driver current is 3.5mA. This current

can be adjusted by serially programming mode control

register A3 (see Table 3). Available current levels are

1.75mA, 2.1mA, 2.5mA, 3mA, 3.5mA, 4mA and 4.5mA.

Phase Shifting the Output Clock

To allow adequate set-up and hold time when latching the

+

output data, the CLKOUT signal may need to be phase

shifted relative to the data output bits. Most FPGAs have

this feature; this is generally the best place to adjust the

timing.

Optional LVDS Driver Internal Termination

In most cases, using just an external 100Ω termination

resistor will give excellent LVDS signal integrity. In ad-

dition, an optional internal 100Ω termination resistor

can be enabled by serially programming mode control

register A3. The internal termination helps absorb any

reflections caused by imperfect termination at the re-

ceiver. When the internal termination is enabled, the

output driver current is doubled to maintain the same

output voltage swing.

+

Alternatively, the ADC can also phase shift the CLKOUT /

–

CLKOUT signals by serially programming mode control

register A2. The output clock can be shifted by 0°, 45°,

90°, or 135°. To use the phase shifting feature, the clock

duty cycle stabilizer must be turned on. Another con-

+

trol register bit can invert the polarity of CLKOUT and

CLKOUT , independently of the phase shift. The combina-

tion of these two features enables phase shifts of 45° up

to 315° (Figure 11).

–

+

ENC

D0-D13, OF

MODE CONTROL BITS

PHASE

SHIFT

CLKINV

0

CLKPHASE1 CLKPHASE0

0°

0

1

0

1

0

1

0

1

0

1

0

1

45°

90°

0

1

135°

180°

225°

270°

+

CLKOUT

315°

21521014 F11

Figure 11. Phase Shifting CLKOUT

21521014fa

21

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LTC2152-14/

LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

DATA FORMAT

CLKOUT

OF

Table 1 shows the relationship between the analog input

voltage, the digital data output bits and the overflow bit.

By default the output data format is offset binary. The 2’s

complement format can be selected by serially program-

ming mode control register A4.

OF

D13

D13/D0

D12/D0

Table 1. Output Codes vs Input Voltage

D12

+

–

A

– A

D13-D0

•

IN

(1.5V Range) OF

(OFFSET BINARY)

(2’s COMPLEMENT)

RANDOMIZER

ON

D1

>0.75 V

1

0

1

11 1111 1111 1111

11 1111 1111 1110

10 0000 0000 0001

10 0000 0000 0000

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

01 1111 1111 1111

01 1111 1111 1110

00 0000 0000 0001

00 0000 0000 0000

11 1111 1111 1111

11 1111 1111 1110

10 0000 0000 0001

10 0000 0000 0000

D1/D0

+0.75V

+0.749908V

+0.0000915V

+0.000000V

–0.0000915V

–0.0001831V

–0.7499084V

–0.75V

D0

21521014 F12

Figure 12. Functional Equivalent of Digital Output Randomizer

< –0.75V

PC BOARD

Digital Output Randomizer

FPGA

CLKOUT

Interference from the A/D digital outputs is sometimes

unavoidable.Digitalinterferencemaybefromcapacitiveor

inductive coupling or coupling through the ground plane.

Even a tiny coupling factor can cause unwanted tones

in the ADC output spectrum. By randomizing the digital

output before it is transmitted off-chip, these unwanted

tones can be randomized, which reduces the unwanted

tone amplitude.

OF

D13/D0

LTC215X-14

D13

D12

D12/D0

D1/D0

D0

•

The digital output is randomized by applying an exclu-

sive-OR logic operation between the LSB and all other

data output bits. To decode, the reverse operation is

applied—an exclusive-OR operation is applied between

the LSB and all other bits. The LSB, OF and CLKOUT out-

puts are not affected. The output randomizer is enabled

by serially programming mode control register A4.

D1

D0

21521014 F13

Figure 13. Unrandomizing for Randomized

Digital Output Signal

21521014fa

22

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LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

Alternate Bit Polarity

it is not designed for multiplexing the data bus between

multiple converters.

Another feature that may reduce digital feedback on the

circuit board is the alternate bit polarity mode. When this

mode is enabled, all of the odd bits (D1, D3, D5, D7, D9,

D11, D13)areinvertedbeforetheoutputbuffers. Theeven

bits (D0, D2, D4, D6, D8, D10, D12), OF and CLKOUT are

not affected. This can reduce digital currents in the circuit

board ground plane and reduce digital noise, particularly

for very small analog input signals.

Sleep Modes

TheA/Dmaybeplacedinapower-downmodetoconserve

power. In sleep mode, the entire A/D converter is powered

down, resulting in < 2mW power consumption. If the en-

code input signal is not disabled, the power consumption

will be higher (up to 2mW at 250Msps). Sleep mode is

enabled by mode control register A1 (serial programming

mode), or by SCK (parallel programming mode).

The digital output is decoded at the receiver by inverting

the odd bits (D1, D3, D5, D7, D9, D11, D13.) The alternate

bit polarity mode is independent of the digital output ran-

domizer—either both or neither function can be on at the

same time. The alternate bit polarity mode is enabled by

serially programming mode control register A4.

The amount of time required to recover from sleep mode

depends on the size of the bypass capacitors on V

.

REF

For the suggested values in Figure 1, the A/D will stabi-

lize after 0.1ms + 2500 • t where t is the period of the

p

sampling clock.

Digital Output Test Patterns

Nap Mode

To allow in-circuit testing of the digital interface to the

A/D, there are several test modes (activate by setting

DTESTON) that force the A/D data outputs (OF, D13 to

D0) to known values:

In nap mode the A/D core is powered down while the

internal reference circuits stay active, allowing faster

wakeup. Recovering from nap mode requires at least 100

clock cycles. Wake-up time from nap mode is guaranteed

only if the clock is kept running, otherwise power-down

wake-up time conditions apply. Nap mode is enabled by

power-down register A1 in the serial programming mode.

All 1s: All outputs are 1

All 0s: All outputs are 0

Alternating: Outputs change from all 1s to all 0s on

alternating samples

DEVICE PROGRAMMING MODES

Checkerboard:Outputschangefrom101010101010101

to 010101010101010 on alternating samples.

The operating modes of the LTC215X-14 can be pro-

grammed by either a parallel interface or a simple serial

interface. The serial interface has more flexibility and

can program all available modes. The parallel interface

is more limited and can only program some of the more

commonly used modes.

The digital output test patterns are enabled by serially

programming mode control register A4. When enabled,

the test patterns override all other formatting modes:

2’s complement, randomizer, alternate-bit polarity.

Parallel Programming Mode

Output Disable

To use the parallel programming mode, PAR/SER should

The digital outputs may be disabled by serially program-

ming mode control register A3. All digital outputs, includ-

ing OF and CLKOUT, are disabled. The high impedance

disabled state is intended for long periods of inactivity,

be tied to V . The CS, SCK and SDI pins are binary logic

DD

inputs that set certain operating modes. These pins can

be tied to V or ground, or driven by 1.8V, 2.5V, or 3.3V

DD

21521014fa

23

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LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

CMOS logic. Table 2 shows the modes set by CS, SCK

Software Reset

and SDI.

If serial programming is used, the mode control registers

shouldbeprogrammedassoonaspossibleafterthepower

supplies turn on and are stable. The first serial command

must be a software reset which will reset all register data

bits to logic 0. To perform a software reset it is neces-

sary to write 1 in register A0 (Bit D7). After the reset is

complete, Bit D7 is automatically set back to zero. This

register is WRITE-ONLY.

Table 2. Parallel Programming Mode Control Bits)

DESCRIPTION

CS

Clock Duty Cycle Stabilizer Control Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

Power-Down Control Bit

SCK

SDI

0 = Normal Operation

1 = Sleep Mode (entire ADC is powered down)

LVDS Current Selection Bit

GROUNDING AND BYPASSING

0 = 3.5mA LVDS Current Mode

1 = 1.75mA LVDS Current Mode

The LTC215X-14 requires a printed circuit board with a

clean unbroken ground plane in the first layer beneath the

ADC. A multilayer board with an internal ground plane is

recommended. Layoutforthe printed circuit board should

ensure that digital and analog signal lines are separated as

much as possible. In particular, care should be taken not

to run any digital track alongside an analog signal track

or underneath the ADC.

Serial Programming Mode

To use the serial programming mode, PAR/SER should be

tied to ground. The CS, SCK, SDI and SDO pins become

a serial interface that program the A/D control registers.

Data is written to a register with a 16-bit serial word. Data

can also be read back from a register to verify its contents.

High quality ceramic bypass capacitors should be used

Serial data transfer starts when CS is taken low. The data

on the SDI pin is latched at the first sixteen rising edges

of SCK. Any SCK rising edges after the first sixteen are

ignored.ThedatatransferendswhenCSistakenhighagain.

at the V , OV , V and V

pins. Bypass capacitors

DD

DD CM

REF

must be located as close to the pins as possible. Size

0402 ceramic capacitors are recommended. The traces

connecting the pins and bypass capacitors must be kept

short and should be made as wide as possible.

The first bit of the 16-bit input word is the R/W bit. The

next seven bits are the address of the register (A6:A0).

The final eight bits are the register data (D7:D0).

The analog inputs, encode signals and digital outputs

should not be routed next to each other. Ground fill and

grounded vias should be used as barriers to isolate these

signals from each other.

If the R/W bit is low, the serial data (D7:D0) will be writ-

ten to the register set by the address bits (A6:A0). If the

R/W bit is high, data in the register set by the address bits

(A6:A0) will be read back on the SDO pin (see the Timing

Diagrams). During a readback command the register is

not updated and data on SDI is ignored.

HEAT TRANSFER

Most of the heat generated by the LTC215X-14 is trans-

ferred from the die through the bottom-side exposed pad

and package leads onto the printed circuit board. For good

electricalandthermalperformance,theexposedpadmust

be soldered to a large grounded pad on the PC board. This

pad should be connected to the internal ground planes by

an array of vias.

The SDO pin is an open-drain output that pulls to ground

with a 200Ω impedance. If register data is read back

through SDO, an external 2k pull-up resistor is required.

If serial data is only written and readback is not needed,

then SDO can be left floating and no pull-up resistor is

needed.Table 3showsamapofthemodecontrolregisters.

21521014fa

24

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LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

Table 3. Serial Programming Mode Register Map (PAR/SER = GND). An “X” indicates an unused bit.

REGISTER A0: RESET REGISTER (ADDRESS 00h) WRITE-ONLY

D7

D6

X

D5

D4

X

D3

X

D2

X

D1

X

D0

X

RESET

X

Bit 7

RESET

0 = Not Used

Software Reset Bit

1 = Software Reset. All mode control registers are reset to 00h. After the Reset SPI Write Command is Complete, Bit D7 is

Automatically Set Back to Zero. The Reset Register is Write Only.

Bits 6-0

Unused bit.

REGISTER A1: POWER-DOWN REGISTER (ADDRESS 01h)

D7

X

D6

X

D5

X

D4

X

D3

D2

D1

0

D0

0

SLEEP

NAP

Bits 7-4

Unused, these bits are read back as 0.

Bit 3

SLEEP

0 = Normal Operation

1 = Power Down Entire ADC

Bit 2

NAP

0 = Normal Mode

1 = Low Power Mode

Must be set to 0.

Bit 1-0

REGISTER A2: TIMING REGISTER (ADDRESS 02h)

D7

X

D6

X

D5

X

D4

X

D3

D2

D1

D0

CLKINV

CLKPHASE1

CLKPHASE0

DCS

Bits 7-4

Unused, these bits are read back as 0.

CLKINV Output Clock Invert Bit

Bit 3

0 = Normal CLKOUT Polarity (as shown in the Timing Diagrams)

1 = Inverted CLKOUT Polarity

Bits 2-1

CLKPHASE1:CLKPHASE0

Output Clock Phase Delay Bits

00 = No CLKOUT Delay (as shown in the Timing Diagrams)

+

–

01 = CLKOUT /CLKOUT delayed by 45° (Clock Period • 1/8)

10 = CLKOUT /CLKOUT delayed by 90° (Clock Period • 1/4)

11 = CLKOUT /CLKOUT delayed by 135° (Clock Period • 3/8)

Note: If the CLKOUT phase delay feature is used, the clock duty cycle stabilizer must also be turned on.

Bit 0

DCS

Clock Duty Cycle Stabilizer Bit

0 = Clock Duty Cycle Stabilizer Off

1 = Clock Duty Cycle Stabilizer On

21521014fa

25

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LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

REGISTER A3: OUTPUT MODE REGISTER (ADDRESS 03h)

D7

X

D6

X

D5

X

D4

D3

D2

D1

D0

ILVDS2

ILVDS1

ILVDS0

TERMON

OUTOFF

Bits 7-5

Unused, these bits are read back as 0.

Bits 4-2

ILVDS2:ILVDS0 LVDS Output Current Bits

000 = 3.5mA LVDS Output Driver Current

001 = 4.0mA LVDS Output Driver Current

010 = 4.5mA LVDS Output Driver Current

011 = Not Used

100 = 3.0mA LVDS Output Driver Current

101 = 2.5mA LVDS Output Driver Current

110 = 2.1mA LVDS Output Driver Current

111 = 1.75mA LVDS Output Driver Current

Bit 1

Bit 0

TERMON

0 = Internal Termination Off

1 = Internal Termination On. LVDS output driver current is 2× the current set by ILVDS2:ILVDS0

LVDS Internal Termination Bit

OUTOFF

0 = LVDS DDR

Digital Output Mode Control Bits

1 = LVDS Tristate (High Impedance)

REGISTER A4: DATA FORMAT REGISTER (ADDRESS 04h)

D7

D6

D5

D4

D3

0

D2

D1

D0

OUTTEST2

OUTTEST1

OUTTEST0

ABP

DTESTON

RAND

TWOSCOMP

Bits 7-5

OUTTEST2:OUTTEST0

000 = All Digital Outputs = 0

001 = All Digital Outputs = 1

Digital Output Test Pattern Bits

010 = Alternating Output Pattern. OF, D13-D0 alternate between 000 0000 0000 0000 and 111 1111 1111 1111

100 = Checkerboard Output Pattern. OF, D13-D0 alternate between 010 1010 1010 1010 and 101 0101 0101 0101

Bit 4

ABP

Alternate Bit Polarity Mode Control Bit

0 = Alternate Bit Polarity Mode Off

1 = Alternate Bit Polarity Mode On

Bit 3

Bit 2

Must be set to 0.

DTESTON

0 = Normal Mode

1 = Enable the Digital Output Test Patterns

Enable digital patterns (Bits 7-5)

Bit 1

Bit 0

RAND

Data Output Randomizer Mode Control Bit

0 = Data Output Randomizer Mode Off

1 = Data Output Randomizer Mode On

TWOSCOMP Two’s Complement Mode Control Bit

0 = Offset Binary Data Format

1 = Two’s Complement Data Format

21521014fa

26

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LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

215210 F14

Silkscreen Top

215210 F15

215210 F16

215210 F17

Inner Layer 1 GND

Inner Layer 2

Inner Layer 3

21521014fa

27

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LTC2151-14/LTC2150-14

APPLICATIONS INFORMATION

215210 F18

215210 F19

215210 F20

Inner Layer 4

Inner Layer 5

Bottom Layer 6

21521014fa

28

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LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL APPLICATIONS

V

DD

OV

DD

L4

BEAD

REGULATED 1.8V

+

C10

1µF

C11

47µF

1210

SDO

SDI

L5

BEAD

SCK

CS

PAR/SER

C12

0.1µF

C34

0.1µF

C35

0.1µF

V

DD

0.2µF

R9, 1k

0.1µF

TP3

SENSE

C13

2.2µF

1

2

V

30

29

28

27

26

25

24

23

22

21

DD

OV

DD

OV

DD

+

V

+

–

D8_9

R14

10Ω

3

GND

–

+

–

+

–

+

–

4

+

–

A

INA

+

–

CLKOUT

D6_7

CLKOUT

5

–

R16

100Ω

LTC2152-14

6

SENSE

GND

R19

10Ω

+

D6_7

7

SENSE

–

D6_7

8

INA

V

REF

+

D4_5

9

C16

2.2µF

V

CM

–

D4_5

10

41

GND

10Ω

OGND

C21

0.1µF

21521014 TA02

0.1µF

OV

DD

0.1µF

100Ω

0.1µF

+

–

CLK

21521014fa

29

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LTC2152-14/

LTC2151-14/LTC2150-14

PACKAGE DESCRIPTION

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

UJ Package

40-Lead Plastic QFN (6mm × 6mm)

(Reference LTC DWG # 05-08-1728 Rev Ø)

0.70 0.05

6.50 0.05

5.10 0.05

4.42 0.05

4.50 0.05

(4 SIDES)

4.42 0.05

PACKAGE OUTLINE

0.25 0.05

0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

0.75 0.05

R = 0.115

TYP

6.00 0.10

(4 SIDES)

R = 0.10

TYP

39 40

0.40 0.10

PIN 1 TOP MARK

(SEE NOTE 6)

1

2

PIN 1 NOTCH

R = 0.45 OR

0.35 ¥ 45

CHAMFER

4.42 0.10

4.50 REF

(4-SIDES)

4.42 0.10

(UJ40) QFN REV Ø 0406

0.200 REF

0.25 0.05

0.50 BSC

0.00 – 0.05

NOTE:

BOTTOM VIEW—EXPOSED PAD

1. DRAWING IS A JEDEC PACKAGE OUTLINE VARIATION OF (WJJD-2)

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE

21521014fa

30

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LTC2152-14/

LTC2151-14/LTC2150-14

REVISION HISTORY

REV

DATE

DESCRIPTION

PAGE NUMBER

A

12/14 Changed pipeline latency to 6

Updated G17

5 and 17

8

21521014fa

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

31

For more information www.linear.com/LTC2152-14

LTC2152-14/

LTC2151-14/LTC2150-14

TYPICAL APPLICATION

LTC2152-14 32K Point FFT,

f_IN= 15MHz, –1dBFS, 250Msps

0

V

DD

OV

DD

–20

D12_13

14-BIT

PIPELINED

ADC

•

–40

–60

CORRECTION

LOGIC

DDR

LVDS

ANALOG

INPUT

OUTPUT

DRIVERS

S/H

•

D0_1

–80

OGND

CLOCK/DUTY

CYCLE

CONTROL

CLOCK

–100

–120

21521014 TA03a

0

40

60

80

100 120

20

FREQUENCY (MHz)

21521014 TA03b

RELATED PARTS

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DESCRIPTION

COMMENTS

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LTC2208

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14-Bit, 150Msps 1.8V ADC, Ultralow Power

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6mm × 6mm QFN-36

RF Mixers/Demodulators

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40MHz to 900MHz Direct Conversion

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High IIP3: 21dBm at 800MHz, Integrated LO Quadrature Generator

LT5527

LT5575

400MHz to 3.7GHz High Linearity

Downconverting Mixer

24.5dBm IIP3 at 900MHz, 23.5dBm IIP3 at 3.5GHz, NF = 12.5dB,

50Ω Single-Ended RF and LO Ports

800MHz to 2.7GHz Direct Conversion

Quadrature Demodulator

High IIP3: 28dBm at 900MHz, Integrated LO Quadrature Generator, Integrated

RF and LO Transformer

Amplifiers/Filters

LTC6409

10GHz GBW, 1.1nV/√Hz Differential Amplifier/ 88dB SFDR at 100MHz, Input Range Includes Ground 52mA Supply Current

ADC Driver

3mm × 2mm QFN Package

LTC6412

800MHz, 31dB Range, Analog-Controlled

Variable Gain Amplifier

Continuously Adjustable Gain Control, 35dBm OIP3 at 240MHz, 10dB Noise

Figure, 4mm × 4mm QFN-24

LTC6420-20

1.8GHz Dual Low Noise, Low Distortion

Differential ADC Drivers for 300MHz IF

Fixed Gain 10V/V, 1nV/√Hz Total Input Noise, 80mA Supply Current per

Amplifier, 3mm × 4mm QFN-20

Receiver Subsystems

LTM^®9002

14-Bit Dual Channel IF/Baseband Receiver

Subsystem

Integrated High Speed ADC, Passive Filters and Fixed Gain Differential Amplifiers

LTM9003

12-Bit Digital Pre-Distortion Receiver

Integrated 12-Bit ADC Down-Converter Mixer with 0.4GHz to 3.8GHz Input

Frequency Range

21521014fa

LT 1214 REV A • PRINTED IN USA

LinearTechnology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

32

For more information www.linear.com/LTC2152-14

(408)432-1900 FAX: (408) 434-0507 www.linear.com/LTC2152-14

●

 LINEAR TECHNOLOGY CORPORATION 2011


型号：	LTC2150-14_15
厂家：	Linear
描述：	14-Bit 250Msps/ 210Msps/170Msps ADCs
文件：	总32页 (文件大小：1025K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LTC2150-14_15 [Linear]

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