LTC2053CMS8#30495 [Linear]
IC INSTRUMENTATION AMPLIFIER, 10 uV OFFSET-MAX, PDSO8, PLASTIC, MSOP-8, Instrumentation Amplifier;
| 型号： | LTC2053CMS8#30495 |
| 厂家： | 
Linear |
| 描述： | IC INSTRUMENTATION AMPLIFIER, 10 uV OFFSET-MAX, PDSO8, PLASTIC, MSOP-8, Instrumentation Amplifier 放大器 光电二极管 |
| 文件： | 总4页 (文件大小：40K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LTC2053 SL30495
Pre c isio n, Ra il-to -Ra il,
Ze ro -Drift Instrum e nta tio n Am p lifie r
with Re sisto r-Pro g ra m m a b le Ga in
U
DESCRIPTIO
FEATURES
The LTC®2053 SL30495 is a high precision instrumenta-
tion amplifier. It uses a charge balanced switched capaci-
tor technique to convert a differential input voltage into a
single ended signal that is in turn amplified by a zero-drift
operational amplifier. The LTC2053 SL30495 is easy to
use; the gain is adjustable with two external resistors, like
a traditional op amp.
■
MS8 Package
Resistor Programmable Gain
Rail-to-Rail Output
Maximum Offset Voltage: 10µV
Maximum Offset Voltage Drift: 50nV/°C
Supply Operation: 2.7V to 5V
Typical Noise: 2.5µVp-p (0.01Hz to 10Hz)
Typical Supply Current: 0.8mA
■
■
■
■
■
■
■
The single-ended output swings from rail-to-rail.
The LTC2053 SL30495 is used in 5V single supply
applications.
U
APPLICATIO S
■
, LTC and LT are registered trademarks of Linear Technology Corporation.
TEC Controllers
U
TYPICAL APPLICATIO
Detailed Schematic of TEC Temperature Controller Includes A1 Thermistor Bridge Amplifier, LTC1923 Switched Mode
Controller and Power Output H-Bridge. DAC Establishes Temperature Setpoint. Gain Adjust and Compensation
Capacitor Optimize Loop Gain Bandwidth. Various LTC1923 Outputs Permit Monitoring TEC Operating Conditions
0.1µF
10k
* = SUGGESTED VALUES
PLLLPF
LTC1923
R
T
L1, L2: SUMIDA CDRH8D28-100NC, 10µH
Q1, Q2: Si9801DY N-P DUAL
330pF
TO 2.5V AT LTC1923
REF
82k
5V
R
SLEW
C
T
10k
0.1%
TEC-R
ARE PART OF LASER MODULE.
THERMISTOR
3
2
SDSYNC
V
REF
2.5V
REF
+
R
IS TYPICALLY 10kΩ AT 25°C.
THERMISTOR
REFIN
A1
10k
1µF
7
+
CLK
LTC2053
#30495
–
EAIN
0.1µF
FILM
D
IN
LTC1658
9k
6
PDRVB
NDRVB
5
CS/LD
EAOUT
LOOP GAIN
1k*
4.7µF*
TANTALUM
0.1µF
+
10M
5V
V
DD
FILM
–
5V
EAIN
1µF
100k
LOOP
AGND
SS
PGND
+
22µF
BANDWIDTH
TEC
PDRVA
NDRVA
L1
L2
1µF
CERAMIC
Q1
Q2
I
LIM
10k
+
17.8k
CS
0.1Ω
22µF
22µF
–
0.1µF
CS
2.5V
REF
TO 2.5V
REF
V
SET
FAULT
V
I
TEC
THERM
H/C
+
2.2µF
TEC
R
THERMAL FEEDBACK
THERMISTOR
–
V
TEC
TEC
2053 TA01
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen-
tationthattheinterconnectionofits circuits as describedhereinwillnotinfringeonexistingpatentrights.
1
LTC2053 SL30495
W W
U W
U
W
U
ABSOLUTE AXI U RATI GS
PACKAGE/ORDER I FOR ATIO
Total Supply Voltage (V+ to V ) ................................. 6V
–
TOP VIEW
ORDER PART NUMBER
LTC2053CMS8#30495
Input Current ...................................................... ±10mA
Output Short Circuit Duration .......................... Indefinite
Operating Temperature Range ................ –40°C to 85°C
Storage Temperature Range ................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
–
V
+
8 V
1
–IN 2
7 OUT
6 RG
5 REF
+IN 3
–
V
4
MS8 PART MARKING
LTMW
MS8 PACKAGE
8-LEAD PLASTIC MSOP
TJMAX = 110°C, θJA = 120°C/W
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. V+ = 5V, V– = 0V, REF = 2.5V.
PARAMETER
CONDITIONS
A = 1
MIN
TYP
0.001
3
MAX
0.01
10
UNITS
%
Gain Error
●
●
V
Gain Nonlinearity
Input Offset Voltage
Average Input Offset Drift
Input Bias Current
Input Offset Current
Input Noise Voltage
Output Voltage Swing High
A = 1
V
ppm
µV
V
CM
= 2.5V (Note 1)
10
(Note 1)
●
●
●
±50
nV/°C
nA
V
= 1V
= 1V
4
1
CM
V
CM
nA
DC to 10Hz
2.5
µV
P-P
–
R = 2k to V
●
●
4.85
4.95
4.94
4.98
V
V
L
–
R = 10k to V
L
Output Voltage Swing Low
Supply Current
20
mV
mA
kHz
No Load
●
0.85
2.5
1.2
Internal Sampling Frequency
Note 1: These parameters are guaranteed by design. Thermocouple effects
preclude the measurements of these voltage levels during automated
testing.
2
LTC2053 SL30495
U
U
U
PI FU CTIO S
–
V (Pins 1, 4): Negative Supply. Both pins must be con-
RG (Pin 6): Inverting Input of Internal Op Amp. With a
resistor, R2, connected between the OUT pin and the RG
pinandaresistor, R1, betweentheRGpinandtheREFpin,
the DC gain is given by 1 + R2 / R1.
nected to the negative supply for proper device operation.
–IN (Pin 2): Inverting Input.
+IN (Pin 3): Noninverting Input.
REF (Pin 5): Ground Reference for Output.
OUT (Pin 7): Amplifier Output.
V+ (Pin 8): Positive Supply.
W
BLOCK DIAGRA
8
+
LTC2053 SL30495
V
ZERO-DRIFT
OP AMP
+IN
3
+
OUT
7
C
S
C
H
–IN
2
–
–
–
REF
RG
V
V
5
6
1
4
2053 BD
3
LTC2053 SL30495
U
W
U U
APPLICATIO S I FOR ATIO
Theory of Operation
Input Current
The LTC2053 SL30495 uses an internal capacitor (CS) to
sample a differential input signal riding on a DC common
modevoltage(seeBlockDiagram).This capacitor’s charge
is transferred to a second internal hold capacitor (CH)
translating the common mode of the input differential
signal to that of the REF pin. The resulting signal is
amplified by a zero-drift op amp in the noninverting
configuration. The RG pin is the negative input of this op
amp and allows external programmability of the DC gain.
Simple filtering can be realized by using an external
capacitor across the feedback resistor.
Whenever the differential input V changes, CH must be
charged up to the new input voltage via CS. This results in
an input charging current during each input sampling
IN
period. Eventually, CH and CS will reach V and, ideally,
IN
the input current would go to zero for DC inputs.
In reality, there are additional parasitic capacitors which
disturb the charge on CS every cycle even if V is a DC
IN
voltage. For example, the parasitic bottom plate capacitor
on CS must be charged from the voltage on the REF pin to
the voltage on the –IN pin every cycle. The resulting input
charging current decays exponentially during each input
samplingperiodwithatimeconstantequaltoRSCS,where
RS is the source resistance between +IN and –IN. If the
voltage disturbance due to these currents settles before
the end of the sampling period, there will be no errors due
to source resistance or the source resistance mismatch
between –IN and +IN. With RS less than 20kΩ, no DC
errors occur due to this input current.
Settling Time
The sampling rate is 2.5kHz and the input sampling period
during which CS is charged to the input differential voltage
V is approximately 180µs. First assume that on each
IN
input sampling period, CS is charged fully to V . Since
IN
CS = CH (=1000pF), a change in the input will settle to N
bits of accuracy at the op amp noninverting input after N
clock cycles or 400µs(N). The settling time at the OUT pin
is alsoaffectedbythesettlingoftheinternalopamp. Since
the gain bandwidth of the internal op amp is typically
200kHz, its settling time alone to N bits would be approxi-
Grounding and Bypassing
TheLTC2053SL30495uses asampleddatatechniqueand
therefore contains some clocked digital circuitry. It is
therefore sensitive to supply bypassing. A 0.1µF ceramic
capacitormustbeconnectedbetweenPin8(V+)andPin 4
(V–) with leads as short as possible.
mately 0.5µs • N • A ; where A is the closed-loop gain
CL
CL
of the op amp. For gains below 100, the settling time is
dominated by the switched capacitor front end.
If the input source resistance between +IN and –IN (RS) is
large, CS may not reach V during each input sampling
IN
period. The voltage across CH and CS will eventually reach
V but the settling time would be larger than described
IN
above. If RS is less than 20kΩ, then the approximation
described above is accurate.
1001 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
4
●
●
(408) 432-1900 FAX: (408) 434-0507 www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
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