LT3958EUHE#TRPBF [Linear]
LT3958 - High Input Voltage, Boost, Flyback, SEPIC and Inverting Converter; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C;
| 型号： | LT3958EUHE#TRPBF |
| 厂家： | 
Linear |
| 描述： | LT3958 - High Input Voltage, Boost, Flyback, SEPIC and Inverting Converter; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C 开关 |
| 文件： | 总30页 (文件大小：756K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3958
High Input Voltage,
Boost, Flyback, SEPIC and
Inverting Converter
FeaTures
DescripTion
The LT®3958 is a wide input range, current mode, DC/DC
converter which is capable of generating either positive
or negative output voltages. It can be configured as either
a boost, flyback, SEPIC or inverting converter. It features
an internal low side N-channel power MOSFET rated for
84V at 3.3A and driven from an internal regulated 7.2V
supply. The fixed frequency, current-mode architecture
results in stable operation over a wide range of supply
and output voltages.
n
Wide Input Voltage Range: 5V to 80V
n
Single Feedback Pin for Positive or Negative
Output Voltage
n
Internal 3.3A/84V Power Switch
n
Current Mode Control Provides Excellent Transient
Response
n
Programmable Operating Frequency (100kHz to
1MHz) with One External Resistor
n
Synchronizeable to an External Clock
n
Low Shutdown Current < 1µA
The operating frequency of LT3958 can be set with an
external resistor over a 100kHz to 1MHz range, and can
be synchronized to an external clock using the SYNC pin.
A minimum operating supply voltage of 5V, and a low
shutdown quiescent current of less than 1µA, make the
LT3958 ideally suited for battery-powered systems.
n
Internal 7.2V Low Dropout Voltage Regulator
n
Programmable Input Undervoltage Lockout with
Hysteresis
Programmable Soft-Start
n
n
Thermally Enhanced QFN (5mm × 6mm) Package
The LT3958 features soft-start and frequency foldback
functions to limit inductor current during start-up.
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
applicaTions
n
Automotive
No R
and ThinSOT are trademarks of Analog Devices, Inc. All other trademarks are the
SENSE
n
Telecom
property of their respective owners. Patents pending.
n
Industrial
Typical applicaTion
High Efficiency Boost Converter
Efficiency vs Output Current
33µH
V
OUT
100
95
90
85
80
75
70
V
IN
V
= 24V
48V
IN
12V TO 40V
0.5A
4.7µF
×2
4.7µF
V
SW
392k
IN
EN/UVLO
GND
53.6k
LT3958
SGND
SYNC
SENSE1
464k
SENSE2
FBX
INTV
CC
RT SS
VC
10k
10nF
15.8k
41.2k
300kHz
0.33µF
4.7µF
0
400
500
100
200
300
OUTPUT CURRENT (mA)
3958 TA01b
3958 TA01a
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For more information www.linear.com/LT3958
LT3958
absoluTe MaxiMuM raTings
pin conFiguraTion
(Note 1)
TOP VIEW
V , EN/UVLO (Note 5)..............................................80V
IN
SW............................................................................84V
INTV .................................................... V + 0.3V, 15V
CC
IN
36 35 34 33 32 31 30
SYNC ..........................................................................8V
NC
NC
1
2
3
4
28 INTV
CC
VC, SS.........................................................................3V
27
V
IN
SENSE2
SGND
RT
1.5V
37
SGND
...............................................................................................
EN/UVLO
25
SENSE1, SGND.................. Internally Connected to GND
SENSE2.................................................................. 0.3V
FBX ................................................................. –6V to 6V
Operating Temperature Range
24 SGND
SGND
23
SENSE1
6
38
SW
SW
SW
8
9
21 SW
20 SW
(Note 2) ............................................. –40°C to 125°C
Maximum Junction Temperature........................... 125°C
Storage Temperature Range................... –65°C to 125°C
NC 10
12 13 14 15 16 17
UHE PACKAGE
36-LEAD (5mm × 6mm) PLASTIC QFN
= 125°C, θ = 43°C/W, θ = 5°C/W
T
JMAX
JA
JC
EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE
EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE
orDer inForMaTion
http://www.linear.com/product/LT3958#orderinfo
PART MARKING* PACKAGE DESCRIPTION
LEAD FREE FINISH
LT3958EUHE#PBF
LT3958IUHE#PBF
TAPE AND REEL
TEMPERATURE RANGE
–40°C to 125°C
LT3958EUHE#TRPBF
LT3958IUHE#TRPBF
3958
3958
36-Lead (5mm × 6mm) Plastic QFN
36-Lead (5mm × 6mm) Plastic QFN
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
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For more information www.linear.com/LT3958
LT3958
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Operating Range
5
80
V
IN
IN
V
Shutdown I
EN/UVLO = 0V
EN/UVLO = 1.15V
0.1
1
6
µA
µA
Q
V
V
Operating I
VC = 0.3V, R = 41.2k
1.6
350
4.0
2.2
400
4.6
mA
µA
A
IN
Q
T
Operating I with Internal LDO Disabled
VC = 0.3V, R = 41.2k, INTV = 7.5V
IN
Q
T
CC
l
SW Pin Current Limit
SW Pin On Voltage
SENSE2 Input Bias Current
Error Amplifier
SENSE2 = SENSE1
3.3
I
SW
= 2A
180
–65
mV
µA
Current Out of Pin
l
l
FBX Regulation Voltage (V
FBX Overvoltage Lockout
FBX Pin Input Current
)
FBX > 0V (Note 3)
FBX < 0V (Note 3)
1.569
1.6
1.631
V
V
FBX(REG)
–0.816 –0.800 –0.784
FBX > 0V (Note 4)
FBX < 0V (Note 4)
6
7
8
11
10
14
%
%
FBX = 1.6V (Note 3)
FBX = –0.8V (Note 3)
70
100
10
nA
nA
–10
(Note 3)
(Note 3)
230
5
µS
Transconductance g (∆I /∆FBX)
m
VC
VC Output Impedance
MΩ
FBX > 0V, 5V < V < 80V (Notes 3, 6)
0.006
0.005
0.03
0.038
%/V
%/V
V
Line Regulation (∆V /[∆V • V
])
IN
FBX
FBX
IN
FBX(REG)
FBX < 0V, 5V < V < 80V (Notes 3, 6)
IN
10
V/V
µA
VC Current Mode Gain (∆V /∆V
)
VC
SENSE
VC Source Current
VC Sink Current
VC = 1.5V, FBX = 0V, Current Out of Pin
–15
FBX = 1.7V
FBX = –0.85V
12
11
µA
µA
Oscillator
Switching Frequency
R = 140k to SGND, FBX = 1.6V, VC = 1.5V
80
270
850
100
300
1000
120
330
1200
kHz
kHz
kHz
T
R = 41.2k to SGND, FBX = 1.6V, VC = 1.5V
T
R = 10.5k to SGND, FBX = 1.6V, VC = 1.5V
T
RT Voltage
FBX = 1.6V
1.2
200
250
V
ns
ns
SW Minimum Off-Time
SW Minimum On-Time
SYNC Input Low
275
300
0.4
SYNC Input High
1.5
SS Pull-Up Current
Low Dropout Regulator
SS = 0V, Current Out of Pin
–10
7.2
µA
V
l
INTV Regulation Voltage
7
7.4
CC
INTV Undervoltage Lockout Threshold
Falling INTV
3.55
3.75
0.15
4.00
V
V
CC
CC
UVLO Hysteresis
INTV Overvoltage Lockout Threshold
11.5
12.8
V
CC
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LT3958
elecTrical characTerisTics The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 24V, EN/UVLO = 24V, SENSE2 = 0V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
INTV Current Limit
V
IN
V
IN
= 80V
= 20V
19
24
50
29
mA
mA
CC
0 < I
< 10mA, V = 8V
–1
–0.4
0.005
500
%
%/V
mV
µA
INTV Load Regulation (∆V
/V
)
INTVCC
IN
CC
INTVCC INTVCC
8V < V < 80V
0.025
INTV Line Regulation (∆V
/[∆V • V
])
IN
CC
INTVCC
IN
INTVCC
Dropout Voltage (V – V
)
V
IN
= 6V, I
= 10mA, VC = 0V
INTVCC
IN
INTVCC
INTV Current in Shutdown
EN/UVLO = 0V, INTV = 8V
16
CC
CC
INTV Voltage to Bypass Internal LDO
7.5
V
CC
Logic Inputs
l
EN/UVLO Threshold Voltage Falling
EN/UVLO Voltage Hysteresis
EN/UVLO Input Low Voltage
EN/UVLO Pin Bias Current Low
EN/UVLO Pin Bias Current High
V
= INTV = 8V
1.17
1.7
1.22
20
1.27
V
mV
V
IN
CC
I
Drops Below 1µA
0.4
2.5
100
VIN
EN/UVLO = 1.15V
EN/UVLO = 1.33V
2
µA
nA
10
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LT3958 is tested in a feedback loop which servos V to the
reference voltages (1.6V and –0.8V) with the VC pin forced to 1.3V.
FBX
Note 4: FBX overvoltage lockout is measured at V
relative
FBX(OVERVOLTAGE)
to regulated V
.
FBX(REG)
Note 2: The LT3958E is guaranteed to meet performance specifications
from the 0°C to 125°C junction temperature. Specifications over the –40°C
to 125°C operating junction temperature range are assured by design,
characterization and correlation with statistical process controls. The
LT3958I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 5: For 5V < V < 6V, the EN/UVLO pin must not exceed V .
IN
IN
Note 6: EN/UVLO = 1.33V when V = 5V.
IN
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LT3958
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
Positive Feedback Voltage
vs Temperature, VIN
Negative Feedback Voltage
vs Temperature, VIN
Quiescent Current
vs Temperature, VIN
1.604
1.602
1.600
1.598
1.596
1.594
1.592
1.590
–792
1.8
1.7
1.6
1.5
1.4
V
= 80V
= 24V
IN
–794
–796
V
= 80V
IN
V
= INTV = 5V
CC
IN
V
IN
V
= 24V
IN
V
= 8V
IN
–798
–800
–802
–804
V
= 8V
IN
V
= 80V
IN
V
= 24V
V
= INTV = 5V
CC
IN
IN
V
= INTV = 5V
CC
IN
–50
0
25
50
75 100 125
–50
0
25
50
75
125
–25
100
–25
50
125
–50
0
25
75 100
–25
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3958 G01
3958 G02
3958 G03
Dynamic Quiescent Current
vs Switching Frequency
Normalized Switching
Frequency vs FBX
RT vs Switching Frequency
120
100
80
60
40
20
0
12
10
8
1000
6
100
4
2
0
10
–0.8
0
0.4
0.8
1.2
1.6
–0.4
100
300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
3958 G04
200
0
300 400 500 600 700 800 900 1000
100 200
FBX VOLTAGE (V)
SWITCHING FREQUENCY (kHz)
3958 G05
3958 G06
Switching Frequency
vs Temperature
SW Pin Current Limit
vs Temperature
SW Pin Current Limit
vs Duty Cycle
325
320
315
310
305
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
4.4
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
R
= 41.2k
T
300
295
290
285
280
275
–50
0
25
50
75 100 125
–25
50
TEMPERATURE (°C)
125
–50
0
25
75 100
–25
0
20
40
60
80
100
TEMPERATURE (°C)
DUTY CYCLE (%)
3958 G08
3958 G09
3958 G07
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LT3958
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
EN/UVLO Hysteresis Current
vs Temperature
EN/UVLO Threshold
vs Temperature
EN/UVLO Current vs Voltage
1.28
1.26
1.24
1.22
1.20
1.18
50
40
30
20
2.4
2.2
2.0
1.8
1.6
EN/UVLO RISING
EN/UVLO FALLING
10
0
50
75 100 125
0
20
40
60
80
–50
0
25
–25
50
TEMPERATURE (°C)
125
–50
0
25
75 100
–25
EN/UVLO VOLTAGE (V)
TEMPERATURE (°C)
3958 G11
3958 G10
3958 G12
INTVCC Line Regulation
INTVCC vs Temperature
INTVCC Load Regulation
7.30
7.25
7.20
7.15
7.10
7.4
7.3
7.2
7.1
7.0
7.3
7.2
V
= 8V
IN
7.1
7
6.9
6.8
60 70 80
0
10 20 30 40 50
(V)
50
75 100 125
0
10
15
INTV LOAD (mA)
20
25
–50
0
25
–25
5
V
TEMPERATURE (°C)
IN
CC
3958 G15
3958 G13
3958 G14
INTVCC Dropout Voltage
vs Current, Temperature
Internal Switch On-Resistance
vs Temperature
Internal Switch On-Resistance
vs INTVCC
900
800
180
160
140
120
100
80
102
100
98
125°C
700
600
500
75°C
25°C
96
400
300
200
100
0
94
0°C
60
92
–40°C
40
90
20
0
88
–50 –25
0
25
50
75 100 125
4
6
8
10
6
7
8
9
10 11 12
0
2
4
5
INTV LOAD (mA)
TEMPERATURE (°C)
INTV (V)
CC
CC
3958 G16
3958 G17
3958 G18
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LT3958
Typical perForMance characTerisTics TA = 25°C, unless otherwise noted.
SEPIC Typical Start-Up
Waveforms
SEPIC FBX Frequency Foldback
Waveforms During Overcurrent
V = 24V
IN
V
= 24V
IN
V
OUT
10V/DIV
V
OUT
5V/DIV
V
SW
20V/DIV
I
+ I
L1A L1B
2A/DIV
I
+ I
L1A L1B
2A/DIV
3958 G20
3958 G19
50µs/DIV
5ms/DIV
SEE TYPICAL APPLICATION: 10V TO 60V INPUT,
12V OUTPUT SEPIC CONVERTER
SEE TYPICAL APPLICATION: 10V TO 60V INPUT,
12V OUTPUT SEPIC CONVERTER
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LT3958
pin FuncTions
NC (Pins 1, 2, 10, 35, 36): No Internal Connection. Leave
these pins open or connect them to the adjacent pins.
INTV (Pin 28): Regulated Supply for Internal Loads
CC
and Gate Driver. Supplied from V and regulated to
IN
7.2V (typical). INTV must be bypassed to SGND with a
CC
SENSE2 (Pin 3): The Current Sense Input for the Control
Loop. Connect this pin to SENSE1 pin directly or through
a low pass filter (connect this pin to SENSE1 pin through
a resistor, and to SGND through a capacitor).
minimum of 4.7µF capacitor placed close to pin. INTV
CC
can be connected directly to V , if V is less than 11.5V.
IN
IN
INTV can also be connected to a power supply whose
CC
voltage is higher than 7.5V, and lower than V , provided
IN
SGND (Pins 4, 23, 24, Exposed Pad Pin 37): Signal
Ground. All small-signal components should connect to
this ground. SGND is connected to GND inside the IC to
ensure Kelvin connection for the internal switch current
sensing. Do not connect SGND and GND externally.
that supply does not exceed 11.5V.
VC (Pin 30): Error Amplifier Compensation Pin. Used to
stabilize the voltage loop with an external RC network.
Place compensation components between the VC pin
and SGND.
SENSE1 (Pin 6): The Current Sense Output of the Inter-
nal N-channel MOSFET. Connect this pin to SENSE2 pin
directly or through a low pass filter (connect this pin to
SENSE1 pin through a resistor, then connect SENSE2 to
SGND through a capacitor).
FBX (Pin 31): Positive and Negative Feedback Pin. Re-
ceives the feedback voltage from the external resistor
divider between the output and SGND. Also modulates the
switching frequency during start-up and fault conditions
when FBX is close to SGND.
SW (Pins 8,9,20,21, Exposed Pad Pin 38): Drain of
Internal Power N-channel MOSFET.
SS (Pin 32): Soft-Start Pin. This pin modulates compen-
sation pin voltage (VC) clamp. The soft-start interval is
set with an external capacitor between SS pin and SGND.
The pin has a 10µA (typical) pull-up current source to
an internal 2.5V rail. The soft-start pin is reset to SGND
GND (Pins 12,13,14,15,16,17): Ground. These pins con-
nect to the source terminal of internal power N-channel
MOSFET through an internal sense resistor. GND is con-
nected to SGND inside the IC to ensure Kelvin connection
for the internal switch current sensing. Do not connect
GND and SGND externally.
by an undervoltage condition at EN/UVLO, an INTV
CC
undervoltage or overvoltage condition or an internal
thermal lockout.
EN/UVLO (Pin 25): Shutdown and Undervoltage Detect
Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
isokayto enable switching. Risinghysteresis is generated
by the external resistor divider and an accurate internal
2µA pull-down current. An undervoltage condition resets
sort-start. Tie to 0.4V, or less, to disable the device and
RT (Pin 33): Switching Frequency Adjustment Pin. Set
the frequency using a resistor to SGND. Do not leave this
pin open.
SYNC (Pin 34): Frequency Synchronization Pin. Used to
synchronize the switching frequency to an outside clock.
If this feature is used, an R resistor should be chosen
T
to program a switching frequency 20% slower than the
SYNC pulse frequency. Tie the SYNC pin to SGND if this
feature is not used. SYNC is ignored when FBX is close
to SGND.
reduce V quiescent current below 1µA.
IN
V
(Pin 27): Input Supply Pin. V pin can be locally
IN
IN
bypassed with a capacitor to GND (not SGND).
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LT3958
block DiagraM
C
DC
L1
D1
V
IN
V
OUT
R4
R3
C
IN
L2
C
OUT
•
EN/UVLO
V
SW
IN
25
27
8, 9, 20,
21, 38
A10
–
+
I
S1
2µA
1.22V
2.5V
INTERNAL
REGULATOR
AND UVLO
CURRENT
LIMIT
I
S2
12.8V
10µA
+
–
UVLO
A9
A8
7.2V LDO
INTV
Q3
CC
INTV
CC
2.5V
28
G4
G3
+
–
C
VCC
I
S3
A11
A12
3.75V
1.72V
–
+
TLO
165˚C
DRIVER
G6
SR1
S
V
C
–
+
–
+
G5
G2
A7
R
O
M1
–0.88V
SENSE1
GND
6
Q2
PWM
COMPARATOR
R
SENSE
48mV
–
+
1.6V
+
A6
A5
A1
12, 13, 14,
15, 16, 17
SLOPE
RAMP
V
ISENSE
–
SENSE
SENSE2
3
+
–
+
–
A2
RAMP
GENERATOR
–0.8V
1.28V
–
A3
100kHz-1MHz
OSCILLATOR
+
G1
1.2V
FREQUENCY
FOLDBACK
+
FREQUENCY
FOLDBACK
+
A4
Q1
–
FREQ
PROG
FBX
VC
SS
SYNC
RT
SGND
31
30
32
34
33
3958 F01
4, 23,
24, 37
R2
V
OUT
C
C
R
C
R
T
C2
SS
R1
C
C1
Figure 1. LT3958 Block Diagram Working as a SEPIC Converter
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LT3958
applicaTions inForMaTion
Main Control Loop
The LT3958 has overvoltage protection functions to
protect the converter from excessive output voltage
overshoot during start-up or recovery from a short-circuit
condition. An overvoltage comparator A11 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
positive regulated voltage (1.6V) by 8% and provides a
reset pulse. Similarly, an overvoltage comparator A12
(with 10mV hysteresis) senses when the FBX pin voltage
exceeds the negative regulated voltage (–0.8V) by 11%
and provides a reset pulse. Both reset pulses are sent to
the main RS latch (SR1) through G6 and G5. The power
MOSFET switch M1 is actively held off for the duration of
an output overvoltage condition.
The LT3958 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation. Op-
eration can be best understood by referring to the Block
Diagram in Figure 1.
The start of each oscillator cycle sets the SR latch (SR1)
andturnsontheinternalpowerMOSFETswitchM1through
driver G2. The switch current flows through the internal
current sensing resistor R
and generates a voltage
SENSE
proportional to the switch current. This current sense
voltage V (amplified by A5) is added to a stabilizing
ISENSE
slope compensation ramp and the resulting sum (SLOPE)
isfedintothepositiveterminalofthePWMcomparatorA7.
When SLOPE exceeds the level at the negative input of A7
(VC pin), SR1 is reset, turning off the power switch. The
level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.
Programming Turn-On and Turn-Off Thresholds with
the EN/UVLO Pin
The EN/UVLO pin controls whether the LT3958 is enabled
or is in shutdown state. A micropower 1.22V reference,
a comparator A10 and a controllable current source I
S1
allow the user to accurately program the supply voltage
at which the IC turns on and off. The falling value can be
accurately set by the resistor dividers R3 and R4. When
EN/UVLO is above 0.4V, and below the 1.22V threshold,
TheLT3958hasaswitchcurrentlimitfunction.Thecurrent
sense voltage is input to the current limit comparator A6.
If the SENSE2 pin voltage is higher than the sense current
the small pull-down current source I (typical 2µA) is
S1
active.
limit threshold V
(48mV, typical), A6 will reset
SENSE(MAX)
SR1 and turn off M1 immediately.
The purpose of this current is to allow the user to program
therisinghysteresis.TheBlockDiagramofthecomparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
The LT3958 is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
configured as a boost, flyback or SEPIC converter to gen-
erate positive output voltage, or as an inverting converter
to generate negative output voltage. When configured as
a SEPIC converter, as shown in Figure 1, the FBX pin is
pulled up to the internal bias voltage of 1.6V by a volt-
(R3+ R4)
VVIN,FALLING = 1.22•
R4
VVIN,RISING = 2µA •R3+ VIN,FALLING
age divider (R1 and R2) connected from V
to SGND.
OUT
For applications where the EN/UVLO pin is only used as
a logic input, the EN/UVLO pin can be connected directly
Comparator A2 becomes inactive and comparator A1
performs the inverting amplification from FBX to VC.
When the LT3958 is in an inverting configuration, the
FBX pin is pulled down to –0.8V by a voltage divider
to the input voltage V through a 1k resistor for always-
IN
on operation.
connected from V
to SGND. Comparator A1 becomes
OUT
inactive and comparator A2 performs the noninverting
amplification from FBX to VC.
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INTV Regulator Bypassing and Operation
If the input voltage V does not exceed the INTV
CC
IN
CC
CC
overvoltagelockoutthresholdvoltage(12.8V), theINTV
Aninternal,lowdropout(LDO)voltageregulatorproduces
pin can be shorted directly to the V pin. In this condi-
IN
the 7.2V INTV supply which powers the gate driver, as
CC
tion, the internal LDO will be turned off and the gate driver
shown in Figure 1. The LT3958 contains an undervoltage
lockout comparator A8 and an overvoltage lockout com-
will be powered directly from the input voltage V . With
IN
the INTV pin shorted to V , however, a small current
CC
IN
paratorA9fortheINTV supply.TheINTV undervoltage
CC
CC
(around16µA)willloadtheINTV inshutdownmode.For
CC
(UV) threshold is 3.75V (typical), with 0.15V hysteresis,
to ensure that the internal MOSFET has sufficient gate
drive voltage before turning on. The logic circuitry within
applications that require the lowest shutdown mode input
supply current, do not connect the INTV pin to V .
CC
IN
the LT3958 is also powered from the internal INTV
supply.
In SEPIC or flyback applications, the INTV pin can be
CC
CC
connected to the output voltage V
through a blocking
OUT
diode, as shown in Figure 2, if V
conditions:
meets the following
OUT
The INTV overvoltage threshold is set to be 12.8V
CC
(typical) to protect the gate of the power MOSFET. When
INTV isbelowtheUVthreshold,orabovetheovervoltage
1. V
2. V
< V (pin voltage)
CC
OUT
OUT
IN
threshold, the internal power switch will be turned off and
< 12.8V (typical)
the soft-start operation will be triggered.
A resistor R can be connected, as shown in Figure 2, to
VCC
The INTV regulator must be bypassed to SGND imme-
CC
limit the inrush current from V . Regardless of whether
OUT
diately adjacent to the IC pins with a minimum of 4.7µF
ceramic capacitor. Good bypassing is necessary to supply
the high transient currents required by the MOSFET gate
driver.
or not the INTV pin is connected to an external voltage
CC
source, it is always necessary to have the driver circuitry
bypassedwitha4.7µFlowESRceramiccapacitortoground
immediately adjacent to the INTV and SGND pins.
CC
In an actual application, most of the IC supply current is
used to drive the gate capacitance of the internal power
MOSFET. The on-chip power dissipation can be significant
when the internal power MOSFET is being driven at a high
D
VCC
R
VCC
V
INTV
OUT
CC
LT3958
C
VCC
4.7µF
frequency and the V voltage is high.
IN
SGND
Aneffectiveapproachtoreducethepowerconsumptionof
theinternalLDOforgatedriveandtoimprovetheefficiency
3958 F02
is to tie the INTV pin to an external voltage source high
CC
Figure 2. Connecting INTVCC to VOUT
enough to turn off the internal LDO regulator.
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Operating Frequency and Synchronization
Duty Cycle Consideration
The choice of operating frequency may be determined by
on-chippowerdissipation(alowswitchingfrequencymay
be required to ensure IC junction temperature does not
exceed125°C),otherwiseitisatrade-offbetweenefficiency
and component size. Low frequency operation improves
efficiency by reducing gate drive current and MOSFET
and diode switching losses. However, lower frequency
operation requires a physically larger inductor. Switching
frequency also has implications for loop compensation.
The LT3958 uses a constant-frequency architecture that
can be programmed over a 100kHz to 1000kHz range
with a single external resistor from the RT pin to ground,
as shown in Figure 1. The RT pin must have an external
resistor to SGND for proper operation of the LT3958.
Switching duty cycle is a key variable defining converter
operation.Assuch,itslimitsmustbeconsidered.Minimum
on-time is the smallest time duration that the LT3958 is
capable of turning on the power MOSFET. This time is
generally about 250ns (typical) (see Minimum On-Time
in the Electrical Characteristics table). In each switching
cycle, the LT3958 keeps the power switch off for at least
200ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
Theminimumon-time,minimumoff-timeandtheswitching
frequency define the minimum and maximum switching
duty cycles a converter is able to generate:
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
A table for selecting the value of R for a given operating
T
frequency is shown in Table 1.
Programming the Output Voltage
Table 1. Timing Resistor (RT) Value
SWITCHING FREQUENCY (kHz)
R (kΩ)
The output voltage V
is set by a resistor divider, as
T
OUT
shown in Figure 1. The positive and negative V
by the following equations:
are set
100
200
300
400
500
600
700
800
900
1000
140
63.4
41.2
30.9
24.3
19.6
16.5
14
OUT
R2
R1
VOUT,POSITIVE = 1.6V • 1+
R2
R1
VOUT,NEGATIVE = –0.8V • 1+
The resistors R1 and R2 are typically chosen so that
the error caused by the current flowing into the FBX pin
during normal operation is less than 1% (this translates
to a maximum value of R1 at about 158k).
12.1
10.5
The operating frequency of the LT3958 can be synchro-
nized to an external clock source. By providing a digital
clock signal into the SYNC pin, the LT3958 will operate
at the SYNC clock frequency. The LT3958 detects the ris-
ing edge of each Sync clock cycle. If this feature is used,
an R resistor should be chosen to program a switching
T
frequency 20% slower than SYNC pulse frequency. Tie
the SYNC pin to SGND if this feature is not used. It is
recommended that the Sync input clock has a minimum
pulse width of 200ns.
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Soft-Start
FBX Frequency Foldback
When V is very low during start-up, or an output short-
The LT3958 contains several features to limit peak switch
OUT
currents and output voltage (V ) overshoot during
circuit on a SEPIC, an inverting, or a flyback converter, the
switching regulator must operate at low duty cycles to
maintain the power switch current within the current limit
range, since the inductor current decay rate is very low
during switch off time. The minimum on-time limitation
may prevent the switcher from attaining a sufficiently low
dutycycleattheprogrammedswitchingfrequency.So,the
switch current may keep increasing through each switch
cycle,exceedingtheprogrammedcurrentlimit.Toprevent
the switch peak currents from exceeding the programmed
value, the LT3958 contains a frequency foldback function
to reduce the switching frequency when the FBX voltage is
low(seetheNormalizedSwitchingFrequencyvsFBXgraph
in the Typical Performance Characteristics section).
OUT
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
High peak switch currents during start-up may occur in
switching regulators. Since V
is far from its final value,
OUT
the feedback loop is saturated and the regulator tries to
chargetheoutputcapacitorasquicklyaspossible,resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
The LT3958 addresses this mechanism with the SS pin.
As shown in Figure 1, the SS pin reduces the power
MOSFET current by pulling down the VC pin through
Q2. In this way the SS allows the output capacitor to
charge gradually toward its final value while limiting the
start-up peak currents. The typical start-up waveforms
are shown in the Typical Performance Characteristics
During frequency foldback, external clock synchroniza-
tion is disabled to prevent interference with frequency
reducing operation.
section. The inductor current I slewing rate is limited by
L
Loop Compensation
the soft-start function.
Loop compensation determines the stability and transient
performance. The LT3958 uses current mode control to
regulate the output which simplifies loop compensation.
The optimum values depend on the converter topology, the
component values and the operating conditions (including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3958, a series resistor-capacitor
network is usually connected from the VC pin to SGND.
Figure 1 shows the typical VC compensation network. For
most applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range of 5k
to 50k. A small capacitor is often connected in parallel with
the RC compensation network to attenuate the VC voltage
ripple induced from the output voltage ripple through the
internalerroramplifier.Theparallelcapacitorusuallyranges
in value from 10pF to 100pF. A practical approach to design
thecompensationnetworkistostartwithoneofthecircuits
inthisdatasheetthatissimilartoyourapplication,andtune
the compensation network to optimize the performance.
Stabilityshouldthenbecheckedacrossalloperatingcondi-
tions,includingloadcurrent,inputvoltageandtemperature.
Application Note 76 is a good reference.
Besides start-up (with EN/UVLO), soft-start can also be
triggered by the following faults:
1. INTV > 12.8V (typical)
CC
2. INTV < 3.55V
CC
3. Thermal lockout
Any of these three faults will cause the LT3958 to stop
switching immediately. The SS pin will be discharged by
Q3. When all faults are cleared and the SS pin has been
discharged below 0.2V, a 10µA current source I starts
S2
charging the SS pin, initiating a soft-start operation.
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
1.25V
10µA
TSS = CSS
•
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The Internal Power Switch Current
On-Chip Power Dissipation and Thermal Lockout (TLO)
Theon-chippowerdissipationofLT3958canbeestimated
using the following equation:
For control and protection, the LT3958 measures the
internal power MOSFET current by using a sense resistor
(R
) between GND and the MOSFET source. Figure 3
2
2
SENSE
P ≈I
IC
• D • R
+V
• I •ƒ•200pF/A+
SW(PEAK) SW
SW
IN
DS(ON)
shows a typical waveform of the internal switch current
V • (1.6mA + ƒ • 10nC)
(I ).
SW
where R
is the internal switch on-resistance which
DS(ON)
I
canbeobtainedfromtheTypicalPerformanceCharacteris-
SW
∆I
SW
ticssection.V
ThemaximumpowerdissipationP
isthepeakswitchoff-statevoltage.
SW(PEAK)
canbeobtained
IC(MAX)
I
SW(PEAK)
by comparing P across all the V range at the maximum
IC
IN
output current . The highest junction temperature can be
t
DT
S
estimated using the following equation:
T
S
3958 F03
T
≈ T + P
• 42°C/W
J(MAX)
A
IC(MAX)
ItisrecommendedtomeasuretheICtemperatureinsteady
state to verify that the junction temperature limit is not
exceeded. A low switching frequency may be required to
Figure 3. The Switch Current During a Switching Cycle
Due to the current limit (minimum 3.3A) of the internal
power switch, the LT3958 should be used in the applica-
ensure T
does not exceed 125°C.
J(MAX)
tions that the switch peak current I
during steady
SW(PEAK)
If LT3958 die temperature reaches thermal lockout
threshold at 165°C (typical), the IC will initiate several
protective actions. The power switch will be turned off.
A soft-start operation will be triggered. The IC will be en-
abled again when the junction temperature has dropped
by 5°C (nominal).
state normal operation is lower than 3.3A by a sufficient
margin (10% or higher is recommended).
The LT3958 switching controller incorporates 100ns
timing interval to blank the ringing on the current sense
signal across R
immediately after M1 is turned on.
SENSE
This ringing is caused by the parasitic inductance and
capacitance of the PCB trace, the sense resistor, the diode,
and the MOSFET. The 100ns timing interval is adequate
for most of the LT3958 applications. In the applications
that have very large and long ringing on the current sense
signal,asmallRCfiltercanbeaddedtofilterouttheexcess
ringing. Figure 4 shows the RC filter on the SENSE1 and
SENSE2 pins. It is usually sufficient to choose 22Ω for
LT3958
SENSE1
R
FLT
SENSE2
C
FLT
SGND
3958 F04
R
and 2.2nF to 10nF for C . Keep R ’s resistance
FLT
FLT FLT
Figure 4. The RC Filter on SENSE1 Pin and SENSE2 Pin
low. Remember that there is 65µA (typical) flowing out of
the SENSE2 pin. Adding R will affect the internal power
FLT
switch current limit threshold:
65µA •RFLT
ISW _ILIM = 1−
•3.3A
48mV
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APPLICATION CIRCUITS
mum output current (I
) is less than the maximum
O(MAX)
output current capability by a sufficient margin (10% or
higher is recommended):
The LT3958 can be configured as different topologies. The
first topology to be analyzed will be the boost converter,
followed by the flyback, SEPIC and inverting converters.
V
IN(MIN)
IO(MAX)
≤
• 3.3A − 0.5• ∆I
(
SW
)
VOUT
Boost Converter: Switch Duty Cycle and Frequency
The inductor ripple current ∆I has a direct effect on the
The LT3958 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
SW
choice of the inductor value and the converter’s maximum
output current capability. Choosing smaller values of
∆I
increases output current capability, but requires
large inductances and reduces the current loop gain (the
converter will approach voltage mode). Accepting larger
SW
valuesof∆I providesfasttransientresponseandallows
SW
the use of low inductances, but results in higher input
current ripple, greater core losses, lower output current
capability and in some cases, subharmonic oscillation. A
The conversion ratio as a function of duty cycle is
good start point for ∆I is 0.6A though careful evaluation
SW
VOUT
VIN 1− D
1
of system stabililty should be made to ensure adequate
=
design margin.
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
theinductorvalueoftheboostconvertercanbedetermined
using the following equation:
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (V ) and the input voltage (V ). The maximum
OUT
duty cycle (D
minimum input voltage:
IN
VIN(MIN)
) occurs when the converter has the
MAX
L =
•DMAX
∆ISW • ƒ
VOUT − VIN(MIN)
Thepeakinductorcurrentistheswitchcurrentlimit(typical
4A), and the RMS inductor current is approximately equal
DMAX
=
VOUT
to I
. The user should choose the inductors having
L(MAX)
Discontinuous conduction mode (DCM) provides higher
conversionratiosatagivenfrequencyatthecostofreduced
efficiencies and higher switching currents.
sufficient saturation and RMS current ratings.
Boost Converter: Output Diode Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current.
Boost Converter: Maximum Output Current Capability
and Inductor Selection
For the boost topology, the maximum average inductor
current is:
1
IL(MAX)= IO(MAX)
•
1− DMAX
It is recommended that the peak repetitive reverse voltage
Due to the current limit of its internal power switch, the
LT3958 should be used in a boost converter whose maxi-
rating V
is higher than V
by a safety margin (a 10V
RRM
OUT
safety margin is usually sufficient).
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The power dissipated by the diode is:
t
t
OFF
ON
∆V
COUT
P = I
• V
D
D
O(MAX)
V
OUT
(AC)
where V is diode’s forward voltage drop, and the diode
D
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
junction temperature is:
∆V
ESR
3958 F05
T = T + P • R
θJA
J
A
D
The R to be used in this equation normally includes the
Figure 5. The Output Ripple Waveform of a Boost Converter
θJA
R
for the device plus the thermal resistance from the
θJC
board to the ambient temperature in the enclosure. T must
Theoutputcapacitorinaboostregulatorexperienceshigh
RMSripplecurrents, asshowninFigure5. TheRMSripple
current rating of the output capacitor can be determined
using the following equation:
J
notexceedthediodemaximumjunctiontemperaturerating.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
thesethreeparameters(ESR,ESLandbulkC)ontheoutput
voltage ripple waveform for a typical boost converter is
illustrated in Figure 5.
DMAX
1− DMAX
IRMS(COUT) ≥ IO(MAX)
•
MultiplecapacitorsareoftenparalleledtomeetESRrequire-
ments.Typically,oncetheESRrequirementissatisfied,the
capacitance is adequate for filtering and has the required
RMS current rating. Additional ceramic capacitors in par-
allel are commonly used to reduce the effect of parasitic
inductance in the output capacitor, which reduces high
frequency switching noise on the converter output.
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ∆V
and the charging/discharg-
ESR
Boost Converter: Input Capacitor Selection
ing ∆V
. For the purpose of simplicity, we will choose
COUT
2% for the maximum output ripple, to be divided equally
between ∆V and ∆V . This percentage ripple will
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 1µF to 100µF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
ESR
COUT
change,dependingontherequirementsoftheapplication,
and the following equations can easily be modified. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:
0.01• VOUT
ID(PEAK)
ESRCOUT
≤
The RMS input capacitor ripple current for a boost con-
verter is:
For the bulk C component, which also contributes 1% to
the total ripple:
I
= 0.3 • ∆I
L
RMS(CIN)
IO(MAX)
COUT
≥
0.01• VOUT • ƒ
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FLYBACK CONVERTER APPLICATIONS
period T , three subintervals occur: DT , D2T , D3T .
S S S S
During DT , M is on, and D is reverse-biased. During
S
TheLT3958canbeconfiguredasaflybackconverterforthe
applications where the converters have multiple outputs,
high output voltages or isolated outputs. Figure 6 shows
a simplified flyback converter.
D2T , M is off, and L is conducting current. Both L and
S
S
P
L currents are zero during D3T .
S
S
The flyback converter conversion ratio in the discontinu-
ous mode operation is:
The flyback converter has a very low parts count for mul-
tipleoutputs, andwithprudentselectionofturnsratio, can
have high output/input voltage conversion ratios with a
desirable duty cycle. However, it has low efficiency due to
thehighpeakcurrents,highpeakvoltagesandconsequent
power loss. The flyback converter is commonly used for
an output power of less than 50W.
VOUT NS
VIN NP D2
D
=
•
According to Figure 6, the peak SW voltage is:
V
= V
+ V
SW(PEAK)
IN(MAX) SN
where V is the snubber capacitor voltage. A smaller V
SN
SN
The flyback converter can be designed to operate either
in continuous or discontinuous mode. Compared to con-
tinuous mode, discontinuous mode has the advantage of
smaller transformer inductances and easy loop compen-
sation, and the disadvantage of higher peak-to-average
current and lower efficiency.
results in a larger snubber loss. A reasonable V is 1.5
SN
to 2 times of the reflected output voltage:
VOUT •NP
VSN = k •
NS
k = 1.5 ~ 2
SUGGESTED
RCD SNUBBER
D
N :N
P
S
AccordingtotheAbsoluteMaximumRatingstable,theSW
voltage Absolute Maximum value is 84V. Therefore, the
maximum primary to secondary turns ratio (for both the
continuous and the discontinuous operation) should be.
V
IN
+
–
+
–
SN
+
V
I
D
C
C
C
+
R
SN
IN
SN
V
OUT
L
L
S
P
OUT
D
SN
84V − V
NP
NS
IN(MAX)
≤
I
SW
k • VOUT
SW
LT3958
GND
V
SW
3958 F06
Figure 6. A Simplified Flyback Converter
I
SW
Flyback Converter: Switch Duty Cycle and Turns Ratio
The flyback converter conversion ratio in the continuous
mode operation is:
I
D
VOUT NS
D
=
•
VIN NP 1− D
I
D(MAX)
where N /N is the second to primary turns ratio. D is
S
P
DT
S
D2T
D3T
S
t
S
duty cycle.
T
S
3958 F07
Figure 7 shows the waveforms of the flyback converter
in discontinuous mode operation. During each switching
Figure 7. Waveforms of the Flyback Converter
in Discontinuous Mode Operation
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Accordingtotheprecedingequations,theuserhasrelative
freedom in selecting the switch duty cycle or turns ratio to
suit a given application. The selections of the duty cycle
and the turns ratio are somewhat iterative processes, due
to the number of variables involved. The user can choose
either a duty cycle or a turns ratio as the start point. The
following trade-offs should be considered when select-
ing the switch duty cycle or turns ratio, to optimize the
converter performance. A higher duty cycle affects the
flyback converter in the following aspects:
output current capability. Choosing smaller values of
∆I increases the output current capability, but requires
SW
large primary and secondary inductances and reduce the
current loop gain (the converter will approach voltage
mode). Accepting larger values of ∆I allows the use
SW
of low primary and secondary inductances, but results
in higher input current ripple, greater core losses, lower
outputcurrentcapabilityandinsomecases, subharmonic
oscillation. A good start point for ∆I is 0.6A though
SW
careful evaluation of system stabililty should be made to
ensure adequate design margin.
• Lower MOSFET RMS current I
, but higher
SW(RMS)
MOSFET V peak voltage
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the primary
winding,theprimarywindinginductancecanbecalculated
using the following equation:
SW
• Lower diode peak reverse voltage, but higher diode
RMS current I
D(RMS)
• Higher transformer turns ratio (N /N )
P
S
V
IN(MIN)
It is recommended to choose a duty cycle between 20%
and 80%.
L =
•DMAX
∆ISW • ƒ
The primary winding peak current is the switch current
limit (typical 4A). The primary and secondary maximum
RMS currents are:
Flyback Converter: Maximum Output Current
Capability and Transformer Design
The maximum output current capability and transformer
design for continuous conduction mode (CCM) is chosen
as presented here.
POUT(MAX)
ILP(RMS)
≈
≈
DMAX • VIN(MIN) • η
Themaximumdutycycle(D )occurswhentheconverter
IOUT(MAX)
MAX
ILS(RMS)
has the minimum V :
IN
1− DMAX
NP
N
where η is the converter efficiency.
VOUT
•
S
DMAX
=
Basedontheprecedingequations,theusershoulddesign/
choose the transformer having sufficient saturation and
RMS current ratings.
NP
VOUT
•
+ V
IN(MIN)
N
S
Due to the current limit of its internal power switch, the
LT3958shouldbeusedinaflybackconverterwhosemaxi-
Flyback Converter: Snubber Design
Transformer leakage inductance (on either the primary
or secondary) causes a voltage spike to occur after the
MOSFET turn-off. This is increasingly prominent at higher
load currents, where more stored energy must be dissi-
pated. In some cases a snubber circuit will be required
to avoid overvoltage breakdown at the MOSFET’s drain
node. There are different snubber circuits (such as RC
snubber, RCD snubber, etc.) and Application Note 19 is
a good reference on snubber design. An RCD snubber is
mum output current (I
) is less than the maximum
O(MAX)
output current capability by a sufficient margin (10% or
higher is recommended):
V
IN(MIN)
IO(MAX)
≤
•DMAX • 3.3A − 0.5• ∆I
SW
(
)
VOUT
The transformer ripple current ∆I has a direct effect on
SW
the design/choice of the transformer and the converter’s
shown in Figure 6.
3958fa
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LT3958
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The snubber resistor value (R ) can be calculated by the
Flyback Converter: Output Capacitor Selection
SN
following equation:
The output capacitor of the flyback converter has a similar
operation condition as that of the boost converter. Refer to
the Boost Converter: Output Capacitor Selection section
NP
V2 − VSN • VOUT
•
SN
NS
RSN = 2 •
for the calculation of C
and ESR
.
I2SW(PEAK) •LLK • ƒ
OUT
COUT
The RMS ripple current rating of the output capacitors
in continuous operation can be determined using the
following equation:
L
is the leakage inductance of the primary winding,
LK
which is usually specified in the transformer character-
istics. L can be obtained by measuring the primary
LK
DMAX
inductance with the secondary windings shorted. The
IRMS(COUT),CONTINUOUS ≈ IO(MAX)
•
1− DMAX
snubber capacitor value (C ) can be determined using
SN
the following equation:
VSN
∆VSN •RSN • ƒ
Flyback Converter: Input Capacitor Selection
CSN
=
The input capacitor in a flyback converter is subject to
a large RMS current due to the discontinuous primary
current. To prevent large voltage transients, use a low
ESR input capacitor sized for the maximum RMS current.
The RMS ripple current rating of the input capacitors in
continuous operation can be determined using the fol-
lowing equation:
where ∆V is the voltage ripple across C . A reasonable
SN
SN
∆V is 5% to 10% of V . The reverse voltage rating of
SN
SN
SN
D
should be higher than the sum of V and V
.
SN
IN(MAX)
Flyback Converter: Output Diode Selection
The output diode in a flyback converter is subject to large
RMS current and peak reverse voltage stresses. A fast
switching diode with a low forward drop and a low reverse
leakage is desired. Schottky diodes are recommended if
the output voltage is below 100V.
POUT(MAX)
1− DMAX
DMAX
IRMS(CIN),CONTINUOUS
≈
•
VIN(MIN) • η
SEPIC CONVERTER APPLICATIONS
Approximate the required peak repetitive reverse voltage
The LT3958 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
rating V
using:
RRM
NS
VRRM
>
• VIN(MAX) + VOUT
NP
The power dissipated by the diode is:
P = I • V
VOUT + VD
D
1− D
=
D
O(MAX)
D
VIN
and the diode junction temperature is:
T = T + P • R
in continuous conduction mode (CCM).
J
A
D
θJA
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
The R to be used in this equation normally includes the
θJA
R
for the device, plus the thermal resistance from the
θJC
board to the ambient temperature in the enclosure. T must
J
notexceedthediodemaximumjunctiontemperaturerating.
3958fa
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LT3958
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Compared to the flyback converter, the SEPIC converter
In a SEPIC converter, the switch current is equal to I
L2
average switch current is defined as:
+
L1
has the advantage that both the power MOSFET and the
I
when the power switch is on, therefore, the maximum
output diode voltages are clamped by the capacitors (C ,
IN
C
DC
and C ), therefore, there is less voltage ringing
OUT
1
across the power MOSFET and the output diodes. The
SEPIC converter requires much smaller input capacitors
than those of the flyback converter. This is due to the fact
that, in the SEPIC converter, the current through inductor
L1 (which is series with the input) is continuous.
ISW(MAX) = IL1(MAX) + IL2(MAX) = IO(MAX)
•
1− DMAX
Due to the current limit of its internal power switch,
the LT3958 should be used in a SEPIC converter whose
maximum output current (I ) is less than the output
O(MAX)
current capability by a sufficient margin (10% or higher
is recommended):
SEPIC Converter: Switch Duty Cycle and Frequency
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
voltage (V ), the input voltage (V ) and the diode
I
< (1 – D
) • (3.3A – 0.5 • ∆I
)
SW
O(MAX)
MAX
The inductor ripple currents ∆I and ∆I are identical:
OUT
IN
L1
L2
forward voltage (V ).
D
∆I
= ∆I = 0.5 • ∆I
L2 SW
L1
Themaximumdutycycle(D )occurswhentheconverter
MAX
The inductor ripple current ∆I has a direct effect on the
SW
has the minimum input voltage:
choice of the inductor value and the converter’s maximum
VOUT + VD
VIN(MIN) + VOUT + VD
outputcurrentcapability.Choosingsmallervaluesof∆I
SW
DMAX
=
requires large inductances and reduces the current loop
gain(theconverterwillapproachvoltagemode).Accepting
larger values of ∆I allows the use of low inductances,
SW
SEPIC Converter: The Maximum Output Current
Capability and Inductor Selection
but results in higher input current ripple, greater core
losses, lower output current capability and in some cases,
As shown in Figure 1, the SEPIC converter contains two
inductors: L1 and L2. L1 and L2 can be independent, but
can also be wound on the same core, since identical volt-
ages are applied to L1 and L2 throughout the switching
cycle.
subharmonic oscillation. A good start point for ∆I is
SW
0.6A though careful evaluation of system stabililty should
be made to ensure adequate design margin.
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the induc-
tor, the inductor value (L1 and L2 are independent) of the
SEPIC converter can be determined using the following
equation:
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
VIN(MIN)
L1= L2=
•DMAX
DMAX
1− DMAX
1.5A • ∆ISW • ƒ
IL1(MAX) = IIN(MAX) = IO(MAX)
•
For most SEPIC applications, the equal inductor values
will fall in the range of 1µH to 100µH.
IL2(MAX) = IO(MAX)
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BymakingL1=L2,andwindingthemonthesamecore,the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
SEPIC Converter: Output and Input Capacitor Selection
The selections of the output and input capacitors of the
SEPICconverteraresimilartothoseoftheboostconverter.
Please refer to the Boost Converter: Output Capacitor
Selection and Boost Converter: Input Capacitor Selection
sections.
VIN(MIN)
L =
•DMAX
∆ISW • ƒ
Thismaintainsthesameripplecurrentandenergystorage
in the inductors. The peak inductor currents are:
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (C ,
as shown in Figure 1) should be larger than the maximum
input voltage:
DC
I
I
= I
= I
+ 0.5 • ∆I
+ 0.5 • ∆I
L1(PEAK)
L2(PEAK)
L1(MAX)
L2(MAX)
L1
L2
The maximum RMS inductor currents are approximately
equal to the maximum average inductor currents.
V
> V
IN(MAX)
CDC
C
has nearly a rectangular current waveform. During
DC
Basedontheprecedingequations,theusershouldchoose
the inductors having sufficient saturation and RMS cur-
rent ratings.
the switch off-time, the current through C is I , while
DC
IN
approximately –I flows during the on-time. The RMS
O
rating of the coupling capacitor is determined by the fol-
lowing equation:
SEPIC Converter: Output Diode Selection
VOUT + VD
VIN(MIN)
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current.
IRMS(CDC) > IO(MAX)
•
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
DC
It is recommended that the peak repetitive reverse voltage
rating V
is higher than V
+ V
by a safety
RRM
OUT
IN(MAX)
INVERTING CONVERTER APPLICATIONS
margin (a 10V safety margin is usually sufficient).
TheLT3958canbeconfiguredasadual-inductorinverting
The power dissipated by the diode is:
topology, as shown in Figure 8. The V
to V ratio is:
OUT
IN
P = I
D
• V
D
O(MAX)
VOUT − VD
D
1− D
= −
where V is diode’s forward voltage drop, and the diode
D
VIN
junction temperature is:
in continuous conduction mode (CCM).
T = T + P • R
θJA
J
A
D
The R used in this equation normally includes the R
θJA
θJC
C
+
DC
L1
L2
for the device, plus the thermal resistance from the board,
–
V
IN
+
–
to the ambient temperature in the enclosure. T must not
J
C
IN
C
V
OUT
OUT
exceed the diode maximum junction temperature rating.
SW
LT3958
+
D1
+
3758 F10
GND
Figure 8. A Simplified Inverting Converter
3958fa
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LT3958
applicaTions inForMaTion
Inverting Converter: Switch Duty Cycle and Frequency
Inverting Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor
ForaninvertingconverteroperatinginCCM,thedutycycle
of themain switch canbecalculatedbased onthenegative
(C , as shown in Figure 10) should be larger than the
DC
output voltage (V ) and the input voltage (V ).
maximum input voltage minus the output voltage (nega-
tive voltage):
OUT
IN
Themaximumdutycycle(D )occurswhentheconverter
MAX
has the minimum input voltage:
V
CDC
> V
– V
IN(MAX) OUT
VOUT − VD
VOUT − VD − VIN(MIN)
C
has nearly a rectangular current waveform. During
DC
DMAX
=
the switch off-time, the current through C is I , while
DC
IN
approximately –I flows during the on-time. The RMS
O
rating of the coupling capacitor is determined by the fol-
lowing equation:
Inverting Converter: Output Diode and Input Capacitor
Selections
DMAX
1− DMAX
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those
of the SEPIC converter. Please refer to the corresponding
SEPIC converter sections.
IRMS(CDC) > IO(MAX)
•
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
DC
Inverting Converter: Output Capacitor Selection
Board Layout
The inverting converter requires much smaller output
capacitors than those of the boost, flyback and SEPIC
convertersforsimilaroutputripples. Thisisduetothefact
that, in the inverting converter, the inductor L2 is in series
with the output, and the ripple current flowing through the
outputcapacitorsarecontinuous.Theoutputripplevoltage
isproducedbytheripplecurrentofL2flowing through the
ESR and bulk capacitance of the output capacitor:
The high power and high speed operation of the LT3958
demands careful attention to board layout and component
placement. Careful attention must be paid to the internal
power dissipation of the LT3958 at high input voltages,
highswitchingfrequencies,andhighinternalpowerswitch
currents to ensure that a junction temperature of 125°C is
not exceeded. This is especially important when operating
at high ambient temperatures. Exposed pads on the bot-
tom of the package are SGND and SW terminals of the IC,
and must be soldered to a SGND ground plane and a SW
plane respectively. It is recommended that multiple vias
in the printed circuit board be used to conduct heat away
from the IC and into the copper planes with as much as
area as possible.
1
∆VOUT(P–P) = ∆IL2 • ESRCOUT
+
8 • ƒ •COUT
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
To prevent radiation and high frequency resonance
problems, proper layout of the components connected
to the IC is essential, especially the power paths with
higher di/dt. The following high di/dt loops of different
topologies should be kept as tight as possible to reduce
inductive ringing:
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
The RMS ripple current rating of the output capacitor
needs to be greater than:
• In boost configuration, the high di/dt loop contains
the output capacitor, the internal power MOSFET and
the Schottky diode.
I
> 0.3 • ∆I
L2
RMS(COUT)
3958fa
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LT3958
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Make sure the inductive ringing does not exceed the
maximum rating of the internal power MOSFET (84V).
• In flyback configuration, the high di/dt primary loop
contains the input capacitor, the primary winding,
the internal power MOSFET. The high di/dt second-
ary loop contains the output capacitor, the secondary
winding and the output diode.
Thesmall-signalcomponentsshouldbeplacedawayfrom
highfrequencyswitchingnodes.Foroptimumloadregula-
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
thetopoftheoutputcapacitor(Kelvinconnection),staying
away from any high dV/dt traces. Place the divider resis-
tors near the LT3958 in order to keep the high impedance
FBX node short.
• In SEPIC configuration, the high di/dt loop con-
tains the internal power MOSFET, output capacitor,
Schottky diode and the coupling capacitor.
• In inverting configuration, the high di/dt loop con-
tains internal power MOSFET, Schottky diode and the
coupling capacitor.
Figure9showsthesuggestedlayoutofthe48VV boost
OUT
converter (see the Typical Applications section).
CheckthestressontheinternalpowerMOSFETbymeasur-
ingtheSW-to-GNDvoltagedirectlyacrosstheICterminals.
R1
VIA TO V
OUT
R2
C
SS
R
R
C
C
T
C
36 35 34 33 32 31 30
C
VCC
1
2
3
4
28
27
R3
37
25
24
23
R4
LT3958
6
8
9
21
20
38
10
12 13 14 15 16 17
L1
D1
C
C
OUT
OUT
C
IN
VIA TO V
OUT
GND
V
OUT
V
IN
3958 F09
VIAS TO SGND GROUND PLANE
VIAS TO SW PLANE
Figure 9. Suggested Layout of the 10V to 40V Input, 48V Output Boost Converter
3958fa
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For more information www.linear.com/LT3958
LT3958
applicaTions inForMaTion
Recommended Component Manufacturers
Some of the recommended component manufacturers
are listed in Table 2.
Table 2. Recommended Component Manufacturers
VENDOR
AVX
COMPONENTS
WEB ADDRESS
avx.com
Capacitors
BH Electronics
Inductors,
Transformers
bhelectronics.com
Coilcraft
Inductors
Inductors
Diodes
coilcraft.com
bussmann.com
diodes.com
Cooper Bussmann
Diodes, Inc
General Semiconductor
Diodes
generalsemiconductor.
com
International Rectifier
Kemet
Diodes
Tantalum Capacitors
Toroid Cores
Diodes
irf.com
kemet.com
Magnetics Inc
Microsemi
Murata-Erie
Nichicon
mag-inc.com
microsemi.com
murata.co.jp
nichicon.com
onsemi.com
panasonic.com
pulseeng.com
sanyo.co.jp
Inductors, Capacitors
Capacitors
On Semiconductor
Panasonic
Pulse
Diodes
Capacitors
Inductors
Sanyo
Capacitors
Sumida
Inductors
sumida.com
t-yuden.com
Taiyo Yuden
TDK
Capacitors
Capacitors, Inductors component.tdk.com
Thermalloy
Tokin
Heat Sinks
Capacitors
aavidthermalloy.com
nec-tokinamerica.com
tokoam.com
Toko
Inductors
United Chemi-Con
Vishay
Capacitors
chemi-com.com
vishay.com
Inductors
Würth Elektronik
Vishay/Sprague
Zetex
Inductors
we-online.com
vishay.com
Capacitors
Small-Signal Discretes
zetex.com
3958fa
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For more information www.linear.com/LT3958
LT3958
Typical applicaTions
10V to 40V Input, 48V Output Boost Converter
L1
Efficiency vs Output Current
D1
33µH
V
OUT
V
IN
48V
100
95
90
85
80
75
70
12V TO 40V
C
C
OUT
0.5A
IN
V
= 24V
IN
R3
392k
4.7µF
50V
X5R
4.7µF
50V
X5R
×2
V
SW
IN
EN/UVLO
GND
R4
53.6k
LT3958
SGND
SYNC
SENSE1
R2
SENSE2
FBX
464k
R1
15.8k
INTV
CC
RT SS
VC
C
R
VCC
R
T
C
C
SS
4.7µF
10V
41.2k
10k
0.33µF
300kHz
C
10nF
X5R
C
0
400
500
100
200
300
OUTPUT CURRENT (mA)
3958 TA02b
3958 TA02a
C
, C
: MURATA GRM32ER71H475KA88L
IN OUT
D1: VISHAY SILICONIX 10BQ060
L2: VISHAY SILICONIX IHLP-4040DZ-11
High Voltage Flyback Power Supply
DANGER! HIGH VOLTAGE OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY
T1
D1
V
OUT
1:10
V
IN
300V
5.5V TO 12V
C
47µF
10mA
OUT
•
68nF
16V
×2
×2
•
220pF
22Ω
1.5M
1.5M
31.6k
10k
V
SW
GND
IN
EN/UVLO
FBX
LT3958
VC
SGND
SYNC
SENSE1
22Ω
SENSE2
INTV
CC
RT SS
10nF
4.7µF
10V
X5R
140k
100kHz
0.1µF
100pF
16.2k
10k
10nF
3958 TA03
C
C
: MURATA GRM32ER61C476M
OUT
IN
: TDK C3225X7R2J683K
D1: VISHAY SILICONIX GSD2004S DUAL DIODE CONNECTED IN SERIES
T1: TDK DCT15EFD-U44S003
3958fa
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For more information www.linear.com/LT3958
LT3958
Typical applicaTions
10V to 60V Input, 12V Output SEPIC Converter
C
DC
2.2µF, 100V
X7R, ×2
L1A
D1
V
12V
1A
OUT
V
IN
10V TO 60V
C
C
OUT
IN
2.2µF
100V
X5R
22µF
16V
X5R
×2
L1B
V
SW
392k
IN
•
EN/UVLO
GND
66.5k
LT3958
SGND
SYNC
SENSE1
105k
SENSE2
FBX
INTV
CC
RT SS
VC
10k
10nF
15.8k
41.2k
300kHz
C
VCC
4.7µF
10V
0.47µF
X5R
3958 TA04a
C
C
, C : MURATA GRM32ER72A225KA35L
OUT
IN DC
: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX 10MQ100N
L1A, L1B: COILTRONICS DRQ125-220
Efficiency vs Output Current
Load Step Waveforms
90
85
80
75
70
65
60
55
50
V
= 24V
V
= 24V
IN
IN
V
OUT
0.5V/DIV
(AC)
0.8A
I
OUT
0.5A/DIV
0.2A
3958 TA04c
500µs/DIV
0
800
1000
200
400
600
OUTPUT CURRENT (mA)
3958 TA04b
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveforms
V
= 24V
V
= 24V
IN
IN
V
OUT
10V/DIV
V
OUT
5V/DIV
V
SW
20V/DIV
I
+ I
L1A L1B
2A/DIV
I
+ I
L1A L1B
2A/DIV
3958 TA04d
3958 TA04e
5ms/DIV
50µs/DIV
3958fa
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For more information www.linear.com/LT3958
LT3958
Typical applicaTions
10V to 60V Input, –12V Output Inverting Converter
C
DC
2.2µF, 100V
X7R, ×2
L1A
L1B
V
–12V
1A
OUT
V
IN
10V TO 60V
C
C
OUT
IN
2.2µF
100V
X5R
22µF
16V
X5R
×2
D1
V
SW
392k
IN
EN/UVLO
GND
66.5k
LT3958
SGND
SYNC
SENSE1
105k
7.5k
SENSE2
FBX
INTV
CC
RT SS
VC
10k
10nF
41.2k
300kHz
C
VCC
4.7µF
10V
0.47µF
X5R
3958 TA05a
C
C
, C : MURATA GRM32ER72A225KA35L
OUT
IN DC
: MURATA GRM32ER61C226KE20
D1: VISHAY SILICONIX 10MQ100N
L1A, L1B: COILTRONICS DRQ125-220
Efficiency vs Output Current
Load Step Waveforms
90
85
80
75
70
65
60
55
50
V
= 24V
V
= 24V
IN
IN
V
OUT
1V/DIV
(AC)
0.8A
I
OUT
0.5A/DIV
0.2A
3958 TA05c
500µs/DIV
0
800
1000
200
400
600
OUTPUT CURRENT (mA)
3958 TA05b
Frequency Foldback Waveforms
When Output Short-Circuit
Start-Up Waveforms
V
= 24V
V
= 24V
IN
IN
V
OUT
V
5V/DIV
OUT
10V/DIV
V
SW
20V/DIV
I
+ I
L1A L1B
2A/DIV
I
+ I
L1A L1B
2A/DIV
3958 TA05e
3958 TA05d
50µs/DIV
5ms/DIV
3958fa
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For more information www.linear.com/LT3958
LT3958
package DescripTion
Please refer to http://www.linear.com/product/LT3958#packaging for the most recent package drawings.
UHE Package
Variation: UHE36(28)MA
36(28)-Lead Plastic QFN (5mm × 6mm)
(Reference LTC DWG # 05-08-1836 Rev D)
28 27
25 24 23
21 20
0.70 ±0.05
17
16
15
14
30
31
1.88
± 0.05
1.53
± 0.05
5.50 ± 0.05
4.10 ± 0.05
3.00 ± 0.05
3.00 ± 0.05
32
33
0.12
± 0.05
PACKAGE OUTLINE
0.48 ± 0.05
13
34
1.50 REF
35
36
12
1
2
3
4
6
8
9
10
0.25 ±0.05
2.00 REF
0.50 BSC
5.10 ± 0.05
6.50 ± 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 ± 0.05
PIN 1 NOTCH
R = 0.30 OR
0.35 × 45°
CHAMFER
R = 0.10
1.50 REF
33 34 35
5.00 ± 0.10
TYP
30 31 32
36
PIN 1
TOP MARK
(NOTE 6)
28
1
2
3
4
27
1.88 ± 0.10
2.00 REF
3.00 ± 0.10
0.12
± 0.10
25
24
6.00 ± 0.10
6
8
23
0.48 ± 0.10
1.53 ± 0.10
R = 0.125
TYP
21
20
3.00 ± 0.10
9
10
0.40 ± 0.10
17 16 15
0.25 ± 0.05
0.50 BSC
14 13 12
0.200 REF
(UHE36(28)MA) QFN 0112 REV D
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3958fa
28
For more information www.linear.com/LT3958
LT3958
revision hisTory
REV
DATE
DESCRIPTION
PAGE NUMBER
A
09/17 Clarification for Boost, Flyback and SEPIC Maximum Output Current Capability sections
15, 18, 20
3958fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
29
LT3958
Typical applicaTions
5V Output Nonisolated Flyback Power Supply
T1
D1
V
5V
2A
Efficiency vs Output Current
OUT
3:1
V
IN
10V TO 40V
90
85
80
75
70
65
60
55
50
•
0.1µF
50V
V
= 24V
C
IN
IN
1.8k
1W
C
OUT
4.7µF
50V
100µF
6.3V
•
X5R
D
SN
200k
V
SW GND
IN
EN/UVLO
32.4k
LT3958
VC
SGND
SYNC
SENSE1
SENSE2
FBX
34k
1%
0
0.5
1
1.5
2
INTV
CC
RT SS
15.8k
1%
OUTPUT CURRENT (A)
3958 TA05b
4.7µF
10V
X5R
63.4k
200kHz
0.47µF
100pF
10k
10nF
3958 TA06a
T1: COILTRONICS VP2-0066
relaTeD parTs
PART NUMBER
DESCRIPTION
COMMENTS
LT3580
Boost/Inverting DC/DC Converter with 2A Switch,
Soft-Start and Synchronization
2.5V ≤ V ≤ 32V, Current Mode Control, 200kHz to 2.5MHz, 3mm × 3mm
IN
DFN-8, MSOP-8E
LT3573
LT3574
LT3757
LT3758
Isolated Flyback Switching Regulator with 60V
Integrated Switch
3V ≤ V ≤ 40V, Up to 7W, No Opto-Isolator or Third Winding Required,
IN
MSOP-16E
Isolated Flyback Switching Regulator with 60V
Integrated Switch
3V ≤ V ≤ 40V, Up to 3W, No Opto-Isolator or Third Winding Required,
IN
MSOP-16E
Boost, Flyback, SEPIC and Inverting Controller
2.9V ≤ V ≤ 40V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
Boost, Flyback, SEPIC and Inverting Controller
5.5V ≤ V ≤ 100V, Current Mode Control, 100kHz to 1MHz Programmable
IN
Operation Frequency, 3mm × 3mm DFN-10 and MSOP-10E Package
LTC®1871/LTC1871-1/ Wide Input Range, No R
™ Low Quiescent
Adjustable Switching Frequency, 2.5V ≤ V ≤ 36V, Burst Mode Operation at
SENSE
IN
LTC1871-7
Current Flyback, Boost and SEPIC Controller
Light Load
LT3825
Isolated No-Opto Synchronous Flyback Controller
V 16V to 75V Limited by External Components, Up to 60W,
IN
Current Mode Control
V 4.5V to 36V Limited by External Components, Up to 60W,
IN
LT3837
Isolated No-Opto Synchronous Flyback Controller
Current Mode Control
LT1725
Isolated No-Opto Flyback Controller
Isolated No-Opto Flyback Controller
200kHz Flyback DC/DC Controller
V
V
V
V
16V to 75V Limited by External Components, Current Mode Control
4.5V to 36V Limited by External Components, Current Mode Control
IN
IN
IN
IN
LT1737
LTC3803/LTC3803-5
LTC3805/LTC3805-5
and V
Limited Only by External Components, ThinSOT™ Package
OUT
Adjustable Fixed 70kHz to 700kHz Operating
Frequency Flyback Controller
and V
Limited Only by External Components, 3mm × 3mm DFN-10,
OUT
MSOP-10E
LT1619
Boost, SEPIC and Flyback Current Mode PWM
Controller
1.9V ≤ V ≤ 18V, 300kHz Fixed Operating Frequency
IN
3958fa
LT 0917 REV A • PRINTED IN USA
www.linear.com/LT3958
LINEAR TECHNOLOGY CORPORATION 2010
30
相关型号：
LT3958IUHE#PBF
LT3958 - High Input Voltage, Boost, Flyback, SEPIC and Inverting Converter; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C
Linear
LT3958IUHE#TRPBF
LT3958 - High Input Voltage, Boost, Flyback, SEPIC and Inverting Converter; Package: QFN; Pins: 36; Temperature Range: -40°C to 85°C
Linear
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