LT3959 [Linear]
Wide Input Voltage Range Boost/SEPIC/Inverting Converter with 6A, 40V Switch; 宽输入电压范围升压/ SEPIC /负输出转换器6A ， 40V开关
| 型号： | LT3959 |
| 厂家： | 
Linear |
| 描述： | Wide Input Voltage Range Boost/SEPIC/Inverting Converter with 6A, 40V Switch |
| 文件： | 总24页 (文件大小：423K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3959
Wide Input Voltage Range
Boost/SEPIC/Inverting Converter
with 6A, 40V Switch
FEATURES
DESCRIPTION
The LT®3959 is a wide input range, current mode, DC/DC
controller which is capable of regulating either positive or
negative output voltages from a single feedback pin. It can
be configured as a boost, SEPIC or inverting converter.
n
Wide V Range: 1.6V (2.5V Start-Up) to 40V
Positive or Negative Output Voltage Programming
IN
n
with a Single Feedback Pin
n
n
n
n
PGOOD Output Voltage Status Report
Internal 6A/40V Power Switch
It features an internal low side N-channel MOSFET rated
for 6A at 40V and driven from an internal regulated sup-
Programmable Soft-Start
Programmable Operating Frequency (100kHz to 1MHz)
with One External Resistor
ply provided from V or DRIVE. The fixed frequency,
IN
current-mode architecture results in stable operation over
a wide range of supply and output voltages. The operating
frequency of LT3959 can be set over a 100kHz to 1MHz
range with an external resistor, or can be synchronized to
an external clock using the SYNC pin.
n
n
n
n
Synchronizable to an External Clock
Low Shutdown Current < 1μA
INTV Regulator Supplied from V or DRIVE
Programmable Input Undervoltage Lockout with
CC
IN
Hysteresis
n
The LT3959 features soft-start and frequency foldback
functions to limit inductor current during start-up and
output short-circuit. A window comparator on the FBX
pin reports via the PGOOD pin, providing output voltage
status indication.
Thermally Enhanced QFN (5mm × 6mm) Package
APPLICATIONS
n
Automotive
n
Telecom
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks and
ThinSOT are trademarks of Linear Technology Corporation. All other trademarks are the
property of their respective owners. Protected by U.S. Patents, including 7825665.
n
Industrial
TYPICAL APPLICATION
2.5V to 24V Input, 12V Output SEPIC Converter
Excellent for Automotive 12V Post Regulator
Efficiency vs Output Current
100
V
IN
= 12V
4.7μF
50V
95
90
85
80
75
70
65
60
V
L1A
OUT
12V
500mA AT V = 2.5V
V
IN
2.5V TO
24V
IN
1.5A AT V > 8V
C
IN
IN
C
22μF
50V
×2
OUT
V
SW
124k
121k
IN
47μF
16V
×2
L1B
EN_UVLO
150k
LT3959
GND
PGOOD
DRIVE
TIE TO SGND
IF NOT USED
SYNC
RT
105K
0
200
400
600
800
1000
FBX
OUTPUT CURRENT (mA)
SS
V
C
SGND GNDK INTV
CC
3959 TA01b
27.4k
300kHz
0.1μF 7.5k
22nF
15.8K
4.7μF
3959 TA01a
3959f
1
LT3959
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Note 1)
TOP VIEW
V ............................................................................40V
IN
EN/UVLO (Note 2).....................................................40V
DRIVE .......................................................................40V
PGOOD......................................................................40V
SW............................................................................40V
36 35 34 33 32 31 30
NC
NC
1
2
3
4
28 DRIVE
27
V
IN
INTV ........................................................................8V
CC
SGND
37
NC
SYNC ..........................................................................8V
SGND
EN/UVLO
25
V , SS.........................................................................3V
24 SGND
NC
23
C
NC
6
RT............................................................................1.5V
GND, GNDK to SGND ............................................. 0.3V
FBX ................................................................. –3V to 3V
Operating Junction Temperature Range (Note 3)
SW
38
SW
SW
8
9
21 SW
20 SW
NC 10
LT3959E/LT3959I .............................. –40°C to 125°C
Storage Temperature Range .................. –65°C to 125°C
12 13 14 15 16 17
UHEMA PACKAGE
36-LEAD (5mm × 6mm) PLASTIC QFN
=125°C, θ = 42°C/W, θ = 3°C/W
T
JMAX
JA
JC
EXPOSED PAD (PIN 37) IS SGND, MUST BE SOLDERED TO SGND PLANE
EXPOSED PAD (PIN 38) IS SW, MUST BE SOLDERED TO SW PLANE
ORDER INFORMATION
LEAD FREE FINISH
LT3959EUHE#PBF
LT3959IUHE#PBF
TAPE AND REEL
PART MARKING*
3959
PACKAGE DESCRIPTION
TEMPERATURE RANGE
–40°C to 125°C
LT3959EUHE#TRPBF
LT3959IUHE#TRPBF
36-Lead (5mm × 6mm) Plastic QFN
36-Lead (5mm × 6mm) Plastic QFN
3959
–40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping
container. Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
3959f
2
LT3959
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
40
UNITS
l
l
V
V
V
Operating Voltage
Start-Up Voltage
1.6
V
V
IN
IN
IN
R = 27.4kΩ, FBX = 0
T
2.5
0.1
2.65
Shutdown I
EN/UVLO < 0.4V
EN/UVLO = 1.15V
1
6
μA
μA
Q
V
Operating I
350
450
μA
IN
Q
DRIVE Shutdown Quiescent Current
EN/UVLO < 0.4V
EN/UVLO = 1.15V
0.1
0.1
1
2
μA
μA
DRIVE Quiescent Current (Not Switching)
SW Pin Current Limit
R = 27.4kΩ, DRIVE = 6V
T
2.0
7.0
2.5
8.0
mA
A
l
6.0
SW Pin On Voltage
I
= 3A
100
mV
μA
SW
SW Pin Leakage Current
Error Amplifier
SW = 40V
5
l
l
FBX Regulation Voltage (V
)
)
FBX > 0V
FBX < 0V
1.580
1.6
1.620
V
V
FBX(REG)
–0.815
–0.80
–0.785
FBX Pin Input Current
FBX = 1.6V
FBX = –0.8V
80
130
10
nA
nA
–10
FBX = V
240
5
μs
Transconductance g (ΔI /ΔV
FBX(REG)
m
VC
FBX
V Output Impedance
C
MΩ
1.6V < V < 40V, FBX >0
0.02
0.02
0.05
0.05
%/V
%/V
FBX Line Regulation [ΔV
/(ΔV • V
)]
FBX(REG)
IN
FBX(REG)
IN
1.6V < V < 40V, FBX <0
IN
V Source Current
C
FBX = 0V, V = 1.3V
–13
μA
C
V Sink Current
C
FBX = 1.7V, V = 1.3V
13
10
μA
μA
C
FBX = –0.85V, V = 1.3V
C
Oscillator
l
Switching Frequency
R = 27.4k to SGND, V
= 1.6V
= 1.6V
= 1.6V
250
300
100
1000
340
kHz
kHz
kHz
T
FBX
FBX
FBX
R = 86.6k to SGND, V
T
R = 6.81k to SGND, V
T
R Voltage
FBX = 1.6V, –0.8V
1.13
150
150
V
ns
ns
T
SW Minimum Off-Time
SW Minimum On-Time
200
200
3959f
3
LT3959
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V, EN/UVLO = 12V, INTVCC = 4.75V, unless otherwise noted.
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
l
l
l
SYNC Input Low
SYNC Input High
SS Pull-Up Current
0.4
V
V
1.5
SS = 0V, Current Out of Pin
–14
–10.5
–7
μA
Low Dropout Regulators (DRIVE LDO and V LDO)
IN
l
l
DRIVE LDO Regulation Voltage
DRIVE = 6V, Not Switching
DRIVE = 0V, Not Switching
4.6
3.6
4.75
3.75
60
4.9
3.9
V
V
V
LDO Regulation Voltage
IN
DRIVE LDO Current Limit
LDO Current Limit
INTV = 4V
mA
mA
%
CC
V
DRIVE = 0V, INTV = 3V
60
IN
CC
0 < I
< 20mA, DRIVE = 6V
–1
–1
–0.6
–0.6
0.03
0.03
190
190
DRIVE LDO Load Regulation (ΔV
/V
)
INTVCC
INTVCC INTVCC
DRIVE = 0V, 0 < I
< 20mA
%
V
LDO Load Regulation (ΔV
/V
INTVCC INTVCC
)
INTVCC
IN
1.6V < V < 40V, DRIVE = 6V
0.07
0.07
400
400
%/V
%/V
mV
mV
DRIVE LDO Line Regulation [ΔV
/(V
• ΔV )]
IN
INTVCC
INTVCC
IN
DRIVE = 0V, 5V < V < 40V
V
LDO Line Regulation [ΔV
/(V
• ΔV )]
INTVCC IN
IN
IN
INTVCC
l
l
DRIVE LDO Dropout Voltage (V
– V
)
DRIVE = 4V, I
= 20mA
DRIVE
INTVCC
INTVCC
V
LDO Dropout Voltage (V – V
)
V
= 3V, DRIVE = 0V,
IN
IN
INTVCC
IN
I
= 20mA
INTVCC
l
l
INTV Undervoltage Lockout Threshold Falling
1.85
2.15
2.0
2.3
25
2.15
2.45
V
V
CC
INTV Undervoltage Lockout Threshold Rising
CC
INTV Current in Shutdown
EN/UVLO = 0V
μA
CC
Logic
l
EN/UVLO Threshold Voltage Falling
EN/UVLO Threshold Voltage Rising Hysteresis
EN/UVLO Input Low Voltage
EN/UVLO Pin Bias Current Low
EN/UVLO Pin Bias Current High
FBX Power Good Threshold Voltage
1.17
1.8
1.22
20
1.27
V
mV
V
I
< 1ꢀA
0.4
2.6
100
VIN
EN/UVLO = 1.15V
EN/UVLO = 1.30V
2.2
10
μA
nA
FBX > 0V, PGOOD Falling
FBX < 0V, PGOOD Falling
V
V
– 0.08
+ 0.04
V
V
FBX(REG)
FBX(REG)
FBX Overvoltage Threshold
FBX > 0V, PGOOD Rising
FBX < 0V, PGOOD Rising
V
+ 0.12
– 0.06
V
V
FBX(REG)
FBX(REG)
V
PGOOD Output Low (V
)
I
= 250μA
PGOOD
210
300
1
mV
μA
V
OL
PGOOD Leakage Current
INTV Minimum Voltage to Enable PGOOD Function
PGOOD = 40V
l
l
2.5
2.5
2.7
2.7
2.9
2.9
CC
INTV Minimum Voltage to Enable SYNC Function
V
CC
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 3: The LT3959E is guaranteed to meet performance specifications
from the 0°C to 125°C operating junction temperature. Specifications over
the –40°C to 125°C operating junction temperature range are assured by
design, characterization and correlation with statistical process controls.
The LT3959I is guaranteed over the full –40°C to 125°C operating junction
temperature range.
Note 2: For V below 4V, the EN/UVLO pin must not exceed V for proper
IN
IN
operation.
Note 4: The LT3959 is tested in a feedback loop which servos V to the
FBX
reference voltages (1.6V and –0.8V) with the V pin forced to 1.3V.
C
3959f
4
LT3959
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
FBX Positive Regulation Voltage
vs Temperature
FBX Negative Regulation Voltage
vs Temperature
Quiescent Current
vs Temperature
–0.78
–0.79
–0.80
–0.81
–0.82
2.4
2.0
1.6
1.2
0.8
0.4
0.0
1.62
1.61
1.60
1.59
1.58
I
(DRIVE)
Q
V
= 12V
IN
DRIVE = 6V
I
Q
(V )
IN
25
50
75 100
25
50
75 100
25
50
75 100
–50 –25
0
125
–50 –25
0
125
–50 –25
0
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3959 G02
3959 G03
3959 G01
Dynamic Quiescent Current
vs Switching Frequency
Normalized Switching Frequency
vs FBX Voltage
RT vs Switching Frequency
25
20
15
10
5
100
90
80
70
60
50
40
30
20
10
0
120
100
80
60
40
20
0
DRIVE = 6V
I
Q
(DRIVE)
I
(V )
IN
Q
0
800
SWITCHING FREQUENCY (kHz)
100 200 300 400 500 600 700 800 900 1000
SWITCHING FREQUENCY (kHz)
3959 G05
–0.4
0
0.4
0.8
FBX VOLTAGE (V)
1.6
0
200
400
600
1000
0
1.2
–0.8
3959 G04
3959 G06
Switching Frequency
vs Temperature
SW Current Limit vs Temperature
SW Current Limit vs Duty Cycle
350
325
300
275
250
7.6
7.4
7.2
7.0
6.8
6.6
6.4
8.0
7.5
7.0
6.5
6.0
5.5
5.0
–50 –25
0
25
TEMPERATURE (°C)
50
75 100 125
20
40
DUTY CYCLE (%)
60
80
100
25
50
75 100
–50 –25
0
125
0
TEMPERATURE (°C)
3959 G07
3959 G08
3959 G09
3959f
5
LT3959
TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted.
EN/UVLO Threshold
vs Temperature
SW Minimum On- and Off-Times
vs Temperature
EN/UVLO Hysteresis Current
vs Temperature
1.27
1.25
1.23
1.21
1.19
1.17
200
190
2.4
2.2
2.0
1.8
1.6
180
170
160
150
140
130
MINIMUM
OFF TIME
EN/UVLO RISING
EN/UVLO FALLING
MINIMUM
ON TIME
25
50
75 100
–50 –25
0
125
25
50
75 100
–50 –25
0
125
25
50
75 100
–50 –25
0
125
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
3959 G10
3959 G11
3959 G12
INTVCC vs Temperature
INTVCC Load Regulation
INTVCC Line Regulation
5
4.5
4
5.0
4.8
4.6
4.4
4.2
4.0
5.0
4.5
4.0
3.5
3.0
DRIVE = 6V
DRIVE LDO
DRIVE LDO
DRIVE LDO
DRIVE = 0V
V
LDO (DRIVE = 0V)
IN
V
LDO
IN
3.5
3
V
LDO
IN
3.8
3.6
5
10
15
20
25
15
35 40 45
25
50
75 100
0
5
10
20 25 30
(V)
–50 –25
0
125
0
INTV LOAD (mA)
TEMPERATURE (°C)
V
CC
IN
3959 G14
3959 G13
3959 G15
INTVCC Dropout Voltage
vs Current, Temperature
Internal Switch On-Resistance
vs Temperature
Internal Switch On-Resistance
vs INTVCC
60
50
40
30
20
400
300
200
100
0
50
45
40
35
30
V
= 12V
IN
DRIVE = 4V
125°C
25°C
–40°C
–25
0
25
50
75 100 125
–50
5
10
15
20
25
2.5
3
3.5
INTC (V)
4
4.5
5
0
2
TEMPERATURE (°C)
INTV LOAD (mA)
CC
CC
3959 G17
3959 G16
3959 G18
3959f
6
LT3959
PIN FUNCTIONS
DRIVE (Pin 28): DRIVE LDO Supply Pin. This pin can be
PGOOD (Pin 35): Output Ready Status Pin. An open-
connectedtoeitherV oraquasi-regulatedvoltagesupply
collector pull down on PGOOD asserts when INTV is
IN
CC
such as a DC converter output. This pin must be bypassed
greater than 2.7V and the FBX voltage is within 5% (80mV
to GND with a minimum of 1μF capacitor placed close to
if V = 1.6V or 40mV if V = –0.8V) of the regulation
FBX
FBX
the pin. Tie this pin to V if not used.
voltage.
IN
EN/UVLO (Pin 25): Shutdown and Undervoltage Detect
Pin. An accurate 1.22V (nominal) falling threshold with
externally programmable hysteresis detects when power
isokaytoenableswitching. Risinghysteresisisgenerated
by the external resistor divider and an accurate internal
2.2ꢀApull-downcurrent.Anundervoltageconditionresets
soft-start. Tie to 0.4V, or less, to disable the device and
RT (Pin 33): Switching Frequency Adjustment Pin. Set
the frequency using a resistor to SGND. Do not leave the
RT pin open.
SGND (Exposed Pad Pin 37, Pins 4, 24): Signal Ground.
Must be soldered directly to the signal ground plane.
Connect to ground terminal of: external resistor dividers
for FBX and EN/UVLO; capacitors for INTV , SS, and V ;
CC
C
reduce V quiescent current below 1ꢀA.
IN
and resistor R .
T
FBX(Pin31):VoltageRegulationFeedbackPinforPositive
or Negative Outputs. Connect this pin to a resistor divider
betweentheoutputandSGND.FBXistheinputoftwoerror
amplifiers—one configured to regulate a positive output;
the other, a negative output. Depending upon topology
selected, switching causes the output to ramp positive or
negative. The appropriate amplifier takes control while the
other becomes inactive. Additionally FBX is input for two
window comparators that indicate through the PGOOD
pin when the output is within 5% of the regulation volt-
ages. FBX also modulates the switching frequency during
start-up and fault conditions when FBX is close to SGND.
SS(Pin32):Soft-StartPin.Thispinmodulatescompensa-
tion pin voltage (V ) clamp. The soft-start interval is set
C
with an external capacitor. The pin has a 10μA (typical)
pull-up current source to an internal 2.5V rail. The soft-
start pin is reset to SGND by an EN/UVLO undervoltage
condition,anINTV undervoltageconditionoraninternal
CC
thermal lockout.
SW (Exposed Pad Pin 38, Pins 8, 9, 20, 21): Drain of
Internal Power N-Channel MOSFET.
SYNC (Pin 34): Frequency Synchronization Pin. Used to
synchronize the internal oscillator to an outside clock. If
this feature is used, an R resistor should be chosen to
GND (Pins 13-17):SourceTerminalofSwitchandtheGND
Input to the Switch Current Comparator.
T
program a switching frequency 20% slower than SYNC
pulse frequency. Tie the SYNC pin to SGND if this feature
is not used. This signal is ignored during FB frequency
GNDK (Pin 12): Kelvin Connection Pin between GND and
SGND. Kelvin connect this pin to the SGND plane close
to the IC. See the Board Layout section.
foldback or when INTV is less than 2.7V.
CC
V
(Pin 27): Supply Pin for Internal Leads and the V
IN
IN
INTV (Pin 36): Regulated Supply for Internal Loads and
CC
LDORegulatorofINTV .MustbelocallybypassedtoGND
CC
Gate Driver. Regulated to 4.75V if powered from DRIVE
with a minimum of 1μF capacitor placed close to this pin.
or regulated to 3.75V if powered from V . The INTV
IN
CC
V (Pin 30): Error Amplifier Compensation Pin. Used to
pin must be bypassed to SGND with a minimum of 4.7μF
C
stabilizethevoltageloopwithanexternalRCnetwork.Place
capacitor placed close to the pin.
compensationcomponentsbetweentheV pinandSGND.
C
NC (Pins 1-3, 6, 10, 23): No Internal Connection. Leave
these pins open or connect them to the adjacent pins.
3959f
7
LT3959
BLOCK DIAGRAM
L1
C
DC
D1
V
OUT
V
IN
SGND
R4
R3
C
IN
R2
R1
L2
C
OUT
t
FBX
SGND
25
27
28
DRIVE
EN/UVLO
V
IN
A10
+
I
S1
2.5V
2.2μA
1.22V
–
2.5V
BANDGAP
REFERENCE
I
S3
CURRENT
LIMIT
CURRENT
LIMIT
I
INTERNAL BIAS
GENERATOR
S2
BG
V
C
10μA
BG_LOW
UVLO
30
V
LDO
DRIVE LDO
IN
Q3
INTERNAL BIAS
C
INTV
C
VCC
CC
C2
G4
36
R
C
OTP
A8
+
–
C
1.2V
C1
A11
1.72V
–
+
TSD
~165˚C
SGND
8, 9, 20, 21
SGND
G6
SR1
S
SW
M1
A12
V
–
C
DRIVER
–
+
G2
A7
R
Q
G5
+
–0.86V
Q2
1.6V
+
–
PWM
COMPARATOR
A1
45mV
–
+
A6
A5
FBX
31
FBX
+
–
V
IN
A2
+
–
SLOPE
RAMP
V
ISENSE
–0.8V
R
PG
PGOOD
R
SENSE
GND
35
Q4
G8
A15
+
2.7V
13, 14
15, 16
17
–
RAMP
A13
A14
1.52V
–
+
GENERATOR
–
+
G7
1.25V
100kHz ~ 1MHz
OSCILLATOR
A3
G1
–
+
–0.76V
FREQ
FOLDBACK
1.25V
+
+
FREQUENCY
FOLDBACK
A4
Q1
–
FREQ
PROG
SS
SYNC
RT
SGND
4, 24
GNDK
32
34
33
12
3759 F01
C
SS
R
T
Figure 1. LT3959 Block Diagram Working as a SEPIC Converter
3959f
8
LT3959
APPLICATIONS INFORMATION
Main Control Loop
TheLT3959hasovervoltageprotectionfunctionstoprotect
the converter from excessive output voltage overshoot
during start-up or recovery from a short-circuit condition.
An overvoltage comparator A11 (with 40mV hysteresis)
senses when the FBX pin voltage exceeds the positive
regulated voltage (1.6V) by 7.5% and turns off M1.
Similarly, an overvoltage comparator A12 (with 20mV
hysteresis) senses when the FBX pin voltage exceeds the
negative regulated voltage (–0.8V) by 7.5% and turns
off M1. Both reset pulses are sent to the main RS latch
(SR1) through G6 and G5. The internal power MOSFET
switch M1 is actively held off for the duration of an output
overvoltage condition.
The LT3959 uses a fixed frequency, current mode control
scheme to provide excellent line and load regulation.
OperationcanbebestunderstoodbyreferringtotheBlock
Diagram in Figure 1.
The start of each oscillator cycle sets the SR latch (SR1)
andturnsontheinternalpowerMOSFETswitchM1through
driver G2. The switch current flows through the internal
current sensing resistor R
and generates a voltage
SENSE
proportional to the switch current. This current sense
voltage V (amplified by A5) is added to a stabilizing
ISENSE
slope compensation ramp and the resulting sum (SLOPE)
isfedintothepositiveterminalofthePWMcomparatorA7.
When SLOPE exceeds the level at the negative input of A7
Programming Turn-On and Turn-Off Thresholds with
EN/UVLO Pin
(V pin), SR1 is reset, turning off the power switch. The
C
level at the negative input of A7 is set by the error amplifier
A1 (or A2) and is an amplified version of the difference
between the feedback voltage (FBX pin) and the reference
voltage (1.6V or –0.8V, depending on the configuration).
In this manner, the error amplifier sets the correct peak
switch current level to keep the output in regulation.
The EN/UVLO pin controls whether the LT3959 is enabled
or is in shutdown state. A micropower 1.22V reference, a
comparator A10 and controllable current source I allow
S1
theusertoaccuratelyprogramthesupplyvoltageatwhich
the IC turns on and off. The falling value can be accurately
set by the resistor dividers R3 and R4. When EN/UVLO
is above 0.7V, and below the 1.22V threshold, the small
The LT3959 has a switch current limit function. The cur-
rent sense voltage is input to the current limit comparator
A6. If the SENSE voltage is higher than the sense current
pull-down current source I (typical 2.2μA) is active.
S1
The purpose of this current is to allow the user to program
therisinghysteresis.TheBlockDiagramofthecomparator
and the external resistors is shown in Figure 1. The typical
falling threshold voltage and rising threshold voltage can
be calculated by the following equations:
limit threshold V
(45mV, typical), A6 will reset
SENSE(MAX)
SR1 and turn off M1 immediately.
The LT3959 is capable of generating either positive or
negative output voltage with a single FBX pin. It can be
configured as a boost or SEPIC converter to generate
positive output voltage, or as an inverting converter to
generate negative output voltage. When configured as a
SEPICconverter,asshowninFigure1,theFBXpinispulled
up to the internal bias voltage of 1.6V by a voltage divider
(R3+R4)
VVIN(FALLING) = 1.22 •
R4
VVIN(RISING) =2.2μA •R3+ V
IN(FALLING)
(R1 and R2) connected from V
to SGND. Comparator
For applications where the EN/UVLO pin is only used as
a logic input, the EN/UVLO pin can be connected directly
OUT
A2 becomes inactive and comparator A1 performs the
invertingamplificationfromFBXtoV .WhentheLT3959is
C
to the input voltage V for always-on operation.
IN
in an inverting configuration, the FBX pin is pulled down to
–0.8V by a voltage divider connected from V
to SGND.
OUT
Comparator A1 becomes inactive and comparator A2
performs the noninverting amplification from FBX to V .
C
3959f
9
LT3959
APPLICATIONS INFORMATION
INTV Low Dropout Voltage Regulators
Operating Frequency and Synchronization
CC
The LT3959 features two internal low dropout (LDO) volt-
The choice of operating frequency may be determined
by on-chip power dissipation, otherwise it is a trade-off
betweenefficiencyandcomponentsize.Lowfrequencyop-
eration improves efficiency by reducing gate drive current
andinternalMOSFETanddiodeswitchinglosses.However,
lower frequency operation requires a physically larger
inductor. Switching frequency also has implications for
loopcompensation.TheLT3959usesaconstant-frequency
architecture that can be programmed over a 100kHz to
1MHz range with a single external resistor from the RT
pin to SGND, as shown in Figure 1. The RT pin must have
an external resistor to SGND for proper operation of the
age regulators (V LDO and DRIVE LDO) powered from
IN
differentsupplies(V andDRIVErespectively).BothLDO’s
IN
regulate the internal INTV supply which powers the gate
CC
driver and the internal loads, as shown in Figure 1. Both
regulatorsaredesignedsothatcurrentdoesnotflowfrom
INTV to the LDO input under a reverse bias condition.
CC
DRIVE LDO regulates the INTV to 4.75V, while V LDO
CC
IN
regulates the INTV to 3.75V. V LDO is turned off when
CC
IN
the INTV voltage is greater than 3.75V (typical). Both
CC
LDO’s can be turned off if the INTV pin is driven by a
CC
supply of 4.75V or higher but less than 8V (the INTV
CC
maximum voltage rating is 8V). A table of the LDO sup-
LT3959. A table for selecting the value of R for a given
T
ply and output voltage combination is shown in Table 1.
operating frequency is shown in Table 2.
Table 1. LDO’s Supply and Output Voltage Combination (Assuming
That the LDO Dropout Voltage is 0.15V)
Table 2. Timing Resistor (RT) Value
OSCILLATOR FREQUENCY (kHz)
R (kΩ)
T
SUPPLY VOLTAGES
DRIVE
LDO OUTPUT
INTV
LDO STATUS
(Note 7)
100
200
300
400
500
600
700
800
900
1000
86.6
41.2
27.4
21.0
16.5
13.7
11.5
9.76
8.45
6.81
V
IN
CC
V
≤ 3.9V
V
DRIVE
V
DRIVE
< V
= V
V
IN
V
IN
– 0.15V
– 0.15V
#1 Is ON
#1 #2 are ON
#2 Is ON
IN
IN
IN
V
< V
< 4.9V
V – 0.15V
DRIVE
IN
DRIVE
4.9V ≤ V
≤ 40V
4.75V
#2 Is ON
DRIVE
3.9V < V ≤ 40V
V
V
< 3.9V
3.75V
3.75V
#1 Is ON
IN
DRIVE
DRIVE
= 3.9V
< 4.9V
#1 #2 are ON
#2 Is ON
3.9V < V
V
– 0.15V
DRIVE
DRIVE
4.9V ≤ V
≤ 40V
4.75V
#2 Is ON
DRIVE
Note 7: #1 is V LDO and #2 is DRIVE LDO
IN
The switching frequency of the LT3959 can be synchro-
nized to the positive edge of an external clock source.
By providing a digital clock signal into the SYNC pin,
the LT3959 will operate at the SYNC clock frequency. If
The DRIVE pin provides flexibility to power the gate driver
and the internal loads from a supply that is available only
when the switcher is enabled and running. If not used,
this feature is used, an R resistor should be chosen to
T
the DRIVE pin should be tied to V .
IN
program a switching frequency 20% slower than SYNC
pulse frequency. The SYNC pulse should have a minimum
pulse width of 200ns. Tie the SYNC pin to SGND if this
feature is not used.
The INTV pin must be bypassed to SGND immediately
CC
adjacenttotheINTV pinwithaminimumof4.7μFceramic
CC
capacitor. Good bypassing is necessary to supply the high
transient currents required by the MOSFET gate driver.
3959f
10
LT3959
APPLICATIONS INFORMATION
Duty Cycle Consideration
High peak switch currents during start-up may occur in
switching regulators. Since V
is far from its final value,
OUT
Switching duty cycle is a key variable defining converter
operation.Assuch,itslimitsmustbeconsidered.Minimum
on-time is the smallest time duration that the LT3959 is
capableofturningontheinternalpowerMOSFET.Thistime
is generally about 150ns (typical) (see Minimum On-Time
in the Electrical Characteristics table). In each switching
cycle, the LT3959 keeps the power switch off for at least
150ns (typical) (see Minimum Off-Time in the Electrical
Characteristics table).
the feedback loop is saturated and the regulator tries to
chargetheoutputcapacitorasquicklyaspossible,resulting
in large peak currents. A large surge current may cause
inductor saturation or power switch failure.
LT3959 addresses this mechanism with the SS pin. As
shown in Figure 1, the SS pin reduces the internal power
MOSFET current by pulling down the V pin through Q2.
C
In this way the SS allows the output capacitor to charge
gradually toward its final value while limiting the start-up
peak currents.
The minimum on-time and minimum off-time and the
switching frequency define the minimum and maximum
switching duty cycles a converter is able to generate:
Besides start-up, soft-start can also be triggered by
INTV undervoltagelockoutand/orthermallockout,which
CC
Minimum duty cycle = minimum on-time • frequency
Maximum duty cycle = 1 – (minimum off-time • frequency)
Programming the Output Voltage
causes the LT3959 to stop switching immediately. The SS
pin will be discharged by Q3. When all faults are cleared
and the SS pin has been discharged below 0.2V, a 10μA
current source I starts charging the SS pin, initiating a
S2
The output voltage (V ) is set by a resistor divider, as
OUT
soft-start operation.
shown in Figure 1. The positive V
are set by the following equations:
and negative V
OUT
OUT
The soft-start interval is set by the soft-start capacitor
selection according to the equation:
⎛
⎞
⎟
⎠
R2
R1
VOUT(POSITIVE) = 1.6V • 1+
⎜
1.25V
⎝
⎛
TSS = CSS
•
10μA
FBX Frequency Foldback
When V is very low during start-up or a short-circuit
⎞
⎟
⎠
R2
R1
VOUT(NEGATIVE) = –0.8V • 1+
⎜
⎝
OUT
The resistors R1 and R2 are typically chosen so that the
error caused by the current flowing into the FBX pin dur-
ing normal operation is less than 1% (this translates to a
maximum value of R1 at about 121k).
fault on the output, the switching regulator must operate
at low duty cycles to maintain the power switch current
within the current limit range, since the inductor current
decayrateisverylowduringswitchofftime.Theminimum
on-timelimitationmaypreventtheswitcherfromattaining
a sufficiently low duty cycle at the programmed switch-
ing frequency. So, the switch current will keep increasing
through each switch cycle, exceeding the programmed
current limit. To prevent the switch peak currents from
exceeding the programmed value, the LT3959 contains
a frequency foldback function to reduce the switching
frequency when the FBX voltage is low (see the Normal-
ized Switching Frequency vs FBX graph in the Typical
Performance Characteristics section).
Soft-Start
The LT3959 contains several features to limit peak switch
currents and output voltage (V ) overshoot during
OUT
start-up or recovery from a fault condition. The primary
purpose of these features is to prevent damage to external
components or the load.
3959f
11
LT3959
APPLICATIONS INFORMATION
Some frequency foldback waveforms are shown in the
I
SW
)I
TypicalApplicationssection.Thefrequencyfoldbackfunc-
SW
tion prevents I from exceeding the programmed limits
L
I
SW(PEAK)
because of the minimum on-time.
Duringfrequencyfoldback,externalclocksynchronization
is disabled to allow the frequency reducing operation to
function properly.
t
DT
S
T
S
3959 F02
Loop Compensation
Figure 2. The SW Current During a Switching Cycle
Loop compensation determines the stability and transient
performance. The LT3959 uses current mode control to
regulate the output which simplifies loop compensation.
Theoptimumvaluesdependontheconvertertopology,the
componentvaluesandtheoperatingconditions(including
the input voltage, load current, etc.). To compensate the
feedback loop of the LT3959, a series resistor-capacitor
Duetothecurrentlimit(minimum6A)oftheinternalpower
switch, the LT3959 should be used in the applications
that the switch peak current I
during steady state
SW(PEAK)
normal operation is lower than 6A by a sufficient margin
(10% or higher is recommended).
ItisrecommendedtomeasuretheICtemperatureinsteady
statetoverifythatthejunctiontemperaturelimit(125°C)is
not exceeded. A low switching frequency may be required
network is usually connected from the V pin to SGND.
C
Figure 1 shows the typical V compensation network. For
C
most applications, the capacitor should be in the range of
470pF to 22nF, and the resistor should be in the range of
5k to 50k. A small capacitor is often connected in paral-
lel with the RC compensation network to attenuate the
to ensure T
does not exceed 125°C.
J(MAX)
If LT3959 die temperature reaches thermal lockout
threshold at 165°C (typical), the IC will initiate several
protective actions. The power switch will be turned off.
A soft-start operation will be triggered. The IC will be en-
abled again when the junction temperature has dropped
by 5°C (nominal).
V voltage ripple induced from the output voltage ripple
C
through the internal error amplifier. The parallel capacitor
usually ranges in value from 10pF to 100pF. A practical
approach to design the compensation network is to start
with one of the circuits in this data sheet that is similar
to your application, and tune the compensation network
to optimize the performance. Stability should then be
checked across all operating conditions, including load
current, input voltage and temperature.
APPLICATION CIRCUITS
The LT3959 can be configured as different topologies.
The design procedure for component selection differs
somewhat between these topologies. The first topology
to be analyzed will be the boost converter, followed by
SEPIC and inverting converters.
The Internal Power Switch Current
For control and protection, the LT3959 measures the
internal power MOSFET current by using a sense resistor
(R
) between GND and the MOSFET source. Figure 2
SENSE
shows a typical wave-form of the internal switch current
(I ).
SW
3959f
12
LT3959
APPLICATIONS INFORMATION
Boost Converter: Switch Duty Cycle and Frequency
Due to the current limit of its internal power switch, the
LT3959 should be used in a boost converter whose maxi-
The LT3959 can be configured as a boost converter for
the applications where the converter output voltage is
higher than the input voltage. Remember that boost con-
verters are not short-circuit protected. Under a shorted
output condition, the inductor current is limited only by
the input supply capability. For applications requiring a
step-up converter that is short-circuit protected, please
refer to the Applications Information section covering
SEPIC converters.
mum output current (I
) is less than the maximum
O(MAX)
output current capability by a sufficient margin (10% or
higher is recommended):
V
VOUT
IN(MIN)
IO(MAX)
<
•(6A – 0.5 • ΔISW )
The inductor ripple current ΔI has a direct effect on the
SW
choice of the inductor value and the converter’s maximum
output current capability. Choosing smaller values of
The conversion ratio as a function of duty cycle is:
ΔI
increases output current capability, but requires
SW
large inductances and reduces the current loop gain (the
VOUT
V
IN
1
1−D
=
converter will approach voltage mode). Accepting larger
values of ΔI
provides fast transient response and
SW
allows the use of low inductances, but results in higher
input current ripple and greater core losses, and reduces
output current capability.
in continuous conduction mode (CCM).
For a boost converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
theinductorvalueoftheboostconvertercanbedetermined
using the following equation:
voltage (V ) and the input voltage (V ). The maximum
OUT
duty cycle (D
minimum input voltage:
IN
) occurs when the converter has the
MAX
VOUT − V
IN(MIN)
V
DMAX
=
IN(MIN)
L =
•DMAX
VOUT
ΔISW • fOSC
The alternative to CCM, discontinuous conduction mode
(DCM) is not limited by duty cycle to provide high con-
version ratios at a given frequency. The price one pays
is reduced efficiency and substantially higher switching
current.
The peak inductor current is the switch current limit (7A
typical), and the RMS inductor current is approximately
equal to I
. The user should choose the inductors
L(MAX)
having sufficient saturation and RMS current ratings.
Boost Converter: Output Diode Selection
Boost Converter: Maximum Output Current Capability
and Inductor Selection
To maximize efficiency, a fast switching diode with low
forward drop and low reverse leakage is desirable. The
peak reverse voltage that the diode must withstand is
equal to the regulator output voltage plus any additional
ringing across its anode-to-cathode during the on-time.
The average forward current in normal operation is equal
to the output current.
For the boost topology, the maximum average inductor
current is:
1
IL(MAX) = IO(MAX)
•
1−DMAX
3959f
13
LT3959
APPLICATIONS INFORMATION
It is recommended that the peak repetitive reverse voltage
and the following equations can easily be modified. For a
1% contribution to the total ripple voltage, the ESR of the
output capacitor can be determined using the following
equation:
rating V
is higher than V
by a safety margin (a 10V
RRM
OUT
safety margin is usually sufficient).
The power dissipated by the diode is:
0.01• VOUT
ESRCOUT
≤
P =IO(MAX) • VD
D
ID(PEAK)
Where V is diode’s forward voltage drop, and the diode
D
For the bulk C component, which also contributes 1% to
the total ripple:
junction temperature is:
TJ T +P R
=
•
A
D
θJA
IO(MAX)
COUT
≥
The R to be used in this equation normally includes the
θJA
0.01• VOUT • ƒOSC
R
for the device plus the thermal resistance from the
θJC
boardtotheambienttemperatureintheenclosure.T must
J
Theoutputcapacitorinaboostregulatorexperienceshigh
RMSripplecurrents, asshowninFigure3. TheRMSripple
current rating of the output capacitor can be determined
using the following equation:
notexceedthediodemaximumjunctiontemperaturerating.
Boost Converter: Output Capacitor Selection
Contributions of ESR (equivalent series resistance), ESL
(equivalent series inductance) and the bulk capacitance
must be considered when choosing the correct output
capacitors for a given output ripple voltage. The effect of
thesethreeparameters(ESR,ESLandbulkC)ontheoutput
voltage ripple waveform for a typical boost converter is
illustrated in Figure 3.
DMAX
1−DMAX
IRMS(COUT) ≥IO(MAX)
•
Multiple capacitors are often paralleled to meet ESR
requirements. Typically, once the ESR requirement is
satisfied, the capacitance is adequate for filtering and has
therequiredRMScurrentrating.Additionalceramiccapaci-
tors in parallel are commonly used to reduce the effect of
parasiticinductanceintheoutputcapacitor,whichreduces
high frequency switching noise on the converter output.
t
ON
t
OFF
)V
COUT
V
OUT
(AC)
Boost Converter: Input Capacitor Selection
RINGING DUE TO
TOTAL INDUCTANCE
(BOARD + CAP)
The input capacitor of a boost converter is less critical
than the output capacitor, due to the fact that the inductor
is in series with the input, and the input current wave-
form is continuous. The input voltage source impedance
determines the size of the input capacitor, which is typi-
cally in the range of 10μF to 100μF. A low ESR capacitor
is recommended, although it is not as critical as for the
output capacitor.
)V
ESR
3959 F03
Figure 3. The Output Ripple Waveform of a Boost Converter
The choice of component(s) begins with the maximum
acceptable ripple voltage (expressed as a percentage of
the output voltage), and how this ripple should be divided
between the ESR step ΔV
and charging/discharging
ESR
The RMS input capacitor ripple current for a boost
converter is:
ΔV
. For the purpose of simplicity, we will choose
COUT
2% for the maximum output ripple, to be divided equally
between ΔV
and ΔV
. This percentage ripple will
ESR
COUT
I
= 0.3 • ΔI
L
RMS(CIN)
change,dependingontherequirementsoftheapplication,
3959f
14
LT3959
APPLICATIONS INFORMATION
SEPIC CONVERTER APPLICATIONS
Due to the current limit of it’s internal power switch,
the LT3959 should be used in a SEPIC converter whose
maximumoutputcurrent(IO(MAX))islessthantheoutput
current capability by a sufficient margin (10% or higher
is recommended):
The LT3959 can be configured as a SEPIC (single-ended
primary inductance converter), as shown in Figure 1. This
topology allows for the input to be higher, equal, or lower
than the desired output voltage. The conversion ratio as
a function of duty cycle is:
I
< (1–D
) • (6A – 0.5 • ΔI
)
SW
O(MAX)
MAX
The inductor ripple currents ΔI and ΔI are identical:
L1
L2
VOUT + VD
D
1−D
=
V
IN
ΔI = ΔI = 0.5 • ΔI
L1 L2 SW
The inductor ripple current ΔI has a direct effect on the
SW
In continuous conduction mode (CCM).
choice of the inductor value and the converter’s maximum
In a SEPIC converter, no DC path exists between the input
and output. This is an advantage over the boost converter
for applications requiring the output to be disconnected
from the input source when the circuit is in shutdown.
outputcurrentcapability.ChoosingsmallervaluesofΔI
SW
requires large inductances and reduces the current loop
gain(theconverterwillapproachvoltagemode).Accepting
larger values of ΔI allows the use of low inductances,
SW
but results in higher input current ripple and greater core
SEPIC Converter: Switch Duty Cycle and Frequency
losses and reduces output current capability.
For a SEPIC converter operating in CCM, the duty cycle
of the main switch can be calculated based on the output
Givenanoperatinginputvoltagerange,andhavingchosen
the operating frequency and ripple current in the inductor,
theinductorvalue(L1andL2areindependent)oftheSEPIC
convertercanbedeterminedusingthefollowingequation:
voltage (V ), the input voltage (V ) and diode forward
OUT
IN
voltage (V ).
D
Themaximumdutycycle(D )occurswhentheconverter
MAX
V
IN(MIN)
has the minimum input voltage:
L1 = L2 =
•DMAX
0.5 • ΔISW • ƒOSC
VOUT + VD
DMAX
=
For most SEPIC applications, the equal inductor values
will fall in the range of 1μH to 100μH.
VIN(MIN) + VOUT + VD
BymakingL1=L2,andwindingthemonthesamecore,the
value of inductance in the preceding equation is replaced
by 2L, due to mutual inductance:
SEPIC Converter: The Maximum Output Current
Capability and Inductor Selection
As shown in Figure 1, the SEPIC converter contains two
inductors:L1andL2.L1andL2canbeindependent,butcan
also be wound on the same core, since identical voltages
are applied to L1 and L2 throughout the switching cycle.
V
IN(MIN)
L =
•DMAX
ΔISW • ƒOSC
Thismaintainsthesameripplecurrentandenergystorage
in the inductors. The peak inductor currents are:
For the SEPIC topology, the current through L1 is the
converter input current. Based on the fact that, ideally, the
output power is equal to the input power, the maximum
average inductor currents of L1 and L2 are:
I
I
= I
= I
+ 0.5 • ΔI
+ 0.5 • ΔI
L1(PEAK)
L2(PEAK)
L1(MAX)
L2(MAX)
L1
L2
The maximum RMS inductor currents are approximately
equal to the maximum average inductor currents.
DMAX
1–DMAX
IL1(MAX) = IIN(MAX) = IO(MAX)
•
IL2(MAX) = IO(MAX)
3959f
15
LT3959
APPLICATIONS INFORMATION
Basedontheprecedingequations,theusershouldchoose
the inductors having sufficient saturation and RMS cur-
rent ratings.
C
has nearly a rectangular current waveform. During
DC
the switch off-time, the current through C is I , while
DC
IN
approximately –I flows during the on-time. The RMS
O
rating of the coupling capacitor is determined by the fol-
SEPIC Converter: Output Diode Selection
lowing equation:
To maximize efficiency, a fast switching diode with a low
forward drop and low reverse leakage is desirable. The
average forward current in normal operation is equal to
the output current.
VOUT + VD
IRMS(CDC) > IO(MAX)
•
V
IN(MIN)
A low ESR and ESL, X5R or X7R ceramic capacitor works
It is recommended that the peak repetitive reverse voltage
well for C .
DC
rating V
is higher than V
V
by a safety
RRM
OUT + IN(MAX)
margin (a 10V safety margin is usually sufficient).
INVERTING CONVERTER APPLICATIONS
The power dissipated by the diode is:
TheLT3959canbeconfiguredasadual-inductorinverting
topology, as shown in Figure 4. The V
to V ratio is:
OUT
IN
P = I
D
• V
D
O(MAX)
VOUT – V
D
1−D
where V is diode’s forward voltage drop, and the diode
D = –
D
V
IN
junction temperature is:
In continuous conduction mode (CCM).
T = T + P • R
θJA
J
A
D
C
+
DC
L1
L2
The R used in this equation normally includes the R
θJA
θJC
–
V
IN
+
–
for the device, plus the thermal resistance from the board,
C
IN
to the ambient temperature in the enclosure. T must not
SW
J
C
V
OUT
OUT
D1
+
exceed the diode maximum junction temperature rating.
LT3959
SEPIC Converter: Output and Input Capacitor Selection
+
GND
3959 F04
The selections of the output and input capacitors of the
SEPICconverteraresimilartothoseoftheboostconverter.
Please refer to the Boost Converter, Output Capacitor
Selection and Boost Converter, Input Capacitor Selection
sections.
Figure 4. A Simplified Inverting Converter
Inverting Converter: Switch Duty Cycle and Frequency
For an inverting converter operating in CCM, the duty
cycle of the main switch can be calculated based on the
SEPIC Converter: Selecting the DC Coupling Capacitor
The DC voltage rating of the DC coupling capacitor (C ,
DC
negativeoutputvoltage(V )andtheinputvoltage(V ).
OUT
IN
as shown in Figure 1) should be larger than the maximum
Themaximumdutycycle(D )occurswhentheconverter
MAX
input voltage:
has the minimum input voltage:
V
CDC
> V
IN(MAX)
VOUT – VD
DMAX
=
VOUT – VD – V
IN(MIN)
3959f
16
LT3959
APPLICATIONS INFORMATION
Inverting Converter: Output Diode and Input Capacitor
Selections
C
has nearly a rectangular current waveform. During
DC
the switch off-time, the current through C is I , while
DC
IN
approximately –I flows during the on-time. The RMS
O
The selections of the inductor, output diode and input
capacitor of an inverting converter are similar to those of
the SEPIC converter. Please refer to the corresponding
SEPIC converter sections.
rating of the coupling capacitor is determined by the fol-
lowing equation:
DMAX
1–DMAX
IRMS(CDC) >IO(MAX)
•
Inverting Converter: Output Capacitor Selection
The inverting converter requires much smaller output
capacitors than those of the boost and SEPIC converters
for similar output ripple. This is due to the fact that, in the
inverting converter, the inductor L2 is in series with the
output, and the ripple current flowing through the output
capacitors are continuous. The output ripple voltage is
produced by the ripple current of L2 flowing through the
ESR and bulk capacitance of the output capacitor:
A low ESR and ESL, X5R or X7R ceramic capacitor works
well for C .
DC
Board Layout
The high power and high speed operation of the LT3959
demands careful attention to board layout and component
placement. Careful attention must be paid to the internal
power dissipation of the LT3959 at high input voltages,
highswitchingfrequencies,andhighinternalpowerswitch
currents to ensure that a junction temperature of 125°C is
not exceeded. This is especially important when operating
at high ambient temperatures. Exposed pads on the bot-
tom of the package are SGND and SW terminals of the IC,
and must be soldered to a SGND ground plane and a SW
plane respectively. It is recommended that multiple vias
in the printed circuit board be used to conduct heat away
from the IC and into the copper planes with as much as
area as possible.
⎛
⎞
1
ΔVOUT(P−P) = ΔI • ESR
+
⎜
⎟
⎠
L2
COUT
8 • fOSC •COUT
⎝
After specifying the maximum output ripple, the user can
select the output capacitors according to the preceding
equation.
The ESR can be minimized by using high quality X5R or
X7R dielectric ceramic capacitors. In many applications,
ceramic capacitors are sufficient to limit the output volt-
age ripple.
To prevent radiation and high frequency resonance prob-
lems, proper layout of the components connected to the
IC is essential, especially the power paths with higher
di/dt. The following high di/dt loops of different topologies
shouldbekeptastightaspossibletoreduceinductiveringing:
The RMS ripple current rating of the output capacitor
needs to be greater than:
I
> 0.3 • ΔI
L2
RMS(COUT)
• In boost configuration, the high di/dt loop contains the
output capacitor, the internal power MOSFET and the
Schottky diode.
Inverting Converter: Selecting the DC Coupling
Capacitor
The DC voltage rating of the DC coupling capacitor (C ,
DC
• In SEPIC configuration, the high di/dt loop contains
the internal power MOSFET, output capacitor, Schottky
diode and the coupling capacitor.
as shown in Figure 4) should be larger than the maximum
input voltage minus the output voltage (negative voltage):
V
CDC
> V
– V
IN(MAX) OUT
• In inverting configuration, the high di/dt loop contains
internalpowerMOSFET,Schottkydiodeandthecoupling
capacitor.
3959f
17
LT3959
APPLICATIONS INFORMATION
Check the stress on the internal power MOSFET by mea-
suring the SW-to-GND voltage directly across the IC ter-
minals. Make sure the inductive ringing does not exceed
the maximum rating of the internal power MOSFET (40V).
thetopoftheoutputcapacitor(Kelvinconnection),staying
away from any high dV/dt traces. Place the divider resis-
tors near the LT3959 in order to keep the high impedance
FBX node short.
Thesmall-signalcomponentsshouldbeplacedawayfrom
highfrequencyswitchingnodes.Foroptimumloadregula-
tion and true remote sensing, the top of the output voltage
sensing resistor divider should connect independently to
Figure 5 shows the suggested layout of the 2.5V to 8V
input, 12V output boost converter in the Typical Applica-
tion section.
3959f
18
LT3959
APPLICATIONS INFORMATION
R1
C
SS
VIA TO V
OUT
R
R2
T
VIA TO V
R5
36 35 34 33 32 31 30
IN
R
C
C
C
C
VCC
VIA TO V
OUT
1
2
3
4
28
27
R3
SGND
25
24
23
R4
LT3959
6
8
9
21
20
SW
10
12 13 14 15 16 17
L1
D1
C
C
OUT
OUT
C
IN
VIA TO V
OUT
GND
V
OUT
V
IN
3959 F05
VIAS TO SGND GROUND PLANE
VIAS TO SW PLANE
Figure 5. Suggested Layout of the 2.5V to 8V Input. 12V Output Boost Converter in the Typical Application Section
3959f
19
LT3959
TYPICAL APPLICATIONS
2.5V to 5V Input, –5V Output Inverting Converter
C
DC
4.7μF, 25V
X7R
L1A
L1B
V
–5V
1A
OUT
V
IN
2.5V TO 5V
C
OUT
C
IN
124k
121k
22k
V
SW
DRIVE
47μF
10V
X5R
×2
D2
D1
47μF
IN
10V
X5R
PGOOD
1μF
16V
X5R
EN/UVLO
LT3959
SYNC
SGND
GNDK
GND
FBX
84.5k
RT SS
V
C
INTV
CC
15.8k
C
VCC
27.4k
300kHz
9.09k
10nF
0.1μF
4.7μF
10V
X5R
3959 TA02
L1A, L1B: COILTRONICS DRQ127-3R3
D1: VISHAY 6CWQ03FN
D2: PHILIPS PMEG2005EJ
Efficiency vs Output Current
100
90
80
70
60
50
V
= 5V
IN
0
200
400
600
800
1000
OUTPUT CURRENT (mA)
3759 TA02a
3959f
20
LT3959
TYPICAL APPLICATIONS
2.5V to 24V Input, 12V Output SEPIC Converter
4.7μF
50V
L1A
D1
V
OUT
V
12V
500mA AT V = 2.5V
IN
t
2.5V TO 24V
C
IN
C
IN
OUT1
1.5A AT V > 8v
22μF
50V
×2
IN
47μF
16V
X5R
×2
L1B
V
SW
124k
121k
IN
EN/UVLO
GND
150k
LT3959
DRIVE
PGOOD
TIE TO SGND IF
NOT USED
SYNC
105k
RT
FBX
SS
V
C
INTV
SGND GNDK
CC
27.4k
300kHz
7.5k
4.7μF
15.8k
0.1μF
22nF
3959 TA03
L1A, L1B: COILTRONICS DRQ127-150
D1: VISHAY 6CWQ06FN
Efficiency vs Output Current
100
95
90
85
80
75
70
65
60
V
= 12V
IN
0
200
400
600
800
1000
OUTPUT CURRENT (mA)
3759 TA03b
Frequency Foldback Waveforms
When Output Short-Circuits
Load Step Response at VIN = 12V
V
OUT
10V/DIV
V
OUT
500mV/DIV
(AC)
V
SW
20V/DIV
0.8A
0.2A
I
I
OUT
L1A+L1B
500mA/DIV
2.5A/DIV
3959 TA03c
3959 TA03d
500μs/DIV
500μs/DIV
3959f
21
LT3959
TYPICAL APPLICATIONS
2.5V to 8V Input, 12V LED Driver
L1
8.2μH
D1
V
IN
2.5V TO 8V
C
C
OUT
IN
R1
V
22μF
16V
22μF
16V
X5R
×2
OUT
124k
V
SW
IN
PGOOD
X5R
EN/UVLO
GND
DRIVE
FBX
R2
121k
12V LEDs
500mA
LT3959
V
SYNC
DZ1
24V
SGND
GNDK
R3
7.68k
R4
3.48k
INTV
CC
RT SS
C
R
T
R
C
0.1μF
C
SS
27.4k
C
VCC
4.99k
R5
0.5Ω
300kHz
4.7μF
10V
C
22nF
C
X5R
3959 TA04
L1: TOKO 962BS-BR2M
D1: VISHAY SILICONIX 20BQ030
DZ1: CENTRAL SEMICONDUCTOR CMHZ5252B
Efficiency vs VIN
94
92
90
88
86
84
82
2
3
4
5
6
7
8
V
(V)
IN
3959 TA04b
3959f
22
LT3959
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
UHE Package
Variation: UHE36(28)MA
36(28)-Lead Plastic QFN (5mm × 6mm)
(Reference LTC DWG # 05-08-1836 Rev D)
28 27
25 24 23
21 20
0.70 0.05
17
16
15
14
30
31
1.88
0.05
1.53
0.05
5.50 0.05
4.10 0.05
3.00 0.05
3.00 0.05
32
33
0.12
0.05
PACKAGE OUTLINE
0.48 0.05
13
34
1.50 REF
35
36
12
1
2
3
4
6
8
9
10
0.25 0.05
0.50 BSC
2.00 REF
5.10 0.05
6.50 0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.75 0.05
R = 0.10
PIN 1 NOTCH
R = 0.30 OR
0.35 × 45°
CHAMFER
1.50 REF
33 34 35
5.00 0.10
TYP
30 31 32
36
PIN 1
TOP MARK
(NOTE 6)
28
1
2
3
4
27
1.88 0.10
3.00 0.10
0.12
0.10
2.00 REF
25
24
6.00 0.10
6
23
0.48 0.10
1.53 0.10
8
R = 0.125
TYP
21
20
3.00 0.10
9
10
0.40 0.10
17 16 15
0.25 0.05
0.50 BSC
14 13 12
0.200 REF
(UHE36(28)MA) QFN 0112 REV D
0.00 – 0.05
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING IS NOT A JEDEC PACKAGE OUTLINE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
3959f
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
23
LT3959
TYPICAL APPLICATION
2.5V to 8V Input, 12V Output Boost Converter
L1
D1
10μH
V
OUT
12V
V
IN
2.5V TO 8V
C
C
500mA, 2.5V ≤ V < 5V
1A, 5V ≤ V ≤ 8V
IN
OUT
IN
R3
R5
22μF
16V
47μF
16V
X5R
×2
IN
124k 47k
V
SW
IN
PGOOD
X5R
EN/UVLO
GND
DRIVE
FBX
R4
121k
LT3959
V
SYNC
R2
SGND
GNDK
105k
R1
INTV
CC
RT SS
C
15.8k
R
C
T
VCC
R
C
C
SS
27.4k
4.7μF
10V
3.4k
0.22μF
300kHz
C
C
X5R
22nF
3959 TA05
L1: COILTRONICS DR125-100
D1: VISHAY SILICONIX 20BQ030
Efficiency vs Output Current
Load Step Response at VIN = 8V
100
95
90
85
80
75
70
V
= 5V
IN
V
OUT
500mV/DIV
(AC)
0.8A
0.2A
I
OUT
500mA/DIV
3959 TA05c
500μs/DIV
1000
0
200
400
600
800
OUTPUT CURRENT (mA)
3759 TA05b
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT3957
Boost, Flyback, SEPIC and Inverting Converter 3V ≤ V ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency,
IN
with 5A, 40V Switch
5mm × 6mm QFN Package
LT3958
LT3759
LT3758
LT3757
Boost, Flyback, SEPIC and Inverting Converter 5V ≤ V ≤ 80V, 100kHz to 1MHz Programmable Operation Frequency,
IN
with 3.3A, 84V Switch
5mm × 6mm QFN Package
Boost, Flyback, SEPIC and Inverting Controller 1.6V ≤ V ≤ 42V, 100kHz to 1MHz Programmable Operation Frequency,
IN
MSOP-12E Package
Boost, Flyback, SEPIC and Inverting Controller 5.5V ≤ V ≤ 100V, 100kHz to 1MHz Programmable Operation Frequency,
IN
3mm × 3mm DFN-10 and MSOP-10E Packages
Boost, Flyback, SEPIC and Inverting Controller 2.9V ≤ V ≤ 40V, 100kHz to 1MHz Programmable Operation Frequency,
IN
3mm × 3mm DFN-10 and MSOP-10E Packages
LT3748
LT3798
100V Isolated Flyback Controller
5V ≤ V ≤ 100V, No Opto Flyback , MSOP-16 with High Voltage Spacing
IN
Off-Line Isolated No Opto-Coupler Flyback
Controller with Active PFC
V
and V
Limited Only by External Components
OUT
IN
3959f
LT 0712 • PRINTED IN USA
LinearTechnology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
24
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