LT3960 [ADI]
I2C to CAN-Physical Transceiver;
| 型号： | LT3960 |
| 厂家： | 
ADI |
| 描述： | I2C to CAN-Physical Transceiver |
| 文件： | 总22页 (文件大小：1746K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
LT3960
2
I C to CAN-Physical Transceiver
FEATURES
DESCRIPTION
The LT®3960 is a robust high speed transceiver that
n
Protected from Overvoltage Line Faults to 40V
2
2
n
Up to 400kbps I C Communications
extends a single-master I C bus through harsh or noisy
n
4V to 60V Power Supply Range with Internal 3.3V
Regulator
3.3V or 5V Bus Voltage
Extended Common Mode Range ( 36V)
8kV HBM ESD on CAN Pins, 2kV HBM ESD on
All Other Pins
environments at up to 400kbps using the CAN-physical
2
layer. One LT3960 sits near the I C master, creating from
SCL and SDA equivalent differential buses (I2CAN) on
two twisted pairs. At the other end of the twisted pairs, a
second LT3960 recreates the I2C bus locally for any slave
n
n
n
2
2
2
I C devices. A built-in 3.3V LDO powers both the I C and
n
n
n
n
n
n
n
Current Limited Drivers with Thermal Shutdown
Power-Up/Down Glitch Free Driver Outputs
Low Current Shutdown Mode
Transmit Data Dominant Timeout Function
E- and J-Grades Available
Available in a 10-Lead MSOP Package
AEC-Q100 Qualification in Progress
I CAN buses from a single input supply from 4V to 60V.
Alternatively, the LT3960 can be powered directly from a
3.3V or 5V supply.
The LT3960 is available in a 10-lead MSOP package.
All registered trademarks and trademarks are the property of their respective owners.
APPLICATIONS
n
Industrial Networking
n
Automotive Networking
n
Remote Sensors
TYPICAL APPLICATION
I2CAN Bus Link with Large Ground Loop Voltage
Receiving I2C Traffic Across 25V
Common-Mode Differential
V
V
IN
4V TO 60V
CC
5V
2.2µF
ꢀꢁA ꢂꢀꢃAꢄꢅꢆ
V
IN
V
IN
ꢇꢄꢈꢁꢉꢄ
V
CC
3.3V
V
CANSDAH
CANSDAH
V
CC
CC
120Ω
120Ω
GND1
120Ω
120Ω
GND2
2.2µF
LT3960
LT3960
ꢀꢁAꢂꢃAꢀꢄꢅRꢆ
ꢇꢈꢉꢁꢊꢈ
10k 10k
10k 10k
CANSDAL
CANSCLH
CANSDAL
CANSCLH
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
CANSCLL
GND
CANSCLL
GND
HIGH = MASTER
EN/MODE
EN/MODE
FLOAT = SLAVE
ꢀꢁꢂꢃꢄꢀꢁꢂꢅ
ꢅꢆꢇꢈꢂꢉꢇ
3960 TA01
AC GROUND
LOOP ≤ 36V PEAK (V = 5V)
< 25V PEAK (V = 3.3V)
CC
CC
ꢀꢁꢂꢃ ꢄAꢃꢅꢆ
ꢀꢁꢂꢃꢄꢅꢆꢇ
ꢀꢁAꢂꢃꢄꢅꢆꢇꢃ ꢁꢈꢉꢊꢋꢌ
ꢍꢆꢎꢃRꢃꢇ ꢏꢐ ꢑꢒꢈꢃRꢒAꢁ ꢁꢇꢆ ꢓꢂ ꢕ ꢉ.ꢉꢂꢖ
ꢔꢔ
Rev. A
1
Document Feedback
For more information www.analog.com
LT3960
ABSOLUTE MAXIMUM RATINGS
PIN CONFIGURATION
(Notes 1, 2, 3)
V ............................................................................60V
IN
V , EN/MODE.........................................................5.5V
ꢗꢕꢘ ꢑꢖꢒꢙ
CC
ꢅAꢆꢇꢈAꢉ
ꢅAꢆꢇꢈAꢊ
ꢋꢆꢈ
ꢅAꢆꢇꢅꢉꢊ
ꢅAꢆꢇꢅꢉꢉ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀꢌ ꢇꢈA
SDA, SCL .........................................–0.3V to V + 0.3V
CC
ꢍ
ꢎ
ꢏ
ꢐ
ꢇꢅꢉ
ꢀꢀ
ꢋꢆꢈ
CANSDAH, CANSDAL, CANSCLH,
ꢑ
ꢅꢅ
ꢒꢆꢓꢔꢕꢈꢒ
CANSCLL................................................ –40V to 40V
Operating Junction Temperature Range
LT3960E ............................................ –40°C to 125°C
LT3960J............................................. –40°C to 150°C
Storage Temperature Range .................. –65°C to 150°C
Lead Temperature (Soldering, 10 sec)...................300°C
ꢑ
ꢖꢆ
ꢔꢇꢒ ꢘAꢅꢚAꢋꢒ
ꢀꢌꢛꢉꢒAꢈ ꢘꢉAꢇꢗꢖꢅ ꢔꢇꢕꢘ
ꢞ ꢀꢁꢄꢟꢅꢠ θ ꢞ ꢃꢌꢟꢅꢓꢙ
ꢜA
ꢒꢝꢘꢕꢇꢒꢈ ꢘAꢈ ꢡꢘꢖꢆ ꢀꢀꢢ ꢖꢇ ꢋꢆꢈꢠ ꢔꢣꢇꢗ ꢤꢒ ꢇꢕꢉꢈꢒRꢒꢈ ꢗꢕ ꢘꢅꢤ
ꢗ
ꢜꢔAꢝ
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING*
LTHJP
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LT3960EMSE#PBF
LT3960EMSE#TRPBF
LT3960JMSE#TRPBF
10-Lead Plastic MSOP
10-Lead Plastic MSOP
–40°C to 125°C
–40°C to 150°C
LT3960JMSE#PBF
LTHJP
AUTOMOTIVE PRODUCTS**
LT3960EMSE#WPBF
LT3960JMSE#WPBF
LT3960EMSE#WTRPBF
LT3960JMSE#WTRPBF
LTHJP
LTHJP
10-Lead Plastic MSOP
10-Lead Plastic MSOP
–40°C to 125°C
–40°C to 150°C
Contact the factory for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
**Versions of this part are available with controlled manufacturing to support the quality and reliability requirements of automotive applications. These
models are designated with a #W suffix. Only the automotive grade products shown are available for use in automotive applications. Contact your
local Analog Devices account representative for specific product ordering information and to obtain the specific Automotive Reliability reports for
these models.
Rev. A
2
For more information www.analog.com
LT3960
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, Figure 1 Applies with RPU = 4.99k, RL = 60Ω,
EN/MODE = VCC, TYP values unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
V
Low Dropout Regulator
IN
l
l
l
V
Input Voltage Operating Range
V
V
V
Regulated Internally from V
IN
4
3
4.5
60
3.6
5.5
V
V
V
IN
CC
IN
IN
Tied to V , 3.3V Range
CC
Tied to V , 5V Range
CC
I
V
Shutdown Current
IN
EN/MODE = 0V
4V ≤ V ≤ 60V, I
20
26
µA
V
IN(SD)
V
V
V
V
LDO Regulation Voltage
LDO Line Regulation
LDO Load Regulation
= 1mA
= 1mA
3.1
3.3
3.5
CC
IN
LDO
LDO
4V ≤ V ≤ 60V, I
0.05
0.05
%/V
%/mA
V
LINE
IN
0.1mA < I
< 100mA
LOAD
CC,LOW
LDO
LDO Voltage at Low V
LDO Current Limit
LDO Foldback Current Limit
I
= 85mA, V = 4V
3
IN
LDO
IN
ILIM
V
V
= 3.0
= 0.5V
100
130
25
160
2.9
mA
mA
CC
CC
CC
l
V
V
V
Undervoltage Lockout Threshold
Undervoltage Lockout Hysteresis
V
Falling
2.6
2.7
75
V
mV
UVLO
CC
CC
CC
I
V
V
Shutdown Supply Current
Operating Supply Current
EN/MODE = 0V, V = V
IN
3
6
mA
mA
CC
CC
CC
CC
EN/MODE ≥ 0.7V, V = V
4.2
CC
IN
EN/MODE Selection
EN/MODE Shutdown Threshold Falling
VSHDN-HYS EN/MODE Shutdown Hysteresis
l
l
V
400
1.9
700
50
2
800
2.2
mV
mV
V
SHDN
V
EN/MODE Master Threshold
MSTR
EN-UP
I
EN/MODE Pin Bias Current Low
EN/MODE = 350mV
2
µA
CAN Drivers
l
l
l
V
Bus Output Voltage
(Dominant)
CANxH t < t
V
= 3.3V
= 5V
2.15
2.75
0.5
2.9
3.6
0.9
1.4
3.3
4.5
V
V
V
V
O(D)
TO:CAN
CC
CC
CC
CC
V
V
V
CANxL t < t
= 3.3V
= 5V
1.65
2.25
TO:CAN
0.5
l
l
V
Bus Output Voltage (Recessive)
V
V
= 3.3V, No Load (Figure 1)
= 5V, No Load (Figure 1)
1.45
2
1.95
2.5
2.45
3
V
V
O(R)
CC
CC
l
V
V
V
V
Differential Output Voltage (Dominant)
Differential Output Voltage (Dominant)
Differential Output Voltage (Recessive)
Common Mode Output Voltage (Dominant)
R = 50Ω to 65Ω
V
V
= 3.3V
= 5V
1.5
2.7
2.2
3.1
0
3
V
V
OD(D)
OD(D)
OD(R)
OC(R)
L
CC
3.5
50
CC
l
No Load (Figure 1)
–500
mV
l
l
V
V
= 3.3V, (Figure 1)
= 5V, (Figure 1)
1.45
2
1.95
2.5
2.45
3
V
V
CC
CC
l
l
l
l
I
Bus Output Short-Circuit Current
(Dominant)
CANxH CANxH = 0V
CANxH –40V < CANxH < V
CANxL CANxL = 5V
–150
–150
25
–75
–40
3
mA
mA
mA
mA
OS(D)
O(R)
75
100
100
CANxL
V
< CANxL < 40V
–3
CC
CAN Receivers
l
l
V
V
V
Bus Common Mode Voltage =
V
V
= 3.3V
= 5V
25
36
V
V
CM
CC
CC
(CANxH+CANxL)/2 for Data Reception
l
l
+
Bus Input Differential Threshold Voltage
(Positive Going)
V
V
= 3.3V, –25V ≤ V ≤ 25V
= 5V, –36V ≤ V ≤ 36V
775
775
900
900
mV
mV
TH
TH
CC
CC
CM
CM
l
l
–
Bus Input Differential Threshold Voltage
(Negative Going)
V
V
= 3.3V, –25V ≤ V ≤ 25V
= 5V, –36V ≤ V ≤ 36V
500
500
625
625
mV
mV
CC
CC
CM
CM
Rev. A
3
For more information www.analog.com
LT3960
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, Figure 1 applies with RPU = 4.99k, RL = 60Ω,
EN/MODE = VCC, TYP values unless otherwise specified.
SYMBOL PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
∆V
Bus Input Differential Hysteresis Voltage
V
V
= 3.3V, –25V ≤ V ≤ 25V
150
150
mV
mV
TH
CC
CC
CM
= 5V, –36V ≤ V ≤ 36V
CM
l
l
l
R
R
Input Resistance (CANxH and CANxL)
Differential Input Resistance
SCL = SDA = V ; R = ∆V/∆I; ∆I = 20 µA
25
50
35.7
71.4
50
100
3
kΩ
kΩ
%
IN
CC IN
SCL = SDA = V ; R = ∆V/∆I; ∆I = 20 µA
ID
CC IN
∆R
Input Resistance Matching
R (CANxH) to R (CANxL)
IN IN
IN
C
C
C
Input Capacitance to GND (CANxH)
Input Capacitance to GND (CANxL)
Differential Input Capacitance
Bus Leakage Current (Power Off)
(Note 4)
(Note 4)
(Note 4)
32
8
pF
pF
pF
µA
µA
IH
IL
8.4
ID
I
V
V
= 0V, CANxH = CANxL = 5V
10
50
L
CC
CC
l
= 0V, CANxH = CANxL = 5V, t < 150°C
2
I C Port
l
l
V
V
SDA, SCL Input Low Voltage
SDA, SCL Input High Voltage
SDA, SCL Input Leakage Current
SDA, SCL Input Hysteresis
SDA, SCL Output Low Voltage
Clock/Data Rise Time
0.4
50
V
V
IL
1.5
–50
IH
I
SDA = SCL = 0V to 5.5V
nA
V
i
l
l
Vhys
0.05 • V
CC
V
I
= 3mA
0.4
300
300
V
OL1
SDA
t
t
C = Capacitance of One Bus Line (pF) (Note 5)
B
20 + 0.1C
20 + 0.1C
ns
ns
r
f
B
Clock/Data Fall Time
C = Capacitance of One Bus Line (pF) (Note 5)
B
B
Rev. A
4
For more information www.analog.com
LT3960
SWITCHING CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, VCC = 3.3V, Figure 2 applies with RPU = 4.99k, RL = 60Ω,
EN/MODE = VCC, TYP values unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
Transceiver Timing
l
l
l
l
l
l
l
l
l
l
l
l
l
l
f
t
SCL Clock Frequency (Notes 5,6)
0
400
130
115
170
120
65
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
µs
ns
ns
SCL
2
2
I C to I CAN Dominant Propagation Delay
(Figure 2, Figure 3)
(Figure 2, Figure 3)
(Figure 2, Figure 3)
(Figure 2, Figure 3)
(Figure 2, Figure 4)
V
V
V
V
V
V
V
V
= 3.3V
= 5V
45
45
80
60
25
25
25
20
0.5
80
75
PI2CBD
CC
CC
CC
CC
CC
CC
CC
CC
2
2
t
t
t
I C to I CAN Recessive Propagation Delay
= 3.3V
= 5V
120
90
PI2CBR
PBI2CD
PBI2CR
2
2
I CAN Dominant to I C Propagation Delay
= 3.3V
= 5V
40
40
65
2
2
I CAN Recessive to I C Propagation Delay
= 3.3V
= 5V
45
80
35
60
2
t
t
t
t
t
I CAN Dominant Timeout Time
1.5
2
TO;CAN
2
I C Driver Enable from Shutdown
V
CC
V
CC
= 3.3V or 5V (Figure 2, Figure 5)
40
EN;I2C
2
I CAN Driver Enable from Shutdown
= 3.3V or 5V (Figure 2, Figure 6)
40
EN;CAN
2
Time to Shutdown, I C
(Figure 2, Figure 5)
(Figure 2, Figure 6)
500
500
SHDN;I2C
SHDN;CAN
2
Time to Shutdown, I CAN
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LT3960E is guaranteed to meet specified performance
from 0°C to 125°C. Specifications over the –40°C to 125°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LT3960J is guaranteed to meet
performance specifications over the full –40°C to 150°C operating
junction temperature range. High junction temperatures degrade operating
lifetimes. Operating lifetime is derated at junction temperatures greater
than 125°C.
Note 3: The LT3960 includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed the maximum operating junction temperature
when overtemperature is active. Continuous operating above the specified
maximum operating junction temperature may impair device reliability.
Note 4: Pin capacitance given for reference only and is not tested in
production.
Note 5: Rise and fall times are measured at 30% and 70% levels.
Note 6: Maximum SCL clock frequency will be affected by delays through
the twisted-pair interface and I/O circuitry of other devices on the bus.
These delays may limit the operation frequency to below the LT3960
maximum specification.
Note 7: The LT3960 does not support clock stretching. SCL should not be
pulled low by slave devices.
Rev. A
5
For more information www.analog.com
LT3960
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3V, RPU = 60Ω unless otherwise noted.
Supply Current (I2CAN Dominant)
vs VCC
Supply Current (I2CAN Recessive)
vs VCC
Supply Current (I2CAN Dominant)
vs Temperature
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀ ꢁꢂ
ꢀꢀ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀꢁꢂ
ꢀ
ꢀ.ꢀ
ꢀ
ꢀ.ꢁ
ꢀ
ꢀ.ꢁ
ꢀꢁꢂ
ꢀ
ꢀ.ꢀ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀ
TEMPERATURE (˚C)
ꢀꢀ
ꢀꢀ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢀ
Supply Current (I2CAN Recessive)
vs Temperature
I2CAN Differential Output Voltage
(Dominant) vs Temperature
I2CAN Common Mode Voltage
(Dominant) vs Temperature
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ
ꢀꢀ
ꢀ ꢁꢂ
ꢀ
ꢀ ꢁꢂ
ꢀꢀ
ꢀ
ꢀꢀ
ꢀ ꢁ.ꢁꢂ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢀ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢀ
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
TEMPERATURE (˚C)
TEMPERATURE (˚C)
TEMPERATURE (˚C)
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢂ
CANxH Short-Circuit Current
(Dominant) vs CANxH Voltage
CANxH Short-Circuit Current
(Dominant) vs CANxH Voltage
I2C to CAN Propagation Delay
vs Temperature
ꢀ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂꢃꢄAꢄꢅ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀ
ꢀꢀ
ꢀ ꢁꢂ
ꢀꢀ
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢀ
ꢀ
ꢀ ꢁꢂ
ꢀꢀ
Rꢀꢁꢀꢂꢂꢃꢄꢀ
ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁ
ꢀAꢁ ꢀ ꢁꢂꢃ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
ꢀAꢁ ꢀ ꢁꢂꢃ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
TEMPERATURE (˚C)
ꢀ
ꢀ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢁ
Rev. A
6
For more information www.analog.com
LT3960
TYPICAL PERFORMANCE CHARACTERISTICS
TA = 25°C, VCC = 3.3V, RPU = 60Ω unless otherwise noted.
CAN to I2C Recessive Propagation
vs Temperature
EN/MODE Shutdown Thresholds
vs Temperature (VCC = 3.3V, 5V)
EN/MODE Current vs Temperature
(VEN/MODE = 0.35V)
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁꢂꢃꢄAꢄꢅ
Rꢀꢁꢀꢂꢃ
ꢀAꢁꢁꢂꢃꢄ
Rꢀꢁꢀꢂꢂꢃꢄꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
TEMPERATURE (˚C)
TEMPERATURE (˚C)
TEMPERATURE (˚C)
ꢀꢁꢂꢃ ꢄꢅꢃ
ꢀꢁꢂꢃ ꢄꢅꢅ
ꢀꢁꢂꢃ ꢄꢅꢆ
VIN Shutdown Current
vs Temperature
VIN Quiescent Current
vs Temperature
VCC vs Temperature (Various VIN)
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢀ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀ.ꢁ
ꢀꢁ
ꢀꢀ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢀꢁ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢀꢁ
ꢀꢁꢁ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂ ꢀ ꢃꢄ
ꢀ
ꢀ ꢁꢂA
ꢀꢁ
ꢀꢀ
ꢀ
ꢀꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
TEMPERATURE (˚C)
TEMPERATURE (˚C)
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢀ
ꢀꢁꢂꢃ ꢄꢅꢆ
VCC vs Current (Various VIN)
VCC UVLO vs Temperature
VCC Current Limit vs VIN
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢀ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀ.ꢁꢂ
ꢀ.ꢀꢁ
ꢀ.ꢀꢁ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢂ
ꢀ.ꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ ꢁꢂ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀꢁ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
ꢀ ꢁꢂꢃ
Rꢀꢁꢀꢂꢃ
ꢀꢁ
ꢀAꢁꢁꢂꢃꢄ
ꢀꢁ
ꢀꢁ
ꢀ
ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢁ ꢀꢁꢂ ꢀꢁꢂ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ ꢀꢁꢂ
ꢀꢁRRꢂꢃꢄ ꢅꢆAꢇ
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢀ ꢀꢁ
ꢀꢁꢂ
ꢀꢁꢂꢃꢁRAꢀꢄRꢁ ꢅꢆꢇꢈ
ꢀ
ꢀ
ꢀꢁ
ꢀꢀ
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢂꢃ ꢄꢅꢂ
ꢀꢁꢂꢃ ꢄꢅꢆ
Rev. A
7
For more information www.analog.com
LT3960
PIN FUNCTIONS
CANSDAL (Pin 1): Low Level CAN Bus Line. Carries the
EN/MODE (Pin 7): MODE/Shutdown pin. Tie above 2.5V
to select master mode, float pin to select slave mode, or
pull this pin to ground for low-power shutdown mode.
2
I C data bus.
CANSDAH (Pin 2): High Level CAN Bus Line. Carries the
2
I C data bus.
V
(Pin 8): Low Dropout Regulator Output and Device
PCoCwer Supply Input. Bypass this pin with a 2.2µF or
greater capacitor to ground. Any bypass capacitors must
be located as close to the pin as possible.
CANSCLH (Pin 4): High Level CAN Bus Line. Carries the
2
I C clock bus.
CANSCLL (Pin 5): Low Level CAN Bus Line. Carries the
2
SCL (Pin 9): Clock Input or Output Pin for the I C Serial
2
I C clock bus.
Port. When EN/MODE is 2.5V or above, the SCL pin is
an input for the master clock. When EN/MODE is float-
ing, the SCL pin is an output for data received on the
CANSCLH/L pins.
GND (Pin 3 and Exposed Pad): Ground. Solder the
exposed pad and pin directly to the ground plane.
V
(Pin 6): Input Voltage Supply. This pin is the power
IN
SDA (Pin 10): Data Input and Output Pin for the I2C
Serial Port.
supply input to the LDO. It must be locally bypassed with
a 1µF filter capacitor to GND as close to the pin as possi-
ble. If the LDO function is unused, tie V to V .
IN
CC
Rev. A
8
For more information www.analog.com
LT3960
BLOCK DIAGRAM
V
IN
4V TO 60V
6
V
IN
–
+
–
+
3.3V
0.5V
SHUTDOWN
V
V
CC
CC
8
2
V
EN/MODE
I C MASTER
V
CC
CC
7
9
2.2μF
R
PU
T
X
TIMEOUT
PREDRIVE
SCL
MODE
SELECT
35.7k
35.7k
CANSCLH
CANSCLL
+
4
5
–
V
CC
1.1k
1.1k
1.1k
1.95V FOR V = 3.3V
CC
2.5V FOR V = 5V
CC
+
–
SHUTDOWN
V
CC
V
CC
1.1k
R
PU
T
TIMEOUT
PREDRIVE
X
SDA
GND
10
READ/WRITE
ARBITRATION
35.7k
35.7k
CANSDAH
CANSDAL
+
–
2
1
11
3
3960 BD
Rev. A
9
For more information www.analog.com
LT3960
TEST CIRCUITS
V
CC
5V
1µF
V
CANSDAH
IN
R
L/2
30.1Ω
1%
CANSDAH
CANSDAL
EN/MODE
CM
SDA
V
V
CC
CC
R
L/2
2.2µF
R
R
PU
4.99k
30.1Ω
1%
PU
4.99k
CANSDAL
CANSCLH
SDA
SDA
SCL
GND
LT3960
R
L/2
30.1Ω
1%
CANSCLH
CANSCLL
SCL
CM
SCL
R
L/2
30.1Ω
1%
CANSCLL
3960 F01
Figure 1. All Electrical Characteristic Measurements
V
CC
5V
1µF
V
CANSDAH
IN
R
L/2
30.1Ω
1%
CANSDAH
CANSDAL
EN/MODE
C
L
CM
4.7nF
V
V
SDA
CC
CC
100pF
R
L/2
2.2µF
15pF
15pF
R
R
30.1Ω
1%
PU
PU
1k
1k
CANSDAL
CANSCLH
SDA
SDA
SCL
GND
LT3960
R
L/2
30.1Ω
1%
CANSCLH
CANSCLL
C
SCL
L
CM
SCL
100pF
R
L/2
4.7nF
30.1Ω
1%
CANSCLL
3960 F02
Figure 2. All Switching Characteristic Measurements
Rev. A
10
For more information www.analog.com
LT3960
TIMING DIAGRAMS
ꢏꢔꢕꢏ
ꢇꢐꢖ
ꢃ.ꢒꢍ
ꢑꢑ
ꢅꢆꢇ ꢈꢉAꢅꢊꢋRꢌ
ꢃ.ꢀꢍ
ꢑꢑ
ꢏꢔꢕꢏ
ꢈꢑꢖ
ꢆAꢎꢅꢆꢇꢏ
ꢆAꢎꢅꢆꢇꢇ
ꢆꢇꢈ ꢉꢊAꢆꢋꢌRꢍ
ꢃ.ꢀꢐ
ꢒꢒ
ꢇAꢎꢆꢇꢈꢏ
ꢇAꢎꢆꢇꢈꢈ
ꢑꢐꢉꢔꢎAꢎꢊ
ꢍ
ꢐꢑ
ꢃ.ꢁꢍ
ꢃ.ꢓꢍ
Rꢋꢆꢋꢅꢅꢔꢍꢋ
ꢏꢔꢕꢏ
ꢒꢑꢊꢔꢎAꢎꢋ
ꢐ
ꢑꢒ
ꢃ.ꢁꢐ
ꢃ.ꢒꢍ
ꢑꢑ
ꢅꢆꢇ ꢈꢅꢇAꢍꢋꢌ
ꢃ.ꢀꢍ
ꢃ.ꢓꢐ
ꢑꢑ
ꢇꢐꢖ
Rꢌꢇꢌꢆꢆꢔꢐꢌ
ꢗ
ꢗ
ꢗ
ꢘꢔꢙꢆꢚꢑ
ꢘꢔꢙꢆꢚR
ꢘꢚꢔꢙꢆꢑ
ꢋꢑꢘꢇAꢎ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢗ
ꢗ
ꢀꢁꢂꢃ ꢄꢃꢀ
ꢘꢚꢔꢙꢆR
Figure 3. Transceiver Data Propagation Timing Diagram
Figure 4. I2CAN Dominant Timeout
ꢑ.ꢒꢎ ꢓꢆꢈAꢎꢐ ꢔꢉꢊꢐꢕ
ꢑ.ꢎꢍ ꢒꢓAꢅꢔꢏR ꢓꢈꢉꢏꢕ
ꢃ.ꢏꢅꢎ
ꢃ.ꢏꢎ
ꢃ.ꢐꢎꢍ
ꢃ.ꢐꢍ
ꢐꢋ
ꢏꢊ
ꢃ.ꢏꢎ
ꢇꢇ
ꢆꢇꢈ ꢉR ꢆꢊA
ꢅꢆꢇ ꢈR ꢅꢉA
ꢃ.ꢀꢎ
ꢃ.ꢀꢍ
ꢊꢊ
ꢉꢉ
ꢖ
ꢖ
ꢖ
ꢖ
ꢅꢌꢉꢊꢗꢆAꢊ
ꢐꢋꢗꢘꢒꢇ
ꢆꢍꢊꢋꢗꢘꢒꢇ
ꢏꢊꢗꢆAꢊ
ꢇAꢋꢌꢍ
ꢇAꢋꢌꢈ
ꢆAꢊꢋꢌ
ꢆAꢊꢋꢇ
ꢆAꢊ
ꢃ.ꢁꢍ
ꢎ
ꢉꢊ
ꢍ
ꢈꢉ
ꢃ.ꢁꢎ
ꢃ.ꢎꢍ
ꢃ.ꢅꢎ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢀꢁꢂꢃ ꢄꢃꢂ
Figure 5. I2CAN Enable and Disable Times
Figure 6. I2CAN Enable and Disable Times
Rev. A
11
For more information www.analog.com
LT3960
OPERATION
The LT3960 is a high-speed transceiver which creates the
functional equivalent of a single-master I2C bus in the CAN
physical layer and is powered from a single wide-ranging
input voltage. Using two integrated CAN transceivers, the
LT3960 creates a differential proxy for each of the sin-
the V pin from which the transceivers and bus lines are
CC
powered. Alternatively, the LT3960 can by powered from
a supply voltage of 3.3V or 5V on V , bypassing the LDO
IN
by shorting V to V .
CC
IN
The EN/MODE pin is used to put the LT3960 in low power
shutdown mode and selects between Master and Slave
modes of operation when enabled. When the EN/MODE
pin is below 0.7V, (typical) the LT3960 is in shutdown
mode, disabling both the LDO and transceivers. When
VIN is powered, floating the EN/MODE pin or driving it
between 0.7V and 2.0V (typical) enables the LDO and
sets the transceiver in Slave Mode. An EN/MODE voltage
2
gle-ended I C clock and data signals which is capable
of traversing harsh or noisy environments across two
twisted pairs.
Each transceiver consists of a transmitter and receiver,
capable of quickly converting a single-ended I C domi-
2
nant signal into a differential dominant signal, and vice
versa. The transmitter is a current-regulated differential
driver that generates a differential voltage between the
CANxH and CANxL pins determined by drive current and
the equivalent resistive load on the CANx bus. Common-
mode voltage of the CANx bus is regulated by the trans-
mitter when driving dominant as described in the applica-
tions section. The receiver is a CAN compatible differential
receiver with a wide common-mode range of 25V or
above 2.0V (typical) with V is powered sets the LT3960
IN
in Master Mode.
Bidirectional communication is supported on the data
channel (SDA and CANSDA) regardless of the mode of
operation. Communication on the clock channel (SCL
and CANSCL) is unidirectional, with the direction deter-
mined by the selected mode of operation. In Slave Mode,
an LT3960 only communicates clock signals from the
CANSCL bus to the SCL bus. Any LT3960 connected to
36V, depending on V voltage.
CC
In the simplest setup, two LT3960 devices are used
(Figure 7). The first is connected to the I2C master (micro-
controller or otherwise). The second LT3960 is connected
to the first by two twisted pairs and regenerates the I C
bus locally for one or more I C slave devices. The LT3960
devices transmit the clock signal in only one direction,
from master to slave. Bidirectional communication of the
data signal is always permitted.
2
slave I C devices should be operated in Slave Mode. In
Master Mode, an LT3960 only communicates clock sig-
nals from the SCL bus to the CANSCL bus. The LT3960
connected to the I2C master device should always be
operated in Master Mode. Regardless of the number of
2
2
2
LT3960 devices tied to a I CAN bus in a given applica-
tion, exactly one will operate in Master Mode, driving the
2
2
clock signal to the I CAN bus and, ultimately, to all I C
slave devices. The LT3960 does not support multi-master
The LT3960 contains an integrated LDO which regulates
an input from the V pin between 4V and 60V to 3.3V on
IN
2
I C systems.
ꢋꢇRꢋꢎꢇꢁ ꢏꢐARꢍ ꢒ
ꢂ.ꢂꢆ ꢐR ꢗꢆ
ꢋꢇRꢋꢎꢇꢁ ꢏꢐARꢍ ꢑ
ꢘꢆ ꢁꢐ ꢄꢅꢆ
ꢆ
ꢇꢈ
ꢆ
ꢇꢈ
ꢆ
ꢋAꢈꢌꢍAꢓ
ꢋAꢈꢌꢍAꢓ
ꢀꢁꢂꢃꢄꢅ
ꢋAꢈꢌꢍAꢀ
ꢔꢈꢕꢖꢐꢍꢔ
ꢋꢋ
ꢀꢁꢂꢃꢄꢅ
ꢆ
ꢋꢋ
ꢚꢋꢐꢈꢁRꢐꢀꢀꢔR
ꢑ
ꢇ ꢋ
ꢋAꢈꢌꢍAꢀ
ꢋAꢈꢌꢋꢀꢓ
ꢌꢀAꢆꢔ
ꢌꢍA
ꢌꢋꢀ
ꢍꢇꢙ ꢇꢕꢐ
ꢌꢍA
ꢋAꢈꢌꢋꢀꢓ
ꢌꢋꢀ
ꢔꢈꢕꢖꢐꢍꢔ
ꢌꢍA
ꢌꢋꢀ
ꢌꢍA
ꢌꢋꢀ
ꢋAꢈꢌꢋꢀꢀ
ꢋAꢈꢌꢋꢀꢀ
ꢙꢈꢍ
ꢙꢈꢍ
Figure 7. Simple Single-Slave Application
Rev. A
12
For more information www.analog.com
LT3960
OPERATION
Data Transmission Detail
CANSDA bus. The primary factor determining the direction
of communication is the time of arrival of dominant sig-
nals on SDA and CANSDA. The first of SDA and CANSDA
to be asserted dominant by an external device will cause
the LT3960 to drive the other dominant, establishing the
direction of communication until it is released and returns
to a recessive state. The transmitter which opposes the
established direction of communication will be blocked
until it can be safely re-enabled without locking up a bus
or misinterpreting the direction of communication. To
fully describe the method of arbitration, communication
in each direction is described in detail below.
The timing diagram in Figure 8 shows how a byte of data
2
2
is sent by the I C master and acknowledged by the I C
slave in the single-master single-slave system described
2
in Figure 7. The I C master issues a start command to
initiate a communication frame. The LT3960 connected to
the master drives the CANSCL and CANSDA buses dom-
inant in response to the change in state on the SCL and
SDA pins without interpretation or delay. The LT3960 con-
2
nected to the I C slave receives the dominant signals on
the CANSCL and CANSDA buses and drives the slave SCL
and SDA pins dominant without interpretation or delay.
2
2
The result on the slave I C bus is an I C Start command
nearly identical to that generated by the master, delayed by
propagation delays of the master LT3960, twisted pairs,
and slave LT3960.
In the default state, SDA and CANSDA are in a recessive
state and no direction of communication is set. If SDA is
2
asserted dominant (low) by an external I C device from
a default state, the LT3960 will drive CANSDA dominant
and the LT3960’s receiver on CANSDA is blocked from
driving SDA. When the SDA line is eventually released by
2
As additional clock and data edges are written by the I C
master, they too are recreated, first on the CANSCL and
2
2
the external I C device and returns to a recessive state,
CANSDA buses and then on the slave I C bus. Once the
2
2
the LT3960 stops driving the CANSDA bus dominant.
After allowing the CANSDA bus sufficient time to return
to a passive state as required by the CAN physical layer
specifications, the LT3960 reopens the possibility of bidi-
rectional traffic and waits for a dominant signal on SDA or
CANSDA to once again set a direction for communication.
entire byte of data is written on the slave I C bus, the I C
slave device issues an ACK, pulling down SDA to acknowl-
edge receipt of a valid byte. The slave LT3960 recognizes
2
that a slave I C device is driving the SDA line dominant
and switches from receiving to transmitting to drive the
CANSDA bus dominant. The master LT3960 then receives
the ACK on the CANSDA bus and pulls the master SDA
low, communicating the ACK to the master.
If, from the default state, CANSDA is asserted dominant
by another LT3960 on the bus while SDA remains reces-
sive (high), the LT3960 will drive SDA dominant (low)
and the CAN transmitter is blocked from driving CANSDA
based on its input while CANSDA is held dominant. When
the CANSDA bus returns to a recessive state, the LT3960
stops driving the other dominant. When it is safe to do so
without causing glitches or latch up, the LT3960 reopens
the possibility of bidirectional traffic and waits for a dom-
inant signal on SDA or CANSDA to once again set a direc-
tion for communication.
Note that clock data is always transmitted from master to
slave, but the LT3960 dynamically switches the direction
of SDA communication based primarily on the time of
arrival of dominant signals on its inputs.
Bidirectional Arbitration of SDA
The LT3960 facilitates bidirectional SDA communication
between master and slave I2C devices by dynamically
controlling the direction of traffic between SDA and the
Rev. A
13
For more information www.analog.com
LT3960
OPERATION
ꢗ
ꢗ
ꢍ ꢆ ꢈꢋARꢋ
ꢍ ꢆ ꢈꢋꢖꢏ
ꢈꢆꢉ ꢐꢑAꢈꢋꢎRꢒ
ꢈꢊA ꢐꢑAꢈꢋꢎRꢒ
ꢓ
ꢓ
ꢃ
ꢃ
ꢓ
ꢓ
ꢃ
ꢃ
Aꢆꢔ
ꢑAꢈꢋꢎR
ꢉꢋꢀꢁꢂꢃ
ꢆAꢇꢈꢆꢉ
ꢆAꢇꢈꢊA
ꢋꢌꢍꢈꢋꢎꢊ ꢏAꢍRꢈ
ꢆAꢇꢈꢊA
Aꢆꢔ
Aꢆꢔ
ꢆAꢇꢈꢆꢉ
ꢈꢉAꢕꢎ
ꢉꢋꢀꢁꢂꢃ
ꢗ
ꢗ
ꢍ ꢆ ꢈꢋARꢋ
ꢍ ꢆ ꢈꢋꢖꢏ
ꢈꢆꢉ ꢐꢈꢉAꢕꢎꢒ
ꢈꢊA ꢐꢈꢉAꢕꢎꢒ
ꢓ
ꢓ
ꢃ
ꢃ
ꢓ
ꢓ
ꢃ
ꢃ
ꢀꢁꢂꢃ ꢄꢃꢅ
ꢗ
Aꢆꢔ ꢄRꢖꢑ ꢍ ꢆ ꢈꢉAꢕꢎ
Figure 8. Simple Single-Slave Application
Rev. A
14
For more information www.analog.com
LT3960
APPLICATIONS INFORMATION
Supply Voltage Ranges
ꢂ.ꢂꢆ ꢊR ꢋꢆ
ꢌꢍꢎ ꢆꢊꢀꢁAꢏꢐ
ꢆ
ꢆ
ꢆ
ꢉꢉ
ꢇꢈ
The LT3960 can be operated with or without using its
ꢖ.ꢖꢔꢗ
ꢉꢉ
ꢂꢅꢕ
ꢀꢁꢂꢃꢄꢅ
internal LDO. Tying V to V and powering directly from
IN
CC
ꢔꢉꢊꢈꢁRꢊꢀꢀꢐR
ꢇꢑꢊ
ꢐꢈꢑꢒꢊꢓꢐ
a 3.3V or 5V supply will bypass the LDO. With a 5V supply
EN
on V , transmitter common-mode voltage and receiver
CC
ꢂꢃꢄꢅ ꢗꢅꢃ
common-mode input range are increased from their 3.3V
values. In this configuration, an internal comparator mon-
itors the supply voltage and switches internal reference
voltages and output drive strengths at approximately
4.1V. Operation with a supply between 3.6V and 4.5V is
not recommended, because of the discontinuity in the
internal voltages at this switch point.
Figure 9. Recommended Master Mode Power Setup
2
An LT3960 connected to slave I C devices must be oper-
ated in Slave Mode, with the EN/MODE pin between 0.7V
and 2V. When left floating, the EN/MODE pin will pull
up to approximately 1.2V, enabling the LT3960 and set-
ting it in Slave Mode, whenever the V pin is powered
IN
When using the internal LDO to generate the 3.3V bus
above approximately 2V. It is recommended that the EN/
MODE pin be left floating for Slave Mode LT3960 devices,
regardless of whether the internal LDO is employed.
supply on V , any V supply voltage between 4V and
CC
60V is allowed. In thIiNs configuration, the switch point
mentioned above is avoided since V is regulated to a
CC
fixed 3.3V.
LT3960 and Standard CAN Transceivers
An LT3960 operating with a VCC at 5V may share an I2CAN
It should be noted that while the LT3960 uses the CAN
physical layer to conduct bidirectional I2C data, the
CANSCL and CANSDA buses created by the LT3960 are
not traditional CAN buses carrying traditional CAN data. As
such, the CANSCL and CANSDA buses between LT3960
devices cannot be shared with standard CAN transceivers
in a multidrop configuration.
bus with an LT3960 operating with V at 3.3V. However,
CC
the fluctuation in common mode voltage between 1.95V
(when an LT3960 with VCC = 3.3V is dominant) and
2.5V (when an LT3960 with V = 5V is dominant) may
CC
increase electromagnetic emissions.
Master and Slave Mode Configurations
2
The LT3960 connected to the I C master must be oper-
40V Fault Protection
ated in Master Mode, with the EN/MODE pin driven greater
than 2.5V. When operating in Master Mode, it is recom-
The LT3960 provides 40V fault protection on the
2
I CAN interface pins (CANSCLH, CANSCLL, CANSDAH,
mended that V be tied to V and driven from a bus
CC
IN
2
CANSDAL), allowing I C communication in applications
voltage of 3.3V or 5V. Additionally, EN/MODE should be
where it was previously impractical. Addressing the need
the overvoltage tolerance in many industrial and auto-
motive applications, the driver outputs use a progressive
foldback current limit to protect against overvoltage faults
while still allowing high current output drive. The LT3960
is protected from 40V faults powered or unpowered,
2
driven from a digital output pin from the I C Master as
shown below. In this configuration, EN/MODE can be held
low until the V cap is fully charged.
CC
Do not tie the EN/MODE pin directly to V when oper-
CC
ating in Master Mode. With EN/MODE and V shorted,
CC
every power-up sequence will set the LT3960 into slave
even in the case of V open or shorted to ground. When
CC
mode for many microseconds while the V capacitor
VCC is open or shorted to GND, the transceivers are off and
CC
2
charges between the enable threshold and the Master
Mode threshold.
the I CAN bus pins remain in the high impedance state.
Rev. A
15
For more information www.analog.com
LT3960
APPLICATIONS INFORMATION
8kV ESD Protection
in the dominant state. For example, if the SCL line is held
low in Master Mode, a dominant state is asserted on the
CANSCL bus until the timer expires, after which the driver
releases the bus to a recessive state. The timer is reset
when SCL is brought high.
2
The LT3960 features robust ESD protection. All I CAN
interface pins (CANSCLH, CANSCLL, CANSDAH,
CANSDAL) are protected to 8kV HBM with respect to
GND, powered or unpowered and all other pins are pro-
tected to 2kV HBM to ensure reliable operation in severe
environmental conditions. For applications where greater
ESD protection of interface pins is needed, a simple net-
work providing IEC 61000-4-2 Level 4 ESD protection is
shown in the Typical Application section.
2
I CAN Driver Overvoltage, Overcurrent, and
Overtemperature Protection
The I2CAN driver outputs are protected from short cir-
cuits to any voltage within the absolute maximum range
2
of -40V to 40V. The maximum current on I CAN interface
36V Extended Common-Mode Range
pins in a fault condition is 150mA. The drivers include a
progressive foldback current limiting circuit that contin-
uously reduces the driver current with increasing output
fault voltage. The fault current is typically 2mA for faults
at the absolute maximum voltages of 40V.
The LT3960 receiver features an extended common
mode range of -36V to 36V when operating from a 5V
VCC and -25V to 25V when operating from a 3.3V VCC.
The wide common mode increases the reliability of oper-
ation in environments with electrical noise or local ground
potential differences due to ground loops. This extended
The LT3960 also features thermal shutdown protection
that disables the chip in the case of excessive power
dissipation from the drivers. When the die temperature
exceeds 168 ˚ C (typical), the LT3960 is forced into shut-
2
common mode range allows the LT3960 to conduct I C
communication in environments inhospitable to standard
2
2
I C, such as between two distant PCBs in an automobile.
down mode and the I CAN drivers enter a high impedance
state.
2
I CAN Driver
Power-Up/Down Glitch-Free Outputs
When the SCL or SDA pin is asserted low by external
2
I C device and the conditions are met (whether by mode
The LT3960 employs an undervoltage monitoring circuit
selection or bidirectional arbitration) to propagate this
on the V supply to control the activation of the trans-
CC
2
2
2
data from I C to CAN, the I CAN driver asserts the dom-
inant state on the corresponding bus lines; the CANxH
driver pulls high and the CANxL driver pulls low. When the
SCL or SDA pin is high under these same conditions, the
ceiver circuitry. During start-up SDA, SCL, and all I CAN
outputs are in a high impedance state until V reaches a
CC
voltage sufficient to reliably operate the chip. At this point,
if EN/MODE is out of its shutdown region, the chip acti-
vates. The CANSCL and CANSDA receivers activate after
2
I CAN driver is in the recessive state; both the CANxH and
CANxL drivers are in the high impedance state and the bus
termination resistor equalizes the voltage on CANxH and
CANxL. In the recessive state, the impedance on CANxH
and CANxL is determined by the receiver input resistance,
a short delay t
allowing SCL or SDA to follow the
EN;I2C
state of CANSCL or CANSDA. The CANSCL and CANSDA
drivers power up in the transmit dominant timeout state
regardless of the state of SCL or SDA and remain in the
recessive state until the first high to low transition of SCL
or SDA, respectively. This assures that the LT3960 does
R . When EN/MODE is low or the V is in UVLO, the
IN
CC
2
LT3960 is in shutdown; all I CAN drivers are in the high
2
impedance state, and the receiver input resistance R is
not disturb the I CAN bus by glitching to the dominant
IN
disconnected from the bus by a FET switch.
state during start-up.
During power-down, similar protection exists. When the
undervoltage detection circuit senses low supply voltage
Transmit Dominant Timeout Function
Both transceivers in the LT3960 include a 1.5ms (typical)
timer to limit the time that driver can hold the I CAN bus
on V , it immediately puts the chip into shutdown. All
CC
2
2
2
I C and I CAN pin outputs go the high impedance state.
Rev. A
16
For more information www.analog.com
LT3960
APPLICATIONS INFORMATION
Passive Leakage on I CAN Bus Pins
2
RESISTOR TERMINATION
CANxH
CANxH BUS
When the power supply is removed or the chip is in shut-
2
down, the I CAN pins are in a high impedance state. The
LT3960
120Ω
2
I CAN receiver inputs are isolated from the CANxH and
CANxL
CANxL BUS
CANxH BUS
CANxL pins by FET switches which open in the absence
of power, preventing the resistor dividers on the receiver
inputs from loading the bus. The high impedance state
SPLIT TERMINATION
CANxH
60Ω
2
of I CAN pins is maintained over a range determined by
the ESD protection of the pins, typically -0.3V to 7V. For
bus voltages outside this range, the current flowing into
the receiver is governed by the conduction voltages of
the ESD device and the 35.7k nominal I2CAN receiver
input resistance.
LT3960
4.7nF
CANxL BUS
60Ω
CANxL
3960 F10
Figure 10. Split Termination for Improved
Common Mode Behavior
2
I CAN Bus Termination
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢀ
ꢀꢁA
I2CAN buses must be terminated at the ends of each
twisted pair with a 120Ω resistor. Split termination is an
optional termination technique to reduce common mode
voltage perturbations that can produce EME. A split ter-
minator divides the single line-end termination resistor
(nominally 120Ω) into two series resistors of half the
value of the single termination resistor (Figure 10).
ꢀꢁꢂꢃꢄꢁ
ꢀAꢁꢂꢃAꢄ
ꢀꢁꢂꢃꢄꢁ
ꢀAꢁꢂꢃAꢄ
ꢀꢁꢂꢃꢄꢁ
ꢀAꢁꢂꢃA ꢀꢄ
ꢀꢁꢂꢃꢄꢅꢆꢃ
ꢀꢁꢂꢃ ꢄꢅꢅ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
Figure 11. I2CAN Common Mode Noise (4.7nF Split Cap)
The center point of the two resistors is connected to a
4.7nF capacitor. Split termination suppresses common
mode voltage perturbations by providing a low impedance
load to common mode noise sources such as transmitter
noise or coupling to external noise sources. In the case
of single resistor termination, the only load on a com-
mon mode noise source is the parallel impedance of the
ꢀ
ꢀ ꢁ.ꢁꢂ
ꢀꢀ
ꢀꢁA
ꢀꢁꢂꢃꢄꢁ
ꢀAꢁꢂꢃAꢄ
ꢀꢁꢂꢃꢄꢁ
ꢀAꢁꢂꢃAꢄ
ꢀꢁꢂꢃꢄꢁ
2
input resistors of the I CAN transceivers on the bus. This
ꢀAꢁꢂꢃA ꢀꢄ
ꢀꢁꢁꢂꢃꢄꢅꢆꢃ
results in a common mode impedance of several kΩ for a
small network. The split termination, on the other hand,
provides a common mode load equal to the parallel resis-
tance of the two split termination resistors (30Ω). This
low common mode impedance results in a reduction of
the common mode noise voltage compared to the much
higher common mode impedance of the single resistor
termination. Figure 11 and Figure 12 compare the com-
mon mode noise of an application with and without split
cap termination.
ꢀꢁꢂꢃ ꢄꢅꢆ
ꢀꢁꢁꢂꢃꢄꢅꢆꢇ
Figure 12. I2CAN Common Mode Noise (No Split Cap)
Rev. A
17
For more information www.analog.com
LT3960
APPLICATIONS INFORMATION
Multidrop Applications
of the propagation delays (t
and t
), slave ACK
). This
SU;ACK
PI2CBD
time (t
), and master data setup tiPmBeI2(CtD
VD;ACK
The LT3960 can be used in a multidrop setup, employ-
ing multiple slave-mode LT3960’s to generate multiple
requirement is shown explicitly in Equation 1.
2
tLOW >2 tPI2CBD,max + tCABLE + tPBI2CD,max
local I C buses on multiple PCBs along the length of the
(
)
2
(1)
I CAN bus lines. No additional termination is required in
+tVD;ACK,max + tSU;ACK
a multidrop system, but some care must be taken in the
design of such systems. The stub length, or the distance
from twisted pairs to any additional LT3960, should be
less than 0.3m. Stub lengths to the CANSDA and CANSCL
buses should be as close as possible in length to avoid
adding unequal transmission delays to the clock and
data signals.
A conservative estimate of propagation delay
through a twisted pair based on cable length is shown in
Equation 2. Equation 2 is useful for rough estimates, but
when designing applications always calculate propaga-
tion delay based on the actual physical properties of the
2
cabling used for the I CAN bus lines.
120Ω
120Ω
ICABLE
0.15m/ns
tCABLE
=
(2)
2
I C SLAVE
LT3960
LT3960
LT3960
Fast-mode (400kHz capable) I2C devices are allowed 0.9µs
to acknowledge a valid data byte, even while ACK times
(t
) are often much shorter in practice. A t
of
VD;ACK
VD;ACK
0.9µs would limit the data transmission rate of a LT3960
application to under 400kHz for even one meter of twisted
2
I C SLAVE
2
pair. For this reason, it is recommended that all I C slaves
be Fast-mode Plus (1MHz) devices instead of Fast-mode
(400kHz) devices when attempting to maximize trans-
mission rate. The shorter maximum tVD;ACK (450ns) of
Fast-mode plus devices allows for communication across
a greater distance at any given clock speed. Figure 14
consolidates the information above, plotting maximum
clock speeds for a given bus length for applications with
fast-mode and fast-mode plus devices.
2
I C SLAVE
2
I C SLAVE
120Ω
120Ω
3960 F14
Figure 13. Multidrop Setup
Maximum Data Transmission Rate
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁ
ꢀꢁꢂ
ꢀꢁꢂ
Successful communication in any I2C application is
2
dependent on slave I C devices’ timely acknowledgment
2
(or ACK) upon receiving a byte of data. Specifically, I C
slaves must assert the SDA line after the eighth clock
pulse leaving enough setup time before the ninth rising
edge of SCL to guarantee that the ACK will be received by
2
the I C master. This requirement is straightforward when
2
2
all I C devices share the same I C bus, but in LT3960
2
applications where master and slave I C buses are sepa-
ꢀꢀꢁ
ꢀAꢁꢂꢃꢄꢅꢆꢇ ꢁꢈAꢉꢇ ꢆꢇꢉꢊꢋꢇꢁ
ꢀAꢁꢂꢃꢄꢅꢆꢇ ꢈꢉꢊꢁ ꢁꢉAꢋꢇ ꢆꢇꢋꢌꢍꢇꢁ
rated by various propagation delays, extra care must be
ꢀꢁꢁ
2
ꢀ
ꢀ
ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ ꢀꢁ
taken to ensure that ACKs from slave I C devices will be
ꢀꢁꢂ ꢃꢄꢅꢆꢇꢈ ꢉꢊꢋ
2
received by the I C master at the desired transmission
ꢀꢁꢂꢃ ꢄꢅꢆ
rate. In LT3960 applications, the SCL low period between
successive clock pulses (tLOW)must be less than the sum
Figure 14. Maximum I2CAN Clock Speed
Rev. A
18
For more information www.analog.com
LT3960
TYPICAL APPLICATIONS
1A Matrix LED Dimmer with Remote I2C Control
ꢀꢁꢂ ꢃꢄ ꢀꢅꢂ
ꢆꢇꢈAꢉꢊꢇꢋ Aꢃ ꢀꢀ ꢌ
ꢍꢎꢏꢃꢋꢄꢐꢈ Aꢃ ꢀꢁꢂꢑ
ꢄ
ꢀꢁꢂꢃ
ꢀ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ
ꢀꢁꢂ
ꢀ.ꢁꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄ
ꢀꢁꢂ
100mΩ
ꢀꢁꢂꢃ
ꢀꢁꢂ
ꢀRꢁꢂ
ꢀ
ꢀꢁꢂ ꢃꢄ ꢀꢅꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀꢁ
ꢀꢁꢁꢂꢃ
ꢀꢁꢂ
1MΩ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅꢆ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁ.ꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁ.ꢂꢃ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂꢃꢄꢅ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢀ
ꢁꢁ
ꢄꢄ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀꢁꢂ
ꢀꢁꢁꢂ
ꢀ.ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂꢃ
ꢀꢁꢂꢃ
ꢀꢁRꢂꢃ
AꢀꢀRꢁ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀRꢁꢂ
ꢀRꢁꢂ
ALERT
ALERT
ꢀꢁꢂꢃꢄꢅ
AꢀꢀRꢁ
AꢀꢀRꢁ
AꢀꢀRꢁ
AꢀꢀRꢁ
ꢀꢁꢂꢃ
ꢄꢄ
ꢀꢁꢁꢂ
AꢀꢀRꢁꢂꢂꢃꢃꢃꢂꢂ
AꢀꢀRꢁꢂꢃꢂꢃꢃꢂꢂ
ꢄꢅRꢁꢆꢇꢀ ꢅꢈꢈ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀꢁꢂꢀ
AꢀꢀRꢁ
ꢀꢁꢂꢃ
ꢀꢀꢁ
ꢀꢁꢂꢃꢄꢃꢅꢆꢇꢈꢉ
ꢀꢁꢂꢀꢃ
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇꢈꢉ
ꢀRꢁꢂ
ꢀRꢁꢂ
Rꢀꢁꢂꢃ
ꢀꢁꢂꢀꢃ
ꢄꢅRꢂꢆ
ꢁꢇꢈꢉꢊꢋꢌ
ALERT
ALERT
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁꢂ
Rꢀ
ꢀꢁꢂꢃ
ꢀRꢁꢂ
ꢀRꢁꢂ
ꢀꢁꢂꢃ
ꢄꢅꢆꢃꢇꢈ
ꢀꢁA
ꢀꢁꢂ
ꢀꢁꢂ
ꢀꢁA
ꢀRꢁꢂ
ꢀ
ꢀꢁꢂꢃRꢄ ꢃ ꢅ ꢃꢆꢇꢄRꢈAꢅꢄ
ꢀꢁꢂ
3.3V
OR 5V
2.2µF
V
IN
V
IN
V
CANSDAH
CANSDAH
V
CC
CC
μCONTROLLER
120Ω
120Ω
120Ω
120Ω
2.2µF
2
LT3960
CANSDAL
LT3960
CANSDAL
CANSCLH
I C MASTER
5k 5k
10k 10k
SDA
SCL
SDA
SCL
CANSCLH
SDA
SCL
DIG I/O
EN/MODE
CANSCLL
CANSCLL
EN/MODE
GND
GND1
GND
GND
3960 TA03
GND2
ꢅ
Rꢀꢁꢂꢃꢀ ꢄ ꢆ ꢁAꢇꢃꢀR
Rev. A
19
For more information www.analog.com
LT3960
PACKAGE DESCRIPTION
MSE Package
10-Lead Plastic MSOP, Exposed Die Pad
(Reference LTC DWG # 05-08-1664 Rev I)
BOTTOM VIEW OF
EXPOSED PAD OPTION
1.88
(.074)
1.88 ±0.102
(.074 ±.004)
0.889 ±0.127
(.035 ±.005)
1
0.29
REF
1.68
(.066)
0.05 REF
5.10
(.201)
MIN
1.68 ±0.102
3.20 – 3.45
DETAIL “B”
(.066 ±.004) (.126 – .136)
CORNER TAIL IS PART OF
THE LEADFRAME FEATURE.
FOR REFERENCE ONLY
DETAIL “B”
10
NO MEASUREMENT PURPOSE
0.50
(.0197)
BSC
0.305 ± 0.038
(.0120 ±.0015)
TYP
3.00 ±0.102
(.118 ±.004)
(NOTE 3)
0.497 ±0.076
(.0196 ±.003)
10 9
8
7 6
RECOMMENDED SOLDER PAD LAYOUT
REF
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
4.90 ±0.152
(.193 ±.006)
DETAIL “A”
0° – 6° TYP
0.254
(.010)
1
2
3
4 5
GAUGE PLANE
0.53 ±0.152
(.021 ±.006)
0.86
(.034)
REF
1.10
(.043)
MAX
DETAIL “A”
0.18
(.007)
SEATING
PLANE
0.17 – 0.27
(.007 – .011)
TYP
0.1016 ±0.0508
(.004 ±.002)
0.50
(.0197)
BSC
MSOP (MSE) 0213 REV I
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
6. EXPOSED PAD DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH ON E-PAD
SHALL NOT EXCEED 0.254mm (.010") PER SIDE.
Rev. A
20
For more information www.analog.com
LT3960
REVISION HISTORY
REV
DATE
DESCRIPTION
PAGE NUMBER
A
02/21 Changed topmark from LHJP to LTHJP
2
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
21
LT3960
TYPICAL APPLICATION
Network for IEC 6100-4-2 Level 4 ESD Protection
ꢀAꢁꢂꢃAꢄ
ꢀAꢁꢂꢃAꢄ
60.4Ω
ꢀAꢁꢂꢃAꢄ
ꢀ.ꢁꢂꢃ
ꢀꢁꢂ
60.4Ω
ꢀAꢁꢂꢃAꢄ
ꢀꢁꢂ
ꢀꢁꢂꢃꢄꢅ
ꢀꢁꢂ
ꢀAꢁꢂꢀꢃꢄ
60.4Ω
ꢀꢁꢂ
ꢀ.ꢁꢂꢃ
ꢀAꢁꢂꢀꢃꢄ
60.4Ω
ꢀAꢁꢂꢀꢃꢃ
ꢀAꢁꢂꢀꢃꢃ
ꢀꢁꢂꢃ ꢄAꢃꢅ
ꢀꢁꢂꢃ ꢄꢅ ꢂꢆꢇꢈ ꢅꢉꢊꢋꢌꢍꢎꢏꢐ ꢑꢎꢍꢒ ꢓꢉAꢏ ꢔꢈꢓꢈRꢆꢕꢀꢈꢄꢅAꢏ ꢀꢁꢂ ꢓꢈꢄꢓꢆꢐ ꢂꢄꢀꢖꢋꢑ
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
2
2
LT3965
8-Switch Matrix LED Dimmer
I C Multidrop Serial Interface, 16 Unique I C Addresses, V Range: 2.7V to 5.5V,
DD
V
Range: 8V to 60V, Digital Programmable 256:1 PWM Dimming, 28-Lead TSSOP
IN
2
LT3967
LT3964
LTC4331
1.3A Eight-Switch Matrix LED
Dimmer with CRC-8
Controls LED Dimming of Strings Up to 54V, I C Serial Interface with Programmable
Address, 28-Lead TSSOP
Dual 36V Synchronous 1.6A Buck
Wide Input Voltage Range: 4V to 36V, Two Independent 1.6A/40V Synchronous Bucks,
I C Interface for Internal True Color PWM™ Dimming (8192:1), 36-Lead QFN
2
2
LED Driver with I C
2
2
I C Slave Device Extender Over
Up to 1MHz Serial Clock, Fast-Mode Plus (FM+), Selectable Link Baud Rates Extend I C
Rugged Differential Link
Up to 1200m, 20-Lead QFN
Rev. A
02/21
www.analog.com
22
ANALOG DEVICES, INC. 2020-2021
相关型号：
©2020 ICPDF网 联系我们和版权申明